drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/drm_fb_helper.h>
  29 #include <drm/radeon_drm.h>
  30 #include <drm/drm_fixed.h>
  31 #include "radeon.h"
  32 #include "atom.h"
  33
  34 static void radeon_overscan_setup(struct drm_crtc *crtc,
  35                                   struct drm_display_mode *mode)
  36 {
  37         struct drm_device *dev = crtc->dev;
  38         struct radeon_device *rdev = dev->dev_private;
  39         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  40
  41         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  42         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  43         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  44 }
  45
  46 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  47                                        struct drm_display_mode *mode)
  48 {
  49         struct drm_device *dev = crtc->dev;
  50         struct radeon_device *rdev = dev->dev_private;
  51         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  52         int xres = mode->hdisplay;
  53         int yres = mode->vdisplay;
  54         bool hscale = true, vscale = true;
  55         int hsync_wid;
  56         int vsync_wid;
  57         int hsync_start;
  58         int blank_width;
  59         u32 scale, inc, crtc_more_cntl;
  60         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  61         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  62         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  63         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  64
  65         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  66                 (RADEON_VERT_STRETCH_RESERVED |
  67                  RADEON_VERT_AUTO_RATIO_INC);
  68         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  69                 (RADEON_HORZ_FP_LOOP_STRETCH |
  70                  RADEON_HORZ_AUTO_RATIO_INC);
  71
  72         crtc_more_cntl = 0;
  73         if ((rdev->family == CHIP_RS100) ||
  74             (rdev->family == CHIP_RS200)) {
  75                 /* This is to workaround the asic bug for RMX, some versions
  76                    of BIOS dosen't have this register initialized correctly. */
  77                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  78         }
  79
  80
  81         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  82                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  83
  84         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  85         if (!hsync_wid)
  86                 hsync_wid = 1;
  87         hsync_start = mode->crtc_hsync_start - 8;
  88
  89         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  90                               | ((hsync_wid & 0x3f) << 16)
  91                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  92                                  ? RADEON_CRTC_H_SYNC_POL
  93                                  : 0));
  94
  95         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  96                                 | ((mode->crtc_vdisplay - 1) << 16));
  97
  98         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  99         if (!vsync_wid)
 100                 vsync_wid = 1;
 101
 102         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 103                               | ((vsync_wid & 0x1f) << 16)
 104                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 105                                  ? RADEON_CRTC_V_SYNC_POL
 106                                  : 0));
 107
 108         fp_horz_vert_active = 0;
 109
 110         if (native_mode->hdisplay == 0 ||
 111             native_mode->vdisplay == 0) {
 112                 hscale = false;
 113                 vscale = false;
 114         } else {
 115                 if (xres > native_mode->hdisplay)
 116                         xres = native_mode->hdisplay;
 117                 if (yres > native_mode->vdisplay)
 118                         yres = native_mode->vdisplay;
 119
 120                 if (xres == native_mode->hdisplay)
 121                         hscale = false;
 122                 if (yres == native_mode->vdisplay)
 123                         vscale = false;
 124         }
 125
 126         switch (radeon_crtc->rmx_type) {
 127         case RMX_FULL:
 128         case RMX_ASPECT:
 129                 if (!hscale)
 130                         fp_horz_stretch |= ((xres/8-1) << 16);
 131                 else {
 132                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 133                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 134                                 / native_mode->hdisplay + 1;
 135                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 136                                         RADEON_HORZ_STRETCH_BLEND |
 137                                         RADEON_HORZ_STRETCH_ENABLE |
 138                                         ((native_mode->hdisplay/8-1) << 16));
 139                 }
 140
 141                 if (!vscale)
 142                         fp_vert_stretch |= ((yres-1) << 12);
 143                 else {
 144                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 145                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 146                                 / native_mode->vdisplay + 1;
 147                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 148                                         RADEON_VERT_STRETCH_ENABLE |
 149                                         RADEON_VERT_STRETCH_BLEND |
 150                                         ((native_mode->vdisplay-1) << 12));
 151                 }
 152                 break;
 153         case RMX_CENTER:
 154                 fp_horz_stretch |= ((xres/8-1) << 16);
 155                 fp_vert_stretch |= ((yres-1) << 12);
 156
 157                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 158                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 159
 160                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 161                 if (blank_width > 110)
 162                         blank_width = 110;
 163
 164                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 165                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 166
 167                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 168                 if (!hsync_wid)
 169                         hsync_wid = 1;
 170
 171                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 172                                 | ((hsync_wid & 0x3f) << 16)
 173                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 174                                         ? RADEON_CRTC_H_SYNC_POL
 175                                         : 0));
 176
 177                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 178                                 | ((mode->crtc_vdisplay - 1) << 16));
 179
 180                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 181                 if (!vsync_wid)
 182                         vsync_wid = 1;
 183
 184                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 185                                         | ((vsync_wid & 0x1f) << 16)
 186                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 187                                                 ? RADEON_CRTC_V_SYNC_POL
 188                                                 : 0)));
 189
 190                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 191                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 192                 break;
 193         case RMX_OFF:
 194         default:
 195                 fp_horz_stretch |= ((xres/8-1) << 16);
 196                 fp_vert_stretch |= ((yres-1) << 12);
 197                 break;
 198         }
 199
 200         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 201         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 202         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 203         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 204         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 205         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 206         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 207         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 208 }
 209
 210 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 211 {
 212         struct radeon_device *rdev = dev->dev_private;
 213         int i = 0;
 214
 215         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 216            the cause yet, but this workaround will mask the problem for now.
 217            Other chips usually will pass at the very first test, so the
 218            workaround shouldn't have any effect on them. */
 219         for (i = 0;
 220              (i < 10000 &&
 221               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 222              i++);
 223 }
 224
 225 static void radeon_pll_write_update(struct drm_device *dev)
 226 {
 227         struct radeon_device *rdev = dev->dev_private;
 228
 229         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 230
 231         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 232                            RADEON_PPLL_ATOMIC_UPDATE_W,
 233                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 234 }
 235
 236 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 237 {
 238         struct radeon_device *rdev = dev->dev_private;
 239         int i = 0;
 240
 241
 242         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 243            the cause yet, but this workaround will mask the problem for now.
 244            Other chips usually will pass at the very first test, so the
 245            workaround shouldn't have any effect on them. */
 246         for (i = 0;
 247              (i < 10000 &&
 248               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 249              i++);
 250 }
 251
 252 static void radeon_pll2_write_update(struct drm_device *dev)
 253 {
 254         struct radeon_device *rdev = dev->dev_private;
 255
 256         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 257
 258         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 259                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 260                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 261 }
 262
 263 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 264                                        uint16_t fb_div)
 265 {
 266         unsigned int vcoFreq;
 267
 268         if (!ref_div)
 269                 return 1;
 270
 271         vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
 272
 273         /*
 274          * This is horribly crude: the VCO frequency range is divided into
 275          * 3 parts, each part having a fixed PLL gain value.
 276          */
 277         if (vcoFreq >= 30000)
 278                 /*
 279                  * [300..max] MHz : 7
 280                  */
 281                 return 7;
 282         else if (vcoFreq >= 18000)
 283                 /*
 284                  * [180..300) MHz : 4
 285                  */
 286                 return 4;
 287         else
 288                 /*
 289                  * [0..180) MHz : 1
 290                  */
 291                 return 1;
 292 }
 293
 294 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 295 {
 296         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 297         struct drm_device *dev = crtc->dev;
 298         struct radeon_device *rdev = dev->dev_private;
 299         uint32_t crtc_ext_cntl = 0;
 300         uint32_t mask;
 301
 302         if (radeon_crtc->crtc_id)
 303                 mask = (RADEON_CRTC2_DISP_DIS |
 304                         RADEON_CRTC2_VSYNC_DIS |
 305                         RADEON_CRTC2_HSYNC_DIS |
 306                         RADEON_CRTC2_DISP_REQ_EN_B);
 307         else
 308                 mask = (RADEON_CRTC_DISPLAY_DIS |
 309                         RADEON_CRTC_VSYNC_DIS |
 310                         RADEON_CRTC_HSYNC_DIS);
 311
 312         /*
 313          * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
 314          * Therefore it is set in the DAC DMPS function.
 315          * This is different for GPU's with a single CRTC but a primary and a
 316          * TV DAC: here it controls the single CRTC no matter where it is
 317          * routed. Therefore we set it here.
 318          */
 319         if (rdev->flags & RADEON_SINGLE_CRTC)
 320                 crtc_ext_cntl = RADEON_CRTC_CRT_ON;
 321
 322         switch (mode) {
 323         case DRM_MODE_DPMS_ON:
 324                 radeon_crtc->enabled = true;
 325                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 326                 radeon_pm_compute_clocks(rdev);
 327                 if (radeon_crtc->crtc_id)
 328                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 329                 else {
 330                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 331                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 332                         WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
 333                 }
 334                 if (dev->num_crtcs > radeon_crtc->crtc_id)
 335                         drm_crtc_vblank_on(crtc);
 336                 radeon_crtc_load_lut(crtc);
 337                 break;
 338         case DRM_MODE_DPMS_STANDBY:
 339         case DRM_MODE_DPMS_SUSPEND:
 340         case DRM_MODE_DPMS_OFF:
 341                 if (dev->num_crtcs > radeon_crtc->crtc_id)
 342                         drm_crtc_vblank_off(crtc);
 343                 if (radeon_crtc->crtc_id)
 344                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 345                 else {
 346                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 347                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 348                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
 349                 }
 350                 radeon_crtc->enabled = false;
 351                 /* adjust pm to dpms changes AFTER disabling crtcs */
 352                 radeon_pm_compute_clocks(rdev);
 353                 break;
 354         }
 355 }
 356
 357 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 358                          struct drm_framebuffer *old_fb)
 359 {
 360         return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
 361 }
 362
 363 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 364                                 struct drm_framebuffer *fb,
 365                                 int x, int y, enum mode_set_atomic state)
 366 {
 367         return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 368 }
 369
 370 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 371                          struct drm_framebuffer *fb,
 372                          int x, int y, int atomic)
 373 {
 374         struct drm_device *dev = crtc->dev;
 375         struct radeon_device *rdev = dev->dev_private;
 376         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 377         struct drm_framebuffer *target_fb;
 378         struct drm_gem_object *obj;
 379         struct radeon_bo *rbo;
 380         uint64_t base;
 381         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 382         uint32_t crtc_pitch, pitch_pixels;
 383         uint32_t tiling_flags;
 384         int format;
 385         uint32_t gen_cntl_reg, gen_cntl_val;
 386         int r;
 387
 388         DRM_DEBUG_KMS("\n");
 389         /* no fb bound */
 390         if (!atomic && !crtc->primary->fb) {
 391                 DRM_DEBUG_KMS("No FB bound\n");
 392                 return 0;
 393         }
 394
 395         if (atomic)
 396                 target_fb = fb;
 397         else
 398                 target_fb = crtc->primary->fb;
 399
 400         switch (target_fb->format->cpp[0] * 8) {
 401         case 8:
 402                 format = 2;
 403                 break;
 404         case 15:      /*  555 */
 405                 format = 3;
 406                 break;
 407         case 16:      /*  565 */
 408                 format = 4;
 409                 break;
 410         case 24:      /*  RGB */
 411                 format = 5;
 412                 break;
 413         case 32:      /* xRGB */
 414                 format = 6;
 415                 break;
 416         default:
 417                 return false;
 418         }
 419
 420         /* Pin framebuffer & get tilling informations */
 421         obj = target_fb->obj[0];
 422         rbo = gem_to_radeon_bo(obj);
 423 retry:
 424         r = radeon_bo_reserve(rbo, false);
 425         if (unlikely(r != 0))
 426                 return r;
 427         /* Only 27 bit offset for legacy CRTC */
 428         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
 429                                      &base);
 430         if (unlikely(r != 0)) {
 431                 radeon_bo_unreserve(rbo);
 432
 433                 /* On old GPU like RN50 with little vram pining can fails because
 434                  * current fb is taking all space needed. So instead of unpining
 435                  * the old buffer after pining the new one, first unpin old one
 436                  * and then retry pining new one.
 437                  *
 438                  * As only master can set mode only master can pin and it is
 439                  * unlikely the master client will race with itself especialy
 440                  * on those old gpu with single crtc.
 441                  *
 442                  * We don't shutdown the display controller because new buffer
 443                  * will end up in same spot.
 444                  */
 445                 if (!atomic && fb && fb != crtc->primary->fb) {
 446                         struct radeon_bo *old_rbo;
 447                         unsigned long nsize, osize;
 448
 449                         old_rbo = gem_to_radeon_bo(fb->obj[0]);
 450                         osize = radeon_bo_size(old_rbo);
 451                         nsize = radeon_bo_size(rbo);
 452                         if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
 453                                 radeon_bo_unpin(old_rbo);
 454                                 radeon_bo_unreserve(old_rbo);
 455                                 fb = NULL;
 456                                 goto retry;
 457                         }
 458                 }
 459                 return -EINVAL;
 460         }
 461         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 462         radeon_bo_unreserve(rbo);
 463         if (tiling_flags & RADEON_TILING_MICRO)
 464                 DRM_ERROR("trying to scanout microtiled buffer\n");
 465
 466         /* if scanout was in GTT this really wouldn't work */
 467         /* crtc offset is from display base addr not FB location */
 468         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 469
 470         base -= radeon_crtc->legacy_display_base_addr;
 471
 472         crtc_offset_cntl = 0;
 473
 474         pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
 475         crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8,
 476                                   target_fb->format->cpp[0] * 8 * 8);
 477         crtc_pitch |= crtc_pitch << 16;
 478
 479         crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
 480         if (tiling_flags & RADEON_TILING_MACRO) {
 481                 if (ASIC_IS_R300(rdev))
 482                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 483                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 484                                              R300_CRTC_MACRO_TILE_EN);
 485                 else
 486                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 487         } else {
 488                 if (ASIC_IS_R300(rdev))
 489                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 490                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 491                                               R300_CRTC_MACRO_TILE_EN);
 492                 else
 493                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 494         }
 495
 496         if (tiling_flags & RADEON_TILING_MACRO) {
 497                 if (ASIC_IS_R300(rdev)) {
 498                         crtc_tile_x0_y0 = x | (y << 16);
 499                         base &= ~0x7ff;
 500                 } else {
 501                         int byteshift = target_fb->format->cpp[0] * 8 >> 4;
 502                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 503                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 504                         crtc_offset_cntl |= (y % 16);
 505                 }
 506         } else {
 507                 int offset = y * pitch_pixels + x;
 508                 switch (target_fb->format->cpp[0] * 8) {
 509                 case 8:
 510                         offset *= 1;
 511                         break;
 512                 case 15:
 513                 case 16:
 514                         offset *= 2;
 515                         break;
 516                 case 24:
 517                         offset *= 3;
 518                         break;
 519                 case 32:
 520                         offset *= 4;
 521                         break;
 522                 default:
 523                         return false;
 524                 }
 525                 base += offset;
 526         }
 527
 528         base &= ~7;
 529
 530         if (radeon_crtc->crtc_id == 1)
 531                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 532         else
 533                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 534
 535         gen_cntl_val = RREG32(gen_cntl_reg);
 536         gen_cntl_val &= ~(0xf << 8);
 537         gen_cntl_val |= (format << 8);
 538         gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
 539         WREG32(gen_cntl_reg, gen_cntl_val);
 540
 541         crtc_offset = (u32)base;
 542
 543         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 544
 545         if (ASIC_IS_R300(rdev)) {
 546                 if (radeon_crtc->crtc_id)
 547                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 548                 else
 549                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 550         }
 551         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 552         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 553         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 554
 555         if (!atomic && fb && fb != crtc->primary->fb) {
 556                 rbo = gem_to_radeon_bo(fb->obj[0]);
 557                 r = radeon_bo_reserve(rbo, false);
 558                 if (unlikely(r != 0))
 559                         return r;
 560                 radeon_bo_unpin(rbo);
 561                 radeon_bo_unreserve(rbo);
 562         }
 563
 564         /* Bytes per pixel may have changed */
 565         radeon_bandwidth_update(rdev);
 566
 567         return 0;
 568 }
 569
 570 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 571 {
 572         struct drm_device *dev = crtc->dev;
 573         struct radeon_device *rdev = dev->dev_private;
 574         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 575         const struct drm_framebuffer *fb = crtc->primary->fb;
 576         struct drm_encoder *encoder;
 577         int format;
 578         int hsync_start;
 579         int hsync_wid;
 580         int vsync_wid;
 581         uint32_t crtc_h_total_disp;
 582         uint32_t crtc_h_sync_strt_wid;
 583         uint32_t crtc_v_total_disp;
 584         uint32_t crtc_v_sync_strt_wid;
 585         bool is_tv = false;
 586
 587         DRM_DEBUG_KMS("\n");
 588         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 589                 if (encoder->crtc == crtc) {
 590                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 591                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 592                                 is_tv = true;
 593                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 594                                 break;
 595                         }
 596                 }
 597         }
 598
 599         switch (fb->format->cpp[0] * 8) {
 600         case 8:
 601                 format = 2;
 602                 break;
 603         case 15:      /*  555 */
 604                 format = 3;
 605                 break;
 606         case 16:      /*  565 */
 607                 format = 4;
 608                 break;
 609         case 24:      /*  RGB */
 610                 format = 5;
 611                 break;
 612         case 32:      /* xRGB */
 613                 format = 6;
 614                 break;
 615         default:
 616                 return false;
 617         }
 618
 619         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 620                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 621
 622         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 623         if (!hsync_wid)
 624                 hsync_wid = 1;
 625         hsync_start = mode->crtc_hsync_start - 8;
 626
 627         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 628                                 | ((hsync_wid & 0x3f) << 16)
 629                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 630                                    ? RADEON_CRTC_H_SYNC_POL
 631                                    : 0));
 632
 633         /* This works for double scan mode. */
 634         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 635                              | ((mode->crtc_vdisplay - 1) << 16));
 636
 637         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 638         if (!vsync_wid)
 639                 vsync_wid = 1;
 640
 641         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 642                                 | ((vsync_wid & 0x1f) << 16)
 643                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 644                                    ? RADEON_CRTC_V_SYNC_POL
 645                                    : 0));
 646
 647         if (radeon_crtc->crtc_id) {
 648                 uint32_t crtc2_gen_cntl;
 649                 uint32_t disp2_merge_cntl;
 650
 651                 /* if TV DAC is enabled for another crtc and keep it enabled */
 652                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 653                 crtc2_gen_cntl |= ((format << 8)
 654                                    | RADEON_CRTC2_VSYNC_DIS
 655                                    | RADEON_CRTC2_HSYNC_DIS
 656                                    | RADEON_CRTC2_DISP_DIS
 657                                    | RADEON_CRTC2_DISP_REQ_EN_B
 658                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 659                                       ? RADEON_CRTC2_DBL_SCAN_EN
 660                                       : 0)
 661                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 662                                       ? RADEON_CRTC2_CSYNC_EN
 663                                       : 0)
 664                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 665                                       ? RADEON_CRTC2_INTERLACE_EN
 666                                       : 0));
 667
 668                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 669                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 670                         crtc2_gen_cntl |= RADEON_CRTC2_EN;
 671
 672                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 673                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 674
 675                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 676                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 677
 678                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 679                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 680         } else {
 681                 uint32_t crtc_gen_cntl;
 682                 uint32_t crtc_ext_cntl;
 683                 uint32_t disp_merge_cntl;
 684
 685                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 686                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 687                                  | (format << 8)
 688                                  | RADEON_CRTC_DISP_REQ_EN_B
 689                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 690                                     ? RADEON_CRTC_DBL_SCAN_EN
 691                                     : 0)
 692                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 693                                     ? RADEON_CRTC_CSYNC_EN
 694                                     : 0)
 695                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 696                                     ? RADEON_CRTC_INTERLACE_EN
 697                                     : 0));
 698
 699                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 700                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 701                         crtc_gen_cntl |= RADEON_CRTC_EN;
 702
 703                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 704                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 705                                   RADEON_CRTC_VSYNC_DIS |
 706                                   RADEON_CRTC_HSYNC_DIS |
 707                                   RADEON_CRTC_DISPLAY_DIS);
 708
 709                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 710                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 711
 712                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 713                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 714                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 715         }
 716
 717         if (is_tv)
 718                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 719                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 720                                                  &crtc_v_sync_strt_wid);
 721
 722         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 723         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 724         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 725         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 726
 727         return true;
 728 }
 729
 730 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 731 {
 732         struct drm_device *dev = crtc->dev;
 733         struct radeon_device *rdev = dev->dev_private;
 734         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 735         struct drm_encoder *encoder;
 736         uint32_t feedback_div = 0;
 737         uint32_t frac_fb_div = 0;
 738         uint32_t reference_div = 0;
 739         uint32_t post_divider = 0;
 740         uint32_t freq = 0;
 741         uint8_t pll_gain;
 742         bool use_bios_divs = false;
 743         /* PLL registers */
 744         uint32_t pll_ref_div = 0;
 745         uint32_t pll_fb_post_div = 0;
 746         uint32_t htotal_cntl = 0;
 747         bool is_tv = false;
 748         struct radeon_pll *pll;
 749
 750         struct {
 751                 int divider;
 752                 int bitvalue;
 753         } *post_div, post_divs[]   = {
 754                 /* From RAGE 128 VR/RAGE 128 GL Register
 755                  * Reference Manual (Technical Reference
 756                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 757                  * 3-17 (PLL_DIV_[3:0]).
 758                  */
 759                 {  1, 0 },              /* VCLK_SRC                 */
 760                 {  2, 1 },              /* VCLK_SRC/2               */
 761                 {  4, 2 },              /* VCLK_SRC/4               */
 762                 {  8, 3 },              /* VCLK_SRC/8               */
 763                 {  3, 4 },              /* VCLK_SRC/3               */
 764                 { 16, 5 },              /* VCLK_SRC/16              */
 765                 {  6, 6 },              /* VCLK_SRC/6               */
 766                 { 12, 7 },              /* VCLK_SRC/12              */
 767                 {  0, 0 }
 768         };
 769
 770         if (radeon_crtc->crtc_id)
 771                 pll = &rdev->clock.p2pll;
 772         else
 773                 pll = &rdev->clock.p1pll;
 774
 775         pll->flags = RADEON_PLL_LEGACY;
 776
 777         if (mode->clock > 200000) /* range limits??? */
 778                 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 779         else
 780                 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 781
 782         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 783                 if (encoder->crtc == crtc) {
 784                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 785
 786                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 787                                 is_tv = true;
 788                                 break;
 789                         }
 790
 791                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 792                                 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 793                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 794                                 if (!rdev->is_atom_bios) {
 795                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 796                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 797                                         if (lvds) {
 798                                                 if (lvds->use_bios_dividers) {
 799                                                         pll_ref_div = lvds->panel_ref_divider;
 800                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
 801                                                                              (lvds->panel_post_divider << 16));
 802                                                         htotal_cntl  = 0;
 803                                                         use_bios_divs = true;
 804                                                 }
 805                                         }
 806                                 }
 807                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 808                         }
 809                 }
 810         }
 811
 812         DRM_DEBUG_KMS("\n");
 813
 814         if (!use_bios_divs) {
 815                 radeon_compute_pll_legacy(pll, mode->clock,
 816                                           &freq, &feedback_div, &frac_fb_div,
 817                                           &reference_div, &post_divider);
 818
 819                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 820                         if (post_div->divider == post_divider)
 821                                 break;
 822                 }
 823
 824                 if (!post_div->divider)
 825                         post_div = &post_divs[0];
 826
 827                 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
 828                           (unsigned)freq,
 829                           feedback_div,
 830                           reference_div,
 831                           post_divider);
 832
 833                 pll_ref_div   = reference_div;
 834 #if defined(__powerpc__) && (0) /* TODO */
 835                 /* apparently programming this otherwise causes a hang??? */
 836                 if (info->MacModel == RADEON_MAC_IBOOK)
 837                         pll_fb_post_div = 0x000600ad;
 838                 else
 839 #endif
 840                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 841
 842                 htotal_cntl    = mode->htotal & 0x7;
 843
 844         }
 845
 846         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 847                                            pll_ref_div & 0x3ff,
 848                                            pll_fb_post_div & 0x7ff);
 849
 850         if (radeon_crtc->crtc_id) {
 851                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 852                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 853                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 854
 855                 if (is_tv) {
 856                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 857                                                      &pll_ref_div, &pll_fb_post_div,
 858                                                      &pixclks_cntl);
 859                 }
 860
 861                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 862                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 863                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 864
 865                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 866                              RADEON_P2PLL_RESET
 867                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 868                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 869                              ~(RADEON_P2PLL_RESET
 870                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 871                                | RADEON_P2PLL_PVG_MASK));
 872
 873                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 874                              pll_ref_div,
 875                              ~RADEON_P2PLL_REF_DIV_MASK);
 876
 877                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 878                              pll_fb_post_div,
 879                              ~RADEON_P2PLL_FB0_DIV_MASK);
 880
 881                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 882                              pll_fb_post_div,
 883                              ~RADEON_P2PLL_POST0_DIV_MASK);
 884
 885                 radeon_pll2_write_update(dev);
 886                 radeon_pll2_wait_for_read_update_complete(dev);
 887
 888                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 889
 890                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 891                              0,
 892                              ~(RADEON_P2PLL_RESET
 893                                | RADEON_P2PLL_SLEEP
 894                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 895
 896                 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 897                           (unsigned)pll_ref_div,
 898                           (unsigned)pll_fb_post_div,
 899                           (unsigned)htotal_cntl,
 900                           RREG32_PLL(RADEON_P2PLL_CNTL));
 901                 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
 902                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 903                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 904                           (unsigned)((pll_fb_post_div &
 905                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 906
 907                 mdelay(50); /* Let the clock to lock */
 908
 909                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 910                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 911                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 912
 913                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 914         } else {
 915                 uint32_t pixclks_cntl;
 916
 917
 918                 if (is_tv) {
 919                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 920                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 921                                                      &pll_fb_post_div, &pixclks_cntl);
 922                 }
 923
 924                 if (rdev->flags & RADEON_IS_MOBILITY) {
 925                         /* A temporal workaround for the occasional blanking on certain laptop panels.
 926                            This appears to related to the PLL divider registers (fail to lock?).
 927                            It occurs even when all dividers are the same with their old settings.
 928                            In this case we really don't need to fiddle with PLL registers.
 929                            By doing this we can avoid the blanking problem with some panels.
 930                         */
 931                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 932                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 933                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 934                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 935                                          RADEON_PLL_DIV_SEL,
 936                                          ~(RADEON_PLL_DIV_SEL));
 937                                 r100_pll_errata_after_index(rdev);
 938                                 return;
 939                         }
 940                 }
 941
 942                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 943                              RADEON_VCLK_SRC_SEL_CPUCLK,
 944                              ~(RADEON_VCLK_SRC_SEL_MASK));
 945                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 946                              RADEON_PPLL_RESET
 947                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 948                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 949                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 950                              ~(RADEON_PPLL_RESET
 951                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 952                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 953                                | RADEON_PPLL_PVG_MASK));
 954
 955                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 956                          RADEON_PLL_DIV_SEL,
 957                          ~(RADEON_PLL_DIV_SEL));
 958                 r100_pll_errata_after_index(rdev);
 959
 960                 if (ASIC_IS_R300(rdev) ||
 961                     (rdev->family == CHIP_RS300) ||
 962                     (rdev->family == CHIP_RS400) ||
 963                     (rdev->family == CHIP_RS480)) {
 964                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 965                                 /* When restoring console mode, use saved PPLL_REF_DIV
 966                                  * setting.
 967                                  */
 968                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 969                                              pll_ref_div,
 970                                              0);
 971                         } else {
 972                                 /* R300 uses ref_div_acc field as real ref divider */
 973                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 974                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 975                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 976                         }
 977                 } else
 978                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 979                                      pll_ref_div,
 980                                      ~RADEON_PPLL_REF_DIV_MASK);
 981
 982                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 983                              pll_fb_post_div,
 984                              ~RADEON_PPLL_FB3_DIV_MASK);
 985
 986                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 987                              pll_fb_post_div,
 988                              ~RADEON_PPLL_POST3_DIV_MASK);
 989
 990                 radeon_pll_write_update(dev);
 991                 radeon_pll_wait_for_read_update_complete(dev);
 992
 993                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 994
 995                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 996                              0,
 997                              ~(RADEON_PPLL_RESET
 998                                | RADEON_PPLL_SLEEP
 999                                | RADEON_PPLL_ATOMIC_UPDATE_EN
1000                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1001
1002                 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1003                           pll_ref_div,
1004                           pll_fb_post_div,
1005                           (unsigned)htotal_cntl,
1006                           RREG32_PLL(RADEON_PPLL_CNTL));
1007                 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
1008                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1009                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1010                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1011
1012                 mdelay(50); /* Let the clock to lock */
1013
1014                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1015                              RADEON_VCLK_SRC_SEL_PPLLCLK,
1016                              ~(RADEON_VCLK_SRC_SEL_MASK));
1017
1018                 if (is_tv)
1019                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1020         }
1021 }
1022
1023 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1024                                    const struct drm_display_mode *mode,
1025                                    struct drm_display_mode *adjusted_mode)
1026 {
1027         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1028                 return false;
1029         return true;
1030 }
1031
1032 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1033                                  struct drm_display_mode *mode,
1034                                  struct drm_display_mode *adjusted_mode,
1035                                  int x, int y, struct drm_framebuffer *old_fb)
1036 {
1037         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1038
1039         /* TODO TV */
1040         radeon_crtc_set_base(crtc, x, y, old_fb);
1041         radeon_set_crtc_timing(crtc, adjusted_mode);
1042         radeon_set_pll(crtc, adjusted_mode);
1043         radeon_overscan_setup(crtc, adjusted_mode);
1044         if (radeon_crtc->crtc_id == 0) {
1045                 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1046         } else {
1047                 if (radeon_crtc->rmx_type != RMX_OFF) {
1048                         /* FIXME: only first crtc has rmx what should we
1049                          * do ?
1050                          */
1051                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1052                 }
1053         }
1054         radeon_cursor_reset(crtc);
1055         return 0;
1056 }
1057
1058 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1059 {
1060         struct drm_device *dev = crtc->dev;
1061         struct drm_crtc *crtci;
1062
1063         /*
1064         * The hardware wedges sometimes if you reconfigure one CRTC
1065         * whilst another is running (see fdo bug #24611).
1066         */
1067         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1068                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1069 }
1070
1071 static void radeon_crtc_commit(struct drm_crtc *crtc)
1072 {
1073         struct drm_device *dev = crtc->dev;
1074         struct drm_crtc *crtci;
1075
1076         /*
1077         * Reenable the CRTCs that should be running.
1078         */
1079         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1080                 if (crtci->enabled)
1081                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1082         }
1083 }
1084
1085 static void radeon_crtc_disable(struct drm_crtc *crtc)
1086 {
1087         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1088         if (crtc->primary->fb) {
1089                 int r;
1090                 struct radeon_bo *rbo;
1091
1092                 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]);
1093                 r = radeon_bo_reserve(rbo, false);
1094                 if (unlikely(r))
1095                         DRM_ERROR("failed to reserve rbo before unpin\n");
1096                 else {
1097                         radeon_bo_unpin(rbo);
1098                         radeon_bo_unreserve(rbo);
1099                 }
1100         }
1101 }
1102
1103 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1104         .dpms = radeon_crtc_dpms,
1105         .mode_fixup = radeon_crtc_mode_fixup,
1106         .mode_set = radeon_crtc_mode_set,
1107         .mode_set_base = radeon_crtc_set_base,
1108         .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1109         .prepare = radeon_crtc_prepare,
1110         .commit = radeon_crtc_commit,
1111         .disable = radeon_crtc_disable
1112 };
1113
1114
1115 void radeon_legacy_init_crtc(struct drm_device *dev,
1116                                struct radeon_crtc *radeon_crtc)
1117 {
1118         if (radeon_crtc->crtc_id == 1)
1119                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1120         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1121 }