2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
37 * radeon_driver_unload_kms - Main unload function for KMS.
39 * @dev: drm dev pointer
41 * This is the main unload function for KMS (all asics).
42 * It calls radeon_modeset_fini() to tear down the
43 * displays, and radeon_device_fini() to tear down
44 * the rest of the device (CP, writeback, etc.).
45 * Returns 0 on success.
47 int radeon_driver_unload_kms(struct drm_device *dev)
49 struct radeon_device *rdev = dev->dev_private;
53 if (rdev->rmmio == NULL)
55 radeon_acpi_fini(rdev);
56 radeon_modeset_fini(rdev);
57 radeon_device_fini(rdev);
61 dev->dev_private = NULL;
66 * radeon_driver_load_kms - Main load function for KMS.
68 * @dev: drm dev pointer
69 * @flags: device flags
71 * This is the main load function for KMS (all asics).
72 * It calls radeon_device_init() to set up the non-display
73 * parts of the chip (asic init, CP, writeback, etc.), and
74 * radeon_modeset_init() to set up the display parts
75 * (crtcs, encoders, hotplug detect, etc.).
76 * Returns 0 on success, error on failure.
78 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
80 struct radeon_device *rdev;
83 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
87 dev->dev_private = (void *)rdev;
90 if (drm_pci_device_is_agp(dev)) {
91 flags |= RADEON_IS_AGP;
92 } else if (pci_is_pcie(dev->pdev)) {
93 flags |= RADEON_IS_PCIE;
95 flags |= RADEON_IS_PCI;
98 /* radeon_device_init should report only fatal error
99 * like memory allocation failure or iomapping failure,
100 * or memory manager initialization failure, it must
101 * properly initialize the GPU MC controller and permit
104 r = radeon_device_init(rdev, dev, dev->pdev, flags);
106 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
110 /* Again modeset_init should fail only on fatal error
111 * otherwise it should provide enough functionalities
112 * for shadowfb to run
114 r = radeon_modeset_init(rdev);
116 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
118 /* Call ACPI methods: require modeset init
119 * but failure is not fatal
122 acpi_status = radeon_acpi_init(rdev);
124 dev_dbg(&dev->pdev->dev,
125 "Error during ACPI methods call\n");
130 radeon_driver_unload_kms(dev);
135 * radeon_set_filp_rights - Set filp right.
137 * @dev: drm dev pointer
142 * Sets the filp rights for the device (all asics).
144 static void radeon_set_filp_rights(struct drm_device *dev,
145 struct drm_file **owner,
146 struct drm_file *applier,
149 mutex_lock(&dev->struct_mutex);
154 } else if (*value == 0) {
156 if (*owner == applier)
159 *value = *owner == applier ? 1 : 0;
160 mutex_unlock(&dev->struct_mutex);
164 * Userspace get information ioctl
167 * radeon_info_ioctl - answer a device specific request.
169 * @rdev: radeon device pointer
170 * @data: request object
173 * This function is used to pass device specific parameters to the userspace
174 * drivers. Examples include: pci device id, pipeline parms, tiling params,
176 * Returns 0 on success, -EINVAL on failure.
178 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
180 struct radeon_device *rdev = dev->dev_private;
181 struct drm_radeon_info *info = data;
182 struct radeon_mode_info *minfo = &rdev->mode_info;
183 uint32_t *value, value_tmp, *value_ptr, value_size;
185 struct drm_crtc *crtc;
188 value_ptr = (uint32_t *)((unsigned long)info->value);
190 value_size = sizeof(uint32_t);
192 switch (info->request) {
193 case RADEON_INFO_DEVICE_ID:
194 *value = dev->pci_device;
196 case RADEON_INFO_NUM_GB_PIPES:
197 *value = rdev->num_gb_pipes;
199 case RADEON_INFO_NUM_Z_PIPES:
200 *value = rdev->num_z_pipes;
202 case RADEON_INFO_ACCEL_WORKING:
203 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
204 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
207 *value = rdev->accel_working;
209 case RADEON_INFO_CRTC_FROM_ID:
210 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
211 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
214 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
215 crtc = (struct drm_crtc *)minfo->crtcs[i];
216 if (crtc && crtc->base.id == *value) {
217 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
218 *value = radeon_crtc->crtc_id;
224 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
228 case RADEON_INFO_ACCEL_WORKING2:
229 *value = rdev->accel_working;
231 case RADEON_INFO_TILING_CONFIG:
232 if (rdev->family >= CHIP_BONAIRE)
233 *value = rdev->config.cik.tile_config;
234 else if (rdev->family >= CHIP_TAHITI)
235 *value = rdev->config.si.tile_config;
236 else if (rdev->family >= CHIP_CAYMAN)
237 *value = rdev->config.cayman.tile_config;
238 else if (rdev->family >= CHIP_CEDAR)
239 *value = rdev->config.evergreen.tile_config;
240 else if (rdev->family >= CHIP_RV770)
241 *value = rdev->config.rv770.tile_config;
242 else if (rdev->family >= CHIP_R600)
243 *value = rdev->config.r600.tile_config;
245 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
249 case RADEON_INFO_WANT_HYPERZ:
250 /* The "value" here is both an input and output parameter.
251 * If the input value is 1, filp requests hyper-z access.
252 * If the input value is 0, filp revokes its hyper-z access.
254 * When returning, the value is 1 if filp owns hyper-z access,
256 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
257 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
261 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
264 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
266 case RADEON_INFO_WANT_CMASK:
267 /* The same logic as Hyper-Z. */
268 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
269 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
273 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
276 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
278 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
279 /* return clock value in KHz */
280 if (rdev->asic->get_xclk)
281 *value = radeon_get_xclk(rdev) * 10;
283 *value = rdev->clock.spll.reference_freq * 10;
285 case RADEON_INFO_NUM_BACKENDS:
286 if (rdev->family >= CHIP_BONAIRE)
287 *value = rdev->config.cik.max_backends_per_se *
288 rdev->config.cik.max_shader_engines;
289 else if (rdev->family >= CHIP_TAHITI)
290 *value = rdev->config.si.max_backends_per_se *
291 rdev->config.si.max_shader_engines;
292 else if (rdev->family >= CHIP_CAYMAN)
293 *value = rdev->config.cayman.max_backends_per_se *
294 rdev->config.cayman.max_shader_engines;
295 else if (rdev->family >= CHIP_CEDAR)
296 *value = rdev->config.evergreen.max_backends;
297 else if (rdev->family >= CHIP_RV770)
298 *value = rdev->config.rv770.max_backends;
299 else if (rdev->family >= CHIP_R600)
300 *value = rdev->config.r600.max_backends;
305 case RADEON_INFO_NUM_TILE_PIPES:
306 if (rdev->family >= CHIP_BONAIRE)
307 *value = rdev->config.cik.max_tile_pipes;
308 else if (rdev->family >= CHIP_TAHITI)
309 *value = rdev->config.si.max_tile_pipes;
310 else if (rdev->family >= CHIP_CAYMAN)
311 *value = rdev->config.cayman.max_tile_pipes;
312 else if (rdev->family >= CHIP_CEDAR)
313 *value = rdev->config.evergreen.max_tile_pipes;
314 else if (rdev->family >= CHIP_RV770)
315 *value = rdev->config.rv770.max_tile_pipes;
316 else if (rdev->family >= CHIP_R600)
317 *value = rdev->config.r600.max_tile_pipes;
322 case RADEON_INFO_FUSION_GART_WORKING:
325 case RADEON_INFO_BACKEND_MAP:
326 if (rdev->family >= CHIP_BONAIRE)
328 else if (rdev->family >= CHIP_TAHITI)
329 *value = rdev->config.si.backend_map;
330 else if (rdev->family >= CHIP_CAYMAN)
331 *value = rdev->config.cayman.backend_map;
332 else if (rdev->family >= CHIP_CEDAR)
333 *value = rdev->config.evergreen.backend_map;
334 else if (rdev->family >= CHIP_RV770)
335 *value = rdev->config.rv770.backend_map;
336 else if (rdev->family >= CHIP_R600)
337 *value = rdev->config.r600.backend_map;
342 case RADEON_INFO_VA_START:
343 /* this is where we report if vm is supported or not */
344 if (rdev->family < CHIP_CAYMAN)
346 *value = RADEON_VA_RESERVED_SIZE;
348 case RADEON_INFO_IB_VM_MAX_SIZE:
349 /* this is where we report if vm is supported or not */
350 if (rdev->family < CHIP_CAYMAN)
352 *value = RADEON_IB_VM_MAX_SIZE;
354 case RADEON_INFO_MAX_PIPES:
355 if (rdev->family >= CHIP_BONAIRE)
356 *value = rdev->config.cik.max_cu_per_sh;
357 else if (rdev->family >= CHIP_TAHITI)
358 *value = rdev->config.si.max_cu_per_sh;
359 else if (rdev->family >= CHIP_CAYMAN)
360 *value = rdev->config.cayman.max_pipes_per_simd;
361 else if (rdev->family >= CHIP_CEDAR)
362 *value = rdev->config.evergreen.max_pipes;
363 else if (rdev->family >= CHIP_RV770)
364 *value = rdev->config.rv770.max_pipes;
365 else if (rdev->family >= CHIP_R600)
366 *value = rdev->config.r600.max_pipes;
371 case RADEON_INFO_TIMESTAMP:
372 if (rdev->family < CHIP_R600) {
373 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
376 value = (uint32_t*)&value64;
377 value_size = sizeof(uint64_t);
378 value64 = radeon_get_gpu_clock_counter(rdev);
380 case RADEON_INFO_MAX_SE:
381 if (rdev->family >= CHIP_BONAIRE)
382 *value = rdev->config.cik.max_shader_engines;
383 else if (rdev->family >= CHIP_TAHITI)
384 *value = rdev->config.si.max_shader_engines;
385 else if (rdev->family >= CHIP_CAYMAN)
386 *value = rdev->config.cayman.max_shader_engines;
387 else if (rdev->family >= CHIP_CEDAR)
388 *value = rdev->config.evergreen.num_ses;
392 case RADEON_INFO_MAX_SH_PER_SE:
393 if (rdev->family >= CHIP_BONAIRE)
394 *value = rdev->config.cik.max_sh_per_se;
395 else if (rdev->family >= CHIP_TAHITI)
396 *value = rdev->config.si.max_sh_per_se;
400 case RADEON_INFO_FASTFB_WORKING:
401 *value = rdev->fastfb_working;
403 case RADEON_INFO_RING_WORKING:
404 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
405 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
409 case RADEON_CS_RING_GFX:
410 case RADEON_CS_RING_COMPUTE:
411 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
413 case RADEON_CS_RING_DMA:
414 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
415 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
417 case RADEON_CS_RING_UVD:
418 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
424 case RADEON_INFO_SI_TILE_MODE_ARRAY:
425 if (rdev->family >= CHIP_BONAIRE) {
426 value = rdev->config.cik.tile_mode_array;
427 value_size = sizeof(uint32_t)*32;
428 } else if (rdev->family >= CHIP_TAHITI) {
429 value = rdev->config.si.tile_mode_array;
430 value_size = sizeof(uint32_t)*32;
432 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
436 case RADEON_INFO_SI_CP_DMA_COMPUTE:
439 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
440 if (rdev->family >= CHIP_BONAIRE) {
441 *value = rdev->config.cik.backend_enable_mask;
442 } else if (rdev->family >= CHIP_TAHITI) {
443 *value = rdev->config.si.backend_enable_mask;
445 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
449 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
452 if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) {
453 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
461 * Outdated mess for old drm with Xorg being in charge (void function now).
464 * radeon_driver_firstopen_kms - drm callback for last close
466 * @dev: drm dev pointer
468 * Switch vga switcheroo state after last close (all asics).
470 void radeon_driver_lastclose_kms(struct drm_device *dev)
472 vga_switcheroo_process_delayed_switch();
476 * radeon_driver_open_kms - drm callback for open
478 * @dev: drm dev pointer
479 * @file_priv: drm file
481 * On device open, init vm on cayman+ (all asics).
482 * Returns 0 on success, error on failure.
484 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
486 struct radeon_device *rdev = dev->dev_private;
488 file_priv->driver_priv = NULL;
490 /* new gpu have virtual address space support */
491 if (rdev->family >= CHIP_CAYMAN) {
492 struct radeon_fpriv *fpriv;
493 struct radeon_bo_va *bo_va;
496 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
497 if (unlikely(!fpriv)) {
501 radeon_vm_init(rdev, &fpriv->vm);
503 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
507 /* map the ib pool buffer read only into
508 * virtual address space */
509 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
510 rdev->ring_tmp_bo.bo);
511 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
512 RADEON_VM_PAGE_READABLE |
513 RADEON_VM_PAGE_SNOOPED);
515 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
517 radeon_vm_fini(rdev, &fpriv->vm);
522 file_priv->driver_priv = fpriv;
528 * radeon_driver_postclose_kms - drm callback for post close
530 * @dev: drm dev pointer
531 * @file_priv: drm file
533 * On device post close, tear down vm on cayman+ (all asics).
535 void radeon_driver_postclose_kms(struct drm_device *dev,
536 struct drm_file *file_priv)
538 struct radeon_device *rdev = dev->dev_private;
540 /* new gpu have virtual address space support */
541 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
542 struct radeon_fpriv *fpriv = file_priv->driver_priv;
543 struct radeon_bo_va *bo_va;
546 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
548 bo_va = radeon_vm_bo_find(&fpriv->vm,
549 rdev->ring_tmp_bo.bo);
551 radeon_vm_bo_rmv(rdev, bo_va);
552 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
555 radeon_vm_fini(rdev, &fpriv->vm);
557 file_priv->driver_priv = NULL;
562 * radeon_driver_preclose_kms - drm callback for pre close
564 * @dev: drm dev pointer
565 * @file_priv: drm file
567 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
570 void radeon_driver_preclose_kms(struct drm_device *dev,
571 struct drm_file *file_priv)
573 struct radeon_device *rdev = dev->dev_private;
574 if (rdev->hyperz_filp == file_priv)
575 rdev->hyperz_filp = NULL;
576 if (rdev->cmask_filp == file_priv)
577 rdev->cmask_filp = NULL;
578 radeon_uvd_free_handles(rdev, file_priv);
582 * VBlank related functions.
585 * radeon_get_vblank_counter_kms - get frame count
587 * @dev: drm dev pointer
588 * @crtc: crtc to get the frame count from
590 * Gets the frame count on the requested crtc (all asics).
591 * Returns frame count on success, -EINVAL on failure.
593 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
595 struct radeon_device *rdev = dev->dev_private;
597 if (crtc < 0 || crtc >= rdev->num_crtc) {
598 DRM_ERROR("Invalid crtc %d\n", crtc);
602 return radeon_get_vblank_counter(rdev, crtc);
606 * radeon_enable_vblank_kms - enable vblank interrupt
608 * @dev: drm dev pointer
609 * @crtc: crtc to enable vblank interrupt for
611 * Enable the interrupt on the requested crtc (all asics).
612 * Returns 0 on success, -EINVAL on failure.
614 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
616 struct radeon_device *rdev = dev->dev_private;
617 unsigned long irqflags;
620 if (crtc < 0 || crtc >= rdev->num_crtc) {
621 DRM_ERROR("Invalid crtc %d\n", crtc);
625 spin_lock_irqsave(&rdev->irq.lock, irqflags);
626 rdev->irq.crtc_vblank_int[crtc] = true;
627 r = radeon_irq_set(rdev);
628 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
633 * radeon_disable_vblank_kms - disable vblank interrupt
635 * @dev: drm dev pointer
636 * @crtc: crtc to disable vblank interrupt for
638 * Disable the interrupt on the requested crtc (all asics).
640 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
642 struct radeon_device *rdev = dev->dev_private;
643 unsigned long irqflags;
645 if (crtc < 0 || crtc >= rdev->num_crtc) {
646 DRM_ERROR("Invalid crtc %d\n", crtc);
650 spin_lock_irqsave(&rdev->irq.lock, irqflags);
651 rdev->irq.crtc_vblank_int[crtc] = false;
652 radeon_irq_set(rdev);
653 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
657 * radeon_get_vblank_timestamp_kms - get vblank timestamp
659 * @dev: drm dev pointer
660 * @crtc: crtc to get the timestamp for
661 * @max_error: max error
662 * @vblank_time: time value
663 * @flags: flags passed to the driver
665 * Gets the timestamp on the requested crtc based on the
666 * scanout position. (all asics).
667 * Returns postive status flags on success, negative error on failure.
669 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
671 struct timeval *vblank_time,
674 struct drm_crtc *drmcrtc;
675 struct radeon_device *rdev = dev->dev_private;
677 if (crtc < 0 || crtc >= dev->num_crtcs) {
678 DRM_ERROR("Invalid crtc %d\n", crtc);
682 /* Get associated drm_crtc: */
683 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
685 /* Helper routine in DRM core does all the work: */
686 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
691 #define KMS_INVALID_IOCTL(name) \
692 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
694 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
699 * All these ioctls are invalid in kms world.
701 KMS_INVALID_IOCTL(radeon_cp_init_kms)
702 KMS_INVALID_IOCTL(radeon_cp_start_kms)
703 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
704 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
705 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
706 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
707 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
708 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
709 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
710 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
711 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
712 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
713 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
714 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
715 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
716 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
717 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
718 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
719 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
720 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
721 KMS_INVALID_IOCTL(radeon_mem_free_kms)
722 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
723 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
724 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
725 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
726 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
727 KMS_INVALID_IOCTL(radeon_surface_free_kms)
730 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
731 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
732 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
733 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
734 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
735 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
736 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
737 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
738 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
739 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
740 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
741 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
742 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
743 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
744 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
745 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
746 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
747 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
748 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
749 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
750 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
751 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
752 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
753 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
754 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
755 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
756 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
757 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
759 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
760 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
761 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
762 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
763 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
764 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
765 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
766 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
767 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
768 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
769 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
770 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
771 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
773 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);