drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset, size;
  73         int i, num_indices;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  79                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  80
  81                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  82                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  83
  84                 for (i = 0; i < num_indices; i++) {
  85                         gpio = &i2c_info->asGPIO_Info[i];
  86
  87                         if (gpio->sucI2cId.ucAccess == id) {
  88                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  89                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  90                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  91                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  92                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  93                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  94                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  95                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  96                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  97                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  98                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  99                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 100                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 101                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 102                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 103                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 104
 105                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 106                                         i2c.hw_capable = true;
 107                                 else
 108                                         i2c.hw_capable = false;
 109
 110                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 111                                         i2c.mm_i2c = true;
 112                                 else
 113                                         i2c.mm_i2c = false;
 114
 115                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 116
 117                                 i2c.valid = true;
 118                                 break;
 119                         }
 120                 }
 121         }
 122
 123         return i2c;
 124 }
 125
 126 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 127                                                         u8 id)
 128 {
 129         struct atom_context *ctx = rdev->mode_info.atom_context;
 130         struct radeon_gpio_rec gpio;
 131         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 132         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 133         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 134         u16 data_offset, size;
 135         int i, num_indices;
 136
 137         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 138         gpio.valid = false;
 139
 140         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 141                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 142
 143                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 144                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 145
 146                 for (i = 0; i < num_indices; i++) {
 147                         pin = &gpio_info->asGPIO_Pin[i];
 148                         if (id == pin->ucGPIO_ID) {
 149                                 gpio.id = pin->ucGPIO_ID;
 150                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 151                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 152                                 gpio.valid = true;
 153                                 break;
 154                         }
 155                 }
 156         }
 157
 158         return gpio;
 159 }
 160
 161 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 162                                                             struct radeon_gpio_rec *gpio)
 163 {
 164         struct radeon_hpd hpd;
 165         u32 reg;
 166
 167         if (ASIC_IS_DCE4(rdev))
 168                 reg = EVERGREEN_DC_GPIO_HPD_A;
 169         else
 170                 reg = AVIVO_DC_GPIO_HPD_A;
 171
 172         hpd.gpio = *gpio;
 173         if (gpio->reg == reg) {
 174                 switch(gpio->mask) {
 175                 case (1 << 0):
 176                         hpd.hpd = RADEON_HPD_1;
 177                         break;
 178                 case (1 << 8):
 179                         hpd.hpd = RADEON_HPD_2;
 180                         break;
 181                 case (1 << 16):
 182                         hpd.hpd = RADEON_HPD_3;
 183                         break;
 184                 case (1 << 24):
 185                         hpd.hpd = RADEON_HPD_4;
 186                         break;
 187                 case (1 << 26):
 188                         hpd.hpd = RADEON_HPD_5;
 189                         break;
 190                 case (1 << 28):
 191                         hpd.hpd = RADEON_HPD_6;
 192                         break;
 193                 default:
 194                         hpd.hpd = RADEON_HPD_NONE;
 195                         break;
 196                 }
 197         } else
 198                 hpd.hpd = RADEON_HPD_NONE;
 199         return hpd;
 200 }
 201
 202 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 203                                      uint32_t supported_device,
 204                                      int *connector_type,
 205                                      struct radeon_i2c_bus_rec *i2c_bus,
 206                                      uint16_t *line_mux,
 207                                      struct radeon_hpd *hpd)
 208 {
 209
 210         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 211         if ((dev->pdev->device == 0x791e) &&
 212             (dev->pdev->subsystem_vendor == 0x1043) &&
 213             (dev->pdev->subsystem_device == 0x826d)) {
 214                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 215                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 216                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 217         }
 218
 219         /* Asrock RS600 board lists the DVI port as HDMI */
 220         if ((dev->pdev->device == 0x7941) &&
 221             (dev->pdev->subsystem_vendor == 0x1849) &&
 222             (dev->pdev->subsystem_device == 0x7941)) {
 223                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 224                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 225                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 226         }
 227
 228         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 229         if ((dev->pdev->device == 0x7941) &&
 230             (dev->pdev->subsystem_vendor == 0x147b) &&
 231             (dev->pdev->subsystem_device == 0x2412)) {
 232                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 233                         return false;
 234         }
 235
 236         /* Falcon NW laptop lists vga ddc line for LVDS */
 237         if ((dev->pdev->device == 0x5653) &&
 238             (dev->pdev->subsystem_vendor == 0x1462) &&
 239             (dev->pdev->subsystem_device == 0x0291)) {
 240                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 241                         i2c_bus->valid = false;
 242                         *line_mux = 53;
 243                 }
 244         }
 245
 246         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 247         if ((dev->pdev->device == 0x7146) &&
 248             (dev->pdev->subsystem_vendor == 0x17af) &&
 249             (dev->pdev->subsystem_device == 0x2058)) {
 250                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 251                         return false;
 252         }
 253
 254         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 255         if ((dev->pdev->device == 0x7142) &&
 256             (dev->pdev->subsystem_vendor == 0x1458) &&
 257             (dev->pdev->subsystem_device == 0x2134)) {
 258                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 259                         return false;
 260         }
 261
 262
 263         /* Funky macbooks */
 264         if ((dev->pdev->device == 0x71C5) &&
 265             (dev->pdev->subsystem_vendor == 0x106b) &&
 266             (dev->pdev->subsystem_device == 0x0080)) {
 267                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 268                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 269                         return false;
 270                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 271                         *line_mux = 0x90;
 272         }
 273
 274         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 275         if ((dev->pdev->device == 0x9598) &&
 276             (dev->pdev->subsystem_vendor == 0x1043) &&
 277             (dev->pdev->subsystem_device == 0x01da)) {
 278                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 279                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 280                 }
 281         }
 282
 283         /* ASUS HD 3600 board lists the DVI port as HDMI */
 284         if ((dev->pdev->device == 0x9598) &&
 285             (dev->pdev->subsystem_vendor == 0x1043) &&
 286             (dev->pdev->subsystem_device == 0x01e4)) {
 287                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 288                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 289                 }
 290         }
 291
 292         /* ASUS HD 3450 board lists the DVI port as HDMI */
 293         if ((dev->pdev->device == 0x95C5) &&
 294             (dev->pdev->subsystem_vendor == 0x1043) &&
 295             (dev->pdev->subsystem_device == 0x01e2)) {
 296                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 297                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 298                 }
 299         }
 300
 301         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 302          * HDMI + VGA reporting as HDMI
 303          */
 304         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 305                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 306                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 307                         *line_mux = 0;
 308                 }
 309         }
 310
 311         /* Acer laptop reports DVI-D as DVI-I */
 312         if ((dev->pdev->device == 0x95c4) &&
 313             (dev->pdev->subsystem_vendor == 0x1025) &&
 314             (dev->pdev->subsystem_device == 0x013c)) {
 315                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 316                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 317                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 318         }
 319
 320         /* XFX Pine Group device rv730 reports no VGA DDC lines
 321          * even though they are wired up to record 0x93
 322          */
 323         if ((dev->pdev->device == 0x9498) &&
 324             (dev->pdev->subsystem_vendor == 0x1682) &&
 325             (dev->pdev->subsystem_device == 0x2452)) {
 326                 struct radeon_device *rdev = dev->dev_private;
 327                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 328         }
 329         return true;
 330 }
 331
 332 const int supported_devices_connector_convert[] = {
 333         DRM_MODE_CONNECTOR_Unknown,
 334         DRM_MODE_CONNECTOR_VGA,
 335         DRM_MODE_CONNECTOR_DVII,
 336         DRM_MODE_CONNECTOR_DVID,
 337         DRM_MODE_CONNECTOR_DVIA,
 338         DRM_MODE_CONNECTOR_SVIDEO,
 339         DRM_MODE_CONNECTOR_Composite,
 340         DRM_MODE_CONNECTOR_LVDS,
 341         DRM_MODE_CONNECTOR_Unknown,
 342         DRM_MODE_CONNECTOR_Unknown,
 343         DRM_MODE_CONNECTOR_HDMIA,
 344         DRM_MODE_CONNECTOR_HDMIB,
 345         DRM_MODE_CONNECTOR_Unknown,
 346         DRM_MODE_CONNECTOR_Unknown,
 347         DRM_MODE_CONNECTOR_9PinDIN,
 348         DRM_MODE_CONNECTOR_DisplayPort
 349 };
 350
 351 const uint16_t supported_devices_connector_object_id_convert[] = {
 352         CONNECTOR_OBJECT_ID_NONE,
 353         CONNECTOR_OBJECT_ID_VGA,
 354         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 355         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 356         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 357         CONNECTOR_OBJECT_ID_COMPOSITE,
 358         CONNECTOR_OBJECT_ID_SVIDEO,
 359         CONNECTOR_OBJECT_ID_LVDS,
 360         CONNECTOR_OBJECT_ID_9PIN_DIN,
 361         CONNECTOR_OBJECT_ID_9PIN_DIN,
 362         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 363         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 364         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 365         CONNECTOR_OBJECT_ID_SVIDEO
 366 };
 367
 368 const int object_connector_convert[] = {
 369         DRM_MODE_CONNECTOR_Unknown,
 370         DRM_MODE_CONNECTOR_DVII,
 371         DRM_MODE_CONNECTOR_DVII,
 372         DRM_MODE_CONNECTOR_DVID,
 373         DRM_MODE_CONNECTOR_DVID,
 374         DRM_MODE_CONNECTOR_VGA,
 375         DRM_MODE_CONNECTOR_Composite,
 376         DRM_MODE_CONNECTOR_SVIDEO,
 377         DRM_MODE_CONNECTOR_Unknown,
 378         DRM_MODE_CONNECTOR_Unknown,
 379         DRM_MODE_CONNECTOR_9PinDIN,
 380         DRM_MODE_CONNECTOR_Unknown,
 381         DRM_MODE_CONNECTOR_HDMIA,
 382         DRM_MODE_CONNECTOR_HDMIB,
 383         DRM_MODE_CONNECTOR_LVDS,
 384         DRM_MODE_CONNECTOR_9PinDIN,
 385         DRM_MODE_CONNECTOR_Unknown,
 386         DRM_MODE_CONNECTOR_Unknown,
 387         DRM_MODE_CONNECTOR_Unknown,
 388         DRM_MODE_CONNECTOR_DisplayPort,
 389         DRM_MODE_CONNECTOR_eDP,
 390         DRM_MODE_CONNECTOR_Unknown
 391 };
 392
 393 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 394 {
 395         struct radeon_device *rdev = dev->dev_private;
 396         struct radeon_mode_info *mode_info = &rdev->mode_info;
 397         struct atom_context *ctx = mode_info->atom_context;
 398         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 399         u16 size, data_offset;
 400         u8 frev, crev;
 401         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 402         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 403         ATOM_OBJECT_HEADER *obj_header;
 404         int i, j, path_size, device_support;
 405         int connector_type;
 406         u16 igp_lane_info, conn_id, connector_object_id;
 407         bool linkb;
 408         struct radeon_i2c_bus_rec ddc_bus;
 409         struct radeon_gpio_rec gpio;
 410         struct radeon_hpd hpd;
 411
 412         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 413                 return false;
 414
 415         if (crev < 2)
 416                 return false;
 417
 418         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 419         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 420             (ctx->bios + data_offset +
 421              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 422         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 423             (ctx->bios + data_offset +
 424              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 425         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 426
 427         path_size = 0;
 428         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 429                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 430                 ATOM_DISPLAY_OBJECT_PATH *path;
 431                 addr += path_size;
 432                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 433                 path_size += le16_to_cpu(path->usSize);
 434                 linkb = false;
 435                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 436                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 437
 438                         con_obj_id =
 439                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 440                             >> OBJECT_ID_SHIFT;
 441                         con_obj_num =
 442                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 443                             >> ENUM_ID_SHIFT;
 444                         con_obj_type =
 445                             (le16_to_cpu(path->usConnObjectId) &
 446                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 447
 448                         /* TODO CV support */
 449                         if (le16_to_cpu(path->usDeviceTag) ==
 450                                 ATOM_DEVICE_CV_SUPPORT)
 451                                 continue;
 452
 453                         /* IGP chips */
 454                         if ((rdev->flags & RADEON_IS_IGP) &&
 455                             (con_obj_id ==
 456                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 457                                 uint16_t igp_offset = 0;
 458                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 459
 460                                 index =
 461                                     GetIndexIntoMasterTable(DATA,
 462                                                             IntegratedSystemInfo);
 463
 464                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 465                                                            &crev, &igp_offset)) {
 466
 467                                         if (crev >= 2) {
 468                                                 igp_obj =
 469                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 470                                                          *) (ctx->bios + igp_offset);
 471
 472                                                 if (igp_obj) {
 473                                                         uint32_t slot_config, ct;
 474
 475                                                         if (con_obj_num == 1)
 476                                                                 slot_config =
 477                                                                         igp_obj->
 478                                                                         ulDDISlot1Config;
 479                                                         else
 480                                                                 slot_config =
 481                                                                         igp_obj->
 482                                                                         ulDDISlot2Config;
 483
 484                                                         ct = (slot_config >> 16) & 0xff;
 485                                                         connector_type =
 486                                                                 object_connector_convert
 487                                                                 [ct];
 488                                                         connector_object_id = ct;
 489                                                         igp_lane_info =
 490                                                                 slot_config & 0xffff;
 491                                                 } else
 492                                                         continue;
 493                                         } else
 494                                                 continue;
 495                                 } else {
 496                                         igp_lane_info = 0;
 497                                         connector_type =
 498                                                 object_connector_convert[con_obj_id];
 499                                         connector_object_id = con_obj_id;
 500                                 }
 501                         } else {
 502                                 igp_lane_info = 0;
 503                                 connector_type =
 504                                     object_connector_convert[con_obj_id];
 505                                 connector_object_id = con_obj_id;
 506                         }
 507
 508                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 509                                 continue;
 510
 511                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 512                              j++) {
 513                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 514
 515                                 enc_obj_id =
 516                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 517                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 518                                 enc_obj_num =
 519                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 520                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 521                                 enc_obj_type =
 522                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 523                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 524
 525                                 /* FIXME: add support for router objects */
 526                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 527                                         if (enc_obj_num == 2)
 528                                                 linkb = true;
 529                                         else
 530                                                 linkb = false;
 531
 532                                         radeon_add_atom_encoder(dev,
 533                                                                 enc_obj_id,
 534                                                                 le16_to_cpu
 535                                                                 (path->
 536                                                                  usDeviceTag));
 537
 538                                 }
 539                         }
 540
 541                         /* look up gpio for ddc, hpd */
 542                         ddc_bus.valid = false;
 543                         hpd.hpd = RADEON_HPD_NONE;
 544                         if ((le16_to_cpu(path->usDeviceTag) &
 545                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 546                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 547                                         if (le16_to_cpu(path->usConnObjectId) ==
 548                                             le16_to_cpu(con_obj->asObjects[j].
 549                                                         usObjectID)) {
 550                                                 ATOM_COMMON_RECORD_HEADER
 551                                                     *record =
 552                                                     (ATOM_COMMON_RECORD_HEADER
 553                                                      *)
 554                                                     (ctx->bios + data_offset +
 555                                                      le16_to_cpu(con_obj->
 556                                                                  asObjects[j].
 557                                                                  usRecordOffset));
 558                                                 ATOM_I2C_RECORD *i2c_record;
 559                                                 ATOM_HPD_INT_RECORD *hpd_record;
 560                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 561                                                 hpd.hpd = RADEON_HPD_NONE;
 562
 563                                                 while (record->ucRecordType > 0
 564                                                        && record->
 565                                                        ucRecordType <=
 566                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 567                                                         switch (record->ucRecordType) {
 568                                                         case ATOM_I2C_RECORD_TYPE:
 569                                                                 i2c_record =
 570                                                                     (ATOM_I2C_RECORD *)
 571                                                                         record;
 572                                                                 i2c_config =
 573                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 574                                                                         &i2c_record->sucI2cId;
 575                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 576                                                                                                  i2c_config->
 577                                                                                                  ucAccess);
 578                                                                 break;
 579                                                         case ATOM_HPD_INT_RECORD_TYPE:
 580                                                                 hpd_record =
 581                                                                         (ATOM_HPD_INT_RECORD *)
 582                                                                         record;
 583                                                                 gpio = radeon_lookup_gpio(rdev,
 584                                                                                           hpd_record->ucHPDIntGPIOID);
 585                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 586                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 587                                                                 break;
 588                                                         }
 589                                                         record =
 590                                                             (ATOM_COMMON_RECORD_HEADER
 591                                                              *) ((char *)record
 592                                                                  +
 593                                                                  record->
 594                                                                  ucRecordSize);
 595                                                 }
 596                                                 break;
 597                                         }
 598                                 }
 599                         }
 600
 601                         /* needed for aux chan transactions */
 602                         ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
 603
 604                         conn_id = le16_to_cpu(path->usConnObjectId);
 605
 606                         if (!radeon_atom_apply_quirks
 607                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 608                              &ddc_bus, &conn_id, &hpd))
 609                                 continue;
 610
 611                         radeon_add_atom_connector(dev,
 612                                                   conn_id,
 613                                                   le16_to_cpu(path->
 614                                                               usDeviceTag),
 615                                                   connector_type, &ddc_bus,
 616                                                   linkb, igp_lane_info,
 617                                                   connector_object_id,
 618                                                   &hpd);
 619
 620                 }
 621         }
 622
 623         radeon_link_encoder_connector(dev);
 624
 625         return true;
 626 }
 627
 628 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 629                                                  int connector_type,
 630                                                  uint16_t devices)
 631 {
 632         struct radeon_device *rdev = dev->dev_private;
 633
 634         if (rdev->flags & RADEON_IS_IGP) {
 635                 return supported_devices_connector_object_id_convert
 636                         [connector_type];
 637         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 638                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 639                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 640                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 641                 struct atom_context *ctx = mode_info->atom_context;
 642                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 643                 uint16_t size, data_offset;
 644                 uint8_t frev, crev;
 645                 ATOM_XTMDS_INFO *xtmds;
 646
 647                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 648                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 649
 650                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 651                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 652                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 653                                 else
 654                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 655                         } else {
 656                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 657                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 658                                 else
 659                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 660                         }
 661                 } else
 662                         return supported_devices_connector_object_id_convert
 663                                 [connector_type];
 664         } else {
 665                 return supported_devices_connector_object_id_convert
 666                         [connector_type];
 667         }
 668 }
 669
 670 struct bios_connector {
 671         bool valid;
 672         uint16_t line_mux;
 673         uint16_t devices;
 674         int connector_type;
 675         struct radeon_i2c_bus_rec ddc_bus;
 676         struct radeon_hpd hpd;
 677 };
 678
 679 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 680                                                                  drm_device
 681                                                                  *dev)
 682 {
 683         struct radeon_device *rdev = dev->dev_private;
 684         struct radeon_mode_info *mode_info = &rdev->mode_info;
 685         struct atom_context *ctx = mode_info->atom_context;
 686         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 687         uint16_t size, data_offset;
 688         uint8_t frev, crev;
 689         uint16_t device_support;
 690         uint8_t dac;
 691         union atom_supported_devices *supported_devices;
 692         int i, j, max_device;
 693         struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
 694
 695         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 696                 return false;
 697
 698         supported_devices =
 699             (union atom_supported_devices *)(ctx->bios + data_offset);
 700
 701         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 702
 703         if (frev > 1)
 704                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 705         else
 706                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 707
 708         for (i = 0; i < max_device; i++) {
 709                 ATOM_CONNECTOR_INFO_I2C ci =
 710                     supported_devices->info.asConnInfo[i];
 711
 712                 bios_connectors[i].valid = false;
 713
 714                 if (!(device_support & (1 << i))) {
 715                         continue;
 716                 }
 717
 718                 if (i == ATOM_DEVICE_CV_INDEX) {
 719                         DRM_DEBUG("Skipping Component Video\n");
 720                         continue;
 721                 }
 722
 723                 bios_connectors[i].connector_type =
 724                     supported_devices_connector_convert[ci.sucConnectorInfo.
 725                                                         sbfAccess.
 726                                                         bfConnectorType];
 727
 728                 if (bios_connectors[i].connector_type ==
 729                     DRM_MODE_CONNECTOR_Unknown)
 730                         continue;
 731
 732                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 733
 734                 bios_connectors[i].line_mux =
 735                         ci.sucI2cId.ucAccess;
 736
 737                 /* give tv unique connector ids */
 738                 if (i == ATOM_DEVICE_TV1_INDEX) {
 739                         bios_connectors[i].ddc_bus.valid = false;
 740                         bios_connectors[i].line_mux = 50;
 741                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 742                         bios_connectors[i].ddc_bus.valid = false;
 743                         bios_connectors[i].line_mux = 51;
 744                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 745                         bios_connectors[i].ddc_bus.valid = false;
 746                         bios_connectors[i].line_mux = 52;
 747                 } else
 748                         bios_connectors[i].ddc_bus =
 749                             radeon_lookup_i2c_gpio(rdev,
 750                                                    bios_connectors[i].line_mux);
 751
 752                 if ((crev > 1) && (frev > 1)) {
 753                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 754                         switch (isb) {
 755                         case 0x4:
 756                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 757                                 break;
 758                         case 0xa:
 759                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 760                                 break;
 761                         default:
 762                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 763                                 break;
 764                         }
 765                 } else {
 766                         if (i == ATOM_DEVICE_DFP1_INDEX)
 767                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 768                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 769                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 770                         else
 771                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 772                 }
 773
 774                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 775                  * shared with a DVI port, we'll pick up the DVI connector when we
 776                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 777                  */
 778                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 779                         bios_connectors[i].connector_type =
 780                             DRM_MODE_CONNECTOR_VGA;
 781
 782                 if (!radeon_atom_apply_quirks
 783                     (dev, (1 << i), &bios_connectors[i].connector_type,
 784                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 785                      &bios_connectors[i].hpd))
 786                         continue;
 787
 788                 bios_connectors[i].valid = true;
 789                 bios_connectors[i].devices = (1 << i);
 790
 791                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 792                         radeon_add_atom_encoder(dev,
 793                                                 radeon_get_encoder_id(dev,
 794                                                                       (1 << i),
 795                                                                       dac),
 796                                                 (1 << i));
 797                 else
 798                         radeon_add_legacy_encoder(dev,
 799                                                   radeon_get_encoder_id(dev,
 800                                                                         (1 << i),
 801                                                                         dac),
 802                                                   (1 << i));
 803         }
 804
 805         /* combine shared connectors */
 806         for (i = 0; i < max_device; i++) {
 807                 if (bios_connectors[i].valid) {
 808                         for (j = 0; j < max_device; j++) {
 809                                 if (bios_connectors[j].valid && (i != j)) {
 810                                         if (bios_connectors[i].line_mux ==
 811                                             bios_connectors[j].line_mux) {
 812                                                 /* make sure not to combine LVDS */
 813                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 814                                                         bios_connectors[i].line_mux = 53;
 815                                                         bios_connectors[i].ddc_bus.valid = false;
 816                                                         continue;
 817                                                 }
 818                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 819                                                         bios_connectors[j].line_mux = 53;
 820                                                         bios_connectors[j].ddc_bus.valid = false;
 821                                                         continue;
 822                                                 }
 823                                                 /* combine analog and digital for DVI-I */
 824                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 825                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 826                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 827                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 828                                                         bios_connectors[i].devices |=
 829                                                                 bios_connectors[j].devices;
 830                                                         bios_connectors[i].connector_type =
 831                                                                 DRM_MODE_CONNECTOR_DVII;
 832                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 833                                                                 bios_connectors[i].hpd =
 834                                                                         bios_connectors[j].hpd;
 835                                                         bios_connectors[j].valid = false;
 836                                                 }
 837                                         }
 838                                 }
 839                         }
 840                 }
 841         }
 842
 843         /* add the connectors */
 844         for (i = 0; i < max_device; i++) {
 845                 if (bios_connectors[i].valid) {
 846                         uint16_t connector_object_id =
 847                                 atombios_get_connector_object_id(dev,
 848                                                       bios_connectors[i].connector_type,
 849                                                       bios_connectors[i].devices);
 850                         radeon_add_atom_connector(dev,
 851                                                   bios_connectors[i].line_mux,
 852                                                   bios_connectors[i].devices,
 853                                                   bios_connectors[i].
 854                                                   connector_type,
 855                                                   &bios_connectors[i].ddc_bus,
 856                                                   false, 0,
 857                                                   connector_object_id,
 858                                                   &bios_connectors[i].hpd);
 859                 }
 860         }
 861
 862         radeon_link_encoder_connector(dev);
 863
 864         return true;
 865 }
 866
 867 union firmware_info {
 868         ATOM_FIRMWARE_INFO info;
 869         ATOM_FIRMWARE_INFO_V1_2 info_12;
 870         ATOM_FIRMWARE_INFO_V1_3 info_13;
 871         ATOM_FIRMWARE_INFO_V1_4 info_14;
 872         ATOM_FIRMWARE_INFO_V2_1 info_21;
 873 };
 874
 875 bool radeon_atom_get_clock_info(struct drm_device *dev)
 876 {
 877         struct radeon_device *rdev = dev->dev_private;
 878         struct radeon_mode_info *mode_info = &rdev->mode_info;
 879         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 880         union firmware_info *firmware_info;
 881         uint8_t frev, crev;
 882         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 883         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 884         struct radeon_pll *dcpll = &rdev->clock.dcpll;
 885         struct radeon_pll *spll = &rdev->clock.spll;
 886         struct radeon_pll *mpll = &rdev->clock.mpll;
 887         uint16_t data_offset;
 888
 889         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
 890                                    &frev, &crev, &data_offset)) {
 891                 firmware_info =
 892                         (union firmware_info *)(mode_info->atom_context->bios +
 893                                                 data_offset);
 894                 /* pixel clocks */
 895                 p1pll->reference_freq =
 896                     le16_to_cpu(firmware_info->info.usReferenceClock);
 897                 p1pll->reference_div = 0;
 898
 899                 if (crev < 2)
 900                         p1pll->pll_out_min =
 901                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 902                 else
 903                         p1pll->pll_out_min =
 904                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 905                 p1pll->pll_out_max =
 906                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 907
 908                 if (crev >= 4) {
 909                         p1pll->lcd_pll_out_min =
 910                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 911                         if (p1pll->lcd_pll_out_min == 0)
 912                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 913                         p1pll->lcd_pll_out_max =
 914                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 915                         if (p1pll->lcd_pll_out_max == 0)
 916                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 917                 } else {
 918                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 919                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 920                 }
 921
 922                 if (p1pll->pll_out_min == 0) {
 923                         if (ASIC_IS_AVIVO(rdev))
 924                                 p1pll->pll_out_min = 64800;
 925                         else
 926                                 p1pll->pll_out_min = 20000;
 927                 } else if (p1pll->pll_out_min > 64800) {
 928                         /* Limiting the pll output range is a good thing generally as
 929                          * it limits the number of possible pll combinations for a given
 930                          * frequency presumably to the ones that work best on each card.
 931                          * However, certain duallink DVI monitors seem to like
 932                          * pll combinations that would be limited by this at least on
 933                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 934                          * family.
 935                          */
 936                         if (!radeon_new_pll)
 937                                 p1pll->pll_out_min = 64800;
 938                 }
 939
 940                 p1pll->pll_in_min =
 941                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 942                 p1pll->pll_in_max =
 943                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 944
 945                 *p2pll = *p1pll;
 946
 947                 /* system clock */
 948                 spll->reference_freq =
 949                     le16_to_cpu(firmware_info->info.usReferenceClock);
 950                 spll->reference_div = 0;
 951
 952                 spll->pll_out_min =
 953                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 954                 spll->pll_out_max =
 955                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 956
 957                 /* ??? */
 958                 if (spll->pll_out_min == 0) {
 959                         if (ASIC_IS_AVIVO(rdev))
 960                                 spll->pll_out_min = 64800;
 961                         else
 962                                 spll->pll_out_min = 20000;
 963                 }
 964
 965                 spll->pll_in_min =
 966                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 967                 spll->pll_in_max =
 968                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 969
 970                 /* memory clock */
 971                 mpll->reference_freq =
 972                     le16_to_cpu(firmware_info->info.usReferenceClock);
 973                 mpll->reference_div = 0;
 974
 975                 mpll->pll_out_min =
 976                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 977                 mpll->pll_out_max =
 978                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 979
 980                 /* ??? */
 981                 if (mpll->pll_out_min == 0) {
 982                         if (ASIC_IS_AVIVO(rdev))
 983                                 mpll->pll_out_min = 64800;
 984                         else
 985                                 mpll->pll_out_min = 20000;
 986                 }
 987
 988                 mpll->pll_in_min =
 989                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 990                 mpll->pll_in_max =
 991                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 992
 993                 rdev->clock.default_sclk =
 994                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 995                 rdev->clock.default_mclk =
 996                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 997
 998                 if (ASIC_IS_DCE4(rdev)) {
 999                         rdev->clock.default_dispclk =
1000                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1001                         if (rdev->clock.default_dispclk == 0)
1002                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1003                         rdev->clock.dp_extclk =
1004                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1005                 }
1006                 *dcpll = *p1pll;
1007
1008                 return true;
1009         }
1010
1011         return false;
1012 }
1013
1014 union igp_info {
1015         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1016         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1017 };
1018
1019 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1020 {
1021         struct radeon_mode_info *mode_info = &rdev->mode_info;
1022         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1023         union igp_info *igp_info;
1024         u8 frev, crev;
1025         u16 data_offset;
1026
1027         /* sideport is AMD only */
1028         if (rdev->family == CHIP_RS600)
1029                 return false;
1030
1031         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1032                                    &frev, &crev, &data_offset)) {
1033                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1034                                       data_offset);
1035                 switch (crev) {
1036                 case 1:
1037                         if (igp_info->info.ulBootUpMemoryClock)
1038                                 return true;
1039                         break;
1040                 case 2:
1041                         if (igp_info->info_2.ucMemoryType & 0x0f)
1042                                 return true;
1043                         break;
1044                 default:
1045                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1046                         break;
1047                 }
1048         }
1049         return false;
1050 }
1051
1052 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1053                                    struct radeon_encoder_int_tmds *tmds)
1054 {
1055         struct drm_device *dev = encoder->base.dev;
1056         struct radeon_device *rdev = dev->dev_private;
1057         struct radeon_mode_info *mode_info = &rdev->mode_info;
1058         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1059         uint16_t data_offset;
1060         struct _ATOM_TMDS_INFO *tmds_info;
1061         uint8_t frev, crev;
1062         uint16_t maxfreq;
1063         int i;
1064
1065         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1066                                    &frev, &crev, &data_offset)) {
1067                 tmds_info =
1068                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1069                                                    data_offset);
1070
1071                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1072                 for (i = 0; i < 4; i++) {
1073                         tmds->tmds_pll[i].freq =
1074                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1075                         tmds->tmds_pll[i].value =
1076                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1077                         tmds->tmds_pll[i].value |=
1078                             (tmds_info->asMiscInfo[i].
1079                              ucPLL_VCO_Gain & 0x3f) << 6;
1080                         tmds->tmds_pll[i].value |=
1081                             (tmds_info->asMiscInfo[i].
1082                              ucPLL_DutyCycle & 0xf) << 12;
1083                         tmds->tmds_pll[i].value |=
1084                             (tmds_info->asMiscInfo[i].
1085                              ucPLL_VoltageSwing & 0xf) << 16;
1086
1087                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1088                                   tmds->tmds_pll[i].freq,
1089                                   tmds->tmds_pll[i].value);
1090
1091                         if (maxfreq == tmds->tmds_pll[i].freq) {
1092                                 tmds->tmds_pll[i].freq = 0xffffffff;
1093                                 break;
1094                         }
1095                 }
1096                 return true;
1097         }
1098         return false;
1099 }
1100
1101 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1102                                                           radeon_encoder
1103                                                           *encoder,
1104                                                           int id)
1105 {
1106         struct drm_device *dev = encoder->base.dev;
1107         struct radeon_device *rdev = dev->dev_private;
1108         struct radeon_mode_info *mode_info = &rdev->mode_info;
1109         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1110         uint16_t data_offset;
1111         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1112         uint8_t frev, crev;
1113         struct radeon_atom_ss *ss = NULL;
1114         int i;
1115
1116         if (id > ATOM_MAX_SS_ENTRY)
1117                 return NULL;
1118
1119         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1120                                    &frev, &crev, &data_offset)) {
1121                 ss_info =
1122                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1123
1124                 ss =
1125                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1126
1127                 if (!ss)
1128                         return NULL;
1129
1130                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1131                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1132                                 ss->percentage =
1133                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1134                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1135                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1136                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1137                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1138                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1139                                 break;
1140                         }
1141                 }
1142         }
1143         return ss;
1144 }
1145
1146 union lvds_info {
1147         struct _ATOM_LVDS_INFO info;
1148         struct _ATOM_LVDS_INFO_V12 info_12;
1149 };
1150
1151 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1152                                                               radeon_encoder
1153                                                               *encoder)
1154 {
1155         struct drm_device *dev = encoder->base.dev;
1156         struct radeon_device *rdev = dev->dev_private;
1157         struct radeon_mode_info *mode_info = &rdev->mode_info;
1158         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1159         uint16_t data_offset, misc;
1160         union lvds_info *lvds_info;
1161         uint8_t frev, crev;
1162         struct radeon_encoder_atom_dig *lvds = NULL;
1163
1164         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1165                                    &frev, &crev, &data_offset)) {
1166                 lvds_info =
1167                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1168                 lvds =
1169                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1170
1171                 if (!lvds)
1172                         return NULL;
1173
1174                 lvds->native_mode.clock =
1175                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1176                 lvds->native_mode.hdisplay =
1177                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1178                 lvds->native_mode.vdisplay =
1179                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1180                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1181                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1182                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1183                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1184                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1185                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1186                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1187                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1188                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1189                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1190                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1191                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1192                 lvds->panel_pwr_delay =
1193                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1194                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1195
1196                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1197                 if (misc & ATOM_VSYNC_POLARITY)
1198                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1199                 if (misc & ATOM_HSYNC_POLARITY)
1200                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1201                 if (misc & ATOM_COMPOSITESYNC)
1202                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1203                 if (misc & ATOM_INTERLACE)
1204                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1205                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1206                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1207
1208                 /* set crtc values */
1209                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1210
1211                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1212
1213                 if (ASIC_IS_AVIVO(rdev)) {
1214                         if (radeon_new_pll == 0)
1215                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1216                         else
1217                                 lvds->pll_algo = PLL_ALGO_NEW;
1218                 } else {
1219                         if (radeon_new_pll == 1)
1220                                 lvds->pll_algo = PLL_ALGO_NEW;
1221                         else
1222                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1223                 }
1224
1225                 encoder->native_mode = lvds->native_mode;
1226         }
1227         return lvds;
1228 }
1229
1230 struct radeon_encoder_primary_dac *
1231 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1232 {
1233         struct drm_device *dev = encoder->base.dev;
1234         struct radeon_device *rdev = dev->dev_private;
1235         struct radeon_mode_info *mode_info = &rdev->mode_info;
1236         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1237         uint16_t data_offset;
1238         struct _COMPASSIONATE_DATA *dac_info;
1239         uint8_t frev, crev;
1240         uint8_t bg, dac;
1241         struct radeon_encoder_primary_dac *p_dac = NULL;
1242
1243         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1244                                    &frev, &crev, &data_offset)) {
1245                 dac_info = (struct _COMPASSIONATE_DATA *)
1246                         (mode_info->atom_context->bios + data_offset);
1247
1248                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1249
1250                 if (!p_dac)
1251                         return NULL;
1252
1253                 bg = dac_info->ucDAC1_BG_Adjustment;
1254                 dac = dac_info->ucDAC1_DAC_Adjustment;
1255                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1256
1257         }
1258         return p_dac;
1259 }
1260
1261 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1262                                 struct drm_display_mode *mode)
1263 {
1264         struct radeon_mode_info *mode_info = &rdev->mode_info;
1265         ATOM_ANALOG_TV_INFO *tv_info;
1266         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1267         ATOM_DTD_FORMAT *dtd_timings;
1268         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1269         u8 frev, crev;
1270         u16 data_offset, misc;
1271
1272         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1273                                     &frev, &crev, &data_offset))
1274                 return false;
1275
1276         switch (crev) {
1277         case 1:
1278                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1279                 if (index >= MAX_SUPPORTED_TV_TIMING)
1280                         return false;
1281
1282                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1283                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1284                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1285                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1286                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1287
1288                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1289                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1290                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1291                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1292                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1293
1294                 mode->flags = 0;
1295                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1296                 if (misc & ATOM_VSYNC_POLARITY)
1297                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1298                 if (misc & ATOM_HSYNC_POLARITY)
1299                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1300                 if (misc & ATOM_COMPOSITESYNC)
1301                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1302                 if (misc & ATOM_INTERLACE)
1303                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1304                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1305                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1306
1307                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1308
1309                 if (index == 1) {
1310                         /* PAL timings appear to have wrong values for totals */
1311                         mode->crtc_htotal -= 1;
1312                         mode->crtc_vtotal -= 1;
1313                 }
1314                 break;
1315         case 2:
1316                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1317                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1318                         return false;
1319
1320                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1321                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1322                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1323                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1324                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1325                         le16_to_cpu(dtd_timings->usHSyncOffset);
1326                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1327                         le16_to_cpu(dtd_timings->usHSyncWidth);
1328
1329                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1330                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1331                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1332                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1333                         le16_to_cpu(dtd_timings->usVSyncOffset);
1334                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1335                         le16_to_cpu(dtd_timings->usVSyncWidth);
1336
1337                 mode->flags = 0;
1338                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1339                 if (misc & ATOM_VSYNC_POLARITY)
1340                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1341                 if (misc & ATOM_HSYNC_POLARITY)
1342                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1343                 if (misc & ATOM_COMPOSITESYNC)
1344                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1345                 if (misc & ATOM_INTERLACE)
1346                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1347                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1348                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1349
1350                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1351                 break;
1352         }
1353         return true;
1354 }
1355
1356 enum radeon_tv_std
1357 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1358 {
1359         struct radeon_mode_info *mode_info = &rdev->mode_info;
1360         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1361         uint16_t data_offset;
1362         uint8_t frev, crev;
1363         struct _ATOM_ANALOG_TV_INFO *tv_info;
1364         enum radeon_tv_std tv_std = TV_STD_NTSC;
1365
1366         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1367                                    &frev, &crev, &data_offset)) {
1368
1369                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1370                         (mode_info->atom_context->bios + data_offset);
1371
1372                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1373                 case ATOM_TV_NTSC:
1374                         tv_std = TV_STD_NTSC;
1375                         DRM_INFO("Default TV standard: NTSC\n");
1376                         break;
1377                 case ATOM_TV_NTSCJ:
1378                         tv_std = TV_STD_NTSC_J;
1379                         DRM_INFO("Default TV standard: NTSC-J\n");
1380                         break;
1381                 case ATOM_TV_PAL:
1382                         tv_std = TV_STD_PAL;
1383                         DRM_INFO("Default TV standard: PAL\n");
1384                         break;
1385                 case ATOM_TV_PALM:
1386                         tv_std = TV_STD_PAL_M;
1387                         DRM_INFO("Default TV standard: PAL-M\n");
1388                         break;
1389                 case ATOM_TV_PALN:
1390                         tv_std = TV_STD_PAL_N;
1391                         DRM_INFO("Default TV standard: PAL-N\n");
1392                         break;
1393                 case ATOM_TV_PALCN:
1394                         tv_std = TV_STD_PAL_CN;
1395                         DRM_INFO("Default TV standard: PAL-CN\n");
1396                         break;
1397                 case ATOM_TV_PAL60:
1398                         tv_std = TV_STD_PAL_60;
1399                         DRM_INFO("Default TV standard: PAL-60\n");
1400                         break;
1401                 case ATOM_TV_SECAM:
1402                         tv_std = TV_STD_SECAM;
1403                         DRM_INFO("Default TV standard: SECAM\n");
1404                         break;
1405                 default:
1406                         tv_std = TV_STD_NTSC;
1407                         DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1408                         break;
1409                 }
1410         }
1411         return tv_std;
1412 }
1413
1414 struct radeon_encoder_tv_dac *
1415 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1416 {
1417         struct drm_device *dev = encoder->base.dev;
1418         struct radeon_device *rdev = dev->dev_private;
1419         struct radeon_mode_info *mode_info = &rdev->mode_info;
1420         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1421         uint16_t data_offset;
1422         struct _COMPASSIONATE_DATA *dac_info;
1423         uint8_t frev, crev;
1424         uint8_t bg, dac;
1425         struct radeon_encoder_tv_dac *tv_dac = NULL;
1426
1427         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1428                                    &frev, &crev, &data_offset)) {
1429
1430                 dac_info = (struct _COMPASSIONATE_DATA *)
1431                         (mode_info->atom_context->bios + data_offset);
1432
1433                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1434
1435                 if (!tv_dac)
1436                         return NULL;
1437
1438                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1439                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1440                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1441
1442                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1443                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1444                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1445
1446                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1447                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1448                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1449
1450                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1451         }
1452         return tv_dac;
1453 }
1454
1455 static const char *thermal_controller_names[] = {
1456         "NONE",
1457         "LM63",
1458         "ADM1032",
1459         "ADM1030",
1460         "MUA6649",
1461         "LM64",
1462         "F75375",
1463         "ASC7512",
1464 };
1465
1466 static const char *pp_lib_thermal_controller_names[] = {
1467         "NONE",
1468         "LM63",
1469         "ADM1032",
1470         "ADM1030",
1471         "MUA6649",
1472         "LM64",
1473         "F75375",
1474         "RV6xx",
1475         "RV770",
1476         "ADT7473",
1477 };
1478
1479 union power_info {
1480         struct _ATOM_POWERPLAY_INFO info;
1481         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1482         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1483         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1484 };
1485
1486 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1487 {
1488         struct radeon_mode_info *mode_info = &rdev->mode_info;
1489         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1490         u16 data_offset;
1491         u8 frev, crev;
1492         u32 misc, misc2 = 0, sclk, mclk;
1493         union power_info *power_info;
1494         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1495         struct _ATOM_PPLIB_STATE *power_state;
1496         int num_modes = 0, i, j;
1497         int state_index = 0, mode_index = 0;
1498         struct radeon_i2c_bus_rec i2c_bus;
1499
1500         rdev->pm.default_power_state = NULL;
1501
1502         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1503                                    &frev, &crev, &data_offset)) {
1504                 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1505                 if (frev < 4) {
1506                         /* add the i2c bus for thermal/fan chip */
1507                         if (power_info->info.ucOverdriveThermalController > 0) {
1508                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1509                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1510                                          power_info->info.ucOverdriveControllerAddress >> 1);
1511                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1512                                 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1513                         }
1514                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1515                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1516                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1517                         for (i = 0; i < num_modes; i++) {
1518                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1519                                 switch (frev) {
1520                                 case 1:
1521                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1522                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1523                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1524                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1525                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1526                                         /* skip invalid modes */
1527                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1528                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1529                                                 continue;
1530                                         /* skip overclock modes for now */
1531                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1532                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1533                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1534                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1535                                                 continue;
1536                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1537                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1538                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1539                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1540                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1541                                                         VOLTAGE_GPIO;
1542                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1543                                                         radeon_lookup_gpio(rdev,
1544                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1545                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1546                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1547                                                                 true;
1548                                                 else
1549                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1550                                                                 false;
1551                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1552                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1553                                                         VOLTAGE_VDDC;
1554                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1555                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1556                                         }
1557                                         /* order matters! */
1558                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1559                                                 rdev->pm.power_state[state_index].type =
1560                                                         POWER_STATE_TYPE_POWERSAVE;
1561                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1562                                                 rdev->pm.power_state[state_index].type =
1563                                                         POWER_STATE_TYPE_BATTERY;
1564                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1565                                                 rdev->pm.power_state[state_index].type =
1566                                                         POWER_STATE_TYPE_BATTERY;
1567                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1568                                                 rdev->pm.power_state[state_index].type =
1569                                                         POWER_STATE_TYPE_BALANCED;
1570                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1571                                                 rdev->pm.power_state[state_index].type =
1572                                                         POWER_STATE_TYPE_PERFORMANCE;
1573                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1574                                                 rdev->pm.power_state[state_index].type =
1575                                                         POWER_STATE_TYPE_DEFAULT;
1576                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1577                                                 rdev->pm.power_state[state_index].default_clock_mode =
1578                                                         &rdev->pm.power_state[state_index].clock_info[0];
1579                                         }
1580                                         state_index++;
1581                                         break;
1582                                 case 2:
1583                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1584                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1585                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1586                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1587                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1588                                         /* skip invalid modes */
1589                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1590                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1591                                                 continue;
1592                                         /* skip overclock modes for now */
1593                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1594                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1595                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1596                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1597                                                 continue;
1598                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1599                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1600                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1601                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1602                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1603                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1604                                                         VOLTAGE_GPIO;
1605                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1606                                                         radeon_lookup_gpio(rdev,
1607                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1608                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1609                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1610                                                                 true;
1611                                                 else
1612                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1613                                                                 false;
1614                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1615                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1616                                                         VOLTAGE_VDDC;
1617                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1618                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1619                                         }
1620                                         /* order matters! */
1621                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1622                                                 rdev->pm.power_state[state_index].type =
1623                                                         POWER_STATE_TYPE_POWERSAVE;
1624                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1625                                                 rdev->pm.power_state[state_index].type =
1626                                                         POWER_STATE_TYPE_BATTERY;
1627                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1628                                                 rdev->pm.power_state[state_index].type =
1629                                                         POWER_STATE_TYPE_BATTERY;
1630                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1631                                                 rdev->pm.power_state[state_index].type =
1632                                                         POWER_STATE_TYPE_BALANCED;
1633                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1634                                                 rdev->pm.power_state[state_index].type =
1635                                                         POWER_STATE_TYPE_PERFORMANCE;
1636                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1637                                                 rdev->pm.power_state[state_index].type =
1638                                                         POWER_STATE_TYPE_BALANCED;
1639                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1640                                                 rdev->pm.power_state[state_index].type =
1641                                                         POWER_STATE_TYPE_DEFAULT;
1642                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1643                                                 rdev->pm.power_state[state_index].default_clock_mode =
1644                                                         &rdev->pm.power_state[state_index].clock_info[0];
1645                                         }
1646                                         state_index++;
1647                                         break;
1648                                 case 3:
1649                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1650                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1651                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1652                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1653                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1654                                         /* skip invalid modes */
1655                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1656                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1657                                                 continue;
1658                                         /* skip overclock modes for now */
1659                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1660                                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1661                                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
1662                                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1663                                                 continue;
1664                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1665                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1666                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1667                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1668                                         if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1669                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1670                                                         VOLTAGE_GPIO;
1671                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1672                                                         radeon_lookup_gpio(rdev,
1673                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1674                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1675                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1676                                                                 true;
1677                                                 else
1678                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1679                                                                 false;
1680                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1681                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1682                                                         VOLTAGE_VDDC;
1683                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1684                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1685                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1686                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1687                                                                 true;
1688                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1689                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1690                                                 }
1691                                         }
1692                                         /* order matters! */
1693                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1694                                                 rdev->pm.power_state[state_index].type =
1695                                                         POWER_STATE_TYPE_POWERSAVE;
1696                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1697                                                 rdev->pm.power_state[state_index].type =
1698                                                         POWER_STATE_TYPE_BATTERY;
1699                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1700                                                 rdev->pm.power_state[state_index].type =
1701                                                         POWER_STATE_TYPE_BATTERY;
1702                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1703                                                 rdev->pm.power_state[state_index].type =
1704                                                         POWER_STATE_TYPE_BALANCED;
1705                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1706                                                 rdev->pm.power_state[state_index].type =
1707                                                         POWER_STATE_TYPE_PERFORMANCE;
1708                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1709                                                 rdev->pm.power_state[state_index].type =
1710                                                         POWER_STATE_TYPE_BALANCED;
1711                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1712                                                 rdev->pm.power_state[state_index].type =
1713                                                         POWER_STATE_TYPE_DEFAULT;
1714                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1715                                                 rdev->pm.power_state[state_index].default_clock_mode =
1716                                                         &rdev->pm.power_state[state_index].clock_info[0];
1717                                         }
1718                                         state_index++;
1719                                         break;
1720                                 }
1721                         }
1722                 } else if (frev == 4) {
1723                         /* add the i2c bus for thermal/fan chip */
1724                         /* no support for internal controller yet */
1725                         if (power_info->info_4.sThermalController.ucType > 0) {
1726                                 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1727                                     (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
1728                                         DRM_INFO("Internal thermal controller %s fan control\n",
1729                                                  (power_info->info_4.sThermalController.ucFanParameters &
1730                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1731                                 } else {
1732                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1733                                                  pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1734                                                  power_info->info_4.sThermalController.ucI2cAddress >> 1,
1735                                                  (power_info->info_4.sThermalController.ucFanParameters &
1736                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1737                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1738                                         rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1739                                 }
1740                         }
1741                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1742                                 mode_index = 0;
1743                                 power_state = (struct _ATOM_PPLIB_STATE *)
1744                                         (mode_info->atom_context->bios +
1745                                          data_offset +
1746                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1747                                          i * power_info->info_4.ucStateEntrySize);
1748                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1749                                         (mode_info->atom_context->bios +
1750                                          data_offset +
1751                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1752                                          (power_state->ucNonClockStateIndex *
1753                                           power_info->info_4.ucNonClockSize));
1754                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1755                                         if (rdev->flags & RADEON_IS_IGP) {
1756                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1757                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1758                                                         (mode_info->atom_context->bios +
1759                                                          data_offset +
1760                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1761                                                          (power_state->ucClockStateIndices[j] *
1762                                                           power_info->info_4.ucClockInfoSize));
1763                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1764                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
1765                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1766                                                 /* skip invalid modes */
1767                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1768                                                         continue;
1769                                                 /* skip overclock modes for now */
1770                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1771                                                     rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1772                                                         continue;
1773                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1774                                                         VOLTAGE_SW;
1775                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1776                                                         clock_info->usVDDC;
1777                                                 mode_index++;
1778                                         } else {
1779                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1780                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1781                                                         (mode_info->atom_context->bios +
1782                                                          data_offset +
1783                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1784                                                          (power_state->ucClockStateIndices[j] *
1785                                                           power_info->info_4.ucClockInfoSize));
1786                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1787                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1788                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1789                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1790                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1791                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1792                                                 /* skip invalid modes */
1793                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1794                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1795                                                         continue;
1796                                                 /* skip overclock modes for now */
1797                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1798                                                      rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1799                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1800                                                      rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1801                                                         continue;
1802                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1803                                                         VOLTAGE_SW;
1804                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1805                                                         clock_info->usVDDC;
1806                                                 mode_index++;
1807                                         }
1808                                 }
1809                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1810                                 if (mode_index) {
1811                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1812                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
1813                                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1814                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1815                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1816                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1817                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1818                                                 rdev->pm.power_state[state_index].type =
1819                                                         POWER_STATE_TYPE_BATTERY;
1820                                                 break;
1821                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1822                                                 rdev->pm.power_state[state_index].type =
1823                                                         POWER_STATE_TYPE_BALANCED;
1824                                                 break;
1825                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1826                                                 rdev->pm.power_state[state_index].type =
1827                                                         POWER_STATE_TYPE_PERFORMANCE;
1828                                                 break;
1829                                         }
1830                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1831                                                 rdev->pm.power_state[state_index].type =
1832                                                         POWER_STATE_TYPE_DEFAULT;
1833                                                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1834                                                 rdev->pm.power_state[state_index].default_clock_mode =
1835                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1836                                         }
1837                                         state_index++;
1838                                 }
1839                         }
1840                 }
1841         } else {
1842                 /* XXX figure out some good default low power mode for cards w/out power tables */
1843         }
1844
1845         if (rdev->pm.default_power_state == NULL) {
1846                 /* add the default mode */
1847                 rdev->pm.power_state[state_index].type =
1848                         POWER_STATE_TYPE_DEFAULT;
1849                 rdev->pm.power_state[state_index].num_clock_modes = 1;
1850                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1851                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1852                 rdev->pm.power_state[state_index].default_clock_mode =
1853                         &rdev->pm.power_state[state_index].clock_info[0];
1854                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1855                 if (rdev->asic->get_pcie_lanes)
1856                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1857                 else
1858                         rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1859                 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1860                 state_index++;
1861         }
1862         rdev->pm.num_power_states = state_index;
1863
1864         rdev->pm.current_power_state = rdev->pm.default_power_state;
1865         rdev->pm.current_clock_mode =
1866                 rdev->pm.default_power_state->default_clock_mode;
1867 }
1868
1869 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1870 {
1871         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1872         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1873
1874         args.ucEnable = enable;
1875
1876         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1877 }
1878
1879 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1880 {
1881         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1882         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1883
1884         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1885         return args.ulReturnEngineClock;
1886 }
1887
1888 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1889 {
1890         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1891         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1892
1893         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1894         return args.ulReturnMemoryClock;
1895 }
1896
1897 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1898                                   uint32_t eng_clock)
1899 {
1900         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1901         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1902
1903         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
1904
1905         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1906 }
1907
1908 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1909                                   uint32_t mem_clock)
1910 {
1911         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1912         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1913
1914         if (rdev->flags & RADEON_IS_IGP)
1915                 return;
1916
1917         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
1918
1919         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1920 }
1921
1922 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1923 {
1924         struct radeon_device *rdev = dev->dev_private;
1925         uint32_t bios_2_scratch, bios_6_scratch;
1926
1927         if (rdev->family >= CHIP_R600) {
1928                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1929                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1930         } else {
1931                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1932                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1933         }
1934
1935         /* let the bios control the backlight */
1936         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1937
1938         /* tell the bios not to handle mode switching */
1939         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1940
1941         if (rdev->family >= CHIP_R600) {
1942                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1943                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1944         } else {
1945                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1946                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1947         }
1948
1949 }
1950
1951 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1952 {
1953         uint32_t scratch_reg;
1954         int i;
1955
1956         if (rdev->family >= CHIP_R600)
1957                 scratch_reg = R600_BIOS_0_SCRATCH;
1958         else
1959                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1960
1961         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1962                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1963 }
1964
1965 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1966 {
1967         uint32_t scratch_reg;
1968         int i;
1969
1970         if (rdev->family >= CHIP_R600)
1971                 scratch_reg = R600_BIOS_0_SCRATCH;
1972         else
1973                 scratch_reg = RADEON_BIOS_0_SCRATCH;
1974
1975         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1976                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1977 }
1978
1979 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1980 {
1981         struct drm_device *dev = encoder->dev;
1982         struct radeon_device *rdev = dev->dev_private;
1983         uint32_t bios_6_scratch;
1984
1985         if (rdev->family >= CHIP_R600)
1986                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1987         else
1988                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1989
1990         if (lock)
1991                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1992         else
1993                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1994
1995         if (rdev->family >= CHIP_R600)
1996                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1997         else
1998                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1999 }
2000
2001 /* at some point we may want to break this out into individual functions */
2002 void
2003 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2004                                        struct drm_encoder *encoder,
2005                                        bool connected)
2006 {
2007         struct drm_device *dev = connector->dev;
2008         struct radeon_device *rdev = dev->dev_private;
2009         struct radeon_connector *radeon_connector =
2010             to_radeon_connector(connector);
2011         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2012         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2013
2014         if (rdev->family >= CHIP_R600) {
2015                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2016                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2017                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2018         } else {
2019                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2020                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2021                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2022         }
2023
2024         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2025             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2026                 if (connected) {
2027                         DRM_DEBUG("TV1 connected\n");
2028                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2029                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2030                 } else {
2031                         DRM_DEBUG("TV1 disconnected\n");
2032                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2033                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2034                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2035                 }
2036         }
2037         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2038             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2039                 if (connected) {
2040                         DRM_DEBUG("CV connected\n");
2041                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2042                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2043                 } else {
2044                         DRM_DEBUG("CV disconnected\n");
2045                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2046                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2047                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2048                 }
2049         }
2050         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2051             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2052                 if (connected) {
2053                         DRM_DEBUG("LCD1 connected\n");
2054                         bios_0_scratch |= ATOM_S0_LCD1;
2055                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2056                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2057                 } else {
2058                         DRM_DEBUG("LCD1 disconnected\n");
2059                         bios_0_scratch &= ~ATOM_S0_LCD1;
2060                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2061                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2062                 }
2063         }
2064         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2065             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2066                 if (connected) {
2067                         DRM_DEBUG("CRT1 connected\n");
2068                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2069                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2070                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2071                 } else {
2072                         DRM_DEBUG("CRT1 disconnected\n");
2073                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2074                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2075                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2076                 }
2077         }
2078         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2079             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2080                 if (connected) {
2081                         DRM_DEBUG("CRT2 connected\n");
2082                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2083                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2084                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2085                 } else {
2086                         DRM_DEBUG("CRT2 disconnected\n");
2087                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2088                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2089                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2090                 }
2091         }
2092         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2093             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2094                 if (connected) {
2095                         DRM_DEBUG("DFP1 connected\n");
2096                         bios_0_scratch |= ATOM_S0_DFP1;
2097                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2098                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2099                 } else {
2100                         DRM_DEBUG("DFP1 disconnected\n");
2101                         bios_0_scratch &= ~ATOM_S0_DFP1;
2102                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2103                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2104                 }
2105         }
2106         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2107             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2108                 if (connected) {
2109                         DRM_DEBUG("DFP2 connected\n");
2110                         bios_0_scratch |= ATOM_S0_DFP2;
2111                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2112                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2113                 } else {
2114                         DRM_DEBUG("DFP2 disconnected\n");
2115                         bios_0_scratch &= ~ATOM_S0_DFP2;
2116                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2117                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2118                 }
2119         }
2120         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2121             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2122                 if (connected) {
2123                         DRM_DEBUG("DFP3 connected\n");
2124                         bios_0_scratch |= ATOM_S0_DFP3;
2125                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2126                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2127                 } else {
2128                         DRM_DEBUG("DFP3 disconnected\n");
2129                         bios_0_scratch &= ~ATOM_S0_DFP3;
2130                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2131                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2132                 }
2133         }
2134         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2135             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2136                 if (connected) {
2137                         DRM_DEBUG("DFP4 connected\n");
2138                         bios_0_scratch |= ATOM_S0_DFP4;
2139                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2140                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2141                 } else {
2142                         DRM_DEBUG("DFP4 disconnected\n");
2143                         bios_0_scratch &= ~ATOM_S0_DFP4;
2144                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2145                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2146                 }
2147         }
2148         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2149             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2150                 if (connected) {
2151                         DRM_DEBUG("DFP5 connected\n");
2152                         bios_0_scratch |= ATOM_S0_DFP5;
2153                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2154                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2155                 } else {
2156                         DRM_DEBUG("DFP5 disconnected\n");
2157                         bios_0_scratch &= ~ATOM_S0_DFP5;
2158                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2159                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2160                 }
2161         }
2162
2163         if (rdev->family >= CHIP_R600) {
2164                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2165                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2166                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2167         } else {
2168                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2169                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2170                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2171         }
2172 }
2173
2174 void
2175 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2176 {
2177         struct drm_device *dev = encoder->dev;
2178         struct radeon_device *rdev = dev->dev_private;
2179         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2180         uint32_t bios_3_scratch;
2181
2182         if (rdev->family >= CHIP_R600)
2183                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2184         else
2185                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2186
2187         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2188                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2189                 bios_3_scratch |= (crtc << 18);
2190         }
2191         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2192                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2193                 bios_3_scratch |= (crtc << 24);
2194         }
2195         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2196                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2197                 bios_3_scratch |= (crtc << 16);
2198         }
2199         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2200                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2201                 bios_3_scratch |= (crtc << 20);
2202         }
2203         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2204                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2205                 bios_3_scratch |= (crtc << 17);
2206         }
2207         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2208                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2209                 bios_3_scratch |= (crtc << 19);
2210         }
2211         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2212                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2213                 bios_3_scratch |= (crtc << 23);
2214         }
2215         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2216                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2217                 bios_3_scratch |= (crtc << 25);
2218         }
2219
2220         if (rdev->family >= CHIP_R600)
2221                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2222         else
2223                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2224 }
2225
2226 void
2227 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2228 {
2229         struct drm_device *dev = encoder->dev;
2230         struct radeon_device *rdev = dev->dev_private;
2231         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2232         uint32_t bios_2_scratch;
2233
2234         if (rdev->family >= CHIP_R600)
2235                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2236         else
2237                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2238
2239         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2240                 if (on)
2241                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2242                 else
2243                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2244         }
2245         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2246                 if (on)
2247                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2248                 else
2249                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2250         }
2251         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2252                 if (on)
2253                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2254                 else
2255                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2256         }
2257         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2258                 if (on)
2259                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2260                 else
2261                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2262         }
2263         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2264                 if (on)
2265                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2266                 else
2267                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2268         }
2269         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2270                 if (on)
2271                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2272                 else
2273                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2274         }
2275         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2276                 if (on)
2277                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2278                 else
2279                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2280         }
2281         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2282                 if (on)
2283                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2284                 else
2285                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2286         }
2287         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2288                 if (on)
2289                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2290                 else
2291                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2292         }
2293         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2294                 if (on)
2295                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2296                 else
2297                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2298         }
2299
2300         if (rdev->family >= CHIP_R600)
2301                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2302         else
2303                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2304 }