drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/module.h>
  32 #include <drm/drmP.h>
  33 #include <drm/radeon_drm.h>
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_audio.h"
  37 #include "radeon_mode.h"
  38 #include "r600d.h"
  39 #include "atom.h"
  40 #include "avivod.h"
  41 #include "radeon_ucode.h"
  42
  43 /* Firmware Names */
  44 /*(DEBLOBBED)*/
  45
  46 static const u32 crtc_offsets[2] =
  47 {
  48         0,
  49         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  50 };
  51
  52 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  53
  54 /* r600,rv610,rv630,rv620,rv635,rv670 */
  55 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  56 static void r600_gpu_init(struct radeon_device *rdev);
  57 void r600_fini(struct radeon_device *rdev);
  58 void r600_irq_disable(struct radeon_device *rdev);
  59 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
  60 extern int evergreen_rlc_resume(struct radeon_device *rdev);
  61 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
  62
  63 /*
  64  * Indirect registers accessor
  65  */
  66 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
  67 {
  68         unsigned long flags;
  69         u32 r;
  70
  71         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
  72         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
  73         r = RREG32(R600_RCU_DATA);
  74         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
  75         return r;
  76 }
  77
  78 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  79 {
  80         unsigned long flags;
  81
  82         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
  83         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
  84         WREG32(R600_RCU_DATA, (v));
  85         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
  86 }
  87
  88 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
  89 {
  90         unsigned long flags;
  91         u32 r;
  92
  93         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
  94         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
  95         r = RREG32(R600_UVD_CTX_DATA);
  96         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
  97         return r;
  98 }
  99
 100 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 101 {
 102         unsigned long flags;
 103
 104         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
 105         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
 106         WREG32(R600_UVD_CTX_DATA, (v));
 107         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
 108 }
 109
 110 /**
 111  * r600_get_allowed_info_register - fetch the register for the info ioctl
 112  *
 113  * @rdev: radeon_device pointer
 114  * @reg: register offset in bytes
 115  * @val: register value
 116  *
 117  * Returns 0 for success or -EINVAL for an invalid register
 118  *
 119  */
 120 int r600_get_allowed_info_register(struct radeon_device *rdev,
 121                                    u32 reg, u32 *val)
 122 {
 123         switch (reg) {
 124         case GRBM_STATUS:
 125         case GRBM_STATUS2:
 126         case R_000E50_SRBM_STATUS:
 127         case DMA_STATUS_REG:
 128         case UVD_STATUS:
 129                 *val = RREG32(reg);
 130                 return 0;
 131         default:
 132                 return -EINVAL;
 133         }
 134 }
 135
 136 /**
 137  * r600_get_xclk - get the xclk
 138  *
 139  * @rdev: radeon_device pointer
 140  *
 141  * Returns the reference clock used by the gfx engine
 142  * (r6xx, IGPs, APUs).
 143  */
 144 u32 r600_get_xclk(struct radeon_device *rdev)
 145 {
 146         return rdev->clock.spll.reference_freq;
 147 }
 148
 149 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 150 {
 151         unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
 152         int r;
 153
 154         /* bypass vclk and dclk with bclk */
 155         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 156                  VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
 157                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 158
 159         /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
 160         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
 161                  UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
 162
 163         if (rdev->family >= CHIP_RS780)
 164                 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
 165                          ~UPLL_BYPASS_CNTL);
 166
 167         if (!vclk || !dclk) {
 168                 /* keep the Bypass mode, put PLL to sleep */
 169                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
 170                 return 0;
 171         }
 172
 173         if (rdev->clock.spll.reference_freq == 10000)
 174                 ref_div = 34;
 175         else
 176                 ref_div = 4;
 177
 178         r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
 179                                           ref_div + 1, 0xFFF, 2, 30, ~0,
 180                                           &fb_div, &vclk_div, &dclk_div);
 181         if (r)
 182                 return r;
 183
 184         if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
 185                 fb_div >>= 1;
 186         else
 187                 fb_div |= 1;
 188
 189         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 190         if (r)
 191                 return r;
 192
 193         /* assert PLL_RESET */
 194         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
 195
 196         /* For RS780 we have to choose ref clk */
 197         if (rdev->family >= CHIP_RS780)
 198                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
 199                          ~UPLL_REFCLK_SRC_SEL_MASK);
 200
 201         /* set the required fb, ref and post divder values */
 202         WREG32_P(CG_UPLL_FUNC_CNTL,
 203                  UPLL_FB_DIV(fb_div) |
 204                  UPLL_REF_DIV(ref_div),
 205                  ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
 206         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 207                  UPLL_SW_HILEN(vclk_div >> 1) |
 208                  UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
 209                  UPLL_SW_HILEN2(dclk_div >> 1) |
 210                  UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
 211                  UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
 212                  ~UPLL_SW_MASK);
 213
 214         /* give the PLL some time to settle */
 215         mdelay(15);
 216
 217         /* deassert PLL_RESET */
 218         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 219
 220         mdelay(15);
 221
 222         /* deassert BYPASS EN */
 223         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 224
 225         if (rdev->family >= CHIP_RS780)
 226                 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
 227
 228         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 229         if (r)
 230                 return r;
 231
 232         /* switch VCLK and DCLK selection */
 233         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 234                  VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
 235                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 236
 237         mdelay(100);
 238
 239         return 0;
 240 }
 241
 242 void dce3_program_fmt(struct drm_encoder *encoder)
 243 {
 244         struct drm_device *dev = encoder->dev;
 245         struct radeon_device *rdev = dev->dev_private;
 246         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 247         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 248         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 249         int bpc = 0;
 250         u32 tmp = 0;
 251         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 252
 253         if (connector) {
 254                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 255                 bpc = radeon_get_monitor_bpc(connector);
 256                 dither = radeon_connector->dither;
 257         }
 258
 259         /* LVDS FMT is set up by atom */
 260         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 261                 return;
 262
 263         /* not needed for analog */
 264         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 265             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 266                 return;
 267
 268         if (bpc == 0)
 269                 return;
 270
 271         switch (bpc) {
 272         case 6:
 273                 if (dither == RADEON_FMT_DITHER_ENABLE)
 274                         /* XXX sort out optimal dither settings */
 275                         tmp |= FMT_SPATIAL_DITHER_EN;
 276                 else
 277                         tmp |= FMT_TRUNCATE_EN;
 278                 break;
 279         case 8:
 280                 if (dither == RADEON_FMT_DITHER_ENABLE)
 281                         /* XXX sort out optimal dither settings */
 282                         tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
 283                 else
 284                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
 285                 break;
 286         case 10:
 287         default:
 288                 /* not needed */
 289                 break;
 290         }
 291
 292         WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
 293 }
 294
 295 /* get temperature in millidegrees */
 296 int rv6xx_get_temp(struct radeon_device *rdev)
 297 {
 298         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 299                 ASIC_T_SHIFT;
 300         int actual_temp = temp & 0xff;
 301
 302         if (temp & 0x100)
 303                 actual_temp -= 256;
 304
 305         return actual_temp * 1000;
 306 }
 307
 308 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 309 {
 310         int i;
 311
 312         rdev->pm.dynpm_can_upclock = true;
 313         rdev->pm.dynpm_can_downclock = true;
 314
 315         /* power state array is low to high, default is first */
 316         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 317                 int min_power_state_index = 0;
 318
 319                 if (rdev->pm.num_power_states > 2)
 320                         min_power_state_index = 1;
 321
 322                 switch (rdev->pm.dynpm_planned_action) {
 323                 case DYNPM_ACTION_MINIMUM:
 324                         rdev->pm.requested_power_state_index = min_power_state_index;
 325                         rdev->pm.requested_clock_mode_index = 0;
 326                         rdev->pm.dynpm_can_downclock = false;
 327                         break;
 328                 case DYNPM_ACTION_DOWNCLOCK:
 329                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 330                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 331                                 rdev->pm.dynpm_can_downclock = false;
 332                         } else {
 333                                 if (rdev->pm.active_crtc_count > 1) {
 334                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 335                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 336                                                         continue;
 337                                                 else if (i >= rdev->pm.current_power_state_index) {
 338                                                         rdev->pm.requested_power_state_index =
 339                                                                 rdev->pm.current_power_state_index;
 340                                                         break;
 341                                                 } else {
 342                                                         rdev->pm.requested_power_state_index = i;
 343                                                         break;
 344                                                 }
 345                                         }
 346                                 } else {
 347                                         if (rdev->pm.current_power_state_index == 0)
 348                                                 rdev->pm.requested_power_state_index =
 349                                                         rdev->pm.num_power_states - 1;
 350                                         else
 351                                                 rdev->pm.requested_power_state_index =
 352                                                         rdev->pm.current_power_state_index - 1;
 353                                 }
 354                         }
 355                         rdev->pm.requested_clock_mode_index = 0;
 356                         /* don't use the power state if crtcs are active and no display flag is set */
 357                         if ((rdev->pm.active_crtc_count > 0) &&
 358                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 359                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 360                              RADEON_PM_MODE_NO_DISPLAY)) {
 361                                 rdev->pm.requested_power_state_index++;
 362                         }
 363                         break;
 364                 case DYNPM_ACTION_UPCLOCK:
 365                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 366                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 367                                 rdev->pm.dynpm_can_upclock = false;
 368                         } else {
 369                                 if (rdev->pm.active_crtc_count > 1) {
 370                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 371                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 372                                                         continue;
 373                                                 else if (i <= rdev->pm.current_power_state_index) {
 374                                                         rdev->pm.requested_power_state_index =
 375                                                                 rdev->pm.current_power_state_index;
 376                                                         break;
 377                                                 } else {
 378                                                         rdev->pm.requested_power_state_index = i;
 379                                                         break;
 380                                                 }
 381                                         }
 382                                 } else
 383                                         rdev->pm.requested_power_state_index =
 384                                                 rdev->pm.current_power_state_index + 1;
 385                         }
 386                         rdev->pm.requested_clock_mode_index = 0;
 387                         break;
 388                 case DYNPM_ACTION_DEFAULT:
 389                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 390                         rdev->pm.requested_clock_mode_index = 0;
 391                         rdev->pm.dynpm_can_upclock = false;
 392                         break;
 393                 case DYNPM_ACTION_NONE:
 394                 default:
 395                         DRM_ERROR("Requested mode for not defined action\n");
 396                         return;
 397                 }
 398         } else {
 399                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 400                 /* for now just select the first power state and switch between clock modes */
 401                 /* power state array is low to high, default is first (0) */
 402                 if (rdev->pm.active_crtc_count > 1) {
 403                         rdev->pm.requested_power_state_index = -1;
 404                         /* start at 1 as we don't want the default mode */
 405                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 406                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 407                                         continue;
 408                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 409                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 410                                         rdev->pm.requested_power_state_index = i;
 411                                         break;
 412                                 }
 413                         }
 414                         /* if nothing selected, grab the default state. */
 415                         if (rdev->pm.requested_power_state_index == -1)
 416                                 rdev->pm.requested_power_state_index = 0;
 417                 } else
 418                         rdev->pm.requested_power_state_index = 1;
 419
 420                 switch (rdev->pm.dynpm_planned_action) {
 421                 case DYNPM_ACTION_MINIMUM:
 422                         rdev->pm.requested_clock_mode_index = 0;
 423                         rdev->pm.dynpm_can_downclock = false;
 424                         break;
 425                 case DYNPM_ACTION_DOWNCLOCK:
 426                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 427                                 if (rdev->pm.current_clock_mode_index == 0) {
 428                                         rdev->pm.requested_clock_mode_index = 0;
 429                                         rdev->pm.dynpm_can_downclock = false;
 430                                 } else
 431                                         rdev->pm.requested_clock_mode_index =
 432                                                 rdev->pm.current_clock_mode_index - 1;
 433                         } else {
 434                                 rdev->pm.requested_clock_mode_index = 0;
 435                                 rdev->pm.dynpm_can_downclock = false;
 436                         }
 437                         /* don't use the power state if crtcs are active and no display flag is set */
 438                         if ((rdev->pm.active_crtc_count > 0) &&
 439                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 440                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 441                              RADEON_PM_MODE_NO_DISPLAY)) {
 442                                 rdev->pm.requested_clock_mode_index++;
 443                         }
 444                         break;
 445                 case DYNPM_ACTION_UPCLOCK:
 446                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 447                                 if (rdev->pm.current_clock_mode_index ==
 448                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 449                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 450                                         rdev->pm.dynpm_can_upclock = false;
 451                                 } else
 452                                         rdev->pm.requested_clock_mode_index =
 453                                                 rdev->pm.current_clock_mode_index + 1;
 454                         } else {
 455                                 rdev->pm.requested_clock_mode_index =
 456                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 457                                 rdev->pm.dynpm_can_upclock = false;
 458                         }
 459                         break;
 460                 case DYNPM_ACTION_DEFAULT:
 461                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 462                         rdev->pm.requested_clock_mode_index = 0;
 463                         rdev->pm.dynpm_can_upclock = false;
 464                         break;
 465                 case DYNPM_ACTION_NONE:
 466                 default:
 467                         DRM_ERROR("Requested mode for not defined action\n");
 468                         return;
 469                 }
 470         }
 471
 472         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 473                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 474                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 475                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 476                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 477                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 478                   pcie_lanes);
 479 }
 480
 481 void rs780_pm_init_profile(struct radeon_device *rdev)
 482 {
 483         if (rdev->pm.num_power_states == 2) {
 484                 /* default */
 485                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 486                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 487                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 488                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 489                 /* low sh */
 490                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 491                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 492                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 493                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 494                 /* mid sh */
 495                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 496                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 497                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 498                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 499                 /* high sh */
 500                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 501                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 502                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 503                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 504                 /* low mh */
 505                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 506                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 507                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 508                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 509                 /* mid mh */
 510                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 511                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 512                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 513                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 514                 /* high mh */
 515                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 516                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 517                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 518                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 519         } else if (rdev->pm.num_power_states == 3) {
 520                 /* default */
 521                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 522                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 523                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 524                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 525                 /* low sh */
 526                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 527                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 528                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 529                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 530                 /* mid sh */
 531                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 532                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 533                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 534                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 535                 /* high sh */
 536                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 537                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 538                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 539                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 540                 /* low mh */
 541                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 542                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 543                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 544                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 545                 /* mid mh */
 546                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 547                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 548                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 549                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 550                 /* high mh */
 551                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 552                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 553                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 554                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 555         } else {
 556                 /* default */
 557                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 558                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 559                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 560                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 561                 /* low sh */
 562                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 563                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 564                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 565                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 566                 /* mid sh */
 567                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 568                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 569                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 570                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 571                 /* high sh */
 572                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 573                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 574                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 575                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 576                 /* low mh */
 577                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 578                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 579                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 580                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 581                 /* mid mh */
 582                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 583                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 584                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 585                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 586                 /* high mh */
 587                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 588                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 589                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 590                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 591         }
 592 }
 593
 594 void r600_pm_init_profile(struct radeon_device *rdev)
 595 {
 596         int idx;
 597
 598         if (rdev->family == CHIP_R600) {
 599                 /* XXX */
 600                 /* default */
 601                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 602                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 603                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 604                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 605                 /* low sh */
 606                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 607                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 608                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 609                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 610                 /* mid sh */
 611                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 612                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 613                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 614                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 615                 /* high sh */
 616                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 617                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 618                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 619                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 620                 /* low mh */
 621                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 622                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 623                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 624                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 625                 /* mid mh */
 626                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 627                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 628                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 629                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 630                 /* high mh */
 631                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 632                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 633                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 634                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 635         } else {
 636                 if (rdev->pm.num_power_states < 4) {
 637                         /* default */
 638                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 639                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 640                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 641                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 642                         /* low sh */
 643                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 644                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 645                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 646                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 647                         /* mid sh */
 648                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 649                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 650                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 651                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 652                         /* high sh */
 653                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 654                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 655                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 656                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 657                         /* low mh */
 658                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 659                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 660                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 661                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 662                         /* low mh */
 663                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 664                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 665                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 666                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 667                         /* high mh */
 668                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 669                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 670                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 671                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 672                 } else {
 673                         /* default */
 674                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 675                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 676                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 677                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 678                         /* low sh */
 679                         if (rdev->flags & RADEON_IS_MOBILITY)
 680                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 681                         else
 682                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 683                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 684                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 685                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 686                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 687                         /* mid sh */
 688                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 689                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 690                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 691                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 692                         /* high sh */
 693                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 694                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 695                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 696                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 697                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 698                         /* low mh */
 699                         if (rdev->flags & RADEON_IS_MOBILITY)
 700                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 701                         else
 702                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 703                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 704                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 705                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 706                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 707                         /* mid mh */
 708                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 709                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 710                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 711                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 712                         /* high mh */
 713                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 714                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 715                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 716                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 717                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 718                 }
 719         }
 720 }
 721
 722 void r600_pm_misc(struct radeon_device *rdev)
 723 {
 724         int req_ps_idx = rdev->pm.requested_power_state_index;
 725         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 726         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 727         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 728
 729         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 730                 /* 0xff01 is a flag rather then an actual voltage */
 731                 if (voltage->voltage == 0xff01)
 732                         return;
 733                 if (voltage->voltage != rdev->pm.current_vddc) {
 734                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 735                         rdev->pm.current_vddc = voltage->voltage;
 736                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 737                 }
 738         }
 739 }
 740
 741 bool r600_gui_idle(struct radeon_device *rdev)
 742 {
 743         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 744                 return false;
 745         else
 746                 return true;
 747 }
 748
 749 /* hpd for digital panel detect/disconnect */
 750 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 751 {
 752         bool connected = false;
 753
 754         if (ASIC_IS_DCE3(rdev)) {
 755                 switch (hpd) {
 756                 case RADEON_HPD_1:
 757                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 758                                 connected = true;
 759                         break;
 760                 case RADEON_HPD_2:
 761                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 762                                 connected = true;
 763                         break;
 764                 case RADEON_HPD_3:
 765                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 766                                 connected = true;
 767                         break;
 768                 case RADEON_HPD_4:
 769                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 770                                 connected = true;
 771                         break;
 772                         /* DCE 3.2 */
 773                 case RADEON_HPD_5:
 774                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 775                                 connected = true;
 776                         break;
 777                 case RADEON_HPD_6:
 778                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 779                                 connected = true;
 780                         break;
 781                 default:
 782                         break;
 783                 }
 784         } else {
 785                 switch (hpd) {
 786                 case RADEON_HPD_1:
 787                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 788                                 connected = true;
 789                         break;
 790                 case RADEON_HPD_2:
 791                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 792                                 connected = true;
 793                         break;
 794                 case RADEON_HPD_3:
 795                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 796                                 connected = true;
 797                         break;
 798                 default:
 799                         break;
 800                 }
 801         }
 802         return connected;
 803 }
 804
 805 void r600_hpd_set_polarity(struct radeon_device *rdev,
 806                            enum radeon_hpd_id hpd)
 807 {
 808         u32 tmp;
 809         bool connected = r600_hpd_sense(rdev, hpd);
 810
 811         if (ASIC_IS_DCE3(rdev)) {
 812                 switch (hpd) {
 813                 case RADEON_HPD_1:
 814                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 815                         if (connected)
 816                                 tmp &= ~DC_HPDx_INT_POLARITY;
 817                         else
 818                                 tmp |= DC_HPDx_INT_POLARITY;
 819                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 820                         break;
 821                 case RADEON_HPD_2:
 822                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 823                         if (connected)
 824                                 tmp &= ~DC_HPDx_INT_POLARITY;
 825                         else
 826                                 tmp |= DC_HPDx_INT_POLARITY;
 827                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 828                         break;
 829                 case RADEON_HPD_3:
 830                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 831                         if (connected)
 832                                 tmp &= ~DC_HPDx_INT_POLARITY;
 833                         else
 834                                 tmp |= DC_HPDx_INT_POLARITY;
 835                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 836                         break;
 837                 case RADEON_HPD_4:
 838                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 839                         if (connected)
 840                                 tmp &= ~DC_HPDx_INT_POLARITY;
 841                         else
 842                                 tmp |= DC_HPDx_INT_POLARITY;
 843                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 844                         break;
 845                 case RADEON_HPD_5:
 846                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 847                         if (connected)
 848                                 tmp &= ~DC_HPDx_INT_POLARITY;
 849                         else
 850                                 tmp |= DC_HPDx_INT_POLARITY;
 851                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 852                         break;
 853                         /* DCE 3.2 */
 854                 case RADEON_HPD_6:
 855                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 856                         if (connected)
 857                                 tmp &= ~DC_HPDx_INT_POLARITY;
 858                         else
 859                                 tmp |= DC_HPDx_INT_POLARITY;
 860                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 861                         break;
 862                 default:
 863                         break;
 864                 }
 865         } else {
 866                 switch (hpd) {
 867                 case RADEON_HPD_1:
 868                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 869                         if (connected)
 870                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 871                         else
 872                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 873                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 874                         break;
 875                 case RADEON_HPD_2:
 876                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 877                         if (connected)
 878                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 879                         else
 880                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 881                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 882                         break;
 883                 case RADEON_HPD_3:
 884                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 885                         if (connected)
 886                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 887                         else
 888                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 889                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 890                         break;
 891                 default:
 892                         break;
 893                 }
 894         }
 895 }
 896
 897 void r600_hpd_init(struct radeon_device *rdev)
 898 {
 899         struct drm_device *dev = rdev->ddev;
 900         struct drm_connector *connector;
 901         unsigned enable = 0;
 902
 903         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 904                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 905
 906                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 907                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 908                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 909                          * aux dp channel on imac and help (but not completely fix)
 910                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 911                          */
 912                         continue;
 913                 }
 914                 if (ASIC_IS_DCE3(rdev)) {
 915                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 916                         if (ASIC_IS_DCE32(rdev))
 917                                 tmp |= DC_HPDx_EN;
 918
 919                         switch (radeon_connector->hpd.hpd) {
 920                         case RADEON_HPD_1:
 921                                 WREG32(DC_HPD1_CONTROL, tmp);
 922                                 break;
 923                         case RADEON_HPD_2:
 924                                 WREG32(DC_HPD2_CONTROL, tmp);
 925                                 break;
 926                         case RADEON_HPD_3:
 927                                 WREG32(DC_HPD3_CONTROL, tmp);
 928                                 break;
 929                         case RADEON_HPD_4:
 930                                 WREG32(DC_HPD4_CONTROL, tmp);
 931                                 break;
 932                                 /* DCE 3.2 */
 933                         case RADEON_HPD_5:
 934                                 WREG32(DC_HPD5_CONTROL, tmp);
 935                                 break;
 936                         case RADEON_HPD_6:
 937                                 WREG32(DC_HPD6_CONTROL, tmp);
 938                                 break;
 939                         default:
 940                                 break;
 941                         }
 942                 } else {
 943                         switch (radeon_connector->hpd.hpd) {
 944                         case RADEON_HPD_1:
 945                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 946                                 break;
 947                         case RADEON_HPD_2:
 948                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 949                                 break;
 950                         case RADEON_HPD_3:
 951                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 952                                 break;
 953                         default:
 954                                 break;
 955                         }
 956                 }
 957                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 958                         enable |= 1 << radeon_connector->hpd.hpd;
 959                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 960         }
 961         radeon_irq_kms_enable_hpd(rdev, enable);
 962 }
 963
 964 void r600_hpd_fini(struct radeon_device *rdev)
 965 {
 966         struct drm_device *dev = rdev->ddev;
 967         struct drm_connector *connector;
 968         unsigned disable = 0;
 969
 970         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 971                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 972                 if (ASIC_IS_DCE3(rdev)) {
 973                         switch (radeon_connector->hpd.hpd) {
 974                         case RADEON_HPD_1:
 975                                 WREG32(DC_HPD1_CONTROL, 0);
 976                                 break;
 977                         case RADEON_HPD_2:
 978                                 WREG32(DC_HPD2_CONTROL, 0);
 979                                 break;
 980                         case RADEON_HPD_3:
 981                                 WREG32(DC_HPD3_CONTROL, 0);
 982                                 break;
 983                         case RADEON_HPD_4:
 984                                 WREG32(DC_HPD4_CONTROL, 0);
 985                                 break;
 986                                 /* DCE 3.2 */
 987                         case RADEON_HPD_5:
 988                                 WREG32(DC_HPD5_CONTROL, 0);
 989                                 break;
 990                         case RADEON_HPD_6:
 991                                 WREG32(DC_HPD6_CONTROL, 0);
 992                                 break;
 993                         default:
 994                                 break;
 995                         }
 996                 } else {
 997                         switch (radeon_connector->hpd.hpd) {
 998                         case RADEON_HPD_1:
 999                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
1000                                 break;
1001                         case RADEON_HPD_2:
1002                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
1003                                 break;
1004                         case RADEON_HPD_3:
1005                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
1006                                 break;
1007                         default:
1008                                 break;
1009                         }
1010                 }
1011                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
1012                         disable |= 1 << radeon_connector->hpd.hpd;
1013         }
1014         radeon_irq_kms_disable_hpd(rdev, disable);
1015 }
1016
1017 /*
1018  * R600 PCIE GART
1019  */
1020 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1021 {
1022         unsigned i;
1023         u32 tmp;
1024
1025         /* flush hdp cache so updates hit vram */
1026         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1027             !(rdev->flags & RADEON_IS_AGP)) {
1028                 void __iomem *ptr = (void *)rdev->gart.ptr;
1029                 u32 tmp;
1030
1031                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
1032                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
1033                  * This seems to cause problems on some AGP cards. Just use the old
1034                  * method for them.
1035                  */
1036                 WREG32(HDP_DEBUG1, 0);
1037                 tmp = readl((void __iomem *)ptr);
1038         } else
1039                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1040
1041         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1042         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1043         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1044         for (i = 0; i < rdev->usec_timeout; i++) {
1045                 /* read MC_STATUS */
1046                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1047                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1048                 if (tmp == 2) {
1049                         pr_warn("[drm] r600 flush TLB failed\n");
1050                         return;
1051                 }
1052                 if (tmp) {
1053                         return;
1054                 }
1055                 udelay(1);
1056         }
1057 }
1058
1059 int r600_pcie_gart_init(struct radeon_device *rdev)
1060 {
1061         int r;
1062
1063         if (rdev->gart.robj) {
1064                 WARN(1, "R600 PCIE GART already initialized\n");
1065                 return 0;
1066         }
1067         /* Initialize common gart structure */
1068         r = radeon_gart_init(rdev);
1069         if (r)
1070                 return r;
1071         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1072         return radeon_gart_table_vram_alloc(rdev);
1073 }
1074
1075 static int r600_pcie_gart_enable(struct radeon_device *rdev)
1076 {
1077         u32 tmp;
1078         int r, i;
1079
1080         if (rdev->gart.robj == NULL) {
1081                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1082                 return -EINVAL;
1083         }
1084         r = radeon_gart_table_vram_pin(rdev);
1085         if (r)
1086                 return r;
1087
1088         /* Setup L2 cache */
1089         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1090                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1091                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1092         WREG32(VM_L2_CNTL2, 0);
1093         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1094         /* Setup TLB control */
1095         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1096                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1097                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1098                 ENABLE_WAIT_L2_QUERY;
1099         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1100         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1101         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1102         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1103         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1104         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1105         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1106         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1107         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1108         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1109         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1110         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1111         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1112         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1113         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1114         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1115         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1116         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1117         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1118         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1119                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1120         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1121                         (u32)(rdev->dummy_page.addr >> 12));
1122         for (i = 1; i < 7; i++)
1123                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1124
1125         r600_pcie_gart_tlb_flush(rdev);
1126         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1127                  (unsigned)(rdev->mc.gtt_size >> 20),
1128                  (unsigned long long)rdev->gart.table_addr);
1129         rdev->gart.ready = true;
1130         return 0;
1131 }
1132
1133 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1134 {
1135         u32 tmp;
1136         int i;
1137
1138         /* Disable all tables */
1139         for (i = 0; i < 7; i++)
1140                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1141
1142         /* Disable L2 cache */
1143         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1144                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1145         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1146         /* Setup L1 TLB control */
1147         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1148                 ENABLE_WAIT_L2_QUERY;
1149         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1150         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1151         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1152         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1153         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1154         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1155         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1156         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1157         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1158         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1159         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1160         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1161         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1162         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1163         WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1164         WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
1165         radeon_gart_table_vram_unpin(rdev);
1166 }
1167
1168 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1169 {
1170         radeon_gart_fini(rdev);
1171         r600_pcie_gart_disable(rdev);
1172         radeon_gart_table_vram_free(rdev);
1173 }
1174
1175 static void r600_agp_enable(struct radeon_device *rdev)
1176 {
1177         u32 tmp;
1178         int i;
1179
1180         /* Setup L2 cache */
1181         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1182                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1183                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1184         WREG32(VM_L2_CNTL2, 0);
1185         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1186         /* Setup TLB control */
1187         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1188                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1189                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1190                 ENABLE_WAIT_L2_QUERY;
1191         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1192         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1193         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1194         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1195         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1196         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1197         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1198         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1199         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1200         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1201         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1202         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1203         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1204         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1205         for (i = 0; i < 7; i++)
1206                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1207 }
1208
1209 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1210 {
1211         unsigned i;
1212         u32 tmp;
1213
1214         for (i = 0; i < rdev->usec_timeout; i++) {
1215                 /* read MC_STATUS */
1216                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1217                 if (!tmp)
1218                         return 0;
1219                 udelay(1);
1220         }
1221         return -1;
1222 }
1223
1224 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1225 {
1226         unsigned long flags;
1227         uint32_t r;
1228
1229         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1230         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1231         r = RREG32(R_0028FC_MC_DATA);
1232         WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1233         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1234         return r;
1235 }
1236
1237 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1238 {
1239         unsigned long flags;
1240
1241         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1242         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1243                 S_0028F8_MC_IND_WR_EN(1));
1244         WREG32(R_0028FC_MC_DATA, v);
1245         WREG32(R_0028F8_MC_INDEX, 0x7F);
1246         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1247 }
1248
1249 static void r600_mc_program(struct radeon_device *rdev)
1250 {
1251         struct rv515_mc_save save;
1252         u32 tmp;
1253         int i, j;
1254
1255         /* Initialize HDP */
1256         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1257                 WREG32((0x2c14 + j), 0x00000000);
1258                 WREG32((0x2c18 + j), 0x00000000);
1259                 WREG32((0x2c1c + j), 0x00000000);
1260                 WREG32((0x2c20 + j), 0x00000000);
1261                 WREG32((0x2c24 + j), 0x00000000);
1262         }
1263         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1264
1265         rv515_mc_stop(rdev, &save);
1266         if (r600_mc_wait_for_idle(rdev)) {
1267                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1268         }
1269         /* Lockout access through VGA aperture (doesn't exist before R600) */
1270         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1271         /* Update configuration */
1272         if (rdev->flags & RADEON_IS_AGP) {
1273                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1274                         /* VRAM before AGP */
1275                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1276                                 rdev->mc.vram_start >> 12);
1277                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1278                                 rdev->mc.gtt_end >> 12);
1279                 } else {
1280                         /* VRAM after AGP */
1281                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1282                                 rdev->mc.gtt_start >> 12);
1283                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1284                                 rdev->mc.vram_end >> 12);
1285                 }
1286         } else {
1287                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1288                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1289         }
1290         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1291         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1292         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1293         WREG32(MC_VM_FB_LOCATION, tmp);
1294         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1295         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1296         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1297         if (rdev->flags & RADEON_IS_AGP) {
1298                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1299                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1300                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1301         } else {
1302                 WREG32(MC_VM_AGP_BASE, 0);
1303                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1304                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1305         }
1306         if (r600_mc_wait_for_idle(rdev)) {
1307                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1308         }
1309         rv515_mc_resume(rdev, &save);
1310         /* we need to own VRAM, so turn off the VGA renderer here
1311          * to stop it overwriting our objects */
1312         rv515_vga_render_disable(rdev);
1313 }
1314
1315 /**
1316  * r600_vram_gtt_location - try to find VRAM & GTT location
1317  * @rdev: radeon device structure holding all necessary informations
1318  * @mc: memory controller structure holding memory informations
1319  *
1320  * Function will place try to place VRAM at same place as in CPU (PCI)
1321  * address space as some GPU seems to have issue when we reprogram at
1322  * different address space.
1323  *
1324  * If there is not enough space to fit the unvisible VRAM after the
1325  * aperture then we limit the VRAM size to the aperture.
1326  *
1327  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1328  * them to be in one from GPU point of view so that we can program GPU to
1329  * catch access outside them (weird GPU policy see ??).
1330  *
1331  * This function will never fails, worst case are limiting VRAM or GTT.
1332  *
1333  * Note: GTT start, end, size should be initialized before calling this
1334  * function on AGP platform.
1335  */
1336 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1337 {
1338         u64 size_bf, size_af;
1339
1340         if (mc->mc_vram_size > 0xE0000000) {
1341                 /* leave room for at least 512M GTT */
1342                 dev_warn(rdev->dev, "limiting VRAM\n");
1343                 mc->real_vram_size = 0xE0000000;
1344                 mc->mc_vram_size = 0xE0000000;
1345         }
1346         if (rdev->flags & RADEON_IS_AGP) {
1347                 size_bf = mc->gtt_start;
1348                 size_af = mc->mc_mask - mc->gtt_end;
1349                 if (size_bf > size_af) {
1350                         if (mc->mc_vram_size > size_bf) {
1351                                 dev_warn(rdev->dev, "limiting VRAM\n");
1352                                 mc->real_vram_size = size_bf;
1353                                 mc->mc_vram_size = size_bf;
1354                         }
1355                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1356                 } else {
1357                         if (mc->mc_vram_size > size_af) {
1358                                 dev_warn(rdev->dev, "limiting VRAM\n");
1359                                 mc->real_vram_size = size_af;
1360                                 mc->mc_vram_size = size_af;
1361                         }
1362                         mc->vram_start = mc->gtt_end + 1;
1363                 }
1364                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1365                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1366                                 mc->mc_vram_size >> 20, mc->vram_start,
1367                                 mc->vram_end, mc->real_vram_size >> 20);
1368         } else {
1369                 u64 base = 0;
1370                 if (rdev->flags & RADEON_IS_IGP) {
1371                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1372                         base <<= 24;
1373                 }
1374                 radeon_vram_location(rdev, &rdev->mc, base);
1375                 rdev->mc.gtt_base_align = 0;
1376                 radeon_gtt_location(rdev, mc);
1377         }
1378 }
1379
1380 static int r600_mc_init(struct radeon_device *rdev)
1381 {
1382         u32 tmp;
1383         int chansize, numchan;
1384         uint32_t h_addr, l_addr;
1385         unsigned long long k8_addr;
1386
1387         /* Get VRAM informations */
1388         rdev->mc.vram_is_ddr = true;
1389         tmp = RREG32(RAMCFG);
1390         if (tmp & CHANSIZE_OVERRIDE) {
1391                 chansize = 16;
1392         } else if (tmp & CHANSIZE_MASK) {
1393                 chansize = 64;
1394         } else {
1395                 chansize = 32;
1396         }
1397         tmp = RREG32(CHMAP);
1398         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1399         case 0:
1400         default:
1401                 numchan = 1;
1402                 break;
1403         case 1:
1404                 numchan = 2;
1405                 break;
1406         case 2:
1407                 numchan = 4;
1408                 break;
1409         case 3:
1410                 numchan = 8;
1411                 break;
1412         }
1413         rdev->mc.vram_width = numchan * chansize;
1414         /* Could aper size report 0 ? */
1415         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1416         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1417         /* Setup GPU memory space */
1418         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1419         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1420         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1421         r600_vram_gtt_location(rdev, &rdev->mc);
1422
1423         if (rdev->flags & RADEON_IS_IGP) {
1424                 rs690_pm_info(rdev);
1425                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1426
1427                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1428                         /* Use K8 direct mapping for fast fb access. */
1429                         rdev->fastfb_working = false;
1430                         h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1431                         l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1432                         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1433 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1434                         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1435 #endif
1436                         {
1437                                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1438                                 * memory is present.
1439                                 */
1440                                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1441                                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1442                                                 (unsigned long long)rdev->mc.aper_base, k8_addr);
1443                                         rdev->mc.aper_base = (resource_size_t)k8_addr;
1444                                         rdev->fastfb_working = true;
1445                                 }
1446                         }
1447                 }
1448         }
1449
1450         radeon_update_bandwidth_info(rdev);
1451         return 0;
1452 }
1453
1454 int r600_vram_scratch_init(struct radeon_device *rdev)
1455 {
1456         int r;
1457
1458         if (rdev->vram_scratch.robj == NULL) {
1459                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1460                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1461                                      0, NULL, NULL, &rdev->vram_scratch.robj);
1462                 if (r) {
1463                         return r;
1464                 }
1465         }
1466
1467         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1468         if (unlikely(r != 0))
1469                 return r;
1470         r = radeon_bo_pin(rdev->vram_scratch.robj,
1471                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1472         if (r) {
1473                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1474                 return r;
1475         }
1476         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1477                                 (void **)&rdev->vram_scratch.ptr);
1478         if (r)
1479                 radeon_bo_unpin(rdev->vram_scratch.robj);
1480         radeon_bo_unreserve(rdev->vram_scratch.robj);
1481
1482         return r;
1483 }
1484
1485 void r600_vram_scratch_fini(struct radeon_device *rdev)
1486 {
1487         int r;
1488
1489         if (rdev->vram_scratch.robj == NULL) {
1490                 return;
1491         }
1492         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1493         if (likely(r == 0)) {
1494                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1495                 radeon_bo_unpin(rdev->vram_scratch.robj);
1496                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1497         }
1498         radeon_bo_unref(&rdev->vram_scratch.robj);
1499 }
1500
1501 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1502 {
1503         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1504
1505         if (hung)
1506                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1507         else
1508                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1509
1510         WREG32(R600_BIOS_3_SCRATCH, tmp);
1511 }
1512
1513 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1514 {
1515         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1516                  RREG32(R_008010_GRBM_STATUS));
1517         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1518                  RREG32(R_008014_GRBM_STATUS2));
1519         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1520                  RREG32(R_000E50_SRBM_STATUS));
1521         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1522                  RREG32(CP_STALLED_STAT1));
1523         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1524                  RREG32(CP_STALLED_STAT2));
1525         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1526                  RREG32(CP_BUSY_STAT));
1527         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1528                  RREG32(CP_STAT));
1529         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1530                 RREG32(DMA_STATUS_REG));
1531 }
1532
1533 static bool r600_is_display_hung(struct radeon_device *rdev)
1534 {
1535         u32 crtc_hung = 0;
1536         u32 crtc_status[2];
1537         u32 i, j, tmp;
1538
1539         for (i = 0; i < rdev->num_crtc; i++) {
1540                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1541                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1542                         crtc_hung |= (1 << i);
1543                 }
1544         }
1545
1546         for (j = 0; j < 10; j++) {
1547                 for (i = 0; i < rdev->num_crtc; i++) {
1548                         if (crtc_hung & (1 << i)) {
1549                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1550                                 if (tmp != crtc_status[i])
1551                                         crtc_hung &= ~(1 << i);
1552                         }
1553                 }
1554                 if (crtc_hung == 0)
1555                         return false;
1556                 udelay(100);
1557         }
1558
1559         return true;
1560 }
1561
1562 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1563 {
1564         u32 reset_mask = 0;
1565         u32 tmp;
1566
1567         /* GRBM_STATUS */
1568         tmp = RREG32(R_008010_GRBM_STATUS);
1569         if (rdev->family >= CHIP_RV770) {
1570                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1571                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1572                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1573                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1574                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1575                         reset_mask |= RADEON_RESET_GFX;
1576         } else {
1577                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1578                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1579                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1580                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1581                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1582                         reset_mask |= RADEON_RESET_GFX;
1583         }
1584
1585         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1586             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1587                 reset_mask |= RADEON_RESET_CP;
1588
1589         if (G_008010_GRBM_EE_BUSY(tmp))
1590                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1591
1592         /* DMA_STATUS_REG */
1593         tmp = RREG32(DMA_STATUS_REG);
1594         if (!(tmp & DMA_IDLE))
1595                 reset_mask |= RADEON_RESET_DMA;
1596
1597         /* SRBM_STATUS */
1598         tmp = RREG32(R_000E50_SRBM_STATUS);
1599         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1600                 reset_mask |= RADEON_RESET_RLC;
1601
1602         if (G_000E50_IH_BUSY(tmp))
1603                 reset_mask |= RADEON_RESET_IH;
1604
1605         if (G_000E50_SEM_BUSY(tmp))
1606                 reset_mask |= RADEON_RESET_SEM;
1607
1608         if (G_000E50_GRBM_RQ_PENDING(tmp))
1609                 reset_mask |= RADEON_RESET_GRBM;
1610
1611         if (G_000E50_VMC_BUSY(tmp))
1612                 reset_mask |= RADEON_RESET_VMC;
1613
1614         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1615             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1616             G_000E50_MCDW_BUSY(tmp))
1617                 reset_mask |= RADEON_RESET_MC;
1618
1619         if (r600_is_display_hung(rdev))
1620                 reset_mask |= RADEON_RESET_DISPLAY;
1621
1622         /* Skip MC reset as it's mostly likely not hung, just busy */
1623         if (reset_mask & RADEON_RESET_MC) {
1624                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1625                 reset_mask &= ~RADEON_RESET_MC;
1626         }
1627
1628         return reset_mask;
1629 }
1630
1631 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1632 {
1633         struct rv515_mc_save save;
1634         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1635         u32 tmp;
1636
1637         if (reset_mask == 0)
1638                 return;
1639
1640         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1641
1642         r600_print_gpu_status_regs(rdev);
1643
1644         /* Disable CP parsing/prefetching */
1645         if (rdev->family >= CHIP_RV770)
1646                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1647         else
1648                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1649
1650         /* disable the RLC */
1651         WREG32(RLC_CNTL, 0);
1652
1653         if (reset_mask & RADEON_RESET_DMA) {
1654                 /* Disable DMA */
1655                 tmp = RREG32(DMA_RB_CNTL);
1656                 tmp &= ~DMA_RB_ENABLE;
1657                 WREG32(DMA_RB_CNTL, tmp);
1658         }
1659
1660         mdelay(50);
1661
1662         rv515_mc_stop(rdev, &save);
1663         if (r600_mc_wait_for_idle(rdev)) {
1664                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1665         }
1666
1667         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1668                 if (rdev->family >= CHIP_RV770)
1669                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1670                                 S_008020_SOFT_RESET_CB(1) |
1671                                 S_008020_SOFT_RESET_PA(1) |
1672                                 S_008020_SOFT_RESET_SC(1) |
1673                                 S_008020_SOFT_RESET_SPI(1) |
1674                                 S_008020_SOFT_RESET_SX(1) |
1675                                 S_008020_SOFT_RESET_SH(1) |
1676                                 S_008020_SOFT_RESET_TC(1) |
1677                                 S_008020_SOFT_RESET_TA(1) |
1678                                 S_008020_SOFT_RESET_VC(1) |
1679                                 S_008020_SOFT_RESET_VGT(1);
1680                 else
1681                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1682                                 S_008020_SOFT_RESET_DB(1) |
1683                                 S_008020_SOFT_RESET_CB(1) |
1684                                 S_008020_SOFT_RESET_PA(1) |
1685                                 S_008020_SOFT_RESET_SC(1) |
1686                                 S_008020_SOFT_RESET_SMX(1) |
1687                                 S_008020_SOFT_RESET_SPI(1) |
1688                                 S_008020_SOFT_RESET_SX(1) |
1689                                 S_008020_SOFT_RESET_SH(1) |
1690                                 S_008020_SOFT_RESET_TC(1) |
1691                                 S_008020_SOFT_RESET_TA(1) |
1692                                 S_008020_SOFT_RESET_VC(1) |
1693                                 S_008020_SOFT_RESET_VGT(1);
1694         }
1695
1696         if (reset_mask & RADEON_RESET_CP) {
1697                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1698                         S_008020_SOFT_RESET_VGT(1);
1699
1700                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1701         }
1702
1703         if (reset_mask & RADEON_RESET_DMA) {
1704                 if (rdev->family >= CHIP_RV770)
1705                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1706                 else
1707                         srbm_soft_reset |= SOFT_RESET_DMA;
1708         }
1709
1710         if (reset_mask & RADEON_RESET_RLC)
1711                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1712
1713         if (reset_mask & RADEON_RESET_SEM)
1714                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1715
1716         if (reset_mask & RADEON_RESET_IH)
1717                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1718
1719         if (reset_mask & RADEON_RESET_GRBM)
1720                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1721
1722         if (!(rdev->flags & RADEON_IS_IGP)) {
1723                 if (reset_mask & RADEON_RESET_MC)
1724                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1725         }
1726
1727         if (reset_mask & RADEON_RESET_VMC)
1728                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1729
1730         if (grbm_soft_reset) {
1731                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1732                 tmp |= grbm_soft_reset;
1733                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1734                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1735                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1736
1737                 udelay(50);
1738
1739                 tmp &= ~grbm_soft_reset;
1740                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1741                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1742         }
1743
1744         if (srbm_soft_reset) {
1745                 tmp = RREG32(SRBM_SOFT_RESET);
1746                 tmp |= srbm_soft_reset;
1747                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1748                 WREG32(SRBM_SOFT_RESET, tmp);
1749                 tmp = RREG32(SRBM_SOFT_RESET);
1750
1751                 udelay(50);
1752
1753                 tmp &= ~srbm_soft_reset;
1754                 WREG32(SRBM_SOFT_RESET, tmp);
1755                 tmp = RREG32(SRBM_SOFT_RESET);
1756         }
1757
1758         /* Wait a little for things to settle down */
1759         mdelay(1);
1760
1761         rv515_mc_resume(rdev, &save);
1762         udelay(50);
1763
1764         r600_print_gpu_status_regs(rdev);
1765 }
1766
1767 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1768 {
1769         struct rv515_mc_save save;
1770         u32 tmp, i;
1771
1772         dev_info(rdev->dev, "GPU pci config reset\n");
1773
1774         /* disable dpm? */
1775
1776         /* Disable CP parsing/prefetching */
1777         if (rdev->family >= CHIP_RV770)
1778                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1779         else
1780                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1781
1782         /* disable the RLC */
1783         WREG32(RLC_CNTL, 0);
1784
1785         /* Disable DMA */
1786         tmp = RREG32(DMA_RB_CNTL);
1787         tmp &= ~DMA_RB_ENABLE;
1788         WREG32(DMA_RB_CNTL, tmp);
1789
1790         mdelay(50);
1791
1792         /* set mclk/sclk to bypass */
1793         if (rdev->family >= CHIP_RV770)
1794                 rv770_set_clk_bypass_mode(rdev);
1795         /* disable BM */
1796         pci_clear_master(rdev->pdev);
1797         /* disable mem access */
1798         rv515_mc_stop(rdev, &save);
1799         if (r600_mc_wait_for_idle(rdev)) {
1800                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1801         }
1802
1803         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1804         tmp = RREG32(BUS_CNTL);
1805         tmp |= VGA_COHE_SPEC_TIMER_DIS;
1806         WREG32(BUS_CNTL, tmp);
1807
1808         tmp = RREG32(BIF_SCRATCH0);
1809
1810         /* reset */
1811         radeon_pci_config_reset(rdev);
1812         mdelay(1);
1813
1814         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1815         tmp = SOFT_RESET_BIF;
1816         WREG32(SRBM_SOFT_RESET, tmp);
1817         mdelay(1);
1818         WREG32(SRBM_SOFT_RESET, 0);
1819
1820         /* wait for asic to come out of reset */
1821         for (i = 0; i < rdev->usec_timeout; i++) {
1822                 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1823                         break;
1824                 udelay(1);
1825         }
1826 }
1827
1828 int r600_asic_reset(struct radeon_device *rdev, bool hard)
1829 {
1830         u32 reset_mask;
1831
1832         if (hard) {
1833                 r600_gpu_pci_config_reset(rdev);
1834                 return 0;
1835         }
1836
1837         reset_mask = r600_gpu_check_soft_reset(rdev);
1838
1839         if (reset_mask)
1840                 r600_set_bios_scratch_engine_hung(rdev, true);
1841
1842         /* try soft reset */
1843         r600_gpu_soft_reset(rdev, reset_mask);
1844
1845         reset_mask = r600_gpu_check_soft_reset(rdev);
1846
1847         /* try pci config reset */
1848         if (reset_mask && radeon_hard_reset)
1849                 r600_gpu_pci_config_reset(rdev);
1850
1851         reset_mask = r600_gpu_check_soft_reset(rdev);
1852
1853         if (!reset_mask)
1854                 r600_set_bios_scratch_engine_hung(rdev, false);
1855
1856         return 0;
1857 }
1858
1859 /**
1860  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1861  *
1862  * @rdev: radeon_device pointer
1863  * @ring: radeon_ring structure holding ring information
1864  *
1865  * Check if the GFX engine is locked up.
1866  * Returns true if the engine appears to be locked up, false if not.
1867  */
1868 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1869 {
1870         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1871
1872         if (!(reset_mask & (RADEON_RESET_GFX |
1873                             RADEON_RESET_COMPUTE |
1874                             RADEON_RESET_CP))) {
1875                 radeon_ring_lockup_update(rdev, ring);
1876                 return false;
1877         }
1878         return radeon_ring_test_lockup(rdev, ring);
1879 }
1880
1881 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1882                               u32 tiling_pipe_num,
1883                               u32 max_rb_num,
1884                               u32 total_max_rb_num,
1885                               u32 disabled_rb_mask)
1886 {
1887         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1888         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1889         u32 data = 0, mask = 1 << (max_rb_num - 1);
1890         unsigned i, j;
1891
1892         /* mask out the RBs that don't exist on that asic */
1893         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1894         /* make sure at least one RB is available */
1895         if ((tmp & 0xff) != 0xff)
1896                 disabled_rb_mask = tmp;
1897
1898         rendering_pipe_num = 1 << tiling_pipe_num;
1899         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1900         BUG_ON(rendering_pipe_num < req_rb_num);
1901
1902         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1903         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1904
1905         if (rdev->family <= CHIP_RV740) {
1906                 /* r6xx/r7xx */
1907                 rb_num_width = 2;
1908         } else {
1909                 /* eg+ */
1910                 rb_num_width = 4;
1911         }
1912
1913         for (i = 0; i < max_rb_num; i++) {
1914                 if (!(mask & disabled_rb_mask)) {
1915                         for (j = 0; j < pipe_rb_ratio; j++) {
1916                                 data <<= rb_num_width;
1917                                 data |= max_rb_num - i - 1;
1918                         }
1919                         if (pipe_rb_remain) {
1920                                 data <<= rb_num_width;
1921                                 data |= max_rb_num - i - 1;
1922                                 pipe_rb_remain--;
1923                         }
1924                 }
1925                 mask >>= 1;
1926         }
1927
1928         return data;
1929 }
1930
1931 int r600_count_pipe_bits(uint32_t val)
1932 {
1933         return hweight32(val);
1934 }
1935
1936 static void r600_gpu_init(struct radeon_device *rdev)
1937 {
1938         u32 tiling_config;
1939         u32 ramcfg;
1940         u32 cc_gc_shader_pipe_config;
1941         u32 tmp;
1942         int i, j;
1943         u32 sq_config;
1944         u32 sq_gpr_resource_mgmt_1 = 0;
1945         u32 sq_gpr_resource_mgmt_2 = 0;
1946         u32 sq_thread_resource_mgmt = 0;
1947         u32 sq_stack_resource_mgmt_1 = 0;
1948         u32 sq_stack_resource_mgmt_2 = 0;
1949         u32 disabled_rb_mask;
1950
1951         rdev->config.r600.tiling_group_size = 256;
1952         switch (rdev->family) {
1953         case CHIP_R600:
1954                 rdev->config.r600.max_pipes = 4;
1955                 rdev->config.r600.max_tile_pipes = 8;
1956                 rdev->config.r600.max_simds = 4;
1957                 rdev->config.r600.max_backends = 4;
1958                 rdev->config.r600.max_gprs = 256;
1959                 rdev->config.r600.max_threads = 192;
1960                 rdev->config.r600.max_stack_entries = 256;
1961                 rdev->config.r600.max_hw_contexts = 8;
1962                 rdev->config.r600.max_gs_threads = 16;
1963                 rdev->config.r600.sx_max_export_size = 128;
1964                 rdev->config.r600.sx_max_export_pos_size = 16;
1965                 rdev->config.r600.sx_max_export_smx_size = 128;
1966                 rdev->config.r600.sq_num_cf_insts = 2;
1967                 break;
1968         case CHIP_RV630:
1969         case CHIP_RV635:
1970                 rdev->config.r600.max_pipes = 2;
1971                 rdev->config.r600.max_tile_pipes = 2;
1972                 rdev->config.r600.max_simds = 3;
1973                 rdev->config.r600.max_backends = 1;
1974                 rdev->config.r600.max_gprs = 128;
1975                 rdev->config.r600.max_threads = 192;
1976                 rdev->config.r600.max_stack_entries = 128;
1977                 rdev->config.r600.max_hw_contexts = 8;
1978                 rdev->config.r600.max_gs_threads = 4;
1979                 rdev->config.r600.sx_max_export_size = 128;
1980                 rdev->config.r600.sx_max_export_pos_size = 16;
1981                 rdev->config.r600.sx_max_export_smx_size = 128;
1982                 rdev->config.r600.sq_num_cf_insts = 2;
1983                 break;
1984         case CHIP_RV610:
1985         case CHIP_RV620:
1986         case CHIP_RS780:
1987         case CHIP_RS880:
1988                 rdev->config.r600.max_pipes = 1;
1989                 rdev->config.r600.max_tile_pipes = 1;
1990                 rdev->config.r600.max_simds = 2;
1991                 rdev->config.r600.max_backends = 1;
1992                 rdev->config.r600.max_gprs = 128;
1993                 rdev->config.r600.max_threads = 192;
1994                 rdev->config.r600.max_stack_entries = 128;
1995                 rdev->config.r600.max_hw_contexts = 4;
1996                 rdev->config.r600.max_gs_threads = 4;
1997                 rdev->config.r600.sx_max_export_size = 128;
1998                 rdev->config.r600.sx_max_export_pos_size = 16;
1999                 rdev->config.r600.sx_max_export_smx_size = 128;
2000                 rdev->config.r600.sq_num_cf_insts = 1;
2001                 break;
2002         case CHIP_RV670:
2003                 rdev->config.r600.max_pipes = 4;
2004                 rdev->config.r600.max_tile_pipes = 4;
2005                 rdev->config.r600.max_simds = 4;
2006                 rdev->config.r600.max_backends = 4;
2007                 rdev->config.r600.max_gprs = 192;
2008                 rdev->config.r600.max_threads = 192;
2009                 rdev->config.r600.max_stack_entries = 256;
2010                 rdev->config.r600.max_hw_contexts = 8;
2011                 rdev->config.r600.max_gs_threads = 16;
2012                 rdev->config.r600.sx_max_export_size = 128;
2013                 rdev->config.r600.sx_max_export_pos_size = 16;
2014                 rdev->config.r600.sx_max_export_smx_size = 128;
2015                 rdev->config.r600.sq_num_cf_insts = 2;
2016                 break;
2017         default:
2018                 break;
2019         }
2020
2021         /* Initialize HDP */
2022         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2023                 WREG32((0x2c14 + j), 0x00000000);
2024                 WREG32((0x2c18 + j), 0x00000000);
2025                 WREG32((0x2c1c + j), 0x00000000);
2026                 WREG32((0x2c20 + j), 0x00000000);
2027                 WREG32((0x2c24 + j), 0x00000000);
2028         }
2029
2030         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2031
2032         /* Setup tiling */
2033         tiling_config = 0;
2034         ramcfg = RREG32(RAMCFG);
2035         switch (rdev->config.r600.max_tile_pipes) {
2036         case 1:
2037                 tiling_config |= PIPE_TILING(0);
2038                 break;
2039         case 2:
2040                 tiling_config |= PIPE_TILING(1);
2041                 break;
2042         case 4:
2043                 tiling_config |= PIPE_TILING(2);
2044                 break;
2045         case 8:
2046                 tiling_config |= PIPE_TILING(3);
2047                 break;
2048         default:
2049                 break;
2050         }
2051         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
2052         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2053         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
2054         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2055
2056         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2057         if (tmp > 3) {
2058                 tiling_config |= ROW_TILING(3);
2059                 tiling_config |= SAMPLE_SPLIT(3);
2060         } else {
2061                 tiling_config |= ROW_TILING(tmp);
2062                 tiling_config |= SAMPLE_SPLIT(tmp);
2063         }
2064         tiling_config |= BANK_SWAPS(1);
2065
2066         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
2067         tmp = rdev->config.r600.max_simds -
2068                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2069         rdev->config.r600.active_simds = tmp;
2070
2071         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
2072         tmp = 0;
2073         for (i = 0; i < rdev->config.r600.max_backends; i++)
2074                 tmp |= (1 << i);
2075         /* if all the backends are disabled, fix it up here */
2076         if ((disabled_rb_mask & tmp) == tmp) {
2077                 for (i = 0; i < rdev->config.r600.max_backends; i++)
2078                         disabled_rb_mask &= ~(1 << i);
2079         }
2080         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2081         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2082                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
2083         tiling_config |= tmp << 16;
2084         rdev->config.r600.backend_map = tmp;
2085
2086         rdev->config.r600.tile_config = tiling_config;
2087         WREG32(GB_TILING_CONFIG, tiling_config);
2088         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2089         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
2090         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
2091
2092         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
2093         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2094         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2095
2096         /* Setup some CP states */
2097         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2098         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2099
2100         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2101                              SYNC_WALKER | SYNC_ALIGNER));
2102         /* Setup various GPU states */
2103         if (rdev->family == CHIP_RV670)
2104                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2105
2106         tmp = RREG32(SX_DEBUG_1);
2107         tmp |= SMX_EVENT_RELEASE;
2108         if ((rdev->family > CHIP_R600))
2109                 tmp |= ENABLE_NEW_SMX_ADDRESS;
2110         WREG32(SX_DEBUG_1, tmp);
2111
2112         if (((rdev->family) == CHIP_R600) ||
2113             ((rdev->family) == CHIP_RV630) ||
2114             ((rdev->family) == CHIP_RV610) ||
2115             ((rdev->family) == CHIP_RV620) ||
2116             ((rdev->family) == CHIP_RS780) ||
2117             ((rdev->family) == CHIP_RS880)) {
2118                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2119         } else {
2120                 WREG32(DB_DEBUG, 0);
2121         }
2122         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2123                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2124
2125         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2126         WREG32(VGT_NUM_INSTANCES, 0);
2127
2128         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2129         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2130
2131         tmp = RREG32(SQ_MS_FIFO_SIZES);
2132         if (((rdev->family) == CHIP_RV610) ||
2133             ((rdev->family) == CHIP_RV620) ||
2134             ((rdev->family) == CHIP_RS780) ||
2135             ((rdev->family) == CHIP_RS880)) {
2136                 tmp = (CACHE_FIFO_SIZE(0xa) |
2137                        FETCH_FIFO_HIWATER(0xa) |
2138                        DONE_FIFO_HIWATER(0xe0) |
2139                        ALU_UPDATE_FIFO_HIWATER(0x8));
2140         } else if (((rdev->family) == CHIP_R600) ||
2141                    ((rdev->family) == CHIP_RV630)) {
2142                 tmp &= ~DONE_FIFO_HIWATER(0xff);
2143                 tmp |= DONE_FIFO_HIWATER(0x4);
2144         }
2145         WREG32(SQ_MS_FIFO_SIZES, tmp);
2146
2147         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2148          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
2149          */
2150         sq_config = RREG32(SQ_CONFIG);
2151         sq_config &= ~(PS_PRIO(3) |
2152                        VS_PRIO(3) |
2153                        GS_PRIO(3) |
2154                        ES_PRIO(3));
2155         sq_config |= (DX9_CONSTS |
2156                       VC_ENABLE |
2157                       PS_PRIO(0) |
2158                       VS_PRIO(1) |
2159                       GS_PRIO(2) |
2160                       ES_PRIO(3));
2161
2162         if ((rdev->family) == CHIP_R600) {
2163                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2164                                           NUM_VS_GPRS(124) |
2165                                           NUM_CLAUSE_TEMP_GPRS(4));
2166                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2167                                           NUM_ES_GPRS(0));
2168                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2169                                            NUM_VS_THREADS(48) |
2170                                            NUM_GS_THREADS(4) |
2171                                            NUM_ES_THREADS(4));
2172                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2173                                             NUM_VS_STACK_ENTRIES(128));
2174                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2175                                             NUM_ES_STACK_ENTRIES(0));
2176         } else if (((rdev->family) == CHIP_RV610) ||
2177                    ((rdev->family) == CHIP_RV620) ||
2178                    ((rdev->family) == CHIP_RS780) ||
2179                    ((rdev->family) == CHIP_RS880)) {
2180                 /* no vertex cache */
2181                 sq_config &= ~VC_ENABLE;
2182
2183                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2184                                           NUM_VS_GPRS(44) |
2185                                           NUM_CLAUSE_TEMP_GPRS(2));
2186                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2187                                           NUM_ES_GPRS(17));
2188                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2189                                            NUM_VS_THREADS(78) |
2190                                            NUM_GS_THREADS(4) |
2191                                            NUM_ES_THREADS(31));
2192                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2193                                             NUM_VS_STACK_ENTRIES(40));
2194                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2195                                             NUM_ES_STACK_ENTRIES(16));
2196         } else if (((rdev->family) == CHIP_RV630) ||
2197                    ((rdev->family) == CHIP_RV635)) {
2198                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2199                                           NUM_VS_GPRS(44) |
2200                                           NUM_CLAUSE_TEMP_GPRS(2));
2201                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2202                                           NUM_ES_GPRS(18));
2203                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2204                                            NUM_VS_THREADS(78) |
2205                                            NUM_GS_THREADS(4) |
2206                                            NUM_ES_THREADS(31));
2207                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2208                                             NUM_VS_STACK_ENTRIES(40));
2209                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2210                                             NUM_ES_STACK_ENTRIES(16));
2211         } else if ((rdev->family) == CHIP_RV670) {
2212                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2213                                           NUM_VS_GPRS(44) |
2214                                           NUM_CLAUSE_TEMP_GPRS(2));
2215                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2216                                           NUM_ES_GPRS(17));
2217                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2218                                            NUM_VS_THREADS(78) |
2219                                            NUM_GS_THREADS(4) |
2220                                            NUM_ES_THREADS(31));
2221                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2222                                             NUM_VS_STACK_ENTRIES(64));
2223                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2224                                             NUM_ES_STACK_ENTRIES(64));
2225         }
2226
2227         WREG32(SQ_CONFIG, sq_config);
2228         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
2229         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
2230         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2231         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2232         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2233
2234         if (((rdev->family) == CHIP_RV610) ||
2235             ((rdev->family) == CHIP_RV620) ||
2236             ((rdev->family) == CHIP_RS780) ||
2237             ((rdev->family) == CHIP_RS880)) {
2238                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2239         } else {
2240                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2241         }
2242
2243         /* More default values. 2D/3D driver should adjust as needed */
2244         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2245                                          S1_X(0x4) | S1_Y(0xc)));
2246         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2247                                          S1_X(0x2) | S1_Y(0x2) |
2248                                          S2_X(0xa) | S2_Y(0x6) |
2249                                          S3_X(0x6) | S3_Y(0xa)));
2250         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2251                                              S1_X(0x4) | S1_Y(0xc) |
2252                                              S2_X(0x1) | S2_Y(0x6) |
2253                                              S3_X(0xa) | S3_Y(0xe)));
2254         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2255                                              S5_X(0x0) | S5_Y(0x0) |
2256                                              S6_X(0xb) | S6_Y(0x4) |
2257                                              S7_X(0x7) | S7_Y(0x8)));
2258
2259         WREG32(VGT_STRMOUT_EN, 0);
2260         tmp = rdev->config.r600.max_pipes * 16;
2261         switch (rdev->family) {
2262         case CHIP_RV610:
2263         case CHIP_RV620:
2264         case CHIP_RS780:
2265         case CHIP_RS880:
2266                 tmp += 32;
2267                 break;
2268         case CHIP_RV670:
2269                 tmp += 128;
2270                 break;
2271         default:
2272                 break;
2273         }
2274         if (tmp > 256) {
2275                 tmp = 256;
2276         }
2277         WREG32(VGT_ES_PER_GS, 128);
2278         WREG32(VGT_GS_PER_ES, tmp);
2279         WREG32(VGT_GS_PER_VS, 2);
2280         WREG32(VGT_GS_VERTEX_REUSE, 16);
2281
2282         /* more default values. 2D/3D driver should adjust as needed */
2283         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2284         WREG32(VGT_STRMOUT_EN, 0);
2285         WREG32(SX_MISC, 0);
2286         WREG32(PA_SC_MODE_CNTL, 0);
2287         WREG32(PA_SC_AA_CONFIG, 0);
2288         WREG32(PA_SC_LINE_STIPPLE, 0);
2289         WREG32(SPI_INPUT_Z, 0);
2290         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2291         WREG32(CB_COLOR7_FRAG, 0);
2292
2293         /* Clear render buffer base addresses */
2294         WREG32(CB_COLOR0_BASE, 0);
2295         WREG32(CB_COLOR1_BASE, 0);
2296         WREG32(CB_COLOR2_BASE, 0);
2297         WREG32(CB_COLOR3_BASE, 0);
2298         WREG32(CB_COLOR4_BASE, 0);
2299         WREG32(CB_COLOR5_BASE, 0);
2300         WREG32(CB_COLOR6_BASE, 0);
2301         WREG32(CB_COLOR7_BASE, 0);
2302         WREG32(CB_COLOR7_FRAG, 0);
2303
2304         switch (rdev->family) {
2305         case CHIP_RV610:
2306         case CHIP_RV620:
2307         case CHIP_RS780:
2308         case CHIP_RS880:
2309                 tmp = TC_L2_SIZE(8);
2310                 break;
2311         case CHIP_RV630:
2312         case CHIP_RV635:
2313                 tmp = TC_L2_SIZE(4);
2314                 break;
2315         case CHIP_R600:
2316                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2317                 break;
2318         default:
2319                 tmp = TC_L2_SIZE(0);
2320                 break;
2321         }
2322         WREG32(TC_CNTL, tmp);
2323
2324         tmp = RREG32(HDP_HOST_PATH_CNTL);
2325         WREG32(HDP_HOST_PATH_CNTL, tmp);
2326
2327         tmp = RREG32(ARB_POP);
2328         tmp |= ENABLE_TC128;
2329         WREG32(ARB_POP, tmp);
2330
2331         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2332         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2333                                NUM_CLIP_SEQ(3)));
2334         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2335         WREG32(VC_ENHANCE, 0);
2336 }
2337
2338
2339 /*
2340  * Indirect registers accessor
2341  */
2342 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2343 {
2344         unsigned long flags;
2345         u32 r;
2346
2347         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2348         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2349         (void)RREG32(PCIE_PORT_INDEX);
2350         r = RREG32(PCIE_PORT_DATA);
2351         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2352         return r;
2353 }
2354
2355 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2356 {
2357         unsigned long flags;
2358
2359         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2360         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2361         (void)RREG32(PCIE_PORT_INDEX);
2362         WREG32(PCIE_PORT_DATA, (v));
2363         (void)RREG32(PCIE_PORT_DATA);
2364         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2365 }
2366
2367 /*
2368  * CP & Ring
2369  */
2370 void r600_cp_stop(struct radeon_device *rdev)
2371 {
2372         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2373                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2374         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2375         WREG32(SCRATCH_UMSK, 0);
2376         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2377 }
2378
2379 int r600_init_microcode(struct radeon_device *rdev)
2380 {
2381         const char *chip_name;
2382         const char *rlc_chip_name;
2383         const char *smc_chip_name = "RV770";
2384         size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2385         char fw_name[30];
2386         int err;
2387
2388         DRM_DEBUG("\n");
2389
2390         switch (rdev->family) {
2391         case CHIP_R600:
2392                 chip_name = "R600";
2393                 rlc_chip_name = "R600";
2394                 break;
2395         case CHIP_RV610:
2396                 chip_name = "RV610";
2397                 rlc_chip_name = "R600";
2398                 break;
2399         case CHIP_RV630:
2400                 chip_name = "RV630";
2401                 rlc_chip_name = "R600";
2402                 break;
2403         case CHIP_RV620:
2404                 chip_name = "RV620";
2405                 rlc_chip_name = "R600";
2406                 break;
2407         case CHIP_RV635:
2408                 chip_name = "RV635";
2409                 rlc_chip_name = "R600";
2410                 break;
2411         case CHIP_RV670:
2412                 chip_name = "RV670";
2413                 rlc_chip_name = "R600";
2414                 break;
2415         case CHIP_RS780:
2416         case CHIP_RS880:
2417                 chip_name = "RS780";
2418                 rlc_chip_name = "R600";
2419                 break;
2420         case CHIP_RV770:
2421                 chip_name = "RV770";
2422                 rlc_chip_name = "R700";
2423                 smc_chip_name = "RV770";
2424                 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2425                 break;
2426         case CHIP_RV730:
2427                 chip_name = "RV730";
2428                 rlc_chip_name = "R700";
2429                 smc_chip_name = "RV730";
2430                 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2431                 break;
2432         case CHIP_RV710:
2433                 chip_name = "RV710";
2434                 rlc_chip_name = "R700";
2435                 smc_chip_name = "RV710";
2436                 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2437                 break;
2438         case CHIP_RV740:
2439                 chip_name = "RV730";
2440                 rlc_chip_name = "R700";
2441                 smc_chip_name = "RV740";
2442                 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2443                 break;
2444         case CHIP_CEDAR:
2445                 chip_name = "CEDAR";
2446                 rlc_chip_name = "CEDAR";
2447                 smc_chip_name = "CEDAR";
2448                 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2449                 break;
2450         case CHIP_REDWOOD:
2451                 chip_name = "REDWOOD";
2452                 rlc_chip_name = "REDWOOD";
2453                 smc_chip_name = "REDWOOD";
2454                 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2455                 break;
2456         case CHIP_JUNIPER:
2457                 chip_name = "JUNIPER";
2458                 rlc_chip_name = "JUNIPER";
2459                 smc_chip_name = "JUNIPER";
2460                 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2461                 break;
2462         case CHIP_CYPRESS:
2463         case CHIP_HEMLOCK:
2464                 chip_name = "CYPRESS";
2465                 rlc_chip_name = "CYPRESS";
2466                 smc_chip_name = "CYPRESS";
2467                 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2468                 break;
2469         case CHIP_PALM:
2470                 chip_name = "PALM";
2471                 rlc_chip_name = "SUMO";
2472                 break;
2473         case CHIP_SUMO:
2474                 chip_name = "SUMO";
2475                 rlc_chip_name = "SUMO";
2476                 break;
2477         case CHIP_SUMO2:
2478                 chip_name = "SUMO2";
2479                 rlc_chip_name = "SUMO";
2480                 break;
2481         default: BUG();
2482         }
2483
2484         if (rdev->family >= CHIP_CEDAR) {
2485                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2486                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2487                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2488         } else if (rdev->family >= CHIP_RV770) {
2489                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2490                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2491                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2492         } else {
2493                 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2494                 me_req_size = R600_PM4_UCODE_SIZE * 12;
2495                 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2496         }
2497
2498         DRM_INFO("Loading %s Microcode\n", chip_name);
2499
2500         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
2501         err = reject_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2502         if (err)
2503                 goto out;
2504         if (rdev->pfp_fw->size != pfp_req_size) {
2505                 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",
2506                        rdev->pfp_fw->size, fw_name);
2507                 err = -EINVAL;
2508                 goto out;
2509         }
2510
2511         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
2512         err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
2513         if (err)
2514                 goto out;
2515         if (rdev->me_fw->size != me_req_size) {
2516                 pr_err("r600_cp: Bogus length %zu in firmware \"%s\"\n",
2517                        rdev->me_fw->size, fw_name);
2518                 err = -EINVAL;
2519         }
2520
2521         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", rlc_chip_name);
2522         err = reject_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2523         if (err)
2524                 goto out;
2525         if (rdev->rlc_fw->size != rlc_req_size) {
2526                 pr_err("r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2527                        rdev->rlc_fw->size, fw_name);
2528                 err = -EINVAL;
2529         }
2530
2531         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2532                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", smc_chip_name);
2533                 err = reject_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2534                 if (err) {
2535                         pr_err("smc: error loading firmware \"%s\"\n", fw_name);
2536                         release_firmware(rdev->smc_fw);
2537                         rdev->smc_fw = NULL;
2538                         err = 0;
2539                 } else if (rdev->smc_fw->size != smc_req_size) {
2540                         pr_err("smc: Bogus length %zu in firmware \"%s\"\n",
2541                                rdev->smc_fw->size, fw_name);
2542                         err = -EINVAL;
2543                 }
2544         }
2545
2546 out:
2547         if (err) {
2548                 if (err != -EINVAL)
2549                         pr_err("r600_cp: Failed to load firmware \"%s\"\n",
2550                                fw_name);
2551                 release_firmware(rdev->pfp_fw);
2552                 rdev->pfp_fw = NULL;
2553                 release_firmware(rdev->me_fw);
2554                 rdev->me_fw = NULL;
2555                 release_firmware(rdev->rlc_fw);
2556                 rdev->rlc_fw = NULL;
2557                 release_firmware(rdev->smc_fw);
2558                 rdev->smc_fw = NULL;
2559         }
2560         return err;
2561 }
2562
2563 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2564                       struct radeon_ring *ring)
2565 {
2566         u32 rptr;
2567
2568         if (rdev->wb.enabled)
2569                 rptr = rdev->wb.wb[ring->rptr_offs/4];
2570         else
2571                 rptr = RREG32(R600_CP_RB_RPTR);
2572
2573         return rptr;
2574 }
2575
2576 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2577                       struct radeon_ring *ring)
2578 {
2579         return RREG32(R600_CP_RB_WPTR);
2580 }
2581
2582 void r600_gfx_set_wptr(struct radeon_device *rdev,
2583                        struct radeon_ring *ring)
2584 {
2585         WREG32(R600_CP_RB_WPTR, ring->wptr);
2586         (void)RREG32(R600_CP_RB_WPTR);
2587 }
2588
2589 static int r600_cp_load_microcode(struct radeon_device *rdev)
2590 {
2591         const __be32 *fw_data;
2592         int i;
2593
2594         if (!rdev->me_fw || !rdev->pfp_fw)
2595                 return -EINVAL;
2596
2597         r600_cp_stop(rdev);
2598
2599         WREG32(CP_RB_CNTL,
2600 #ifdef __BIG_ENDIAN
2601                BUF_SWAP_32BIT |
2602 #endif
2603                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2604
2605         /* Reset cp */
2606         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2607         RREG32(GRBM_SOFT_RESET);
2608         mdelay(15);
2609         WREG32(GRBM_SOFT_RESET, 0);
2610
2611         WREG32(CP_ME_RAM_WADDR, 0);
2612
2613         fw_data = (const __be32 *)rdev->me_fw->data;
2614         WREG32(CP_ME_RAM_WADDR, 0);
2615         for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2616                 WREG32(CP_ME_RAM_DATA,
2617                        be32_to_cpup(fw_data++));
2618
2619         fw_data = (const __be32 *)rdev->pfp_fw->data;
2620         WREG32(CP_PFP_UCODE_ADDR, 0);
2621         for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2622                 WREG32(CP_PFP_UCODE_DATA,
2623                        be32_to_cpup(fw_data++));
2624
2625         WREG32(CP_PFP_UCODE_ADDR, 0);
2626         WREG32(CP_ME_RAM_WADDR, 0);
2627         WREG32(CP_ME_RAM_RADDR, 0);
2628         return 0;
2629 }
2630
2631 int r600_cp_start(struct radeon_device *rdev)
2632 {
2633         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2634         int r;
2635         uint32_t cp_me;
2636
2637         r = radeon_ring_lock(rdev, ring, 7);
2638         if (r) {
2639                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2640                 return r;
2641         }
2642         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2643         radeon_ring_write(ring, 0x1);
2644         if (rdev->family >= CHIP_RV770) {
2645                 radeon_ring_write(ring, 0x0);
2646                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2647         } else {
2648                 radeon_ring_write(ring, 0x3);
2649                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2650         }
2651         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2652         radeon_ring_write(ring, 0);
2653         radeon_ring_write(ring, 0);
2654         radeon_ring_unlock_commit(rdev, ring, false);
2655
2656         cp_me = 0xff;
2657         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2658         return 0;
2659 }
2660
2661 int r600_cp_resume(struct radeon_device *rdev)
2662 {
2663         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2664         u32 tmp;
2665         u32 rb_bufsz;
2666         int r;
2667
2668         /* Reset cp */
2669         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2670         RREG32(GRBM_SOFT_RESET);
2671         mdelay(15);
2672         WREG32(GRBM_SOFT_RESET, 0);
2673
2674         /* Set ring buffer size */
2675         rb_bufsz = order_base_2(ring->ring_size / 8);
2676         tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2677 #ifdef __BIG_ENDIAN
2678         tmp |= BUF_SWAP_32BIT;
2679 #endif
2680         WREG32(CP_RB_CNTL, tmp);
2681         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2682
2683         /* Set the write pointer delay */
2684         WREG32(CP_RB_WPTR_DELAY, 0);
2685
2686         /* Initialize the ring buffer's read and write pointers */
2687         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2688         WREG32(CP_RB_RPTR_WR, 0);
2689         ring->wptr = 0;
2690         WREG32(CP_RB_WPTR, ring->wptr);
2691
2692         /* set the wb address whether it's enabled or not */
2693         WREG32(CP_RB_RPTR_ADDR,
2694                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2695         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2696         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2697
2698         if (rdev->wb.enabled)
2699                 WREG32(SCRATCH_UMSK, 0xff);
2700         else {
2701                 tmp |= RB_NO_UPDATE;
2702                 WREG32(SCRATCH_UMSK, 0);
2703         }
2704
2705         mdelay(1);
2706         WREG32(CP_RB_CNTL, tmp);
2707
2708         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2709         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2710
2711         r600_cp_start(rdev);
2712         ring->ready = true;
2713         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2714         if (r) {
2715                 ring->ready = false;
2716                 return r;
2717         }
2718
2719         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2720                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2721
2722         return 0;
2723 }
2724
2725 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2726 {
2727         u32 rb_bufsz;
2728         int r;
2729
2730         /* Align ring size */
2731         rb_bufsz = order_base_2(ring_size / 8);
2732         ring_size = (1 << (rb_bufsz + 1)) * 4;
2733         ring->ring_size = ring_size;
2734         ring->align_mask = 16 - 1;
2735
2736         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2737                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2738                 if (r) {
2739                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2740                         ring->rptr_save_reg = 0;
2741                 }
2742         }
2743 }
2744
2745 void r600_cp_fini(struct radeon_device *rdev)
2746 {
2747         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2748         r600_cp_stop(rdev);
2749         radeon_ring_fini(rdev, ring);
2750         radeon_scratch_free(rdev, ring->rptr_save_reg);
2751 }
2752
2753 /*
2754  * GPU scratch registers helpers function.
2755  */
2756 void r600_scratch_init(struct radeon_device *rdev)
2757 {
2758         int i;
2759
2760         rdev->scratch.num_reg = 7;
2761         rdev->scratch.reg_base = SCRATCH_REG0;
2762         for (i = 0; i < rdev->scratch.num_reg; i++) {
2763                 rdev->scratch.free[i] = true;
2764                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2765         }
2766 }
2767
2768 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2769 {
2770         uint32_t scratch;
2771         uint32_t tmp = 0;
2772         unsigned i;
2773         int r;
2774
2775         r = radeon_scratch_get(rdev, &scratch);
2776         if (r) {
2777                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2778                 return r;
2779         }
2780         WREG32(scratch, 0xCAFEDEAD);
2781         r = radeon_ring_lock(rdev, ring, 3);
2782         if (r) {
2783                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2784                 radeon_scratch_free(rdev, scratch);
2785                 return r;
2786         }
2787         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2788         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2789         radeon_ring_write(ring, 0xDEADBEEF);
2790         radeon_ring_unlock_commit(rdev, ring, false);
2791         for (i = 0; i < rdev->usec_timeout; i++) {
2792                 tmp = RREG32(scratch);
2793                 if (tmp == 0xDEADBEEF)
2794                         break;
2795                 DRM_UDELAY(1);
2796         }
2797         if (i < rdev->usec_timeout) {
2798                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2799         } else {
2800                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2801                           ring->idx, scratch, tmp);
2802                 r = -EINVAL;
2803         }
2804         radeon_scratch_free(rdev, scratch);
2805         return r;
2806 }
2807
2808 /*
2809  * CP fences/semaphores
2810  */
2811
2812 void r600_fence_ring_emit(struct radeon_device *rdev,
2813                           struct radeon_fence *fence)
2814 {
2815         struct radeon_ring *ring = &rdev->ring[fence->ring];
2816         u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2817                 PACKET3_SH_ACTION_ENA;
2818
2819         if (rdev->family >= CHIP_RV770)
2820                 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2821
2822         if (rdev->wb.use_event) {
2823                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2824                 /* flush read cache over gart */
2825                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2826                 radeon_ring_write(ring, cp_coher_cntl);
2827                 radeon_ring_write(ring, 0xFFFFFFFF);
2828                 radeon_ring_write(ring, 0);
2829                 radeon_ring_write(ring, 10); /* poll interval */
2830                 /* EVENT_WRITE_EOP - flush caches, send int */
2831                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2832                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2833                 radeon_ring_write(ring, lower_32_bits(addr));
2834                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2835                 radeon_ring_write(ring, fence->seq);
2836                 radeon_ring_write(ring, 0);
2837         } else {
2838                 /* flush read cache over gart */
2839                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2840                 radeon_ring_write(ring, cp_coher_cntl);
2841                 radeon_ring_write(ring, 0xFFFFFFFF);
2842                 radeon_ring_write(ring, 0);
2843                 radeon_ring_write(ring, 10); /* poll interval */
2844                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2845                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2846                 /* wait for 3D idle clean */
2847                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2848                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2849                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2850                 /* Emit fence sequence & fire IRQ */
2851                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2852                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2853                 radeon_ring_write(ring, fence->seq);
2854                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2855                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2856                 radeon_ring_write(ring, RB_INT_STAT);
2857         }
2858 }
2859
2860 /**
2861  * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2862  *
2863  * @rdev: radeon_device pointer
2864  * @ring: radeon ring buffer object
2865  * @semaphore: radeon semaphore object
2866  * @emit_wait: Is this a sempahore wait?
2867  *
2868  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2869  * from running ahead of semaphore waits.
2870  */
2871 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2872                               struct radeon_ring *ring,
2873                               struct radeon_semaphore *semaphore,
2874                               bool emit_wait)
2875 {
2876         uint64_t addr = semaphore->gpu_addr;
2877         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2878
2879         if (rdev->family < CHIP_CAYMAN)
2880                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2881
2882         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2883         radeon_ring_write(ring, lower_32_bits(addr));
2884         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2885
2886         /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2887         if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
2888                 /* Prevent the PFP from running ahead of the semaphore wait */
2889                 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2890                 radeon_ring_write(ring, 0x0);
2891         }
2892
2893         return true;
2894 }
2895
2896 /**
2897  * r600_copy_cpdma - copy pages using the CP DMA engine
2898  *
2899  * @rdev: radeon_device pointer
2900  * @src_offset: src GPU address
2901  * @dst_offset: dst GPU address
2902  * @num_gpu_pages: number of GPU pages to xfer
2903  * @fence: radeon fence object
2904  *
2905  * Copy GPU paging using the CP DMA engine (r6xx+).
2906  * Used by the radeon ttm implementation to move pages if
2907  * registered as the asic copy callback.
2908  */
2909 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2910                                      uint64_t src_offset, uint64_t dst_offset,
2911                                      unsigned num_gpu_pages,
2912                                      struct reservation_object *resv)
2913 {
2914         struct radeon_fence *fence;
2915         struct radeon_sync sync;
2916         int ring_index = rdev->asic->copy.blit_ring_index;
2917         struct radeon_ring *ring = &rdev->ring[ring_index];
2918         u32 size_in_bytes, cur_size_in_bytes, tmp;
2919         int i, num_loops;
2920         int r = 0;
2921
2922         radeon_sync_create(&sync);
2923
2924         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2925         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2926         r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2927         if (r) {
2928                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2929                 radeon_sync_free(rdev, &sync, NULL);
2930                 return ERR_PTR(r);
2931         }
2932
2933         radeon_sync_resv(rdev, &sync, resv, false);
2934         radeon_sync_rings(rdev, &sync, ring->idx);
2935
2936         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2937         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2938         radeon_ring_write(ring, WAIT_3D_IDLE_bit);
2939         for (i = 0; i < num_loops; i++) {
2940                 cur_size_in_bytes = size_in_bytes;
2941                 if (cur_size_in_bytes > 0x1fffff)
2942                         cur_size_in_bytes = 0x1fffff;
2943                 size_in_bytes -= cur_size_in_bytes;
2944                 tmp = upper_32_bits(src_offset) & 0xff;
2945                 if (size_in_bytes == 0)
2946                         tmp |= PACKET3_CP_DMA_CP_SYNC;
2947                 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
2948                 radeon_ring_write(ring, lower_32_bits(src_offset));
2949                 radeon_ring_write(ring, tmp);
2950                 radeon_ring_write(ring, lower_32_bits(dst_offset));
2951                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2952                 radeon_ring_write(ring, cur_size_in_bytes);
2953                 src_offset += cur_size_in_bytes;
2954                 dst_offset += cur_size_in_bytes;
2955         }
2956         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2957         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2958         radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2959
2960         r = radeon_fence_emit(rdev, &fence, ring->idx);
2961         if (r) {
2962                 radeon_ring_unlock_undo(rdev, ring);
2963                 radeon_sync_free(rdev, &sync, NULL);
2964                 return ERR_PTR(r);
2965         }
2966
2967         radeon_ring_unlock_commit(rdev, ring, false);
2968         radeon_sync_free(rdev, &sync, fence);
2969
2970         return fence;
2971 }
2972
2973 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2974                          uint32_t tiling_flags, uint32_t pitch,
2975                          uint32_t offset, uint32_t obj_size)
2976 {
2977         /* FIXME: implement */
2978         return 0;
2979 }
2980
2981 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2982 {
2983         /* FIXME: implement */
2984 }
2985
2986 static void r600_uvd_init(struct radeon_device *rdev)
2987 {
2988         int r;
2989
2990         if (!rdev->has_uvd)
2991                 return;
2992
2993         r = radeon_uvd_init(rdev);
2994         if (r) {
2995                 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
2996                 /*
2997                  * At this point rdev->uvd.vcpu_bo is NULL which trickles down
2998                  * to early fails uvd_v1_0_resume() and thus nothing happens
2999                  * there. So it is pointless to try to go through that code
3000                  * hence why we disable uvd here.
3001                  */
3002                 rdev->has_uvd = 0;
3003                 return;
3004         }
3005         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3006         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3007 }
3008
3009 static void r600_uvd_start(struct radeon_device *rdev)
3010 {
3011         int r;
3012
3013         if (!rdev->has_uvd)
3014                 return;
3015
3016         r = uvd_v1_0_resume(rdev);
3017         if (r) {
3018                 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
3019                 goto error;
3020         }
3021         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3022         if (r) {
3023                 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3024                 goto error;
3025         }
3026         return;
3027
3028 error:
3029         rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3030 }
3031
3032 static void r600_uvd_resume(struct radeon_device *rdev)
3033 {
3034         struct radeon_ring *ring;
3035         int r;
3036
3037         if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
3038                 return;
3039
3040         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3041         r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
3042         if (r) {
3043                 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
3044                 return;
3045         }
3046         r = uvd_v1_0_init(rdev);
3047         if (r) {
3048                 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
3049                 return;
3050         }
3051 }
3052
3053 static int r600_startup(struct radeon_device *rdev)
3054 {
3055         struct radeon_ring *ring;
3056         int r;
3057
3058         /* enable pcie gen2 link */
3059         r600_pcie_gen2_enable(rdev);
3060
3061         /* scratch needs to be initialized before MC */
3062         r = r600_vram_scratch_init(rdev);
3063         if (r)
3064                 return r;
3065
3066         r600_mc_program(rdev);
3067
3068         if (rdev->flags & RADEON_IS_AGP) {
3069                 r600_agp_enable(rdev);
3070         } else {
3071                 r = r600_pcie_gart_enable(rdev);
3072                 if (r)
3073                         return r;
3074         }
3075         r600_gpu_init(rdev);
3076
3077         /* allocate wb buffer */
3078         r = radeon_wb_init(rdev);
3079         if (r)
3080                 return r;
3081
3082         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3083         if (r) {
3084                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3085                 return r;
3086         }
3087
3088         r600_uvd_start(rdev);
3089
3090         /* Enable IRQ */
3091         if (!rdev->irq.installed) {
3092                 r = radeon_irq_kms_init(rdev);
3093                 if (r)
3094                         return r;
3095         }
3096
3097         r = r600_irq_init(rdev);
3098         if (r) {
3099                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3100                 radeon_irq_kms_fini(rdev);
3101                 return r;
3102         }
3103         r600_irq_set(rdev);
3104
3105         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3106         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3107                              RADEON_CP_PACKET2);
3108         if (r)
3109                 return r;
3110
3111         r = r600_cp_load_microcode(rdev);
3112         if (r)
3113                 return r;
3114         r = r600_cp_resume(rdev);
3115         if (r)
3116                 return r;
3117
3118         r600_uvd_resume(rdev);
3119
3120         r = radeon_ib_pool_init(rdev);
3121         if (r) {
3122                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3123                 return r;
3124         }
3125
3126         r = radeon_audio_init(rdev);
3127         if (r) {
3128                 DRM_ERROR("radeon: audio init failed\n");
3129                 return r;
3130         }
3131
3132         return 0;
3133 }
3134
3135 void r600_vga_set_state(struct radeon_device *rdev, bool state)
3136 {
3137         uint32_t temp;
3138
3139         temp = RREG32(CONFIG_CNTL);
3140         if (state == false) {
3141                 temp &= ~(1<<0);
3142                 temp |= (1<<1);
3143         } else {
3144                 temp &= ~(1<<1);
3145         }
3146         WREG32(CONFIG_CNTL, temp);
3147 }
3148
3149 int r600_resume(struct radeon_device *rdev)
3150 {
3151         int r;
3152
3153         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3154          * posting will perform necessary task to bring back GPU into good
3155          * shape.
3156          */
3157         /* post card */
3158         atom_asic_init(rdev->mode_info.atom_context);
3159
3160         if (rdev->pm.pm_method == PM_METHOD_DPM)
3161                 radeon_pm_resume(rdev);
3162
3163         rdev->accel_working = true;
3164         r = r600_startup(rdev);
3165         if (r) {
3166                 DRM_ERROR("r600 startup failed on resume\n");
3167                 rdev->accel_working = false;
3168                 return r;
3169         }
3170
3171         return r;
3172 }
3173
3174 int r600_suspend(struct radeon_device *rdev)
3175 {
3176         radeon_pm_suspend(rdev);
3177         radeon_audio_fini(rdev);
3178         r600_cp_stop(rdev);
3179         if (rdev->has_uvd) {
3180                 uvd_v1_0_fini(rdev);
3181                 radeon_uvd_suspend(rdev);
3182         }
3183         r600_irq_suspend(rdev);
3184         radeon_wb_disable(rdev);
3185         r600_pcie_gart_disable(rdev);
3186
3187         return 0;
3188 }
3189
3190 /* Plan is to move initialization in that function and use
3191  * helper function so that radeon_device_init pretty much
3192  * do nothing more than calling asic specific function. This
3193  * should also allow to remove a bunch of callback function
3194  * like vram_info.
3195  */
3196 int r600_init(struct radeon_device *rdev)
3197 {
3198         int r;
3199
3200         if (r600_debugfs_mc_info_init(rdev)) {
3201                 DRM_ERROR("Failed to register debugfs file for mc !\n");
3202         }
3203         /* Read BIOS */
3204         if (!radeon_get_bios(rdev)) {
3205                 if (ASIC_IS_AVIVO(rdev))
3206                         return -EINVAL;
3207         }
3208         /* Must be an ATOMBIOS */
3209         if (!rdev->is_atom_bios) {
3210                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3211                 return -EINVAL;
3212         }
3213         r = radeon_atombios_init(rdev);
3214         if (r)
3215                 return r;
3216         /* Post card if necessary */
3217         if (!radeon_card_posted(rdev)) {
3218                 if (!rdev->bios) {
3219                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3220                         return -EINVAL;
3221                 }
3222                 DRM_INFO("GPU not posted. posting now...\n");
3223                 atom_asic_init(rdev->mode_info.atom_context);
3224         }
3225         /* Initialize scratch registers */
3226         r600_scratch_init(rdev);
3227         /* Initialize surface registers */
3228         radeon_surface_init(rdev);
3229         /* Initialize clocks */
3230         radeon_get_clock_info(rdev->ddev);
3231         /* Fence driver */
3232         r = radeon_fence_driver_init(rdev);
3233         if (r)
3234                 return r;
3235         if (rdev->flags & RADEON_IS_AGP) {
3236                 r = radeon_agp_init(rdev);
3237                 if (r)
3238                         radeon_agp_disable(rdev);
3239         }
3240         r = r600_mc_init(rdev);
3241         if (r)
3242                 return r;
3243         /* Memory manager */
3244         r = radeon_bo_init(rdev);
3245         if (r)
3246                 return r;
3247
3248         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3249                 r = r600_init_microcode(rdev);
3250                 if (r) {
3251                         DRM_ERROR("Failed to load firmware!\n");
3252                         /*(DEBLOBBED)*/
3253                 }
3254         }
3255
3256         /* Initialize power management */
3257         radeon_pm_init(rdev);
3258
3259         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3260         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3261
3262         r600_uvd_init(rdev);
3263
3264         rdev->ih.ring_obj = NULL;
3265         r600_ih_ring_init(rdev, 64 * 1024);
3266
3267         r = r600_pcie_gart_init(rdev);
3268         if (r)
3269                 return r;
3270
3271         rdev->accel_working = true;
3272         r = r600_startup(rdev);
3273         if (r) {
3274                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3275                 r600_cp_fini(rdev);
3276                 r600_irq_fini(rdev);
3277                 radeon_wb_fini(rdev);
3278                 radeon_ib_pool_fini(rdev);
3279                 radeon_irq_kms_fini(rdev);
3280                 r600_pcie_gart_fini(rdev);
3281                 rdev->accel_working = false;
3282         }
3283
3284         return 0;
3285 }
3286
3287 void r600_fini(struct radeon_device *rdev)
3288 {
3289         radeon_pm_fini(rdev);
3290         radeon_audio_fini(rdev);
3291         r600_cp_fini(rdev);
3292         r600_irq_fini(rdev);
3293         if (rdev->has_uvd) {
3294                 uvd_v1_0_fini(rdev);
3295                 radeon_uvd_fini(rdev);
3296         }
3297         radeon_wb_fini(rdev);
3298         radeon_ib_pool_fini(rdev);
3299         radeon_irq_kms_fini(rdev);
3300         r600_pcie_gart_fini(rdev);
3301         r600_vram_scratch_fini(rdev);
3302         radeon_agp_fini(rdev);
3303         radeon_gem_fini(rdev);
3304         radeon_fence_driver_fini(rdev);
3305         radeon_bo_fini(rdev);
3306         radeon_atombios_fini(rdev);
3307         kfree(rdev->bios);
3308         rdev->bios = NULL;
3309 }
3310
3311
3312 /*
3313  * CS stuff
3314  */
3315 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3316 {
3317         struct radeon_ring *ring = &rdev->ring[ib->ring];
3318         u32 next_rptr;
3319
3320         if (ring->rptr_save_reg) {
3321                 next_rptr = ring->wptr + 3 + 4;
3322                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3323                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3324                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3325                 radeon_ring_write(ring, next_rptr);
3326         } else if (rdev->wb.enabled) {
3327                 next_rptr = ring->wptr + 5 + 4;
3328                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3329                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3330                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3331                 radeon_ring_write(ring, next_rptr);
3332                 radeon_ring_write(ring, 0);
3333         }
3334
3335         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3336         radeon_ring_write(ring,
3337 #ifdef __BIG_ENDIAN
3338                           (2 << 0) |
3339 #endif
3340                           (ib->gpu_addr & 0xFFFFFFFC));
3341         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3342         radeon_ring_write(ring, ib->length_dw);
3343 }
3344
3345 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3346 {
3347         struct radeon_ib ib;
3348         uint32_t scratch;
3349         uint32_t tmp = 0;
3350         unsigned i;
3351         int r;
3352
3353         r = radeon_scratch_get(rdev, &scratch);
3354         if (r) {
3355                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3356                 return r;
3357         }
3358         WREG32(scratch, 0xCAFEDEAD);
3359         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3360         if (r) {
3361                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3362                 goto free_scratch;
3363         }
3364         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3365         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3366         ib.ptr[2] = 0xDEADBEEF;
3367         ib.length_dw = 3;
3368         r = radeon_ib_schedule(rdev, &ib, NULL, false);
3369         if (r) {
3370                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3371                 goto free_ib;
3372         }
3373         r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3374                 RADEON_USEC_IB_TEST_TIMEOUT));
3375         if (r < 0) {
3376                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3377                 goto free_ib;
3378         } else if (r == 0) {
3379                 DRM_ERROR("radeon: fence wait timed out.\n");
3380                 r = -ETIMEDOUT;
3381                 goto free_ib;
3382         }
3383         r = 0;
3384         for (i = 0; i < rdev->usec_timeout; i++) {
3385                 tmp = RREG32(scratch);
3386                 if (tmp == 0xDEADBEEF)
3387                         break;
3388                 DRM_UDELAY(1);
3389         }
3390         if (i < rdev->usec_timeout) {
3391                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3392         } else {
3393                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3394                           scratch, tmp);
3395                 r = -EINVAL;
3396         }
3397 free_ib:
3398         radeon_ib_free(rdev, &ib);
3399 free_scratch:
3400         radeon_scratch_free(rdev, scratch);
3401         return r;
3402 }
3403
3404 /*
3405  * Interrupts
3406  *
3407  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3408  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3409  * writing to the ring and the GPU consuming, the GPU writes to the ring
3410  * and host consumes.  As the host irq handler processes interrupts, it
3411  * increments the rptr.  When the rptr catches up with the wptr, all the
3412  * current interrupts have been processed.
3413  */
3414
3415 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3416 {
3417         u32 rb_bufsz;
3418
3419         /* Align ring size */
3420         rb_bufsz = order_base_2(ring_size / 4);
3421         ring_size = (1 << rb_bufsz) * 4;
3422         rdev->ih.ring_size = ring_size;
3423         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3424         rdev->ih.rptr = 0;
3425 }
3426
3427 int r600_ih_ring_alloc(struct radeon_device *rdev)
3428 {
3429         int r;
3430
3431         /* Allocate ring buffer */
3432         if (rdev->ih.ring_obj == NULL) {
3433                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3434                                      PAGE_SIZE, true,
3435                                      RADEON_GEM_DOMAIN_GTT, 0,
3436                                      NULL, NULL, &rdev->ih.ring_obj);
3437                 if (r) {
3438                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3439                         return r;
3440                 }
3441                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3442                 if (unlikely(r != 0))
3443                         return r;
3444                 r = radeon_bo_pin(rdev->ih.ring_obj,
3445                                   RADEON_GEM_DOMAIN_GTT,
3446                                   &rdev->ih.gpu_addr);
3447                 if (r) {
3448                         radeon_bo_unreserve(rdev->ih.ring_obj);
3449                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3450                         return r;
3451                 }
3452                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3453                                    (void **)&rdev->ih.ring);
3454                 radeon_bo_unreserve(rdev->ih.ring_obj);
3455                 if (r) {
3456                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3457                         return r;
3458                 }
3459         }
3460         return 0;
3461 }
3462
3463 void r600_ih_ring_fini(struct radeon_device *rdev)
3464 {
3465         int r;
3466         if (rdev->ih.ring_obj) {
3467                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3468                 if (likely(r == 0)) {
3469                         radeon_bo_kunmap(rdev->ih.ring_obj);
3470                         radeon_bo_unpin(rdev->ih.ring_obj);
3471                         radeon_bo_unreserve(rdev->ih.ring_obj);
3472                 }
3473                 radeon_bo_unref(&rdev->ih.ring_obj);
3474                 rdev->ih.ring = NULL;
3475                 rdev->ih.ring_obj = NULL;
3476         }
3477 }
3478
3479 void r600_rlc_stop(struct radeon_device *rdev)
3480 {
3481
3482         if ((rdev->family >= CHIP_RV770) &&
3483             (rdev->family <= CHIP_RV740)) {
3484                 /* r7xx asics need to soft reset RLC before halting */
3485                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3486                 RREG32(SRBM_SOFT_RESET);
3487                 mdelay(15);
3488                 WREG32(SRBM_SOFT_RESET, 0);
3489                 RREG32(SRBM_SOFT_RESET);
3490         }
3491
3492         WREG32(RLC_CNTL, 0);
3493 }
3494
3495 static void r600_rlc_start(struct radeon_device *rdev)
3496 {
3497         WREG32(RLC_CNTL, RLC_ENABLE);
3498 }
3499
3500 static int r600_rlc_resume(struct radeon_device *rdev)
3501 {
3502         u32 i;
3503         const __be32 *fw_data;
3504
3505         if (!rdev->rlc_fw)
3506                 return -EINVAL;
3507
3508         r600_rlc_stop(rdev);
3509
3510         WREG32(RLC_HB_CNTL, 0);
3511
3512         WREG32(RLC_HB_BASE, 0);
3513         WREG32(RLC_HB_RPTR, 0);
3514         WREG32(RLC_HB_WPTR, 0);
3515         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3516         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3517         WREG32(RLC_MC_CNTL, 0);
3518         WREG32(RLC_UCODE_CNTL, 0);
3519
3520         fw_data = (const __be32 *)rdev->rlc_fw->data;
3521         if (rdev->family >= CHIP_RV770) {
3522                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3523                         WREG32(RLC_UCODE_ADDR, i);
3524                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3525                 }
3526         } else {
3527                 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3528                         WREG32(RLC_UCODE_ADDR, i);
3529                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3530                 }
3531         }
3532         WREG32(RLC_UCODE_ADDR, 0);
3533
3534         r600_rlc_start(rdev);
3535
3536         return 0;
3537 }
3538
3539 static void r600_enable_interrupts(struct radeon_device *rdev)
3540 {
3541         u32 ih_cntl = RREG32(IH_CNTL);
3542         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3543
3544         ih_cntl |= ENABLE_INTR;
3545         ih_rb_cntl |= IH_RB_ENABLE;
3546         WREG32(IH_CNTL, ih_cntl);
3547         WREG32(IH_RB_CNTL, ih_rb_cntl);
3548         rdev->ih.enabled = true;
3549 }
3550
3551 void r600_disable_interrupts(struct radeon_device *rdev)
3552 {
3553         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3554         u32 ih_cntl = RREG32(IH_CNTL);
3555
3556         ih_rb_cntl &= ~IH_RB_ENABLE;
3557         ih_cntl &= ~ENABLE_INTR;
3558         WREG32(IH_RB_CNTL, ih_rb_cntl);
3559         WREG32(IH_CNTL, ih_cntl);
3560         /* set rptr, wptr to 0 */
3561         WREG32(IH_RB_RPTR, 0);
3562         WREG32(IH_RB_WPTR, 0);
3563         rdev->ih.enabled = false;
3564         rdev->ih.rptr = 0;
3565 }
3566
3567 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3568 {
3569         u32 tmp;
3570
3571         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3572         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3573         WREG32(DMA_CNTL, tmp);
3574         WREG32(GRBM_INT_CNTL, 0);
3575         WREG32(DxMODE_INT_MASK, 0);
3576         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3577         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3578         if (ASIC_IS_DCE3(rdev)) {
3579                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3580                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3581                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3582                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3583                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3584                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3585                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3586                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3587                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3588                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3589                 if (ASIC_IS_DCE32(rdev)) {
3590                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3591                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3592                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3593                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3594                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3595                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3596                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3597                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3598                 } else {
3599                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3600                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3601                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3602                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3603                 }
3604         } else {
3605                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3606                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3607                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3608                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3609                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3610                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3611                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3612                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3613                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3614                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3615                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3616                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3617         }
3618 }
3619
3620 int r600_irq_init(struct radeon_device *rdev)
3621 {
3622         int ret = 0;
3623         int rb_bufsz;
3624         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3625
3626         /* allocate ring */
3627         ret = r600_ih_ring_alloc(rdev);
3628         if (ret)
3629                 return ret;
3630
3631         /* disable irqs */
3632         r600_disable_interrupts(rdev);
3633
3634         /* init rlc */
3635         if (rdev->family >= CHIP_CEDAR)
3636                 ret = evergreen_rlc_resume(rdev);
3637         else
3638                 ret = r600_rlc_resume(rdev);
3639         if (ret) {
3640                 r600_ih_ring_fini(rdev);
3641                 return ret;
3642         }
3643
3644         /* setup interrupt control */
3645         /* set dummy read address to ring address */
3646         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3647         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3648         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3649          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3650          */
3651         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3652         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3653         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3654         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3655
3656         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3657         rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3658
3659         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3660                       IH_WPTR_OVERFLOW_CLEAR |
3661                       (rb_bufsz << 1));
3662
3663         if (rdev->wb.enabled)
3664                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3665
3666         /* set the writeback address whether it's enabled or not */
3667         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3668         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3669
3670         WREG32(IH_RB_CNTL, ih_rb_cntl);
3671
3672         /* set rptr, wptr to 0 */
3673         WREG32(IH_RB_RPTR, 0);
3674         WREG32(IH_RB_WPTR, 0);
3675
3676         /* Default settings for IH_CNTL (disabled at first) */
3677         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3678         /* RPTR_REARM only works if msi's are enabled */
3679         if (rdev->msi_enabled)
3680                 ih_cntl |= RPTR_REARM;
3681         WREG32(IH_CNTL, ih_cntl);
3682
3683         /* force the active interrupt state to all disabled */
3684         if (rdev->family >= CHIP_CEDAR)
3685                 evergreen_disable_interrupt_state(rdev);
3686         else
3687                 r600_disable_interrupt_state(rdev);
3688
3689         /* at this point everything should be setup correctly to enable master */
3690         pci_set_master(rdev->pdev);
3691
3692         /* enable irqs */
3693         r600_enable_interrupts(rdev);
3694
3695         return ret;
3696 }
3697
3698 void r600_irq_suspend(struct radeon_device *rdev)
3699 {
3700         r600_irq_disable(rdev);
3701         r600_rlc_stop(rdev);
3702 }
3703
3704 void r600_irq_fini(struct radeon_device *rdev)
3705 {
3706         r600_irq_suspend(rdev);
3707         r600_ih_ring_fini(rdev);
3708 }
3709
3710 int r600_irq_set(struct radeon_device *rdev)
3711 {
3712         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3713         u32 mode_int = 0;
3714         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3715         u32 grbm_int_cntl = 0;
3716         u32 hdmi0, hdmi1;
3717         u32 dma_cntl;
3718         u32 thermal_int = 0;
3719
3720         if (!rdev->irq.installed) {
3721                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3722                 return -EINVAL;
3723         }
3724         /* don't enable anything if the ih is disabled */
3725         if (!rdev->ih.enabled) {
3726                 r600_disable_interrupts(rdev);
3727                 /* force the active interrupt state to all disabled */
3728                 r600_disable_interrupt_state(rdev);
3729                 return 0;
3730         }
3731
3732         if (ASIC_IS_DCE3(rdev)) {
3733                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3734                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3735                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3736                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3737                 if (ASIC_IS_DCE32(rdev)) {
3738                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3739                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3740                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3741                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3742                 } else {
3743                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3744                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3745                 }
3746         } else {
3747                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3748                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3749                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3750                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3751                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3752         }
3753
3754         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3755
3756         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3757                 thermal_int = RREG32(CG_THERMAL_INT) &
3758                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3759         } else if (rdev->family >= CHIP_RV770) {
3760                 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3761                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3762         }
3763         if (rdev->irq.dpm_thermal) {
3764                 DRM_DEBUG("dpm thermal\n");
3765                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3766         }
3767
3768         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3769                 DRM_DEBUG("r600_irq_set: sw int\n");
3770                 cp_int_cntl |= RB_INT_ENABLE;
3771                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3772         }
3773
3774         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3775                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3776                 dma_cntl |= TRAP_ENABLE;
3777         }
3778
3779         if (rdev->irq.crtc_vblank_int[0] ||
3780             atomic_read(&rdev->irq.pflip[0])) {
3781                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3782                 mode_int |= D1MODE_VBLANK_INT_MASK;
3783         }
3784         if (rdev->irq.crtc_vblank_int[1] ||
3785             atomic_read(&rdev->irq.pflip[1])) {
3786                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3787                 mode_int |= D2MODE_VBLANK_INT_MASK;
3788         }
3789         if (rdev->irq.hpd[0]) {
3790                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3791                 hpd1 |= DC_HPDx_INT_EN;
3792         }
3793         if (rdev->irq.hpd[1]) {
3794                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3795                 hpd2 |= DC_HPDx_INT_EN;
3796         }
3797         if (rdev->irq.hpd[2]) {
3798                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3799                 hpd3 |= DC_HPDx_INT_EN;
3800         }
3801         if (rdev->irq.hpd[3]) {
3802                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3803                 hpd4 |= DC_HPDx_INT_EN;
3804         }
3805         if (rdev->irq.hpd[4]) {
3806                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3807                 hpd5 |= DC_HPDx_INT_EN;
3808         }
3809         if (rdev->irq.hpd[5]) {
3810                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3811                 hpd6 |= DC_HPDx_INT_EN;
3812         }
3813         if (rdev->irq.afmt[0]) {
3814                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3815                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3816         }
3817         if (rdev->irq.afmt[1]) {
3818                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3819                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3820         }
3821
3822         WREG32(CP_INT_CNTL, cp_int_cntl);
3823         WREG32(DMA_CNTL, dma_cntl);
3824         WREG32(DxMODE_INT_MASK, mode_int);
3825         WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3826         WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3827         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3828         if (ASIC_IS_DCE3(rdev)) {
3829                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3830                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3831                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3832                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3833                 if (ASIC_IS_DCE32(rdev)) {
3834                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3835                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3836                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3837                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3838                 } else {
3839                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3840                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3841                 }
3842         } else {
3843                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3844                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3845                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3846                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3847                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3848         }
3849         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3850                 WREG32(CG_THERMAL_INT, thermal_int);
3851         } else if (rdev->family >= CHIP_RV770) {
3852                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3853         }
3854
3855         /* posting read */
3856         RREG32(R_000E50_SRBM_STATUS);
3857
3858         return 0;
3859 }
3860
3861 static void r600_irq_ack(struct radeon_device *rdev)
3862 {
3863         u32 tmp;
3864
3865         if (ASIC_IS_DCE3(rdev)) {
3866                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3867                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3868                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3869                 if (ASIC_IS_DCE32(rdev)) {
3870                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3871                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3872                 } else {
3873                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3874                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3875                 }
3876         } else {
3877                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3878                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3879                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3880                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3881                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3882         }
3883         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3884         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3885
3886         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3887                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3888         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3889                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3890         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3891                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3892         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3893                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3894         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3895                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3896         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3897                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3898         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3899                 if (ASIC_IS_DCE3(rdev)) {
3900                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3901                         tmp |= DC_HPDx_INT_ACK;
3902                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3903                 } else {
3904                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3905                         tmp |= DC_HPDx_INT_ACK;
3906                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3907                 }
3908         }
3909         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3910                 if (ASIC_IS_DCE3(rdev)) {
3911                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3912                         tmp |= DC_HPDx_INT_ACK;
3913                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3914                 } else {
3915                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3916                         tmp |= DC_HPDx_INT_ACK;
3917                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3918                 }
3919         }
3920         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3921                 if (ASIC_IS_DCE3(rdev)) {
3922                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3923                         tmp |= DC_HPDx_INT_ACK;
3924                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3925                 } else {
3926                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3927                         tmp |= DC_HPDx_INT_ACK;
3928                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3929                 }
3930         }
3931         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3932                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3933                 tmp |= DC_HPDx_INT_ACK;
3934                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3935         }
3936         if (ASIC_IS_DCE32(rdev)) {
3937                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3938                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3939                         tmp |= DC_HPDx_INT_ACK;
3940                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3941                 }
3942                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3943                         tmp = RREG32(DC_HPD6_INT_CONTROL);
3944                         tmp |= DC_HPDx_INT_ACK;
3945                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3946                 }
3947                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3948                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3949                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3950                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3951                 }
3952                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3953                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3954                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3955                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3956                 }
3957         } else {
3958                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3959                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3960                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3961                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3962                 }
3963                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3964                         if (ASIC_IS_DCE3(rdev)) {
3965                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3966                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3967                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3968                         } else {
3969                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3970                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3971                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3972                         }
3973                 }
3974         }
3975 }
3976
3977 void r600_irq_disable(struct radeon_device *rdev)
3978 {
3979         r600_disable_interrupts(rdev);
3980         /* Wait and acknowledge irq */
3981         mdelay(1);
3982         r600_irq_ack(rdev);
3983         r600_disable_interrupt_state(rdev);
3984 }
3985
3986 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3987 {
3988         u32 wptr, tmp;
3989
3990         if (rdev->wb.enabled)
3991                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3992         else
3993                 wptr = RREG32(IH_RB_WPTR);
3994
3995         if (wptr & RB_OVERFLOW) {
3996                 wptr &= ~RB_OVERFLOW;
3997                 /* When a ring buffer overflow happen start parsing interrupt
3998                  * from the last not overwritten vector (wptr + 16). Hopefully
3999                  * this should allow us to catchup.
4000                  */
4001                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4002                          wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
4003                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4004                 tmp = RREG32(IH_RB_CNTL);
4005                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4006                 WREG32(IH_RB_CNTL, tmp);
4007         }
4008         return (wptr & rdev->ih.ptr_mask);
4009 }
4010
4011 /*        r600 IV Ring
4012  * Each IV ring entry is 128 bits:
4013  * [7:0]    - interrupt source id
4014  * [31:8]   - reserved
4015  * [59:32]  - interrupt source data
4016  * [127:60]  - reserved
4017  *
4018  * The basic interrupt vector entries
4019  * are decoded as follows:
4020  * src_id  src_data  description
4021  *      1         0  D1 Vblank
4022  *      1         1  D1 Vline
4023  *      5         0  D2 Vblank
4024  *      5         1  D2 Vline
4025  *     19         0  FP Hot plug detection A
4026  *     19         1  FP Hot plug detection B
4027  *     19         2  DAC A auto-detection
4028  *     19         3  DAC B auto-detection
4029  *     21         4  HDMI block A
4030  *     21         5  HDMI block B
4031  *    176         -  CP_INT RB
4032  *    177         -  CP_INT IB1
4033  *    178         -  CP_INT IB2
4034  *    181         -  EOP Interrupt
4035  *    233         -  GUI Idle
4036  *
4037  * Note, these are based on r600 and may need to be
4038  * adjusted or added to on newer asics
4039  */
4040
4041 int r600_irq_process(struct radeon_device *rdev)
4042 {
4043         u32 wptr;
4044         u32 rptr;
4045         u32 src_id, src_data;
4046         u32 ring_index;
4047         bool queue_hotplug = false;
4048         bool queue_hdmi = false;
4049         bool queue_thermal = false;
4050
4051         if (!rdev->ih.enabled || rdev->shutdown)
4052                 return IRQ_NONE;
4053
4054         /* No MSIs, need a dummy read to flush PCI DMAs */
4055         if (!rdev->msi_enabled)
4056                 RREG32(IH_RB_WPTR);
4057
4058         wptr = r600_get_ih_wptr(rdev);
4059
4060 restart_ih:
4061         /* is somebody else already processing irqs? */
4062         if (atomic_xchg(&rdev->ih.lock, 1))
4063                 return IRQ_NONE;
4064
4065         rptr = rdev->ih.rptr;
4066         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4067
4068         /* Order reading of wptr vs. reading of IH ring data */
4069         rmb();
4070
4071         /* display interrupts */
4072         r600_irq_ack(rdev);
4073
4074         while (rptr != wptr) {
4075                 /* wptr/rptr are in bytes! */
4076                 ring_index = rptr / 4;
4077                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4078                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4079
4080                 switch (src_id) {
4081                 case 1: /* D1 vblank/vline */
4082                         switch (src_data) {
4083                         case 0: /* D1 vblank */
4084                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4085                                         DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
4086
4087                                 if (rdev->irq.crtc_vblank_int[0]) {
4088                                         drm_handle_vblank(rdev->ddev, 0);
4089                                         rdev->pm.vblank_sync = true;
4090                                         wake_up(&rdev->irq.vblank_queue);
4091                                 }
4092                                 if (atomic_read(&rdev->irq.pflip[0]))
4093                                         radeon_crtc_handle_vblank(rdev, 0);
4094                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4095                                 DRM_DEBUG("IH: D1 vblank\n");
4096
4097                                 break;
4098                         case 1: /* D1 vline */
4099                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4100                                     DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
4101
4102                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4103                                 DRM_DEBUG("IH: D1 vline\n");
4104
4105                                 break;
4106                         default:
4107                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4108                                 break;
4109                         }
4110                         break;
4111                 case 5: /* D2 vblank/vline */
4112                         switch (src_data) {
4113                         case 0: /* D2 vblank */
4114                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4115                                         DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
4116
4117                                 if (rdev->irq.crtc_vblank_int[1]) {
4118                                         drm_handle_vblank(rdev->ddev, 1);
4119                                         rdev->pm.vblank_sync = true;
4120                                         wake_up(&rdev->irq.vblank_queue);
4121                                 }
4122                                 if (atomic_read(&rdev->irq.pflip[1]))
4123                                         radeon_crtc_handle_vblank(rdev, 1);
4124                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4125                                 DRM_DEBUG("IH: D2 vblank\n");
4126
4127                                 break;
4128                         case 1: /* D1 vline */
4129                                 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4130                                         DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
4131
4132                                 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4133                                 DRM_DEBUG("IH: D2 vline\n");
4134
4135                                 break;
4136                         default:
4137                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4138                                 break;
4139                         }
4140                         break;
4141                 case 9: /* D1 pflip */
4142                         DRM_DEBUG("IH: D1 flip\n");
4143                         if (radeon_use_pflipirq > 0)
4144                                 radeon_crtc_handle_flip(rdev, 0);
4145                         break;
4146                 case 11: /* D2 pflip */
4147                         DRM_DEBUG("IH: D2 flip\n");
4148                         if (radeon_use_pflipirq > 0)
4149                                 radeon_crtc_handle_flip(rdev, 1);
4150                         break;
4151                 case 19: /* HPD/DAC hotplug */
4152                         switch (src_data) {
4153                         case 0:
4154                                 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4155                                         DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n");
4156
4157                                 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4158                                 queue_hotplug = true;
4159                                 DRM_DEBUG("IH: HPD1\n");
4160                                 break;
4161                         case 1:
4162                                 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4163                                         DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n");
4164
4165                                 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4166                                 queue_hotplug = true;
4167                                 DRM_DEBUG("IH: HPD2\n");
4168                                 break;
4169                         case 4:
4170                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4171                                         DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n");
4172
4173                                 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4174                                 queue_hotplug = true;
4175                                 DRM_DEBUG("IH: HPD3\n");
4176                                 break;
4177                         case 5:
4178                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4179                                         DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n");
4180
4181                                 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4182                                 queue_hotplug = true;
4183                                 DRM_DEBUG("IH: HPD4\n");
4184                                 break;
4185                         case 10:
4186                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4187                                         DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n");
4188
4189                                 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4190                                 queue_hotplug = true;
4191                                 DRM_DEBUG("IH: HPD5\n");
4192                                 break;
4193                         case 12:
4194                                 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4195                                         DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n");
4196
4197                                 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4198                                 queue_hotplug = true;
4199                                 DRM_DEBUG("IH: HPD6\n");
4200
4201                                 break;
4202                         default:
4203                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4204                                 break;
4205                         }
4206                         break;
4207                 case 21: /* hdmi */
4208                         switch (src_data) {
4209                         case 4:
4210                                 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4211                                         DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n");
4212
4213                                 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4214                                 queue_hdmi = true;
4215                                 DRM_DEBUG("IH: HDMI0\n");
4216
4217                                 break;
4218                         case 5:
4219                                 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4220                                         DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n");
4221
4222                                 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4223                                 queue_hdmi = true;
4224                                 DRM_DEBUG("IH: HDMI1\n");
4225
4226                                 break;
4227                         default:
4228                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4229                                 break;
4230                         }
4231                         break;
4232                 case 124: /* UVD */
4233                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4234                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4235                         break;
4236                 case 176: /* CP_INT in ring buffer */
4237                 case 177: /* CP_INT in IB1 */
4238                 case 178: /* CP_INT in IB2 */
4239                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4240                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4241                         break;
4242                 case 181: /* CP EOP event */
4243                         DRM_DEBUG("IH: CP EOP\n");
4244                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4245                         break;
4246                 case 224: /* DMA trap event */
4247                         DRM_DEBUG("IH: DMA trap\n");
4248                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4249                         break;
4250                 case 230: /* thermal low to high */
4251                         DRM_DEBUG("IH: thermal low to high\n");
4252                         rdev->pm.dpm.thermal.high_to_low = false;
4253                         queue_thermal = true;
4254                         break;
4255                 case 231: /* thermal high to low */
4256                         DRM_DEBUG("IH: thermal high to low\n");
4257                         rdev->pm.dpm.thermal.high_to_low = true;
4258                         queue_thermal = true;
4259                         break;
4260                 case 233: /* GUI IDLE */
4261                         DRM_DEBUG("IH: GUI idle\n");
4262                         break;
4263                 default:
4264                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4265                         break;
4266                 }
4267
4268                 /* wptr/rptr are in bytes! */
4269                 rptr += 16;
4270                 rptr &= rdev->ih.ptr_mask;
4271                 WREG32(IH_RB_RPTR, rptr);
4272         }
4273         if (queue_hotplug)
4274                 schedule_delayed_work(&rdev->hotplug_work, 0);
4275         if (queue_hdmi)
4276                 schedule_work(&rdev->audio_work);
4277         if (queue_thermal && rdev->pm.dpm_enabled)
4278                 schedule_work(&rdev->pm.dpm.thermal.work);
4279         rdev->ih.rptr = rptr;
4280         atomic_set(&rdev->ih.lock, 0);
4281
4282         /* make sure wptr hasn't changed while processing */
4283         wptr = r600_get_ih_wptr(rdev);
4284         if (wptr != rptr)
4285                 goto restart_ih;
4286
4287         return IRQ_HANDLED;
4288 }
4289
4290 /*
4291  * Debugfs info
4292  */
4293 #if defined(CONFIG_DEBUG_FS)
4294
4295 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4296 {
4297         struct drm_info_node *node = (struct drm_info_node *) m->private;
4298         struct drm_device *dev = node->minor->dev;
4299         struct radeon_device *rdev = dev->dev_private;
4300
4301         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4302         DREG32_SYS(m, rdev, VM_L2_STATUS);
4303         return 0;
4304 }
4305
4306 static struct drm_info_list r600_mc_info_list[] = {
4307         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4308 };
4309 #endif
4310
4311 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4312 {
4313 #if defined(CONFIG_DEBUG_FS)
4314         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4315 #else
4316         return 0;
4317 #endif
4318 }
4319
4320 /**
4321  * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4322  * rdev: radeon device structure
4323  *
4324  * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4325  * through the ring buffer. This leads to corruption in rendering, see
4326  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4327  * directly perform the HDP flush by writing the register through MMIO.
4328  */
4329 void r600_mmio_hdp_flush(struct radeon_device *rdev)
4330 {
4331         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4332          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4333          * This seems to cause problems on some AGP cards. Just use the old
4334          * method for them.
4335          */
4336         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4337             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4338                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4339                 u32 tmp;
4340
4341                 WREG32(HDP_DEBUG1, 0);
4342                 tmp = readl((void __iomem *)ptr);
4343         } else
4344                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4345 }
4346
4347 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4348 {
4349         u32 link_width_cntl, mask;
4350
4351         if (rdev->flags & RADEON_IS_IGP)
4352                 return;
4353
4354         if (!(rdev->flags & RADEON_IS_PCIE))
4355                 return;
4356
4357         /* x2 cards have a special sequence */
4358         if (ASIC_IS_X2(rdev))
4359                 return;
4360
4361         radeon_gui_idle(rdev);
4362
4363         switch (lanes) {
4364         case 0:
4365                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4366                 break;
4367         case 1:
4368                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4369                 break;
4370         case 2:
4371                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4372                 break;
4373         case 4:
4374                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4375                 break;
4376         case 8:
4377                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4378                 break;
4379         case 12:
4380                 /* not actually supported */
4381                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4382                 break;
4383         case 16:
4384                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4385                 break;
4386         default:
4387                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4388                 return;
4389         }
4390
4391         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4392         link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4393         link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4394         link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4395                             R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4396
4397         WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4398 }
4399
4400 int r600_get_pcie_lanes(struct radeon_device *rdev)
4401 {
4402         u32 link_width_cntl;
4403
4404         if (rdev->flags & RADEON_IS_IGP)
4405                 return 0;
4406
4407         if (!(rdev->flags & RADEON_IS_PCIE))
4408                 return 0;
4409
4410         /* x2 cards have a special sequence */
4411         if (ASIC_IS_X2(rdev))
4412                 return 0;
4413
4414         radeon_gui_idle(rdev);
4415
4416         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4417
4418         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4419         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4420                 return 1;
4421         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4422                 return 2;
4423         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4424                 return 4;
4425         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4426                 return 8;
4427         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4428                 /* not actually supported */
4429                 return 12;
4430         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4431         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4432         default:
4433                 return 16;
4434         }
4435 }
4436
4437 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4438 {
4439         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4440         u16 link_cntl2;
4441
4442         if (radeon_pcie_gen2 == 0)
4443                 return;
4444
4445         if (rdev->flags & RADEON_IS_IGP)
4446                 return;
4447
4448         if (!(rdev->flags & RADEON_IS_PCIE))
4449                 return;
4450
4451         /* x2 cards have a special sequence */
4452         if (ASIC_IS_X2(rdev))
4453                 return;
4454
4455         /* only RV6xx+ chips are supported */
4456         if (rdev->family <= CHIP_R600)
4457                 return;
4458
4459         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4460                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4461                 return;
4462
4463         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4464         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4465                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4466                 return;
4467         }
4468
4469         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4470
4471         /* 55 nm r6xx asics */
4472         if ((rdev->family == CHIP_RV670) ||
4473             (rdev->family == CHIP_RV620) ||
4474             (rdev->family == CHIP_RV635)) {
4475                 /* advertise upconfig capability */
4476                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4477                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4478                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4479                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4480                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4481                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4482                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4483                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4484                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4485                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4486                 } else {
4487                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4488                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4489                 }
4490         }
4491
4492         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4493         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4494             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4495
4496                 /* 55 nm r6xx asics */
4497                 if ((rdev->family == CHIP_RV670) ||
4498                     (rdev->family == CHIP_RV620) ||
4499                     (rdev->family == CHIP_RV635)) {
4500                         WREG32(MM_CFGREGS_CNTL, 0x8);
4501                         link_cntl2 = RREG32(0x4088);
4502                         WREG32(MM_CFGREGS_CNTL, 0);
4503                         /* not supported yet */
4504                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4505                                 return;
4506                 }
4507
4508                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4509                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4510                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4511                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4512                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4513                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4514
4515                 tmp = RREG32(0x541c);
4516                 WREG32(0x541c, tmp | 0x8);
4517                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4518                 link_cntl2 = RREG16(0x4088);
4519                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4520                 link_cntl2 |= 0x2;
4521                 WREG16(0x4088, link_cntl2);
4522                 WREG32(MM_CFGREGS_CNTL, 0);
4523
4524                 if ((rdev->family == CHIP_RV670) ||
4525                     (rdev->family == CHIP_RV620) ||
4526                     (rdev->family == CHIP_RV635)) {
4527                         training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4528                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4529                         WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4530                 } else {
4531                         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4532                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4533                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4534                 }
4535
4536                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4537                 speed_cntl |= LC_GEN2_EN_STRAP;
4538                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4539
4540         } else {
4541                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4542                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4543                 if (1)
4544                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4545                 else
4546                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4547                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4548         }
4549 }
4550
4551 /**
4552  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4553  *
4554  * @rdev: radeon_device pointer
4555  *
4556  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4557  * Returns the 64 bit clock counter snapshot.
4558  */
4559 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4560 {
4561         uint64_t clock;
4562
4563         mutex_lock(&rdev->gpu_clock_mutex);
4564         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4565         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4566                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4567         mutex_unlock(&rdev->gpu_clock_mutex);
4568         return clock;
4569 }