drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_mode.h"
  35 #include "r600d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define PFP_UCODE_SIZE 576
  40 #define PM4_UCODE_SIZE 1792
  41 #define R700_PFP_UCODE_SIZE 848
  42 #define R700_PM4_UCODE_SIZE 1360
  43
  44 /* Firmware Names */
  45 /*(DEBLOBBED)*/
  46
  47 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  48
  49 /* r600,rv610,rv630,rv620,rv635,rv670 */
  50 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  51 void r600_gpu_init(struct radeon_device *rdev);
  52 void r600_fini(struct radeon_device *rdev);
  53
  54 /*
  55  * R600 PCIE GART
  56  */
  57 int r600_gart_clear_page(struct radeon_device *rdev, int i)
  58 {
  59         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  60         u64 pte;
  61
  62         if (i < 0 || i > rdev->gart.num_gpu_pages)
  63                 return -EINVAL;
  64         pte = 0;
  65         writeq(pte, ((void __iomem *)ptr) + (i * 8));
  66         return 0;
  67 }
  68
  69 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
  70 {
  71         unsigned i;
  72         u32 tmp;
  73
  74         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
  75         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
  76         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
  77         for (i = 0; i < rdev->usec_timeout; i++) {
  78                 /* read MC_STATUS */
  79                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
  80                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
  81                 if (tmp == 2) {
  82                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
  83                         return;
  84                 }
  85                 if (tmp) {
  86                         return;
  87                 }
  88                 udelay(1);
  89         }
  90 }
  91
  92 int r600_pcie_gart_init(struct radeon_device *rdev)
  93 {
  94         int r;
  95
  96         if (rdev->gart.table.vram.robj) {
  97                 WARN(1, "R600 PCIE GART already initialized.\n");
  98                 return 0;
  99         }
 100         /* Initialize common gart structure */
 101         r = radeon_gart_init(rdev);
 102         if (r)
 103                 return r;
 104         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 105         return radeon_gart_table_vram_alloc(rdev);
 106 }
 107
 108 int r600_pcie_gart_enable(struct radeon_device *rdev)
 109 {
 110         u32 tmp;
 111         int r, i;
 112
 113         if (rdev->gart.table.vram.robj == NULL) {
 114                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 115                 return -EINVAL;
 116         }
 117         r = radeon_gart_table_vram_pin(rdev);
 118         if (r)
 119                 return r;
 120
 121         /* Setup L2 cache */
 122         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 123                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 124                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 125         WREG32(VM_L2_CNTL2, 0);
 126         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 127         /* Setup TLB control */
 128         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 129                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 130                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 131                 ENABLE_WAIT_L2_QUERY;
 132         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 133         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 134         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 135         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 136         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 137         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 138         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 139         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 140         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 141         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 142         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 143         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 144         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 145         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 146         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 147         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 148         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 149         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 150                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 151         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 152                         (u32)(rdev->dummy_page.addr >> 12));
 153         for (i = 1; i < 7; i++)
 154                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 155
 156         r600_pcie_gart_tlb_flush(rdev);
 157         rdev->gart.ready = true;
 158         return 0;
 159 }
 160
 161 void r600_pcie_gart_disable(struct radeon_device *rdev)
 162 {
 163         u32 tmp;
 164         int i;
 165
 166         /* Disable all tables */
 167         for (i = 0; i < 7; i++)
 168                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 169
 170         /* Disable L2 cache */
 171         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 172                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 173         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 174         /* Setup L1 TLB control */
 175         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 176                 ENABLE_WAIT_L2_QUERY;
 177         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 178         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 179         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 180         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 181         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 182         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 183         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 184         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 185         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 186         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 187         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 188         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 189         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 190         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 191         if (rdev->gart.table.vram.robj) {
 192                 radeon_object_kunmap(rdev->gart.table.vram.robj);
 193                 radeon_object_unpin(rdev->gart.table.vram.robj);
 194         }
 195 }
 196
 197 void r600_pcie_gart_fini(struct radeon_device *rdev)
 198 {
 199         r600_pcie_gart_disable(rdev);
 200         radeon_gart_table_vram_free(rdev);
 201         radeon_gart_fini(rdev);
 202 }
 203
 204 void r600_agp_enable(struct radeon_device *rdev)
 205 {
 206         u32 tmp;
 207         int i;
 208
 209         /* Setup L2 cache */
 210         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 211                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 212                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 213         WREG32(VM_L2_CNTL2, 0);
 214         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 215         /* Setup TLB control */
 216         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 217                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 218                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 219                 ENABLE_WAIT_L2_QUERY;
 220         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 221         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 222         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 223         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 224         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 225         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 226         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 227         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 228         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 229         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 230         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 231         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 232         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 233         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 234         for (i = 0; i < 7; i++)
 235                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 236 }
 237
 238 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 239 {
 240         unsigned i;
 241         u32 tmp;
 242
 243         for (i = 0; i < rdev->usec_timeout; i++) {
 244                 /* read MC_STATUS */
 245                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 246                 if (!tmp)
 247                         return 0;
 248                 udelay(1);
 249         }
 250         return -1;
 251 }
 252
 253 static void r600_mc_program(struct radeon_device *rdev)
 254 {
 255         struct rv515_mc_save save;
 256         u32 tmp;
 257         int i, j;
 258
 259         /* Initialize HDP */
 260         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 261                 WREG32((0x2c14 + j), 0x00000000);
 262                 WREG32((0x2c18 + j), 0x00000000);
 263                 WREG32((0x2c1c + j), 0x00000000);
 264                 WREG32((0x2c20 + j), 0x00000000);
 265                 WREG32((0x2c24 + j), 0x00000000);
 266         }
 267         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 268
 269         rv515_mc_stop(rdev, &save);
 270         if (r600_mc_wait_for_idle(rdev)) {
 271                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 272         }
 273         /* Lockout access through VGA aperture (doesn't exist before R600) */
 274         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 275         /* Update configuration */
 276         if (rdev->flags & RADEON_IS_AGP) {
 277                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 278                         /* VRAM before AGP */
 279                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 280                                 rdev->mc.vram_start >> 12);
 281                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 282                                 rdev->mc.gtt_end >> 12);
 283                 } else {
 284                         /* VRAM after AGP */
 285                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 286                                 rdev->mc.gtt_start >> 12);
 287                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 288                                 rdev->mc.vram_end >> 12);
 289                 }
 290         } else {
 291                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 292                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 293         }
 294         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 295         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 296         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 297         WREG32(MC_VM_FB_LOCATION, tmp);
 298         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 299         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 300         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 301         if (rdev->flags & RADEON_IS_AGP) {
 302                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 303                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 304                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 305         } else {
 306                 WREG32(MC_VM_AGP_BASE, 0);
 307                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 308                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 309         }
 310         if (r600_mc_wait_for_idle(rdev)) {
 311                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 312         }
 313         rv515_mc_resume(rdev, &save);
 314         /* we need to own VRAM, so turn off the VGA renderer here
 315          * to stop it overwriting our objects */
 316         rv515_vga_render_disable(rdev);
 317 }
 318
 319 int r600_mc_init(struct radeon_device *rdev)
 320 {
 321         fixed20_12 a;
 322         u32 tmp;
 323         int chansize, numchan;
 324         int r;
 325
 326         /* Get VRAM informations */
 327         rdev->mc.vram_is_ddr = true;
 328         tmp = RREG32(RAMCFG);
 329         if (tmp & CHANSIZE_OVERRIDE) {
 330                 chansize = 16;
 331         } else if (tmp & CHANSIZE_MASK) {
 332                 chansize = 64;
 333         } else {
 334                 chansize = 32;
 335         }
 336         tmp = RREG32(CHMAP);
 337         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 338         case 0:
 339         default:
 340                 numchan = 1;
 341                 break;
 342         case 1:
 343                 numchan = 2;
 344                 break;
 345         case 2:
 346                 numchan = 4;
 347                 break;
 348         case 3:
 349                 numchan = 8;
 350                 break;
 351         }
 352         rdev->mc.vram_width = numchan * chansize;
 353         /* Could aper size report 0 ? */
 354         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 355         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 356         /* Setup GPU memory space */
 357         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 358         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 359
 360         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
 361                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 362
 363         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
 364                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 365
 366         if (rdev->flags & RADEON_IS_AGP) {
 367                 r = radeon_agp_init(rdev);
 368                 if (r)
 369                         return r;
 370                 /* gtt_size is setup by radeon_agp_init */
 371                 rdev->mc.gtt_location = rdev->mc.agp_base;
 372                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
 373                 /* Try to put vram before or after AGP because we
 374                  * we want SYSTEM_APERTURE to cover both VRAM and
 375                  * AGP so that GPU can catch out of VRAM/AGP access
 376                  */
 377                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 378                         /* Enought place before */
 379                         rdev->mc.vram_location = rdev->mc.gtt_location -
 380                                                         rdev->mc.mc_vram_size;
 381                 } else if (tmp > rdev->mc.mc_vram_size) {
 382                         /* Enought place after */
 383                         rdev->mc.vram_location = rdev->mc.gtt_location +
 384                                                         rdev->mc.gtt_size;
 385                 } else {
 386                         /* Try to setup VRAM then AGP might not
 387                          * not work on some card
 388                          */
 389                         rdev->mc.vram_location = 0x00000000UL;
 390                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 391                 }
 392         } else {
 393                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 394                 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
 395                                                         0xFFFF) << 24;
 396                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 397                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 398                         /* Enough place after vram */
 399                         rdev->mc.gtt_location = tmp;
 400                 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
 401                         /* Enough place before vram */
 402                         rdev->mc.gtt_location = 0;
 403                 } else {
 404                         /* Not enough place after or before shrink
 405                          * gart size
 406                          */
 407                         if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
 408                                 rdev->mc.gtt_location = 0;
 409                                 rdev->mc.gtt_size = rdev->mc.vram_location;
 410                         } else {
 411                                 rdev->mc.gtt_location = tmp;
 412                                 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
 413                         }
 414                 }
 415                 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 416         }
 417         rdev->mc.vram_start = rdev->mc.vram_location;
 418         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 419         rdev->mc.gtt_start = rdev->mc.gtt_location;
 420         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 421         /* FIXME: we should enforce default clock in case GPU is not in
 422          * default setup
 423          */
 424         a.full = rfixed_const(100);
 425         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 426         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 427         return 0;
 428 }
 429
 430 /* We doesn't check that the GPU really needs a reset we simply do the
 431  * reset, it's up to the caller to determine if the GPU needs one. We
 432  * might add an helper function to check that.
 433  */
 434 int r600_gpu_soft_reset(struct radeon_device *rdev)
 435 {
 436         struct rv515_mc_save save;
 437         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 438                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 439                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 440                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 441                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 442                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 443                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 444                                 S_008010_GUI_ACTIVE(1);
 445         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 446                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 447                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 448                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 449                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 450                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 451                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 452                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 453         u32 srbm_reset = 0;
 454         u32 tmp;
 455
 456         dev_info(rdev->dev, "GPU softreset \n");
 457         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 458                 RREG32(R_008010_GRBM_STATUS));
 459         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 460                 RREG32(R_008014_GRBM_STATUS2));
 461         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 462                 RREG32(R_000E50_SRBM_STATUS));
 463         rv515_mc_stop(rdev, &save);
 464         if (r600_mc_wait_for_idle(rdev)) {
 465                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 466         }
 467         /* Disable CP parsing/prefetching */
 468         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 469         /* Check if any of the rendering block is busy and reset it */
 470         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 471             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 472                 tmp = S_008020_SOFT_RESET_CR(1) |
 473                         S_008020_SOFT_RESET_DB(1) |
 474                         S_008020_SOFT_RESET_CB(1) |
 475                         S_008020_SOFT_RESET_PA(1) |
 476                         S_008020_SOFT_RESET_SC(1) |
 477                         S_008020_SOFT_RESET_SMX(1) |
 478                         S_008020_SOFT_RESET_SPI(1) |
 479                         S_008020_SOFT_RESET_SX(1) |
 480                         S_008020_SOFT_RESET_SH(1) |
 481                         S_008020_SOFT_RESET_TC(1) |
 482                         S_008020_SOFT_RESET_TA(1) |
 483                         S_008020_SOFT_RESET_VC(1) |
 484                         S_008020_SOFT_RESET_VGT(1);
 485                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 486                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 487                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 488                 udelay(50);
 489                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 490                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 491         }
 492         /* Reset CP (we always reset CP) */
 493         tmp = S_008020_SOFT_RESET_CP(1);
 494         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 495         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 496         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 497         udelay(50);
 498         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 499         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 500         /* Reset others GPU block if necessary */
 501         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 502                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 503         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 504                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 505         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 506                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 507         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 508                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 509         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 510                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 511         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 512                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 513         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 514                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 515         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 516                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 517         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 518                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 519         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 520                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 521         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 522                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 523         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 524                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
 525         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
 526         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 527         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 528         udelay(50);
 529         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 530         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 531         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 532         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 533         udelay(50);
 534         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 535         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 536         /* Wait a little for things to settle down */
 537         udelay(50);
 538         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 539                 RREG32(R_008010_GRBM_STATUS));
 540         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 541                 RREG32(R_008014_GRBM_STATUS2));
 542         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 543                 RREG32(R_000E50_SRBM_STATUS));
 544         /* After reset we need to reinit the asic as GPU often endup in an
 545          * incoherent state.
 546          */
 547         atom_asic_init(rdev->mode_info.atom_context);
 548         rv515_mc_resume(rdev, &save);
 549         return 0;
 550 }
 551
 552 int r600_gpu_reset(struct radeon_device *rdev)
 553 {
 554         return r600_gpu_soft_reset(rdev);
 555 }
 556
 557 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 558                                              u32 num_backends,
 559                                              u32 backend_disable_mask)
 560 {
 561         u32 backend_map = 0;
 562         u32 enabled_backends_mask;
 563         u32 enabled_backends_count;
 564         u32 cur_pipe;
 565         u32 swizzle_pipe[R6XX_MAX_PIPES];
 566         u32 cur_backend;
 567         u32 i;
 568
 569         if (num_tile_pipes > R6XX_MAX_PIPES)
 570                 num_tile_pipes = R6XX_MAX_PIPES;
 571         if (num_tile_pipes < 1)
 572                 num_tile_pipes = 1;
 573         if (num_backends > R6XX_MAX_BACKENDS)
 574                 num_backends = R6XX_MAX_BACKENDS;
 575         if (num_backends < 1)
 576                 num_backends = 1;
 577
 578         enabled_backends_mask = 0;
 579         enabled_backends_count = 0;
 580         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 581                 if (((backend_disable_mask >> i) & 1) == 0) {
 582                         enabled_backends_mask |= (1 << i);
 583                         ++enabled_backends_count;
 584                 }
 585                 if (enabled_backends_count == num_backends)
 586                         break;
 587         }
 588
 589         if (enabled_backends_count == 0) {
 590                 enabled_backends_mask = 1;
 591                 enabled_backends_count = 1;
 592         }
 593
 594         if (enabled_backends_count != num_backends)
 595                 num_backends = enabled_backends_count;
 596
 597         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 598         switch (num_tile_pipes) {
 599         case 1:
 600                 swizzle_pipe[0] = 0;
 601                 break;
 602         case 2:
 603                 swizzle_pipe[0] = 0;
 604                 swizzle_pipe[1] = 1;
 605                 break;
 606         case 3:
 607                 swizzle_pipe[0] = 0;
 608                 swizzle_pipe[1] = 1;
 609                 swizzle_pipe[2] = 2;
 610                 break;
 611         case 4:
 612                 swizzle_pipe[0] = 0;
 613                 swizzle_pipe[1] = 1;
 614                 swizzle_pipe[2] = 2;
 615                 swizzle_pipe[3] = 3;
 616                 break;
 617         case 5:
 618                 swizzle_pipe[0] = 0;
 619                 swizzle_pipe[1] = 1;
 620                 swizzle_pipe[2] = 2;
 621                 swizzle_pipe[3] = 3;
 622                 swizzle_pipe[4] = 4;
 623                 break;
 624         case 6:
 625                 swizzle_pipe[0] = 0;
 626                 swizzle_pipe[1] = 2;
 627                 swizzle_pipe[2] = 4;
 628                 swizzle_pipe[3] = 5;
 629                 swizzle_pipe[4] = 1;
 630                 swizzle_pipe[5] = 3;
 631                 break;
 632         case 7:
 633                 swizzle_pipe[0] = 0;
 634                 swizzle_pipe[1] = 2;
 635                 swizzle_pipe[2] = 4;
 636                 swizzle_pipe[3] = 6;
 637                 swizzle_pipe[4] = 1;
 638                 swizzle_pipe[5] = 3;
 639                 swizzle_pipe[6] = 5;
 640                 break;
 641         case 8:
 642                 swizzle_pipe[0] = 0;
 643                 swizzle_pipe[1] = 2;
 644                 swizzle_pipe[2] = 4;
 645                 swizzle_pipe[3] = 6;
 646                 swizzle_pipe[4] = 1;
 647                 swizzle_pipe[5] = 3;
 648                 swizzle_pipe[6] = 5;
 649                 swizzle_pipe[7] = 7;
 650                 break;
 651         }
 652
 653         cur_backend = 0;
 654         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 655                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 656                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 657
 658                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 659
 660                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 661         }
 662
 663         return backend_map;
 664 }
 665
 666 int r600_count_pipe_bits(uint32_t val)
 667 {
 668         int i, ret = 0;
 669
 670         for (i = 0; i < 32; i++) {
 671                 ret += val & 1;
 672                 val >>= 1;
 673         }
 674         return ret;
 675 }
 676
 677 void r600_gpu_init(struct radeon_device *rdev)
 678 {
 679         u32 tiling_config;
 680         u32 ramcfg;
 681         u32 tmp;
 682         int i, j;
 683         u32 sq_config;
 684         u32 sq_gpr_resource_mgmt_1 = 0;
 685         u32 sq_gpr_resource_mgmt_2 = 0;
 686         u32 sq_thread_resource_mgmt = 0;
 687         u32 sq_stack_resource_mgmt_1 = 0;
 688         u32 sq_stack_resource_mgmt_2 = 0;
 689
 690         /* FIXME: implement */
 691         switch (rdev->family) {
 692         case CHIP_R600:
 693                 rdev->config.r600.max_pipes = 4;
 694                 rdev->config.r600.max_tile_pipes = 8;
 695                 rdev->config.r600.max_simds = 4;
 696                 rdev->config.r600.max_backends = 4;
 697                 rdev->config.r600.max_gprs = 256;
 698                 rdev->config.r600.max_threads = 192;
 699                 rdev->config.r600.max_stack_entries = 256;
 700                 rdev->config.r600.max_hw_contexts = 8;
 701                 rdev->config.r600.max_gs_threads = 16;
 702                 rdev->config.r600.sx_max_export_size = 128;
 703                 rdev->config.r600.sx_max_export_pos_size = 16;
 704                 rdev->config.r600.sx_max_export_smx_size = 128;
 705                 rdev->config.r600.sq_num_cf_insts = 2;
 706                 break;
 707         case CHIP_RV630:
 708         case CHIP_RV635:
 709                 rdev->config.r600.max_pipes = 2;
 710                 rdev->config.r600.max_tile_pipes = 2;
 711                 rdev->config.r600.max_simds = 3;
 712                 rdev->config.r600.max_backends = 1;
 713                 rdev->config.r600.max_gprs = 128;
 714                 rdev->config.r600.max_threads = 192;
 715                 rdev->config.r600.max_stack_entries = 128;
 716                 rdev->config.r600.max_hw_contexts = 8;
 717                 rdev->config.r600.max_gs_threads = 4;
 718                 rdev->config.r600.sx_max_export_size = 128;
 719                 rdev->config.r600.sx_max_export_pos_size = 16;
 720                 rdev->config.r600.sx_max_export_smx_size = 128;
 721                 rdev->config.r600.sq_num_cf_insts = 2;
 722                 break;
 723         case CHIP_RV610:
 724         case CHIP_RV620:
 725         case CHIP_RS780:
 726         case CHIP_RS880:
 727                 rdev->config.r600.max_pipes = 1;
 728                 rdev->config.r600.max_tile_pipes = 1;
 729                 rdev->config.r600.max_simds = 2;
 730                 rdev->config.r600.max_backends = 1;
 731                 rdev->config.r600.max_gprs = 128;
 732                 rdev->config.r600.max_threads = 192;
 733                 rdev->config.r600.max_stack_entries = 128;
 734                 rdev->config.r600.max_hw_contexts = 4;
 735                 rdev->config.r600.max_gs_threads = 4;
 736                 rdev->config.r600.sx_max_export_size = 128;
 737                 rdev->config.r600.sx_max_export_pos_size = 16;
 738                 rdev->config.r600.sx_max_export_smx_size = 128;
 739                 rdev->config.r600.sq_num_cf_insts = 1;
 740                 break;
 741         case CHIP_RV670:
 742                 rdev->config.r600.max_pipes = 4;
 743                 rdev->config.r600.max_tile_pipes = 4;
 744                 rdev->config.r600.max_simds = 4;
 745                 rdev->config.r600.max_backends = 4;
 746                 rdev->config.r600.max_gprs = 192;
 747                 rdev->config.r600.max_threads = 192;
 748                 rdev->config.r600.max_stack_entries = 256;
 749                 rdev->config.r600.max_hw_contexts = 8;
 750                 rdev->config.r600.max_gs_threads = 16;
 751                 rdev->config.r600.sx_max_export_size = 128;
 752                 rdev->config.r600.sx_max_export_pos_size = 16;
 753                 rdev->config.r600.sx_max_export_smx_size = 128;
 754                 rdev->config.r600.sq_num_cf_insts = 2;
 755                 break;
 756         default:
 757                 break;
 758         }
 759
 760         /* Initialize HDP */
 761         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 762                 WREG32((0x2c14 + j), 0x00000000);
 763                 WREG32((0x2c18 + j), 0x00000000);
 764                 WREG32((0x2c1c + j), 0x00000000);
 765                 WREG32((0x2c20 + j), 0x00000000);
 766                 WREG32((0x2c24 + j), 0x00000000);
 767         }
 768
 769         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 770
 771         /* Setup tiling */
 772         tiling_config = 0;
 773         ramcfg = RREG32(RAMCFG);
 774         switch (rdev->config.r600.max_tile_pipes) {
 775         case 1:
 776                 tiling_config |= PIPE_TILING(0);
 777                 break;
 778         case 2:
 779                 tiling_config |= PIPE_TILING(1);
 780                 break;
 781         case 4:
 782                 tiling_config |= PIPE_TILING(2);
 783                 break;
 784         case 8:
 785                 tiling_config |= PIPE_TILING(3);
 786                 break;
 787         default:
 788                 break;
 789         }
 790         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 791         tiling_config |= GROUP_SIZE(0);
 792         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
 793         if (tmp > 3) {
 794                 tiling_config |= ROW_TILING(3);
 795                 tiling_config |= SAMPLE_SPLIT(3);
 796         } else {
 797                 tiling_config |= ROW_TILING(tmp);
 798                 tiling_config |= SAMPLE_SPLIT(tmp);
 799         }
 800         tiling_config |= BANK_SWAPS(1);
 801         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
 802                                                 rdev->config.r600.max_backends,
 803                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
 804         tiling_config |= BACKEND_MAP(tmp);
 805         WREG32(GB_TILING_CONFIG, tiling_config);
 806         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
 807         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
 808
 809         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
 810         WREG32(CC_RB_BACKEND_DISABLE, tmp);
 811
 812         /* Setup pipes */
 813         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
 814         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
 815         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
 816         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
 817
 818         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
 819         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
 820         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 821
 822         /* Setup some CP states */
 823         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
 824         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
 825
 826         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
 827                              SYNC_WALKER | SYNC_ALIGNER));
 828         /* Setup various GPU states */
 829         if (rdev->family == CHIP_RV670)
 830                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
 831
 832         tmp = RREG32(SX_DEBUG_1);
 833         tmp |= SMX_EVENT_RELEASE;
 834         if ((rdev->family > CHIP_R600))
 835                 tmp |= ENABLE_NEW_SMX_ADDRESS;
 836         WREG32(SX_DEBUG_1, tmp);
 837
 838         if (((rdev->family) == CHIP_R600) ||
 839             ((rdev->family) == CHIP_RV630) ||
 840             ((rdev->family) == CHIP_RV610) ||
 841             ((rdev->family) == CHIP_RV620) ||
 842             ((rdev->family) == CHIP_RS780) ||
 843             ((rdev->family) == CHIP_RS880)) {
 844                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 845         } else {
 846                 WREG32(DB_DEBUG, 0);
 847         }
 848         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
 849                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
 850
 851         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 852         WREG32(VGT_NUM_INSTANCES, 0);
 853
 854         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 855         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
 856
 857         tmp = RREG32(SQ_MS_FIFO_SIZES);
 858         if (((rdev->family) == CHIP_RV610) ||
 859             ((rdev->family) == CHIP_RV620) ||
 860             ((rdev->family) == CHIP_RS780) ||
 861             ((rdev->family) == CHIP_RS880)) {
 862                 tmp = (CACHE_FIFO_SIZE(0xa) |
 863                        FETCH_FIFO_HIWATER(0xa) |
 864                        DONE_FIFO_HIWATER(0xe0) |
 865                        ALU_UPDATE_FIFO_HIWATER(0x8));
 866         } else if (((rdev->family) == CHIP_R600) ||
 867                    ((rdev->family) == CHIP_RV630)) {
 868                 tmp &= ~DONE_FIFO_HIWATER(0xff);
 869                 tmp |= DONE_FIFO_HIWATER(0x4);
 870         }
 871         WREG32(SQ_MS_FIFO_SIZES, tmp);
 872
 873         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 874          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 875          */
 876         sq_config = RREG32(SQ_CONFIG);
 877         sq_config &= ~(PS_PRIO(3) |
 878                        VS_PRIO(3) |
 879                        GS_PRIO(3) |
 880                        ES_PRIO(3));
 881         sq_config |= (DX9_CONSTS |
 882                       VC_ENABLE |
 883                       PS_PRIO(0) |
 884                       VS_PRIO(1) |
 885                       GS_PRIO(2) |
 886                       ES_PRIO(3));
 887
 888         if ((rdev->family) == CHIP_R600) {
 889                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
 890                                           NUM_VS_GPRS(124) |
 891                                           NUM_CLAUSE_TEMP_GPRS(4));
 892                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
 893                                           NUM_ES_GPRS(0));
 894                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
 895                                            NUM_VS_THREADS(48) |
 896                                            NUM_GS_THREADS(4) |
 897                                            NUM_ES_THREADS(4));
 898                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
 899                                             NUM_VS_STACK_ENTRIES(128));
 900                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
 901                                             NUM_ES_STACK_ENTRIES(0));
 902         } else if (((rdev->family) == CHIP_RV610) ||
 903                    ((rdev->family) == CHIP_RV620) ||
 904                    ((rdev->family) == CHIP_RS780) ||
 905                    ((rdev->family) == CHIP_RS880)) {
 906                 /* no vertex cache */
 907                 sq_config &= ~VC_ENABLE;
 908
 909                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 910                                           NUM_VS_GPRS(44) |
 911                                           NUM_CLAUSE_TEMP_GPRS(2));
 912                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
 913                                           NUM_ES_GPRS(17));
 914                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 915                                            NUM_VS_THREADS(78) |
 916                                            NUM_GS_THREADS(4) |
 917                                            NUM_ES_THREADS(31));
 918                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
 919                                             NUM_VS_STACK_ENTRIES(40));
 920                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
 921                                             NUM_ES_STACK_ENTRIES(16));
 922         } else if (((rdev->family) == CHIP_RV630) ||
 923                    ((rdev->family) == CHIP_RV635)) {
 924                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 925                                           NUM_VS_GPRS(44) |
 926                                           NUM_CLAUSE_TEMP_GPRS(2));
 927                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
 928                                           NUM_ES_GPRS(18));
 929                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 930                                            NUM_VS_THREADS(78) |
 931                                            NUM_GS_THREADS(4) |
 932                                            NUM_ES_THREADS(31));
 933                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
 934                                             NUM_VS_STACK_ENTRIES(40));
 935                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
 936                                             NUM_ES_STACK_ENTRIES(16));
 937         } else if ((rdev->family) == CHIP_RV670) {
 938                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 939                                           NUM_VS_GPRS(44) |
 940                                           NUM_CLAUSE_TEMP_GPRS(2));
 941                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
 942                                           NUM_ES_GPRS(17));
 943                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 944                                            NUM_VS_THREADS(78) |
 945                                            NUM_GS_THREADS(4) |
 946                                            NUM_ES_THREADS(31));
 947                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
 948                                             NUM_VS_STACK_ENTRIES(64));
 949                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
 950                                             NUM_ES_STACK_ENTRIES(64));
 951         }
 952
 953         WREG32(SQ_CONFIG, sq_config);
 954         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 955         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 956         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 957         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 958         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 959
 960         if (((rdev->family) == CHIP_RV610) ||
 961             ((rdev->family) == CHIP_RV620) ||
 962             ((rdev->family) == CHIP_RS780) ||
 963             ((rdev->family) == CHIP_RS880)) {
 964                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
 965         } else {
 966                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
 967         }
 968
 969         /* More default values. 2D/3D driver should adjust as needed */
 970         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
 971                                          S1_X(0x4) | S1_Y(0xc)));
 972         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
 973                                          S1_X(0x2) | S1_Y(0x2) |
 974                                          S2_X(0xa) | S2_Y(0x6) |
 975                                          S3_X(0x6) | S3_Y(0xa)));
 976         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
 977                                              S1_X(0x4) | S1_Y(0xc) |
 978                                              S2_X(0x1) | S2_Y(0x6) |
 979                                              S3_X(0xa) | S3_Y(0xe)));
 980         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
 981                                              S5_X(0x0) | S5_Y(0x0) |
 982                                              S6_X(0xb) | S6_Y(0x4) |
 983                                              S7_X(0x7) | S7_Y(0x8)));
 984
 985         WREG32(VGT_STRMOUT_EN, 0);
 986         tmp = rdev->config.r600.max_pipes * 16;
 987         switch (rdev->family) {
 988         case CHIP_RV610:
 989         case CHIP_RV620:
 990         case CHIP_RS780:
 991         case CHIP_RS880:
 992                 tmp += 32;
 993                 break;
 994         case CHIP_RV670:
 995                 tmp += 128;
 996                 break;
 997         default:
 998                 break;
 999         }
1000         if (tmp > 256) {
1001                 tmp = 256;
1002         }
1003         WREG32(VGT_ES_PER_GS, 128);
1004         WREG32(VGT_GS_PER_ES, tmp);
1005         WREG32(VGT_GS_PER_VS, 2);
1006         WREG32(VGT_GS_VERTEX_REUSE, 16);
1007
1008         /* more default values. 2D/3D driver should adjust as needed */
1009         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1010         WREG32(VGT_STRMOUT_EN, 0);
1011         WREG32(SX_MISC, 0);
1012         WREG32(PA_SC_MODE_CNTL, 0);
1013         WREG32(PA_SC_AA_CONFIG, 0);
1014         WREG32(PA_SC_LINE_STIPPLE, 0);
1015         WREG32(SPI_INPUT_Z, 0);
1016         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1017         WREG32(CB_COLOR7_FRAG, 0);
1018
1019         /* Clear render buffer base addresses */
1020         WREG32(CB_COLOR0_BASE, 0);
1021         WREG32(CB_COLOR1_BASE, 0);
1022         WREG32(CB_COLOR2_BASE, 0);
1023         WREG32(CB_COLOR3_BASE, 0);
1024         WREG32(CB_COLOR4_BASE, 0);
1025         WREG32(CB_COLOR5_BASE, 0);
1026         WREG32(CB_COLOR6_BASE, 0);
1027         WREG32(CB_COLOR7_BASE, 0);
1028         WREG32(CB_COLOR7_FRAG, 0);
1029
1030         switch (rdev->family) {
1031         case CHIP_RV610:
1032         case CHIP_RV620:
1033         case CHIP_RS780:
1034         case CHIP_RS880:
1035                 tmp = TC_L2_SIZE(8);
1036                 break;
1037         case CHIP_RV630:
1038         case CHIP_RV635:
1039                 tmp = TC_L2_SIZE(4);
1040                 break;
1041         case CHIP_R600:
1042                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1043                 break;
1044         default:
1045                 tmp = TC_L2_SIZE(0);
1046                 break;
1047         }
1048         WREG32(TC_CNTL, tmp);
1049
1050         tmp = RREG32(HDP_HOST_PATH_CNTL);
1051         WREG32(HDP_HOST_PATH_CNTL, tmp);
1052
1053         tmp = RREG32(ARB_POP);
1054         tmp |= ENABLE_TC128;
1055         WREG32(ARB_POP, tmp);
1056
1057         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1058         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1059                                NUM_CLIP_SEQ(3)));
1060         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1061 }
1062
1063
1064 /*
1065  * Indirect registers accessor
1066  */
1067 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1068 {
1069         u32 r;
1070
1071         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1072         (void)RREG32(PCIE_PORT_INDEX);
1073         r = RREG32(PCIE_PORT_DATA);
1074         return r;
1075 }
1076
1077 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1078 {
1079         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1080         (void)RREG32(PCIE_PORT_INDEX);
1081         WREG32(PCIE_PORT_DATA, (v));
1082         (void)RREG32(PCIE_PORT_DATA);
1083 }
1084
1085
1086 /*
1087  * CP & Ring
1088  */
1089 void r600_cp_stop(struct radeon_device *rdev)
1090 {
1091         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1092 }
1093
1094 int r600_cp_init_microcode(struct radeon_device *rdev)
1095 {
1096         struct platform_device *pdev;
1097         const char *chip_name;
1098         size_t pfp_req_size, me_req_size;
1099         char fw_name[30];
1100         int err;
1101
1102         DRM_DEBUG("\n");
1103
1104         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1105         err = IS_ERR(pdev);
1106         if (err) {
1107                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1108                 return -EINVAL;
1109         }
1110
1111         switch (rdev->family) {
1112         case CHIP_R600: chip_name = "R600"; break;
1113         case CHIP_RV610: chip_name = "RV610"; break;
1114         case CHIP_RV630: chip_name = "RV630"; break;
1115         case CHIP_RV620: chip_name = "RV620"; break;
1116         case CHIP_RV635: chip_name = "RV635"; break;
1117         case CHIP_RV670: chip_name = "RV670"; break;
1118         case CHIP_RS780:
1119         case CHIP_RS880: chip_name = "RS780"; break;
1120         case CHIP_RV770: chip_name = "RV770"; break;
1121         case CHIP_RV730:
1122         case CHIP_RV740: chip_name = "RV730"; break;
1123         case CHIP_RV710: chip_name = "RV710"; break;
1124         default: BUG();
1125         }
1126
1127         if (rdev->family >= CHIP_RV770) {
1128                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1129                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1130         } else {
1131                 pfp_req_size = PFP_UCODE_SIZE * 4;
1132                 me_req_size = PM4_UCODE_SIZE * 12;
1133         }
1134
1135         DRM_INFO("Loading %s CP Microcode\n", chip_name);
1136
1137         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1138         err = reject_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1139         if (err)
1140                 goto out;
1141         if (rdev->pfp_fw->size != pfp_req_size) {
1142                 printk(KERN_ERR
1143                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1144                        rdev->pfp_fw->size, fw_name);
1145                 err = -EINVAL;
1146                 goto out;
1147         }
1148
1149         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
1150         err = reject_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1151         if (err)
1152                 goto out;
1153         if (rdev->me_fw->size != me_req_size) {
1154                 printk(KERN_ERR
1155                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1156                        rdev->me_fw->size, fw_name);
1157                 err = -EINVAL;
1158         }
1159 out:
1160         platform_device_unregister(pdev);
1161
1162         if (err) {
1163                 if (err != -EINVAL)
1164                         printk(KERN_ERR
1165                                "r600_cp: Failed to load firmware \"%s\"\n",
1166                                fw_name);
1167                 release_firmware(rdev->pfp_fw);
1168                 rdev->pfp_fw = NULL;
1169                 release_firmware(rdev->me_fw);
1170                 rdev->me_fw = NULL;
1171         }
1172         return err;
1173 }
1174
1175 static int r600_cp_load_microcode(struct radeon_device *rdev)
1176 {
1177         const __be32 *fw_data;
1178         int i;
1179
1180         if (!rdev->me_fw || !rdev->pfp_fw)
1181                 return -EINVAL;
1182
1183         r600_cp_stop(rdev);
1184
1185         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1186
1187         /* Reset cp */
1188         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1189         RREG32(GRBM_SOFT_RESET);
1190         mdelay(15);
1191         WREG32(GRBM_SOFT_RESET, 0);
1192
1193         WREG32(CP_ME_RAM_WADDR, 0);
1194
1195         fw_data = (const __be32 *)rdev->me_fw->data;
1196         WREG32(CP_ME_RAM_WADDR, 0);
1197         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1198                 WREG32(CP_ME_RAM_DATA,
1199                        be32_to_cpup(fw_data++));
1200
1201         fw_data = (const __be32 *)rdev->pfp_fw->data;
1202         WREG32(CP_PFP_UCODE_ADDR, 0);
1203         for (i = 0; i < PFP_UCODE_SIZE; i++)
1204                 WREG32(CP_PFP_UCODE_DATA,
1205                        be32_to_cpup(fw_data++));
1206
1207         WREG32(CP_PFP_UCODE_ADDR, 0);
1208         WREG32(CP_ME_RAM_WADDR, 0);
1209         WREG32(CP_ME_RAM_RADDR, 0);
1210         return 0;
1211 }
1212
1213 int r600_cp_start(struct radeon_device *rdev)
1214 {
1215         int r;
1216         uint32_t cp_me;
1217
1218         r = radeon_ring_lock(rdev, 7);
1219         if (r) {
1220                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1221                 return r;
1222         }
1223         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1224         radeon_ring_write(rdev, 0x1);
1225         if (rdev->family < CHIP_RV770) {
1226                 radeon_ring_write(rdev, 0x3);
1227                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1228         } else {
1229                 radeon_ring_write(rdev, 0x0);
1230                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1231         }
1232         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1233         radeon_ring_write(rdev, 0);
1234         radeon_ring_write(rdev, 0);
1235         radeon_ring_unlock_commit(rdev);
1236
1237         cp_me = 0xff;
1238         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1239         return 0;
1240 }
1241
1242 int r600_cp_resume(struct radeon_device *rdev)
1243 {
1244         u32 tmp;
1245         u32 rb_bufsz;
1246         int r;
1247
1248         /* Reset cp */
1249         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1250         RREG32(GRBM_SOFT_RESET);
1251         mdelay(15);
1252         WREG32(GRBM_SOFT_RESET, 0);
1253
1254         /* Set ring buffer size */
1255         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1256         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1257 #ifdef __BIG_ENDIAN
1258         tmp |= BUF_SWAP_32BIT;
1259 #endif
1260         WREG32(CP_RB_CNTL, tmp);
1261         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1262
1263         /* Set the write pointer delay */
1264         WREG32(CP_RB_WPTR_DELAY, 0);
1265
1266         /* Initialize the ring buffer's read and write pointers */
1267         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1268         WREG32(CP_RB_RPTR_WR, 0);
1269         WREG32(CP_RB_WPTR, 0);
1270         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1271         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1272         mdelay(1);
1273         WREG32(CP_RB_CNTL, tmp);
1274
1275         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1276         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1277
1278         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1279         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1280
1281         r600_cp_start(rdev);
1282         rdev->cp.ready = true;
1283         r = radeon_ring_test(rdev);
1284         if (r) {
1285                 rdev->cp.ready = false;
1286                 return r;
1287         }
1288         return 0;
1289 }
1290
1291 void r600_cp_commit(struct radeon_device *rdev)
1292 {
1293         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1294         (void)RREG32(CP_RB_WPTR);
1295 }
1296
1297 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1298 {
1299         u32 rb_bufsz;
1300
1301         /* Align ring size */
1302         rb_bufsz = drm_order(ring_size / 8);
1303         ring_size = (1 << (rb_bufsz + 1)) * 4;
1304         rdev->cp.ring_size = ring_size;
1305         rdev->cp.align_mask = 16 - 1;
1306 }
1307
1308
1309 /*
1310  * GPU scratch registers helpers function.
1311  */
1312 void r600_scratch_init(struct radeon_device *rdev)
1313 {
1314         int i;
1315
1316         rdev->scratch.num_reg = 7;
1317         for (i = 0; i < rdev->scratch.num_reg; i++) {
1318                 rdev->scratch.free[i] = true;
1319                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1320         }
1321 }
1322
1323 int r600_ring_test(struct radeon_device *rdev)
1324 {
1325         uint32_t scratch;
1326         uint32_t tmp = 0;
1327         unsigned i;
1328         int r;
1329
1330         r = radeon_scratch_get(rdev, &scratch);
1331         if (r) {
1332                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1333                 return r;
1334         }
1335         WREG32(scratch, 0xCAFEDEAD);
1336         r = radeon_ring_lock(rdev, 3);
1337         if (r) {
1338                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1339                 radeon_scratch_free(rdev, scratch);
1340                 return r;
1341         }
1342         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1343         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1344         radeon_ring_write(rdev, 0xDEADBEEF);
1345         radeon_ring_unlock_commit(rdev);
1346         for (i = 0; i < rdev->usec_timeout; i++) {
1347                 tmp = RREG32(scratch);
1348                 if (tmp == 0xDEADBEEF)
1349                         break;
1350                 DRM_UDELAY(1);
1351         }
1352         if (i < rdev->usec_timeout) {
1353                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1354         } else {
1355                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1356                           scratch, tmp);
1357                 r = -EINVAL;
1358         }
1359         radeon_scratch_free(rdev, scratch);
1360         return r;
1361 }
1362
1363 void r600_wb_disable(struct radeon_device *rdev)
1364 {
1365         WREG32(SCRATCH_UMSK, 0);
1366         if (rdev->wb.wb_obj) {
1367                 radeon_object_kunmap(rdev->wb.wb_obj);
1368                 radeon_object_unpin(rdev->wb.wb_obj);
1369         }
1370 }
1371
1372 void r600_wb_fini(struct radeon_device *rdev)
1373 {
1374         r600_wb_disable(rdev);
1375         if (rdev->wb.wb_obj) {
1376                 radeon_object_unref(&rdev->wb.wb_obj);
1377                 rdev->wb.wb = NULL;
1378                 rdev->wb.wb_obj = NULL;
1379         }
1380 }
1381
1382 int r600_wb_enable(struct radeon_device *rdev)
1383 {
1384         int r;
1385
1386         if (rdev->wb.wb_obj == NULL) {
1387                 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1388                                 RADEON_GEM_DOMAIN_GTT, false, &rdev->wb.wb_obj);
1389                 if (r) {
1390                         dev_warn(rdev->dev, "failed to create WB buffer (%d).\n", r);
1391                         return r;
1392                 }
1393                 r = radeon_object_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1394                                 &rdev->wb.gpu_addr);
1395                 if (r) {
1396                         dev_warn(rdev->dev, "failed to pin WB buffer (%d).\n", r);
1397                         r600_wb_fini(rdev);
1398                         return r;
1399                 }
1400                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1401                 if (r) {
1402                         dev_warn(rdev->dev, "failed to map WB buffer (%d).\n", r);
1403                         r600_wb_fini(rdev);
1404                         return r;
1405                 }
1406         }
1407         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1408         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1409         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1410         WREG32(SCRATCH_UMSK, 0xff);
1411         return 0;
1412 }
1413
1414 void r600_fence_ring_emit(struct radeon_device *rdev,
1415                           struct radeon_fence *fence)
1416 {
1417         /* Emit fence sequence & fire IRQ */
1418         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1419         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1420         radeon_ring_write(rdev, fence->seq);
1421 }
1422
1423 int r600_copy_dma(struct radeon_device *rdev,
1424                   uint64_t src_offset,
1425                   uint64_t dst_offset,
1426                   unsigned num_pages,
1427                   struct radeon_fence *fence)
1428 {
1429         /* FIXME: implement */
1430         return 0;
1431 }
1432
1433 int r600_copy_blit(struct radeon_device *rdev,
1434                    uint64_t src_offset, uint64_t dst_offset,
1435                    unsigned num_pages, struct radeon_fence *fence)
1436 {
1437         r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1438         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1439         r600_blit_done_copy(rdev, fence);
1440         return 0;
1441 }
1442
1443 int r600_irq_process(struct radeon_device *rdev)
1444 {
1445         /* FIXME: implement */
1446         return 0;
1447 }
1448
1449 int r600_irq_set(struct radeon_device *rdev)
1450 {
1451         /* FIXME: implement */
1452         return 0;
1453 }
1454
1455 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1456                          uint32_t tiling_flags, uint32_t pitch,
1457                          uint32_t offset, uint32_t obj_size)
1458 {
1459         /* FIXME: implement */
1460         return 0;
1461 }
1462
1463 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1464 {
1465         /* FIXME: implement */
1466 }
1467
1468
1469 bool r600_card_posted(struct radeon_device *rdev)
1470 {
1471         uint32_t reg;
1472
1473         /* first check CRTCs */
1474         reg = RREG32(D1CRTC_CONTROL) |
1475                 RREG32(D2CRTC_CONTROL);
1476         if (reg & CRTC_EN)
1477                 return true;
1478
1479         /* then check MEM_SIZE, in case the crtcs are off */
1480         if (RREG32(CONFIG_MEMSIZE))
1481                 return true;
1482
1483         return false;
1484 }
1485
1486 int r600_startup(struct radeon_device *rdev)
1487 {
1488         int r;
1489
1490         r600_mc_program(rdev);
1491         if (rdev->flags & RADEON_IS_AGP) {
1492                 r600_agp_enable(rdev);
1493         } else {
1494                 r = r600_pcie_gart_enable(rdev);
1495                 if (r)
1496                         return r;
1497         }
1498         r600_gpu_init(rdev);
1499
1500         r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1501                               &rdev->r600_blit.shader_gpu_addr);
1502         if (r) {
1503                 DRM_ERROR("failed to pin blit object %d\n", r);
1504                 return r;
1505         }
1506
1507         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1508         if (r)
1509                 return r;
1510         r = r600_cp_load_microcode(rdev);
1511         if (r)
1512                 return r;
1513         r = r600_cp_resume(rdev);
1514         if (r)
1515                 return r;
1516         /* write back buffer are not vital so don't worry about failure */
1517         r600_wb_enable(rdev);
1518         return 0;
1519 }
1520
1521 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1522 {
1523         uint32_t temp;
1524
1525         temp = RREG32(CONFIG_CNTL);
1526         if (state == false) {
1527                 temp &= ~(1<<0);
1528                 temp |= (1<<1);
1529         } else {
1530                 temp &= ~(1<<1);
1531         }
1532         WREG32(CONFIG_CNTL, temp);
1533 }
1534
1535 int r600_resume(struct radeon_device *rdev)
1536 {
1537         int r;
1538
1539         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1540          * posting will perform necessary task to bring back GPU into good
1541          * shape.
1542          */
1543         /* post card */
1544         atom_asic_init(rdev->mode_info.atom_context);
1545         /* Initialize clocks */
1546         r = radeon_clocks_init(rdev);
1547         if (r) {
1548                 return r;
1549         }
1550
1551         r = r600_startup(rdev);
1552         if (r) {
1553                 DRM_ERROR("r600 startup failed on resume\n");
1554                 return r;
1555         }
1556
1557         r = r600_ib_test(rdev);
1558         if (r) {
1559                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1560                 return r;
1561         }
1562         return r;
1563 }
1564
1565 int r600_suspend(struct radeon_device *rdev)
1566 {
1567         /* FIXME: we should wait for ring to be empty */
1568         r600_cp_stop(rdev);
1569         rdev->cp.ready = false;
1570         r600_wb_disable(rdev);
1571         r600_pcie_gart_disable(rdev);
1572         /* unpin shaders bo */
1573         radeon_object_unpin(rdev->r600_blit.shader_obj);
1574         return 0;
1575 }
1576
1577 /* Plan is to move initialization in that function and use
1578  * helper function so that radeon_device_init pretty much
1579  * do nothing more than calling asic specific function. This
1580  * should also allow to remove a bunch of callback function
1581  * like vram_info.
1582  */
1583 int r600_init(struct radeon_device *rdev)
1584 {
1585         int r;
1586
1587         r = radeon_dummy_page_init(rdev);
1588         if (r)
1589                 return r;
1590         if (r600_debugfs_mc_info_init(rdev)) {
1591                 DRM_ERROR("Failed to register debugfs file for mc !\n");
1592         }
1593         /* This don't do much */
1594         r = radeon_gem_init(rdev);
1595         if (r)
1596                 return r;
1597         /* Read BIOS */
1598         if (!radeon_get_bios(rdev)) {
1599                 if (ASIC_IS_AVIVO(rdev))
1600                         return -EINVAL;
1601         }
1602         /* Must be an ATOMBIOS */
1603         if (!rdev->is_atom_bios) {
1604                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1605                 return -EINVAL;
1606         }
1607         r = radeon_atombios_init(rdev);
1608         if (r)
1609                 return r;
1610         /* Post card if necessary */
1611         if (!r600_card_posted(rdev) && rdev->bios) {
1612                 DRM_INFO("GPU not posted. posting now...\n");
1613                 atom_asic_init(rdev->mode_info.atom_context);
1614         }
1615         /* Initialize scratch registers */
1616         r600_scratch_init(rdev);
1617         /* Initialize surface registers */
1618         radeon_surface_init(rdev);
1619         /* Initialize clocks */
1620         radeon_get_clock_info(rdev->ddev);
1621         r = radeon_clocks_init(rdev);
1622         if (r)
1623                 return r;
1624         /* Initialize power management */
1625         radeon_pm_init(rdev);
1626         /* Fence driver */
1627         r = radeon_fence_driver_init(rdev);
1628         if (r)
1629                 return r;
1630         r = r600_mc_init(rdev);
1631         if (r)
1632                 return r;
1633         /* Memory manager */
1634         r = radeon_object_init(rdev);
1635         if (r)
1636                 return r;
1637         rdev->cp.ring_obj = NULL;
1638         r600_ring_init(rdev, 1024 * 1024);
1639
1640         if (!rdev->me_fw || !rdev->pfp_fw) {
1641                 r = r600_cp_init_microcode(rdev);
1642                 if (r) {
1643                         DRM_ERROR("Failed to load firmware!\n");
1644                         return r;
1645                 }
1646         }
1647
1648         r = r600_pcie_gart_init(rdev);
1649         if (r)
1650                 return r;
1651
1652         rdev->accel_working = true;
1653         r = r600_blit_init(rdev);
1654         if (r) {
1655                 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1656                 return r;
1657         }
1658
1659         r = r600_startup(rdev);
1660         if (r) {
1661                 r600_suspend(rdev);
1662                 r600_wb_fini(rdev);
1663                 radeon_ring_fini(rdev);
1664                 r600_pcie_gart_fini(rdev);
1665                 rdev->accel_working = false;
1666         }
1667         if (rdev->accel_working) {
1668                 r = radeon_ib_pool_init(rdev);
1669                 if (r) {
1670                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1671                         rdev->accel_working = false;
1672                 } else {
1673                         r = r600_ib_test(rdev);
1674                         if (r) {
1675                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1676                                 rdev->accel_working = false;
1677                         }
1678                 }
1679         }
1680         return 0;
1681 }
1682
1683 void r600_fini(struct radeon_device *rdev)
1684 {
1685         /* Suspend operations */
1686         r600_suspend(rdev);
1687
1688         r600_blit_fini(rdev);
1689         radeon_ring_fini(rdev);
1690         r600_wb_fini(rdev);
1691         r600_pcie_gart_fini(rdev);
1692         radeon_gem_fini(rdev);
1693         radeon_fence_driver_fini(rdev);
1694         radeon_clocks_fini(rdev);
1695         if (rdev->flags & RADEON_IS_AGP)
1696                 radeon_agp_fini(rdev);
1697         radeon_object_fini(rdev);
1698         radeon_atombios_fini(rdev);
1699         kfree(rdev->bios);
1700         rdev->bios = NULL;
1701         radeon_dummy_page_fini(rdev);
1702 }
1703
1704
1705 /*
1706  * CS stuff
1707  */
1708 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1709 {
1710         /* FIXME: implement */
1711         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1712         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1713         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1714         radeon_ring_write(rdev, ib->length_dw);
1715 }
1716
1717 int r600_ib_test(struct radeon_device *rdev)
1718 {
1719         struct radeon_ib *ib;
1720         uint32_t scratch;
1721         uint32_t tmp = 0;
1722         unsigned i;
1723         int r;
1724
1725         r = radeon_scratch_get(rdev, &scratch);
1726         if (r) {
1727                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1728                 return r;
1729         }
1730         WREG32(scratch, 0xCAFEDEAD);
1731         r = radeon_ib_get(rdev, &ib);
1732         if (r) {
1733                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1734                 return r;
1735         }
1736         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1737         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1738         ib->ptr[2] = 0xDEADBEEF;
1739         ib->ptr[3] = PACKET2(0);
1740         ib->ptr[4] = PACKET2(0);
1741         ib->ptr[5] = PACKET2(0);
1742         ib->ptr[6] = PACKET2(0);
1743         ib->ptr[7] = PACKET2(0);
1744         ib->ptr[8] = PACKET2(0);
1745         ib->ptr[9] = PACKET2(0);
1746         ib->ptr[10] = PACKET2(0);
1747         ib->ptr[11] = PACKET2(0);
1748         ib->ptr[12] = PACKET2(0);
1749         ib->ptr[13] = PACKET2(0);
1750         ib->ptr[14] = PACKET2(0);
1751         ib->ptr[15] = PACKET2(0);
1752         ib->length_dw = 16;
1753         r = radeon_ib_schedule(rdev, ib);
1754         if (r) {
1755                 radeon_scratch_free(rdev, scratch);
1756                 radeon_ib_free(rdev, &ib);
1757                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1758                 return r;
1759         }
1760         r = radeon_fence_wait(ib->fence, false);
1761         if (r) {
1762                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1763                 return r;
1764         }
1765         for (i = 0; i < rdev->usec_timeout; i++) {
1766                 tmp = RREG32(scratch);
1767                 if (tmp == 0xDEADBEEF)
1768                         break;
1769                 DRM_UDELAY(1);
1770         }
1771         if (i < rdev->usec_timeout) {
1772                 DRM_INFO("ib test succeeded in %u usecs\n", i);
1773         } else {
1774                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1775                           scratch, tmp);
1776                 r = -EINVAL;
1777         }
1778         radeon_scratch_free(rdev, scratch);
1779         radeon_ib_free(rdev, &ib);
1780         return r;
1781 }
1782
1783
1784
1785
1786 /*
1787  * Debugfs info
1788  */
1789 #if defined(CONFIG_DEBUG_FS)
1790
1791 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
1792 {
1793         struct drm_info_node *node = (struct drm_info_node *) m->private;
1794         struct drm_device *dev = node->minor->dev;
1795         struct radeon_device *rdev = dev->dev_private;
1796         uint32_t rdp, wdp;
1797         unsigned count, i, j;
1798
1799         radeon_ring_free_size(rdev);
1800         rdp = RREG32(CP_RB_RPTR);
1801         wdp = RREG32(CP_RB_WPTR);
1802         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1803         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1804         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1805         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1806         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1807         seq_printf(m, "%u dwords in ring\n", count);
1808         for (j = 0; j <= count; j++) {
1809                 i = (rdp + j) & rdev->cp.ptr_mask;
1810                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1811         }
1812         return 0;
1813 }
1814
1815 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1816 {
1817         struct drm_info_node *node = (struct drm_info_node *) m->private;
1818         struct drm_device *dev = node->minor->dev;
1819         struct radeon_device *rdev = dev->dev_private;
1820
1821         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1822         DREG32_SYS(m, rdev, VM_L2_STATUS);
1823         return 0;
1824 }
1825
1826 static struct drm_info_list r600_mc_info_list[] = {
1827         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1828         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1829 };
1830 #endif
1831
1832 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1833 {
1834 #if defined(CONFIG_DEBUG_FS)
1835         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1836 #else
1837         return 0;
1838 #endif
1839 }