2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
41 #include <linux/firmware.h>
42 #include <linux/module.h>
44 #include "r100_reg_safe.h"
45 #include "rn50_reg_safe.h"
48 #define FIRMWARE_R100 "/*(DEBLOBBED)*/"
49 #define FIRMWARE_R200 "/*(DEBLOBBED)*/"
50 #define FIRMWARE_R300 "/*(DEBLOBBED)*/"
51 #define FIRMWARE_R420 "/*(DEBLOBBED)*/"
52 #define FIRMWARE_RS690 "/*(DEBLOBBED)*/"
53 #define FIRMWARE_RS600 "/*(DEBLOBBED)*/"
54 #define FIRMWARE_R520 "/*(DEBLOBBED)*/"
58 #include "r100_track.h"
60 /* This files gather functions specifics to:
61 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
62 * and others in some cases.
65 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
68 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
73 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
80 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
85 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
86 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
88 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
89 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
98 * r100_wait_for_vblank - vblank wait asic callback.
100 * @rdev: radeon_device pointer
101 * @crtc: crtc to wait for vblank on
103 * Wait for vblank on the requested crtc (r1xx-r4xx).
105 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
109 if (crtc >= rdev->num_crtc)
113 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
116 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
120 /* depending on when we hit vblank, we may be close to active; if so,
121 * wait for another frame.
123 while (r100_is_in_vblank(rdev, crtc)) {
124 if (i++ % 100 == 0) {
125 if (!r100_is_counter_moving(rdev, crtc))
130 while (!r100_is_in_vblank(rdev, crtc)) {
131 if (i++ % 100 == 0) {
132 if (!r100_is_counter_moving(rdev, crtc))
139 * r100_pre_page_flip - pre-pageflip callback.
141 * @rdev: radeon_device pointer
142 * @crtc: crtc to prepare for pageflip on
144 * Pre-pageflip callback (r1xx-r4xx).
145 * Enables the pageflip irq (vblank irq).
147 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
149 /* enable the pflip int */
150 radeon_irq_kms_pflip_irq_get(rdev, crtc);
154 * r100_post_page_flip - pos-pageflip callback.
156 * @rdev: radeon_device pointer
157 * @crtc: crtc to cleanup pageflip on
159 * Post-pageflip callback (r1xx-r4xx).
160 * Disables the pageflip irq (vblank irq).
162 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
164 /* disable the pflip int */
165 radeon_irq_kms_pflip_irq_put(rdev, crtc);
169 * r100_page_flip - pageflip callback.
171 * @rdev: radeon_device pointer
172 * @crtc_id: crtc to cleanup pageflip on
173 * @crtc_base: new address of the crtc (GPU MC address)
175 * Does the actual pageflip (r1xx-r4xx).
176 * During vblank we take the crtc lock and wait for the update_pending
177 * bit to go high, when it does, we release the lock, and allow the
178 * double buffered update to take place.
179 * Returns the current update pending status.
181 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
183 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
184 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
187 /* Lock the graphics update lock */
188 /* update the scanout addresses */
189 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
191 /* Wait for update_pending to go high. */
192 for (i = 0; i < rdev->usec_timeout; i++) {
193 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
197 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
199 /* Unlock the lock, so double-buffering can take place inside vblank */
200 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
201 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
203 /* Return current update_pending status: */
204 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
208 * r100_pm_get_dynpm_state - look up dynpm power state callback.
210 * @rdev: radeon_device pointer
212 * Look up the optimal power state based on the
213 * current state of the GPU (r1xx-r5xx).
214 * Used for dynpm only.
216 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
219 rdev->pm.dynpm_can_upclock = true;
220 rdev->pm.dynpm_can_downclock = true;
222 switch (rdev->pm.dynpm_planned_action) {
223 case DYNPM_ACTION_MINIMUM:
224 rdev->pm.requested_power_state_index = 0;
225 rdev->pm.dynpm_can_downclock = false;
227 case DYNPM_ACTION_DOWNCLOCK:
228 if (rdev->pm.current_power_state_index == 0) {
229 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
230 rdev->pm.dynpm_can_downclock = false;
232 if (rdev->pm.active_crtc_count > 1) {
233 for (i = 0; i < rdev->pm.num_power_states; i++) {
234 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
236 else if (i >= rdev->pm.current_power_state_index) {
237 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
240 rdev->pm.requested_power_state_index = i;
245 rdev->pm.requested_power_state_index =
246 rdev->pm.current_power_state_index - 1;
248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
251 RADEON_PM_MODE_NO_DISPLAY)) {
252 rdev->pm.requested_power_state_index++;
255 case DYNPM_ACTION_UPCLOCK:
256 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
257 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
258 rdev->pm.dynpm_can_upclock = false;
260 if (rdev->pm.active_crtc_count > 1) {
261 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
262 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
264 else if (i <= rdev->pm.current_power_state_index) {
265 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
268 rdev->pm.requested_power_state_index = i;
273 rdev->pm.requested_power_state_index =
274 rdev->pm.current_power_state_index + 1;
277 case DYNPM_ACTION_DEFAULT:
278 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
279 rdev->pm.dynpm_can_upclock = false;
281 case DYNPM_ACTION_NONE:
283 DRM_ERROR("Requested mode for not defined action\n");
286 /* only one clock mode per power state */
287 rdev->pm.requested_clock_mode_index = 0;
289 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
290 rdev->pm.power_state[rdev->pm.requested_power_state_index].
291 clock_info[rdev->pm.requested_clock_mode_index].sclk,
292 rdev->pm.power_state[rdev->pm.requested_power_state_index].
293 clock_info[rdev->pm.requested_clock_mode_index].mclk,
294 rdev->pm.power_state[rdev->pm.requested_power_state_index].
299 * r100_pm_init_profile - Initialize power profiles callback.
301 * @rdev: radeon_device pointer
303 * Initialize the power states used in profile mode
305 * Used for profile mode only.
307 void r100_pm_init_profile(struct radeon_device *rdev)
310 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
311 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
347 * r100_pm_misc - set additional pm hw parameters callback.
349 * @rdev: radeon_device pointer
351 * Set non-clock parameters associated with a power state
352 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
354 void r100_pm_misc(struct radeon_device *rdev)
356 int requested_index = rdev->pm.requested_power_state_index;
357 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
358 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
359 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
361 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
362 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
363 tmp = RREG32(voltage->gpio.reg);
364 if (voltage->active_high)
365 tmp |= voltage->gpio.mask;
367 tmp &= ~(voltage->gpio.mask);
368 WREG32(voltage->gpio.reg, tmp);
370 udelay(voltage->delay);
372 tmp = RREG32(voltage->gpio.reg);
373 if (voltage->active_high)
374 tmp &= ~voltage->gpio.mask;
376 tmp |= voltage->gpio.mask;
377 WREG32(voltage->gpio.reg, tmp);
379 udelay(voltage->delay);
383 sclk_cntl = RREG32_PLL(SCLK_CNTL);
384 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
385 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
386 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
387 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
388 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
389 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
390 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
391 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
393 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
394 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
395 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
396 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
397 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
399 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
401 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
402 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
403 if (voltage->delay) {
404 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
405 switch (voltage->delay) {
407 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
410 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
413 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
416 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
420 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
422 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
424 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
425 sclk_cntl &= ~FORCE_HDP;
427 sclk_cntl |= FORCE_HDP;
429 WREG32_PLL(SCLK_CNTL, sclk_cntl);
430 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
431 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
434 if ((rdev->flags & RADEON_IS_PCIE) &&
435 !(rdev->flags & RADEON_IS_IGP) &&
436 rdev->asic->pm.set_pcie_lanes &&
438 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
439 radeon_set_pcie_lanes(rdev,
441 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
446 * r100_pm_prepare - pre-power state change callback.
448 * @rdev: radeon_device pointer
450 * Prepare for a power state change (r1xx-r4xx).
452 void r100_pm_prepare(struct radeon_device *rdev)
454 struct drm_device *ddev = rdev->ddev;
455 struct drm_crtc *crtc;
456 struct radeon_crtc *radeon_crtc;
459 /* disable any active CRTCs */
460 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
461 radeon_crtc = to_radeon_crtc(crtc);
462 if (radeon_crtc->enabled) {
463 if (radeon_crtc->crtc_id) {
464 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
465 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
466 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
468 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
469 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
470 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
477 * r100_pm_finish - post-power state change callback.
479 * @rdev: radeon_device pointer
481 * Clean up after a power state change (r1xx-r4xx).
483 void r100_pm_finish(struct radeon_device *rdev)
485 struct drm_device *ddev = rdev->ddev;
486 struct drm_crtc *crtc;
487 struct radeon_crtc *radeon_crtc;
490 /* enable any active CRTCs */
491 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
492 radeon_crtc = to_radeon_crtc(crtc);
493 if (radeon_crtc->enabled) {
494 if (radeon_crtc->crtc_id) {
495 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
496 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
497 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
499 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
500 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
501 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
508 * r100_gui_idle - gui idle callback.
510 * @rdev: radeon_device pointer
512 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
513 * Returns true if idle, false if not.
515 bool r100_gui_idle(struct radeon_device *rdev)
517 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
523 /* hpd for digital panel detect/disconnect */
525 * r100_hpd_sense - hpd sense callback.
527 * @rdev: radeon_device pointer
528 * @hpd: hpd (hotplug detect) pin
530 * Checks if a digital monitor is connected (r1xx-r4xx).
531 * Returns true if connected, false if not connected.
533 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
535 bool connected = false;
539 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
543 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
553 * r100_hpd_set_polarity - hpd set polarity callback.
555 * @rdev: radeon_device pointer
556 * @hpd: hpd (hotplug detect) pin
558 * Set the polarity of the hpd pin (r1xx-r4xx).
560 void r100_hpd_set_polarity(struct radeon_device *rdev,
561 enum radeon_hpd_id hpd)
564 bool connected = r100_hpd_sense(rdev, hpd);
568 tmp = RREG32(RADEON_FP_GEN_CNTL);
570 tmp &= ~RADEON_FP_DETECT_INT_POL;
572 tmp |= RADEON_FP_DETECT_INT_POL;
573 WREG32(RADEON_FP_GEN_CNTL, tmp);
576 tmp = RREG32(RADEON_FP2_GEN_CNTL);
578 tmp &= ~RADEON_FP2_DETECT_INT_POL;
580 tmp |= RADEON_FP2_DETECT_INT_POL;
581 WREG32(RADEON_FP2_GEN_CNTL, tmp);
589 * r100_hpd_init - hpd setup callback.
591 * @rdev: radeon_device pointer
593 * Setup the hpd pins used by the card (r1xx-r4xx).
594 * Set the polarity, and enable the hpd interrupts.
596 void r100_hpd_init(struct radeon_device *rdev)
598 struct drm_device *dev = rdev->ddev;
599 struct drm_connector *connector;
602 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
603 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
604 enable |= 1 << radeon_connector->hpd.hpd;
605 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
607 radeon_irq_kms_enable_hpd(rdev, enable);
611 * r100_hpd_fini - hpd tear down callback.
613 * @rdev: radeon_device pointer
615 * Tear down the hpd pins used by the card (r1xx-r4xx).
616 * Disable the hpd interrupts.
618 void r100_hpd_fini(struct radeon_device *rdev)
620 struct drm_device *dev = rdev->ddev;
621 struct drm_connector *connector;
622 unsigned disable = 0;
624 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
625 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
626 disable |= 1 << radeon_connector->hpd.hpd;
628 radeon_irq_kms_disable_hpd(rdev, disable);
634 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
636 /* TODO: can we do somethings here ? */
637 /* It seems hw only cache one entry so we should discard this
638 * entry otherwise if first GPU GART read hit this entry it
639 * could end up in wrong address. */
642 int r100_pci_gart_init(struct radeon_device *rdev)
646 if (rdev->gart.ptr) {
647 WARN(1, "R100 PCI GART already initialized\n");
650 /* Initialize common gart structure */
651 r = radeon_gart_init(rdev);
654 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
655 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
656 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
657 return radeon_gart_table_ram_alloc(rdev);
660 int r100_pci_gart_enable(struct radeon_device *rdev)
664 radeon_gart_restore(rdev);
665 /* discard memory request outside of configured range */
666 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
667 WREG32(RADEON_AIC_CNTL, tmp);
668 /* set address range for PCI address translate */
669 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
670 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
671 /* set PCI GART page-table base address */
672 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
673 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
674 WREG32(RADEON_AIC_CNTL, tmp);
675 r100_pci_gart_tlb_flush(rdev);
676 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
677 (unsigned)(rdev->mc.gtt_size >> 20),
678 (unsigned long long)rdev->gart.table_addr);
679 rdev->gart.ready = true;
683 void r100_pci_gart_disable(struct radeon_device *rdev)
687 /* discard memory request outside of configured range */
688 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
689 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
690 WREG32(RADEON_AIC_LO_ADDR, 0);
691 WREG32(RADEON_AIC_HI_ADDR, 0);
694 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
696 u32 *gtt = rdev->gart.ptr;
698 if (i < 0 || i > rdev->gart.num_gpu_pages) {
701 gtt[i] = cpu_to_le32(lower_32_bits(addr));
705 void r100_pci_gart_fini(struct radeon_device *rdev)
707 radeon_gart_fini(rdev);
708 r100_pci_gart_disable(rdev);
709 radeon_gart_table_ram_free(rdev);
712 int r100_irq_set(struct radeon_device *rdev)
716 if (!rdev->irq.installed) {
717 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
718 WREG32(R_000040_GEN_INT_CNTL, 0);
721 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
722 tmp |= RADEON_SW_INT_ENABLE;
724 if (rdev->irq.crtc_vblank_int[0] ||
725 atomic_read(&rdev->irq.pflip[0])) {
726 tmp |= RADEON_CRTC_VBLANK_MASK;
728 if (rdev->irq.crtc_vblank_int[1] ||
729 atomic_read(&rdev->irq.pflip[1])) {
730 tmp |= RADEON_CRTC2_VBLANK_MASK;
732 if (rdev->irq.hpd[0]) {
733 tmp |= RADEON_FP_DETECT_MASK;
735 if (rdev->irq.hpd[1]) {
736 tmp |= RADEON_FP2_DETECT_MASK;
738 WREG32(RADEON_GEN_INT_CNTL, tmp);
740 /* read back to post the write */
741 RREG32(RADEON_GEN_INT_CNTL);
746 void r100_irq_disable(struct radeon_device *rdev)
750 WREG32(R_000040_GEN_INT_CNTL, 0);
751 /* Wait and acknowledge irq */
753 tmp = RREG32(R_000044_GEN_INT_STATUS);
754 WREG32(R_000044_GEN_INT_STATUS, tmp);
757 static uint32_t r100_irq_ack(struct radeon_device *rdev)
759 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
760 uint32_t irq_mask = RADEON_SW_INT_TEST |
761 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
762 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
765 WREG32(RADEON_GEN_INT_STATUS, irqs);
767 return irqs & irq_mask;
770 int r100_irq_process(struct radeon_device *rdev)
772 uint32_t status, msi_rearm;
773 bool queue_hotplug = false;
775 status = r100_irq_ack(rdev);
779 if (rdev->shutdown) {
784 if (status & RADEON_SW_INT_TEST) {
785 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
787 /* Vertical blank interrupts */
788 if (status & RADEON_CRTC_VBLANK_STAT) {
789 if (rdev->irq.crtc_vblank_int[0]) {
790 drm_handle_vblank(rdev->ddev, 0);
791 rdev->pm.vblank_sync = true;
792 wake_up(&rdev->irq.vblank_queue);
794 if (atomic_read(&rdev->irq.pflip[0]))
795 radeon_crtc_handle_flip(rdev, 0);
797 if (status & RADEON_CRTC2_VBLANK_STAT) {
798 if (rdev->irq.crtc_vblank_int[1]) {
799 drm_handle_vblank(rdev->ddev, 1);
800 rdev->pm.vblank_sync = true;
801 wake_up(&rdev->irq.vblank_queue);
803 if (atomic_read(&rdev->irq.pflip[1]))
804 radeon_crtc_handle_flip(rdev, 1);
806 if (status & RADEON_FP_DETECT_STAT) {
807 queue_hotplug = true;
810 if (status & RADEON_FP2_DETECT_STAT) {
811 queue_hotplug = true;
814 status = r100_irq_ack(rdev);
817 schedule_work(&rdev->hotplug_work);
818 if (rdev->msi_enabled) {
819 switch (rdev->family) {
822 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
823 WREG32(RADEON_AIC_CNTL, msi_rearm);
824 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
827 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
834 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
837 return RREG32(RADEON_CRTC_CRNT_FRAME);
839 return RREG32(RADEON_CRTC2_CRNT_FRAME);
842 /* Who ever call radeon_fence_emit should call ring_lock and ask
843 * for enough space (today caller are ib schedule and buffer move) */
844 void r100_fence_ring_emit(struct radeon_device *rdev,
845 struct radeon_fence *fence)
847 struct radeon_ring *ring = &rdev->ring[fence->ring];
849 /* We have to make sure that caches are flushed before
850 * CPU might read something from VRAM. */
851 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
852 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
853 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
854 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
855 /* Wait until IDLE & CLEAN */
856 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
857 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
858 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
859 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
860 RADEON_HDP_READ_BUFFER_INVALIDATE);
861 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
862 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
863 /* Emit fence sequence & fire IRQ */
864 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
865 radeon_ring_write(ring, fence->seq);
866 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
867 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
870 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
871 struct radeon_ring *ring,
872 struct radeon_semaphore *semaphore,
875 /* Unused on older asics, since we don't have semaphores or multiple rings */
880 int r100_copy_blit(struct radeon_device *rdev,
883 unsigned num_gpu_pages,
884 struct radeon_fence **fence)
886 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
888 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
890 uint32_t stride_pixels;
895 /* radeon limited to 16k stride */
896 stride_bytes &= 0x3fff;
897 /* radeon pitch is /64 */
898 pitch = stride_bytes / 64;
899 stride_pixels = stride_bytes / 4;
900 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
902 /* Ask for enough room for blit + flush + fence */
903 ndw = 64 + (10 * num_loops);
904 r = radeon_ring_lock(rdev, ring, ndw);
906 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
909 while (num_gpu_pages > 0) {
910 cur_pages = num_gpu_pages;
911 if (cur_pages > 8191) {
914 num_gpu_pages -= cur_pages;
916 /* pages are in Y direction - height
917 page width in X direction - width */
918 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
919 radeon_ring_write(ring,
920 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
921 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
922 RADEON_GMC_SRC_CLIPPING |
923 RADEON_GMC_DST_CLIPPING |
924 RADEON_GMC_BRUSH_NONE |
925 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
926 RADEON_GMC_SRC_DATATYPE_COLOR |
928 RADEON_DP_SRC_SOURCE_MEMORY |
929 RADEON_GMC_CLR_CMP_CNTL_DIS |
930 RADEON_GMC_WR_MSK_DIS);
931 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
932 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
933 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
934 radeon_ring_write(ring, 0);
935 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
936 radeon_ring_write(ring, num_gpu_pages);
937 radeon_ring_write(ring, num_gpu_pages);
938 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
940 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
941 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
942 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
943 radeon_ring_write(ring,
944 RADEON_WAIT_2D_IDLECLEAN |
945 RADEON_WAIT_HOST_IDLECLEAN |
946 RADEON_WAIT_DMA_GUI_IDLE);
948 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
950 radeon_ring_unlock_commit(rdev, ring);
954 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
959 for (i = 0; i < rdev->usec_timeout; i++) {
960 tmp = RREG32(R_000E40_RBBM_STATUS);
961 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
969 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
973 r = radeon_ring_lock(rdev, ring, 2);
977 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
978 radeon_ring_write(ring,
979 RADEON_ISYNC_ANY2D_IDLE3D |
980 RADEON_ISYNC_ANY3D_IDLE2D |
981 RADEON_ISYNC_WAIT_IDLEGUI |
982 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
983 radeon_ring_unlock_commit(rdev, ring);
987 /* Load the microcode for the CP */
988 static int r100_cp_init_microcode(struct radeon_device *rdev)
990 const char *fw_name = NULL;
995 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
996 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
997 (rdev->family == CHIP_RS200)) {
998 DRM_INFO("Loading R100 Microcode\n");
999 fw_name = FIRMWARE_R100;
1000 } else if ((rdev->family == CHIP_R200) ||
1001 (rdev->family == CHIP_RV250) ||
1002 (rdev->family == CHIP_RV280) ||
1003 (rdev->family == CHIP_RS300)) {
1004 DRM_INFO("Loading R200 Microcode\n");
1005 fw_name = FIRMWARE_R200;
1006 } else if ((rdev->family == CHIP_R300) ||
1007 (rdev->family == CHIP_R350) ||
1008 (rdev->family == CHIP_RV350) ||
1009 (rdev->family == CHIP_RV380) ||
1010 (rdev->family == CHIP_RS400) ||
1011 (rdev->family == CHIP_RS480)) {
1012 DRM_INFO("Loading R300 Microcode\n");
1013 fw_name = FIRMWARE_R300;
1014 } else if ((rdev->family == CHIP_R420) ||
1015 (rdev->family == CHIP_R423) ||
1016 (rdev->family == CHIP_RV410)) {
1017 DRM_INFO("Loading R400 Microcode\n");
1018 fw_name = FIRMWARE_R420;
1019 } else if ((rdev->family == CHIP_RS690) ||
1020 (rdev->family == CHIP_RS740)) {
1021 DRM_INFO("Loading RS690/RS740 Microcode\n");
1022 fw_name = FIRMWARE_RS690;
1023 } else if (rdev->family == CHIP_RS600) {
1024 DRM_INFO("Loading RS600 Microcode\n");
1025 fw_name = FIRMWARE_RS600;
1026 } else if ((rdev->family == CHIP_RV515) ||
1027 (rdev->family == CHIP_R520) ||
1028 (rdev->family == CHIP_RV530) ||
1029 (rdev->family == CHIP_R580) ||
1030 (rdev->family == CHIP_RV560) ||
1031 (rdev->family == CHIP_RV570)) {
1032 DRM_INFO("Loading R500 Microcode\n");
1033 fw_name = FIRMWARE_R520;
1036 err = reject_firmware(&rdev->me_fw, fw_name, rdev->dev);
1038 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1040 } else if (rdev->me_fw->size % 8) {
1042 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1043 rdev->me_fw->size, fw_name);
1045 release_firmware(rdev->me_fw);
1051 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1052 struct radeon_ring *ring)
1056 if (rdev->wb.enabled)
1057 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1059 rptr = RREG32(RADEON_CP_RB_RPTR);
1064 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1065 struct radeon_ring *ring)
1069 wptr = RREG32(RADEON_CP_RB_WPTR);
1074 void r100_gfx_set_wptr(struct radeon_device *rdev,
1075 struct radeon_ring *ring)
1077 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1078 (void)RREG32(RADEON_CP_RB_WPTR);
1081 static void r100_cp_load_microcode(struct radeon_device *rdev)
1083 const __be32 *fw_data;
1086 if (r100_gui_wait_for_idle(rdev)) {
1087 printk(KERN_WARNING "Failed to wait GUI idle while "
1088 "programming pipes. Bad things might happen.\n");
1092 size = rdev->me_fw->size / 4;
1093 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1094 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1095 for (i = 0; i < size; i += 2) {
1096 WREG32(RADEON_CP_ME_RAM_DATAH,
1097 be32_to_cpup(&fw_data[i]));
1098 WREG32(RADEON_CP_ME_RAM_DATAL,
1099 be32_to_cpup(&fw_data[i + 1]));
1104 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1106 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1110 unsigned pre_write_timer;
1111 unsigned pre_write_limit;
1112 unsigned indirect2_start;
1113 unsigned indirect1_start;
1117 if (r100_debugfs_cp_init(rdev)) {
1118 DRM_ERROR("Failed to register debugfs file for CP !\n");
1121 r = r100_cp_init_microcode(rdev);
1123 DRM_ERROR("Failed to load firmware!\n");
1128 /* Align ring size */
1129 rb_bufsz = order_base_2(ring_size / 8);
1130 ring_size = (1 << (rb_bufsz + 1)) * 4;
1131 r100_cp_load_microcode(rdev);
1132 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1137 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1138 * the rptr copy in system ram */
1140 /* cp will read 128bytes at a time (4 dwords) */
1142 ring->align_mask = 16 - 1;
1143 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1144 pre_write_timer = 64;
1145 /* Force CP_RB_WPTR write if written more than one time before the
1148 pre_write_limit = 0;
1149 /* Setup the cp cache like this (cache size is 96 dwords) :
1151 * INDIRECT1 16 to 79
1152 * INDIRECT2 80 to 95
1153 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1154 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1155 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1156 * Idea being that most of the gpu cmd will be through indirect1 buffer
1157 * so it gets the bigger cache.
1159 indirect2_start = 80;
1160 indirect1_start = 16;
1162 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1163 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1164 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1165 REG_SET(RADEON_MAX_FETCH, max_fetch));
1167 tmp |= RADEON_BUF_SWAP_32BIT;
1169 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1171 /* Set ring address */
1172 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1173 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1174 /* Force read & write ptr to 0 */
1175 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1176 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1178 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1180 /* set the wb address whether it's enabled or not */
1181 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1182 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1183 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1185 if (rdev->wb.enabled)
1186 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1188 tmp |= RADEON_RB_NO_UPDATE;
1189 WREG32(R_000770_SCRATCH_UMSK, 0);
1192 WREG32(RADEON_CP_RB_CNTL, tmp);
1194 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1195 /* Set cp mode to bus mastering & enable cp*/
1196 WREG32(RADEON_CP_CSQ_MODE,
1197 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1198 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1199 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1200 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1201 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1203 /* at this point everything should be setup correctly to enable master */
1204 pci_set_master(rdev->pdev);
1206 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1207 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1209 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1213 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1215 if (!ring->rptr_save_reg /* not resuming from suspend */
1216 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1217 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1219 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1220 ring->rptr_save_reg = 0;
1226 void r100_cp_fini(struct radeon_device *rdev)
1228 if (r100_cp_wait_for_idle(rdev)) {
1229 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1232 r100_cp_disable(rdev);
1233 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1234 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1235 DRM_INFO("radeon: cp finalized\n");
1238 void r100_cp_disable(struct radeon_device *rdev)
1241 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1242 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1243 WREG32(RADEON_CP_CSQ_MODE, 0);
1244 WREG32(RADEON_CP_CSQ_CNTL, 0);
1245 WREG32(R_000770_SCRATCH_UMSK, 0);
1246 if (r100_gui_wait_for_idle(rdev)) {
1247 printk(KERN_WARNING "Failed to wait GUI idle while "
1248 "programming pipes. Bad things might happen.\n");
1255 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1256 struct radeon_cs_packet *pkt,
1263 struct radeon_cs_reloc *reloc;
1266 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1268 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1270 radeon_cs_dump_packet(p, pkt);
1274 value = radeon_get_ib_value(p, idx);
1275 tmp = value & 0x003fffff;
1276 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1278 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1279 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1280 tile_flags |= RADEON_DST_TILE_MACRO;
1281 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1282 if (reg == RADEON_SRC_PITCH_OFFSET) {
1283 DRM_ERROR("Cannot src blit from microtiled surface\n");
1284 radeon_cs_dump_packet(p, pkt);
1287 tile_flags |= RADEON_DST_TILE_MICRO;
1291 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1293 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1297 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1298 struct radeon_cs_packet *pkt,
1302 struct radeon_cs_reloc *reloc;
1303 struct r100_cs_track *track;
1305 volatile uint32_t *ib;
1309 track = (struct r100_cs_track *)p->track;
1310 c = radeon_get_ib_value(p, idx++) & 0x1F;
1312 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1314 radeon_cs_dump_packet(p, pkt);
1317 track->num_arrays = c;
1318 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1319 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1321 DRM_ERROR("No reloc for packet3 %d\n",
1323 radeon_cs_dump_packet(p, pkt);
1326 idx_value = radeon_get_ib_value(p, idx);
1327 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1329 track->arrays[i + 0].esize = idx_value >> 8;
1330 track->arrays[i + 0].robj = reloc->robj;
1331 track->arrays[i + 0].esize &= 0x7F;
1332 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1334 DRM_ERROR("No reloc for packet3 %d\n",
1336 radeon_cs_dump_packet(p, pkt);
1339 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1340 track->arrays[i + 1].robj = reloc->robj;
1341 track->arrays[i + 1].esize = idx_value >> 24;
1342 track->arrays[i + 1].esize &= 0x7F;
1345 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1347 DRM_ERROR("No reloc for packet3 %d\n",
1349 radeon_cs_dump_packet(p, pkt);
1352 idx_value = radeon_get_ib_value(p, idx);
1353 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1354 track->arrays[i + 0].robj = reloc->robj;
1355 track->arrays[i + 0].esize = idx_value >> 8;
1356 track->arrays[i + 0].esize &= 0x7F;
1361 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1362 struct radeon_cs_packet *pkt,
1363 const unsigned *auth, unsigned n,
1364 radeon_packet0_check_t check)
1373 /* Check that register fall into register range
1374 * determined by the number of entry (n) in the
1375 * safe register bitmap.
1377 if (pkt->one_reg_wr) {
1378 if ((reg >> 7) > n) {
1382 if (((reg + (pkt->count << 2)) >> 7) > n) {
1386 for (i = 0; i <= pkt->count; i++, idx++) {
1388 m = 1 << ((reg >> 2) & 31);
1390 r = check(p, pkt, idx, reg);
1395 if (pkt->one_reg_wr) {
1396 if (!(auth[j] & m)) {
1407 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1408 * @parser: parser structure holding parsing context.
1410 * Userspace sends a special sequence for VLINE waits.
1411 * PACKET0 - VLINE_START_END + value
1412 * PACKET0 - WAIT_UNTIL +_value
1413 * RELOC (P3) - crtc_id in reloc.
1415 * This function parses this and relocates the VLINE START END
1416 * and WAIT UNTIL packets to the correct crtc.
1417 * It also detects a switched off crtc and nulls out the
1418 * wait in that case.
1420 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1422 struct drm_mode_object *obj;
1423 struct drm_crtc *crtc;
1424 struct radeon_crtc *radeon_crtc;
1425 struct radeon_cs_packet p3reloc, waitreloc;
1428 uint32_t header, h_idx, reg;
1429 volatile uint32_t *ib;
1433 /* parse the wait until */
1434 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1438 /* check its a wait until and only 1 count */
1439 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1440 waitreloc.count != 0) {
1441 DRM_ERROR("vline wait had illegal wait until segment\n");
1445 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1446 DRM_ERROR("vline wait had illegal wait until\n");
1450 /* jump over the NOP */
1451 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1456 p->idx += waitreloc.count + 2;
1457 p->idx += p3reloc.count + 2;
1459 header = radeon_get_ib_value(p, h_idx);
1460 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1461 reg = R100_CP_PACKET0_GET_REG(header);
1462 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1464 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1467 crtc = obj_to_crtc(obj);
1468 radeon_crtc = to_radeon_crtc(crtc);
1469 crtc_id = radeon_crtc->crtc_id;
1471 if (!crtc->enabled) {
1472 /* if the CRTC isn't enabled - we need to nop out the wait until */
1473 ib[h_idx + 2] = PACKET2(0);
1474 ib[h_idx + 3] = PACKET2(0);
1475 } else if (crtc_id == 1) {
1477 case AVIVO_D1MODE_VLINE_START_END:
1478 header &= ~R300_CP_PACKET0_REG_MASK;
1479 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1481 case RADEON_CRTC_GUI_TRIG_VLINE:
1482 header &= ~R300_CP_PACKET0_REG_MASK;
1483 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1486 DRM_ERROR("unknown crtc reloc\n");
1490 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1496 static int r100_get_vtx_size(uint32_t vtx_fmt)
1500 /* ordered according to bits in spec */
1501 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1503 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1505 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1507 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1509 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1511 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1513 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1515 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1517 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1519 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1521 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1523 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1525 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1527 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1529 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1532 if (vtx_fmt & (0x7 << 15))
1533 vtx_size += (vtx_fmt >> 15) & 0x7;
1534 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1536 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1538 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1540 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1542 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1544 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1549 static int r100_packet0_check(struct radeon_cs_parser *p,
1550 struct radeon_cs_packet *pkt,
1551 unsigned idx, unsigned reg)
1553 struct radeon_cs_reloc *reloc;
1554 struct r100_cs_track *track;
1555 volatile uint32_t *ib;
1563 track = (struct r100_cs_track *)p->track;
1565 idx_value = radeon_get_ib_value(p, idx);
1568 case RADEON_CRTC_GUI_TRIG_VLINE:
1569 r = r100_cs_packet_parse_vline(p);
1571 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1573 radeon_cs_dump_packet(p, pkt);
1577 /* FIXME: only allow PACKET3 blit? easier to check for out of
1579 case RADEON_DST_PITCH_OFFSET:
1580 case RADEON_SRC_PITCH_OFFSET:
1581 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1585 case RADEON_RB3D_DEPTHOFFSET:
1586 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1588 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1590 radeon_cs_dump_packet(p, pkt);
1593 track->zb.robj = reloc->robj;
1594 track->zb.offset = idx_value;
1595 track->zb_dirty = true;
1596 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1598 case RADEON_RB3D_COLOROFFSET:
1599 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1601 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1603 radeon_cs_dump_packet(p, pkt);
1606 track->cb[0].robj = reloc->robj;
1607 track->cb[0].offset = idx_value;
1608 track->cb_dirty = true;
1609 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1611 case RADEON_PP_TXOFFSET_0:
1612 case RADEON_PP_TXOFFSET_1:
1613 case RADEON_PP_TXOFFSET_2:
1614 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1615 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1617 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1619 radeon_cs_dump_packet(p, pkt);
1622 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1623 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1624 tile_flags |= RADEON_TXO_MACRO_TILE;
1625 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1626 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1628 tmp = idx_value & ~(0x7 << 2);
1630 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1632 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1633 track->textures[i].robj = reloc->robj;
1634 track->tex_dirty = true;
1636 case RADEON_PP_CUBIC_OFFSET_T0_0:
1637 case RADEON_PP_CUBIC_OFFSET_T0_1:
1638 case RADEON_PP_CUBIC_OFFSET_T0_2:
1639 case RADEON_PP_CUBIC_OFFSET_T0_3:
1640 case RADEON_PP_CUBIC_OFFSET_T0_4:
1641 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1642 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1644 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1646 radeon_cs_dump_packet(p, pkt);
1649 track->textures[0].cube_info[i].offset = idx_value;
1650 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1651 track->textures[0].cube_info[i].robj = reloc->robj;
1652 track->tex_dirty = true;
1654 case RADEON_PP_CUBIC_OFFSET_T1_0:
1655 case RADEON_PP_CUBIC_OFFSET_T1_1:
1656 case RADEON_PP_CUBIC_OFFSET_T1_2:
1657 case RADEON_PP_CUBIC_OFFSET_T1_3:
1658 case RADEON_PP_CUBIC_OFFSET_T1_4:
1659 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1660 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1662 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1664 radeon_cs_dump_packet(p, pkt);
1667 track->textures[1].cube_info[i].offset = idx_value;
1668 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1669 track->textures[1].cube_info[i].robj = reloc->robj;
1670 track->tex_dirty = true;
1672 case RADEON_PP_CUBIC_OFFSET_T2_0:
1673 case RADEON_PP_CUBIC_OFFSET_T2_1:
1674 case RADEON_PP_CUBIC_OFFSET_T2_2:
1675 case RADEON_PP_CUBIC_OFFSET_T2_3:
1676 case RADEON_PP_CUBIC_OFFSET_T2_4:
1677 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1678 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1680 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1682 radeon_cs_dump_packet(p, pkt);
1685 track->textures[2].cube_info[i].offset = idx_value;
1686 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1687 track->textures[2].cube_info[i].robj = reloc->robj;
1688 track->tex_dirty = true;
1690 case RADEON_RE_WIDTH_HEIGHT:
1691 track->maxy = ((idx_value >> 16) & 0x7FF);
1692 track->cb_dirty = true;
1693 track->zb_dirty = true;
1695 case RADEON_RB3D_COLORPITCH:
1696 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1700 radeon_cs_dump_packet(p, pkt);
1703 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1704 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1705 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1706 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1707 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1709 tmp = idx_value & ~(0x7 << 16);
1713 ib[idx] = idx_value;
1715 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1716 track->cb_dirty = true;
1718 case RADEON_RB3D_DEPTHPITCH:
1719 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1720 track->zb_dirty = true;
1722 case RADEON_RB3D_CNTL:
1723 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1729 track->cb[0].cpp = 1;
1734 track->cb[0].cpp = 2;
1737 track->cb[0].cpp = 4;
1740 DRM_ERROR("Invalid color buffer format (%d) !\n",
1741 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1744 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1745 track->cb_dirty = true;
1746 track->zb_dirty = true;
1748 case RADEON_RB3D_ZSTENCILCNTL:
1749 switch (idx_value & 0xf) {
1764 track->zb_dirty = true;
1766 case RADEON_RB3D_ZPASS_ADDR:
1767 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1769 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1771 radeon_cs_dump_packet(p, pkt);
1774 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1776 case RADEON_PP_CNTL:
1778 uint32_t temp = idx_value >> 4;
1779 for (i = 0; i < track->num_texture; i++)
1780 track->textures[i].enabled = !!(temp & (1 << i));
1781 track->tex_dirty = true;
1784 case RADEON_SE_VF_CNTL:
1785 track->vap_vf_cntl = idx_value;
1787 case RADEON_SE_VTX_FMT:
1788 track->vtx_size = r100_get_vtx_size(idx_value);
1790 case RADEON_PP_TEX_SIZE_0:
1791 case RADEON_PP_TEX_SIZE_1:
1792 case RADEON_PP_TEX_SIZE_2:
1793 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1794 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1795 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1796 track->tex_dirty = true;
1798 case RADEON_PP_TEX_PITCH_0:
1799 case RADEON_PP_TEX_PITCH_1:
1800 case RADEON_PP_TEX_PITCH_2:
1801 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1802 track->textures[i].pitch = idx_value + 32;
1803 track->tex_dirty = true;
1805 case RADEON_PP_TXFILTER_0:
1806 case RADEON_PP_TXFILTER_1:
1807 case RADEON_PP_TXFILTER_2:
1808 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1809 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1810 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1811 tmp = (idx_value >> 23) & 0x7;
1812 if (tmp == 2 || tmp == 6)
1813 track->textures[i].roundup_w = false;
1814 tmp = (idx_value >> 27) & 0x7;
1815 if (tmp == 2 || tmp == 6)
1816 track->textures[i].roundup_h = false;
1817 track->tex_dirty = true;
1819 case RADEON_PP_TXFORMAT_0:
1820 case RADEON_PP_TXFORMAT_1:
1821 case RADEON_PP_TXFORMAT_2:
1822 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1823 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1824 track->textures[i].use_pitch = 1;
1826 track->textures[i].use_pitch = 0;
1827 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1828 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1830 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1831 track->textures[i].tex_coord_type = 2;
1832 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1833 case RADEON_TXFORMAT_I8:
1834 case RADEON_TXFORMAT_RGB332:
1835 case RADEON_TXFORMAT_Y8:
1836 track->textures[i].cpp = 1;
1837 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1839 case RADEON_TXFORMAT_AI88:
1840 case RADEON_TXFORMAT_ARGB1555:
1841 case RADEON_TXFORMAT_RGB565:
1842 case RADEON_TXFORMAT_ARGB4444:
1843 case RADEON_TXFORMAT_VYUY422:
1844 case RADEON_TXFORMAT_YVYU422:
1845 case RADEON_TXFORMAT_SHADOW16:
1846 case RADEON_TXFORMAT_LDUDV655:
1847 case RADEON_TXFORMAT_DUDV88:
1848 track->textures[i].cpp = 2;
1849 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1851 case RADEON_TXFORMAT_ARGB8888:
1852 case RADEON_TXFORMAT_RGBA8888:
1853 case RADEON_TXFORMAT_SHADOW32:
1854 case RADEON_TXFORMAT_LDUDUV8888:
1855 track->textures[i].cpp = 4;
1856 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1858 case RADEON_TXFORMAT_DXT1:
1859 track->textures[i].cpp = 1;
1860 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1862 case RADEON_TXFORMAT_DXT23:
1863 case RADEON_TXFORMAT_DXT45:
1864 track->textures[i].cpp = 1;
1865 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1868 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1869 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1870 track->tex_dirty = true;
1872 case RADEON_PP_CUBIC_FACES_0:
1873 case RADEON_PP_CUBIC_FACES_1:
1874 case RADEON_PP_CUBIC_FACES_2:
1876 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1877 for (face = 0; face < 4; face++) {
1878 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1879 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1881 track->tex_dirty = true;
1884 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1891 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1892 struct radeon_cs_packet *pkt,
1893 struct radeon_bo *robj)
1898 value = radeon_get_ib_value(p, idx + 2);
1899 if ((value + 1) > radeon_bo_size(robj)) {
1900 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1901 "(need %u have %lu) !\n",
1903 radeon_bo_size(robj));
1909 static int r100_packet3_check(struct radeon_cs_parser *p,
1910 struct radeon_cs_packet *pkt)
1912 struct radeon_cs_reloc *reloc;
1913 struct r100_cs_track *track;
1915 volatile uint32_t *ib;
1920 track = (struct r100_cs_track *)p->track;
1921 switch (pkt->opcode) {
1922 case PACKET3_3D_LOAD_VBPNTR:
1923 r = r100_packet3_load_vbpntr(p, pkt, idx);
1927 case PACKET3_INDX_BUFFER:
1928 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1930 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1931 radeon_cs_dump_packet(p, pkt);
1934 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1935 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1941 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1942 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1944 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1945 radeon_cs_dump_packet(p, pkt);
1948 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1949 track->num_arrays = 1;
1950 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1952 track->arrays[0].robj = reloc->robj;
1953 track->arrays[0].esize = track->vtx_size;
1955 track->max_indx = radeon_get_ib_value(p, idx+1);
1957 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1958 track->immd_dwords = pkt->count - 1;
1959 r = r100_cs_track_check(p->rdev, track);
1963 case PACKET3_3D_DRAW_IMMD:
1964 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1965 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1968 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1969 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1970 track->immd_dwords = pkt->count - 1;
1971 r = r100_cs_track_check(p->rdev, track);
1975 /* triggers drawing using in-packet vertex data */
1976 case PACKET3_3D_DRAW_IMMD_2:
1977 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1978 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1981 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1982 track->immd_dwords = pkt->count;
1983 r = r100_cs_track_check(p->rdev, track);
1987 /* triggers drawing using in-packet vertex data */
1988 case PACKET3_3D_DRAW_VBUF_2:
1989 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1990 r = r100_cs_track_check(p->rdev, track);
1994 /* triggers drawing of vertex buffers setup elsewhere */
1995 case PACKET3_3D_DRAW_INDX_2:
1996 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1997 r = r100_cs_track_check(p->rdev, track);
2001 /* triggers drawing using indices to vertex buffer */
2002 case PACKET3_3D_DRAW_VBUF:
2003 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2004 r = r100_cs_track_check(p->rdev, track);
2008 /* triggers drawing of vertex buffers setup elsewhere */
2009 case PACKET3_3D_DRAW_INDX:
2010 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2011 r = r100_cs_track_check(p->rdev, track);
2015 /* triggers drawing using indices to vertex buffer */
2016 case PACKET3_3D_CLEAR_HIZ:
2017 case PACKET3_3D_CLEAR_ZMASK:
2018 if (p->rdev->hyperz_filp != p->filp)
2024 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2030 int r100_cs_parse(struct radeon_cs_parser *p)
2032 struct radeon_cs_packet pkt;
2033 struct r100_cs_track *track;
2036 track = kzalloc(sizeof(*track), GFP_KERNEL);
2039 r100_cs_track_clear(p->rdev, track);
2042 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2046 p->idx += pkt.count + 2;
2048 case RADEON_PACKET_TYPE0:
2049 if (p->rdev->family >= CHIP_R200)
2050 r = r100_cs_parse_packet0(p, &pkt,
2051 p->rdev->config.r100.reg_safe_bm,
2052 p->rdev->config.r100.reg_safe_bm_size,
2053 &r200_packet0_check);
2055 r = r100_cs_parse_packet0(p, &pkt,
2056 p->rdev->config.r100.reg_safe_bm,
2057 p->rdev->config.r100.reg_safe_bm_size,
2058 &r100_packet0_check);
2060 case RADEON_PACKET_TYPE2:
2062 case RADEON_PACKET_TYPE3:
2063 r = r100_packet3_check(p, &pkt);
2066 DRM_ERROR("Unknown packet type %d !\n",
2072 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2076 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2078 DRM_ERROR("pitch %d\n", t->pitch);
2079 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2080 DRM_ERROR("width %d\n", t->width);
2081 DRM_ERROR("width_11 %d\n", t->width_11);
2082 DRM_ERROR("height %d\n", t->height);
2083 DRM_ERROR("height_11 %d\n", t->height_11);
2084 DRM_ERROR("num levels %d\n", t->num_levels);
2085 DRM_ERROR("depth %d\n", t->txdepth);
2086 DRM_ERROR("bpp %d\n", t->cpp);
2087 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2088 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2089 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2090 DRM_ERROR("compress format %d\n", t->compress_format);
2093 static int r100_track_compress_size(int compress_format, int w, int h)
2095 int block_width, block_height, block_bytes;
2096 int wblocks, hblocks;
2103 switch (compress_format) {
2104 case R100_TRACK_COMP_DXT1:
2109 case R100_TRACK_COMP_DXT35:
2115 hblocks = (h + block_height - 1) / block_height;
2116 wblocks = (w + block_width - 1) / block_width;
2117 if (wblocks < min_wblocks)
2118 wblocks = min_wblocks;
2119 sz = wblocks * hblocks * block_bytes;
2123 static int r100_cs_track_cube(struct radeon_device *rdev,
2124 struct r100_cs_track *track, unsigned idx)
2126 unsigned face, w, h;
2127 struct radeon_bo *cube_robj;
2129 unsigned compress_format = track->textures[idx].compress_format;
2131 for (face = 0; face < 5; face++) {
2132 cube_robj = track->textures[idx].cube_info[face].robj;
2133 w = track->textures[idx].cube_info[face].width;
2134 h = track->textures[idx].cube_info[face].height;
2136 if (compress_format) {
2137 size = r100_track_compress_size(compress_format, w, h);
2140 size *= track->textures[idx].cpp;
2142 size += track->textures[idx].cube_info[face].offset;
2144 if (size > radeon_bo_size(cube_robj)) {
2145 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2146 size, radeon_bo_size(cube_robj));
2147 r100_cs_track_texture_print(&track->textures[idx]);
2154 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2155 struct r100_cs_track *track)
2157 struct radeon_bo *robj;
2159 unsigned u, i, w, h, d;
2162 for (u = 0; u < track->num_texture; u++) {
2163 if (!track->textures[u].enabled)
2165 if (track->textures[u].lookup_disable)
2167 robj = track->textures[u].robj;
2169 DRM_ERROR("No texture bound to unit %u\n", u);
2173 for (i = 0; i <= track->textures[u].num_levels; i++) {
2174 if (track->textures[u].use_pitch) {
2175 if (rdev->family < CHIP_R300)
2176 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2178 w = track->textures[u].pitch / (1 << i);
2180 w = track->textures[u].width;
2181 if (rdev->family >= CHIP_RV515)
2182 w |= track->textures[u].width_11;
2184 if (track->textures[u].roundup_w)
2185 w = roundup_pow_of_two(w);
2187 h = track->textures[u].height;
2188 if (rdev->family >= CHIP_RV515)
2189 h |= track->textures[u].height_11;
2191 if (track->textures[u].roundup_h)
2192 h = roundup_pow_of_two(h);
2193 if (track->textures[u].tex_coord_type == 1) {
2194 d = (1 << track->textures[u].txdepth) / (1 << i);
2200 if (track->textures[u].compress_format) {
2202 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2203 /* compressed textures are block based */
2207 size *= track->textures[u].cpp;
2209 switch (track->textures[u].tex_coord_type) {
2214 if (track->separate_cube) {
2215 ret = r100_cs_track_cube(rdev, track, u);
2222 DRM_ERROR("Invalid texture coordinate type %u for unit "
2223 "%u\n", track->textures[u].tex_coord_type, u);
2226 if (size > radeon_bo_size(robj)) {
2227 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2228 "%lu\n", u, size, radeon_bo_size(robj));
2229 r100_cs_track_texture_print(&track->textures[u]);
2236 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2242 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2244 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2245 !track->blend_read_enable)
2248 for (i = 0; i < num_cb; i++) {
2249 if (track->cb[i].robj == NULL) {
2250 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2253 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2254 size += track->cb[i].offset;
2255 if (size > radeon_bo_size(track->cb[i].robj)) {
2256 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2257 "(need %lu have %lu) !\n", i, size,
2258 radeon_bo_size(track->cb[i].robj));
2259 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2260 i, track->cb[i].pitch, track->cb[i].cpp,
2261 track->cb[i].offset, track->maxy);
2265 track->cb_dirty = false;
2267 if (track->zb_dirty && track->z_enabled) {
2268 if (track->zb.robj == NULL) {
2269 DRM_ERROR("[drm] No buffer for z buffer !\n");
2272 size = track->zb.pitch * track->zb.cpp * track->maxy;
2273 size += track->zb.offset;
2274 if (size > radeon_bo_size(track->zb.robj)) {
2275 DRM_ERROR("[drm] Buffer too small for z buffer "
2276 "(need %lu have %lu) !\n", size,
2277 radeon_bo_size(track->zb.robj));
2278 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2279 track->zb.pitch, track->zb.cpp,
2280 track->zb.offset, track->maxy);
2284 track->zb_dirty = false;
2286 if (track->aa_dirty && track->aaresolve) {
2287 if (track->aa.robj == NULL) {
2288 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2291 /* I believe the format comes from colorbuffer0. */
2292 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2293 size += track->aa.offset;
2294 if (size > radeon_bo_size(track->aa.robj)) {
2295 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2296 "(need %lu have %lu) !\n", i, size,
2297 radeon_bo_size(track->aa.robj));
2298 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2299 i, track->aa.pitch, track->cb[0].cpp,
2300 track->aa.offset, track->maxy);
2304 track->aa_dirty = false;
2306 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2307 if (track->vap_vf_cntl & (1 << 14)) {
2308 nverts = track->vap_alt_nverts;
2310 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2312 switch (prim_walk) {
2314 for (i = 0; i < track->num_arrays; i++) {
2315 size = track->arrays[i].esize * track->max_indx * 4;
2316 if (track->arrays[i].robj == NULL) {
2317 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2318 "bound\n", prim_walk, i);
2321 if (size > radeon_bo_size(track->arrays[i].robj)) {
2322 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2323 "need %lu dwords have %lu dwords\n",
2324 prim_walk, i, size >> 2,
2325 radeon_bo_size(track->arrays[i].robj)
2327 DRM_ERROR("Max indices %u\n", track->max_indx);
2333 for (i = 0; i < track->num_arrays; i++) {
2334 size = track->arrays[i].esize * (nverts - 1) * 4;
2335 if (track->arrays[i].robj == NULL) {
2336 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2337 "bound\n", prim_walk, i);
2340 if (size > radeon_bo_size(track->arrays[i].robj)) {
2341 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2342 "need %lu dwords have %lu dwords\n",
2343 prim_walk, i, size >> 2,
2344 radeon_bo_size(track->arrays[i].robj)
2351 size = track->vtx_size * nverts;
2352 if (size != track->immd_dwords) {
2353 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2354 track->immd_dwords, size);
2355 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2356 nverts, track->vtx_size);
2361 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2366 if (track->tex_dirty) {
2367 track->tex_dirty = false;
2368 return r100_cs_track_texture_check(rdev, track);
2373 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2377 track->cb_dirty = true;
2378 track->zb_dirty = true;
2379 track->tex_dirty = true;
2380 track->aa_dirty = true;
2382 if (rdev->family < CHIP_R300) {
2384 if (rdev->family <= CHIP_RS200)
2385 track->num_texture = 3;
2387 track->num_texture = 6;
2389 track->separate_cube = 1;
2392 track->num_texture = 16;
2394 track->separate_cube = 0;
2395 track->aaresolve = false;
2396 track->aa.robj = NULL;
2399 for (i = 0; i < track->num_cb; i++) {
2400 track->cb[i].robj = NULL;
2401 track->cb[i].pitch = 8192;
2402 track->cb[i].cpp = 16;
2403 track->cb[i].offset = 0;
2405 track->z_enabled = true;
2406 track->zb.robj = NULL;
2407 track->zb.pitch = 8192;
2409 track->zb.offset = 0;
2410 track->vtx_size = 0x7F;
2411 track->immd_dwords = 0xFFFFFFFFUL;
2412 track->num_arrays = 11;
2413 track->max_indx = 0x00FFFFFFUL;
2414 for (i = 0; i < track->num_arrays; i++) {
2415 track->arrays[i].robj = NULL;
2416 track->arrays[i].esize = 0x7F;
2418 for (i = 0; i < track->num_texture; i++) {
2419 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2420 track->textures[i].pitch = 16536;
2421 track->textures[i].width = 16536;
2422 track->textures[i].height = 16536;
2423 track->textures[i].width_11 = 1 << 11;
2424 track->textures[i].height_11 = 1 << 11;
2425 track->textures[i].num_levels = 12;
2426 if (rdev->family <= CHIP_RS200) {
2427 track->textures[i].tex_coord_type = 0;
2428 track->textures[i].txdepth = 0;
2430 track->textures[i].txdepth = 16;
2431 track->textures[i].tex_coord_type = 1;
2433 track->textures[i].cpp = 64;
2434 track->textures[i].robj = NULL;
2435 /* CS IB emission code makes sure texture unit are disabled */
2436 track->textures[i].enabled = false;
2437 track->textures[i].lookup_disable = false;
2438 track->textures[i].roundup_w = true;
2439 track->textures[i].roundup_h = true;
2440 if (track->separate_cube)
2441 for (face = 0; face < 5; face++) {
2442 track->textures[i].cube_info[face].robj = NULL;
2443 track->textures[i].cube_info[face].width = 16536;
2444 track->textures[i].cube_info[face].height = 16536;
2445 track->textures[i].cube_info[face].offset = 0;
2451 * Global GPU functions
2453 static void r100_errata(struct radeon_device *rdev)
2455 rdev->pll_errata = 0;
2457 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2458 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2461 if (rdev->family == CHIP_RV100 ||
2462 rdev->family == CHIP_RS100 ||
2463 rdev->family == CHIP_RS200) {
2464 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2468 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2473 for (i = 0; i < rdev->usec_timeout; i++) {
2474 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2483 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2488 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2489 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2490 " Bad things might happen.\n");
2492 for (i = 0; i < rdev->usec_timeout; i++) {
2493 tmp = RREG32(RADEON_RBBM_STATUS);
2494 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2502 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2507 for (i = 0; i < rdev->usec_timeout; i++) {
2508 /* read MC_STATUS */
2509 tmp = RREG32(RADEON_MC_STATUS);
2510 if (tmp & RADEON_MC_IDLE) {
2518 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2522 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2523 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2524 radeon_ring_lockup_update(ring);
2527 /* force CP activities */
2528 radeon_ring_force_activity(rdev, ring);
2529 return radeon_ring_test_lockup(rdev, ring);
2532 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2533 void r100_enable_bm(struct radeon_device *rdev)
2536 /* Enable bus mastering */
2537 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2538 WREG32(RADEON_BUS_CNTL, tmp);
2541 void r100_bm_disable(struct radeon_device *rdev)
2545 /* disable bus mastering */
2546 tmp = RREG32(R_000030_BUS_CNTL);
2547 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2549 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2551 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2552 tmp = RREG32(RADEON_BUS_CNTL);
2554 pci_clear_master(rdev->pdev);
2558 int r100_asic_reset(struct radeon_device *rdev)
2560 struct r100_mc_save save;
2564 status = RREG32(R_000E40_RBBM_STATUS);
2565 if (!G_000E40_GUI_ACTIVE(status)) {
2568 r100_mc_stop(rdev, &save);
2569 status = RREG32(R_000E40_RBBM_STATUS);
2570 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2572 WREG32(RADEON_CP_CSQ_CNTL, 0);
2573 tmp = RREG32(RADEON_CP_RB_CNTL);
2574 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2575 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2576 WREG32(RADEON_CP_RB_WPTR, 0);
2577 WREG32(RADEON_CP_RB_CNTL, tmp);
2578 /* save PCI state */
2579 pci_save_state(rdev->pdev);
2580 /* disable bus mastering */
2581 r100_bm_disable(rdev);
2582 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2583 S_0000F0_SOFT_RESET_RE(1) |
2584 S_0000F0_SOFT_RESET_PP(1) |
2585 S_0000F0_SOFT_RESET_RB(1));
2586 RREG32(R_0000F0_RBBM_SOFT_RESET);
2588 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2590 status = RREG32(R_000E40_RBBM_STATUS);
2591 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2593 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2594 RREG32(R_0000F0_RBBM_SOFT_RESET);
2596 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2598 status = RREG32(R_000E40_RBBM_STATUS);
2599 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2600 /* restore PCI & busmastering */
2601 pci_restore_state(rdev->pdev);
2602 r100_enable_bm(rdev);
2603 /* Check if GPU is idle */
2604 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2605 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2606 dev_err(rdev->dev, "failed to reset GPU\n");
2609 dev_info(rdev->dev, "GPU reset succeed\n");
2610 r100_mc_resume(rdev, &save);
2614 void r100_set_common_regs(struct radeon_device *rdev)
2616 struct drm_device *dev = rdev->ddev;
2617 bool force_dac2 = false;
2620 /* set these so they don't interfere with anything */
2621 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2622 WREG32(RADEON_SUBPIC_CNTL, 0);
2623 WREG32(RADEON_VIPH_CONTROL, 0);
2624 WREG32(RADEON_I2C_CNTL_1, 0);
2625 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2626 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2627 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2629 /* always set up dac2 on rn50 and some rv100 as lots
2630 * of servers seem to wire it up to a VGA port but
2631 * don't report it in the bios connector
2634 switch (dev->pdev->device) {
2643 /* DELL triple head servers */
2644 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2645 ((dev->pdev->subsystem_device == 0x016c) ||
2646 (dev->pdev->subsystem_device == 0x016d) ||
2647 (dev->pdev->subsystem_device == 0x016e) ||
2648 (dev->pdev->subsystem_device == 0x016f) ||
2649 (dev->pdev->subsystem_device == 0x0170) ||
2650 (dev->pdev->subsystem_device == 0x017d) ||
2651 (dev->pdev->subsystem_device == 0x017e) ||
2652 (dev->pdev->subsystem_device == 0x0183) ||
2653 (dev->pdev->subsystem_device == 0x018a) ||
2654 (dev->pdev->subsystem_device == 0x019a)))
2660 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2661 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2662 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2664 /* For CRT on DAC2, don't turn it on if BIOS didn't
2665 enable it, even it's detected.
2668 /* force it to crtc0 */
2669 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2670 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2671 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2673 /* set up the TV DAC */
2674 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2675 RADEON_TV_DAC_STD_MASK |
2676 RADEON_TV_DAC_RDACPD |
2677 RADEON_TV_DAC_GDACPD |
2678 RADEON_TV_DAC_BDACPD |
2679 RADEON_TV_DAC_BGADJ_MASK |
2680 RADEON_TV_DAC_DACADJ_MASK);
2681 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2682 RADEON_TV_DAC_NHOLD |
2683 RADEON_TV_DAC_STD_PS2 |
2686 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2687 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2688 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2691 /* switch PM block to ACPI mode */
2692 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2693 tmp &= ~RADEON_PM_MODE_SEL;
2694 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2701 static void r100_vram_get_type(struct radeon_device *rdev)
2705 rdev->mc.vram_is_ddr = false;
2706 if (rdev->flags & RADEON_IS_IGP)
2707 rdev->mc.vram_is_ddr = true;
2708 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2709 rdev->mc.vram_is_ddr = true;
2710 if ((rdev->family == CHIP_RV100) ||
2711 (rdev->family == CHIP_RS100) ||
2712 (rdev->family == CHIP_RS200)) {
2713 tmp = RREG32(RADEON_MEM_CNTL);
2714 if (tmp & RV100_HALF_MODE) {
2715 rdev->mc.vram_width = 32;
2717 rdev->mc.vram_width = 64;
2719 if (rdev->flags & RADEON_SINGLE_CRTC) {
2720 rdev->mc.vram_width /= 4;
2721 rdev->mc.vram_is_ddr = true;
2723 } else if (rdev->family <= CHIP_RV280) {
2724 tmp = RREG32(RADEON_MEM_CNTL);
2725 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2726 rdev->mc.vram_width = 128;
2728 rdev->mc.vram_width = 64;
2732 rdev->mc.vram_width = 128;
2736 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2741 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2743 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2744 * that is has the 2nd generation multifunction PCI interface
2746 if (rdev->family == CHIP_RV280 ||
2747 rdev->family >= CHIP_RV350) {
2748 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2749 ~RADEON_HDP_APER_CNTL);
2750 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2751 return aper_size * 2;
2754 /* Older cards have all sorts of funny issues to deal with. First
2755 * check if it's a multifunction card by reading the PCI config
2756 * header type... Limit those to one aperture size
2758 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2760 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2761 DRM_INFO("Limiting VRAM to one aperture\n");
2765 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2766 * have set it up. We don't write this as it's broken on some ASICs but
2767 * we expect the BIOS to have done the right thing (might be too optimistic...)
2769 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2770 return aper_size * 2;
2774 void r100_vram_init_sizes(struct radeon_device *rdev)
2776 u64 config_aper_size;
2778 /* work out accessible VRAM */
2779 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2780 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2781 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2782 /* FIXME we don't use the second aperture yet when we could use it */
2783 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2784 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2785 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2786 if (rdev->flags & RADEON_IS_IGP) {
2788 /* read NB_TOM to get the amount of ram stolen for the GPU */
2789 tom = RREG32(RADEON_NB_TOM);
2790 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2791 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2792 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2794 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2795 /* Some production boards of m6 will report 0
2798 if (rdev->mc.real_vram_size == 0) {
2799 rdev->mc.real_vram_size = 8192 * 1024;
2800 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2802 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2803 * Novell bug 204882 + along with lots of ubuntu ones
2805 if (rdev->mc.aper_size > config_aper_size)
2806 config_aper_size = rdev->mc.aper_size;
2808 if (config_aper_size > rdev->mc.real_vram_size)
2809 rdev->mc.mc_vram_size = config_aper_size;
2811 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2815 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2819 temp = RREG32(RADEON_CONFIG_CNTL);
2820 if (state == false) {
2821 temp &= ~RADEON_CFG_VGA_RAM_EN;
2822 temp |= RADEON_CFG_VGA_IO_DIS;
2824 temp &= ~RADEON_CFG_VGA_IO_DIS;
2826 WREG32(RADEON_CONFIG_CNTL, temp);
2829 static void r100_mc_init(struct radeon_device *rdev)
2833 r100_vram_get_type(rdev);
2834 r100_vram_init_sizes(rdev);
2835 base = rdev->mc.aper_base;
2836 if (rdev->flags & RADEON_IS_IGP)
2837 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2838 radeon_vram_location(rdev, &rdev->mc, base);
2839 rdev->mc.gtt_base_align = 0;
2840 if (!(rdev->flags & RADEON_IS_AGP))
2841 radeon_gtt_location(rdev, &rdev->mc);
2842 radeon_update_bandwidth_info(rdev);
2847 * Indirect registers accessor
2849 void r100_pll_errata_after_index(struct radeon_device *rdev)
2851 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2852 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2853 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2857 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2859 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2860 * or the chip could hang on a subsequent access
2862 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2866 /* This function is required to workaround a hardware bug in some (all?)
2867 * revisions of the R300. This workaround should be called after every
2868 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2869 * may not be correct.
2871 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2874 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2875 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2876 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2877 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2878 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2882 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2884 unsigned long flags;
2887 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2888 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2889 r100_pll_errata_after_index(rdev);
2890 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2891 r100_pll_errata_after_data(rdev);
2892 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2896 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2898 unsigned long flags;
2900 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2901 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2902 r100_pll_errata_after_index(rdev);
2903 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2904 r100_pll_errata_after_data(rdev);
2905 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2908 static void r100_set_safe_registers(struct radeon_device *rdev)
2910 if (ASIC_IS_RN50(rdev)) {
2911 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2912 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2913 } else if (rdev->family < CHIP_R200) {
2914 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2915 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2917 r200_set_safe_registers(rdev);
2924 #if defined(CONFIG_DEBUG_FS)
2925 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2927 struct drm_info_node *node = (struct drm_info_node *) m->private;
2928 struct drm_device *dev = node->minor->dev;
2929 struct radeon_device *rdev = dev->dev_private;
2930 uint32_t reg, value;
2933 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2934 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2935 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2936 for (i = 0; i < 64; i++) {
2937 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2938 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2939 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2940 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2941 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2946 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2948 struct drm_info_node *node = (struct drm_info_node *) m->private;
2949 struct drm_device *dev = node->minor->dev;
2950 struct radeon_device *rdev = dev->dev_private;
2951 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2953 unsigned count, i, j;
2955 radeon_ring_free_size(rdev, ring);
2956 rdp = RREG32(RADEON_CP_RB_RPTR);
2957 wdp = RREG32(RADEON_CP_RB_WPTR);
2958 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2959 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2960 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2961 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2962 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2963 seq_printf(m, "%u dwords in ring\n", count);
2965 for (j = 0; j <= count; j++) {
2966 i = (rdp + j) & ring->ptr_mask;
2967 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2974 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2976 struct drm_info_node *node = (struct drm_info_node *) m->private;
2977 struct drm_device *dev = node->minor->dev;
2978 struct radeon_device *rdev = dev->dev_private;
2979 uint32_t csq_stat, csq2_stat, tmp;
2980 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2983 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2984 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2985 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2986 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2987 r_rptr = (csq_stat >> 0) & 0x3ff;
2988 r_wptr = (csq_stat >> 10) & 0x3ff;
2989 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2990 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2991 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2992 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2993 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2994 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2995 seq_printf(m, "Ring rptr %u\n", r_rptr);
2996 seq_printf(m, "Ring wptr %u\n", r_wptr);
2997 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2998 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2999 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3000 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3001 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3002 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3003 seq_printf(m, "Ring fifo:\n");
3004 for (i = 0; i < 256; i++) {
3005 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3006 tmp = RREG32(RADEON_CP_CSQ_DATA);
3007 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3009 seq_printf(m, "Indirect1 fifo:\n");
3010 for (i = 256; i <= 512; i++) {
3011 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3012 tmp = RREG32(RADEON_CP_CSQ_DATA);
3013 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3015 seq_printf(m, "Indirect2 fifo:\n");
3016 for (i = 640; i < ib1_wptr; i++) {
3017 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3018 tmp = RREG32(RADEON_CP_CSQ_DATA);
3019 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3024 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3026 struct drm_info_node *node = (struct drm_info_node *) m->private;
3027 struct drm_device *dev = node->minor->dev;
3028 struct radeon_device *rdev = dev->dev_private;
3031 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3032 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3033 tmp = RREG32(RADEON_MC_FB_LOCATION);
3034 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3035 tmp = RREG32(RADEON_BUS_CNTL);
3036 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3037 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3038 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3039 tmp = RREG32(RADEON_AGP_BASE);
3040 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3041 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3042 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3043 tmp = RREG32(0x01D0);
3044 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3045 tmp = RREG32(RADEON_AIC_LO_ADDR);
3046 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3047 tmp = RREG32(RADEON_AIC_HI_ADDR);
3048 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3049 tmp = RREG32(0x01E4);
3050 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3054 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3055 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3058 static struct drm_info_list r100_debugfs_cp_list[] = {
3059 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3060 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3063 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3064 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3068 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3070 #if defined(CONFIG_DEBUG_FS)
3071 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3077 int r100_debugfs_cp_init(struct radeon_device *rdev)
3079 #if defined(CONFIG_DEBUG_FS)
3080 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3086 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3088 #if defined(CONFIG_DEBUG_FS)
3089 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3095 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3096 uint32_t tiling_flags, uint32_t pitch,
3097 uint32_t offset, uint32_t obj_size)
3099 int surf_index = reg * 16;
3102 if (rdev->family <= CHIP_RS200) {
3103 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3104 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3105 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3106 if (tiling_flags & RADEON_TILING_MACRO)
3107 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3108 /* setting pitch to 0 disables tiling */
3109 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3112 } else if (rdev->family <= CHIP_RV280) {
3113 if (tiling_flags & (RADEON_TILING_MACRO))
3114 flags |= R200_SURF_TILE_COLOR_MACRO;
3115 if (tiling_flags & RADEON_TILING_MICRO)
3116 flags |= R200_SURF_TILE_COLOR_MICRO;
3118 if (tiling_flags & RADEON_TILING_MACRO)
3119 flags |= R300_SURF_TILE_MACRO;
3120 if (tiling_flags & RADEON_TILING_MICRO)
3121 flags |= R300_SURF_TILE_MICRO;
3124 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3125 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3126 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3127 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3129 /* r100/r200 divide by 16 */
3130 if (rdev->family < CHIP_R300)
3131 flags |= pitch / 16;
3136 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3137 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3138 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3139 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3143 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3145 int surf_index = reg * 16;
3146 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3149 void r100_bandwidth_update(struct radeon_device *rdev)
3151 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3152 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3153 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3154 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3155 fixed20_12 memtcas_ff[8] = {
3160 dfixed_init_half(1),
3161 dfixed_init_half(2),
3164 fixed20_12 memtcas_rs480_ff[8] = {
3170 dfixed_init_half(1),
3171 dfixed_init_half(2),
3172 dfixed_init_half(3),
3174 fixed20_12 memtcas2_ff[8] = {
3184 fixed20_12 memtrbs[8] = {
3186 dfixed_init_half(1),
3188 dfixed_init_half(2),
3190 dfixed_init_half(3),
3194 fixed20_12 memtrbs_r4xx[8] = {
3204 fixed20_12 min_mem_eff;
3205 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3206 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3207 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3208 disp_drain_rate2, read_return_rate;
3209 fixed20_12 time_disp1_drop_priority;
3211 int cur_size = 16; /* in octawords */
3212 int critical_point = 0, critical_point2;
3213 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3214 int stop_req, max_stop_req;
3215 struct drm_display_mode *mode1 = NULL;
3216 struct drm_display_mode *mode2 = NULL;
3217 uint32_t pixel_bytes1 = 0;
3218 uint32_t pixel_bytes2 = 0;
3220 if (!rdev->mode_info.mode_config_initialized)
3223 radeon_update_display_priority(rdev);
3225 if (rdev->mode_info.crtcs[0]->base.enabled) {
3226 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3227 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3229 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3230 if (rdev->mode_info.crtcs[1]->base.enabled) {
3231 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3232 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3236 min_mem_eff.full = dfixed_const_8(0);
3238 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3239 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3240 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3241 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3242 /* check crtc enables */
3244 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3246 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3247 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3251 * determine is there is enough bw for current mode
3253 sclk_ff = rdev->pm.sclk;
3254 mclk_ff = rdev->pm.mclk;
3256 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3257 temp_ff.full = dfixed_const(temp);
3258 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3262 peak_disp_bw.full = 0;
3264 temp_ff.full = dfixed_const(1000);
3265 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3266 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3267 temp_ff.full = dfixed_const(pixel_bytes1);
3268 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3271 temp_ff.full = dfixed_const(1000);
3272 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3273 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3274 temp_ff.full = dfixed_const(pixel_bytes2);
3275 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3278 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3279 if (peak_disp_bw.full >= mem_bw.full) {
3280 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3281 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3284 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3285 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3286 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3287 mem_trcd = ((temp >> 2) & 0x3) + 1;
3288 mem_trp = ((temp & 0x3)) + 1;
3289 mem_tras = ((temp & 0x70) >> 4) + 1;
3290 } else if (rdev->family == CHIP_R300 ||
3291 rdev->family == CHIP_R350) { /* r300, r350 */
3292 mem_trcd = (temp & 0x7) + 1;
3293 mem_trp = ((temp >> 8) & 0x7) + 1;
3294 mem_tras = ((temp >> 11) & 0xf) + 4;
3295 } else if (rdev->family == CHIP_RV350 ||
3296 rdev->family <= CHIP_RV380) {
3298 mem_trcd = (temp & 0x7) + 3;
3299 mem_trp = ((temp >> 8) & 0x7) + 3;
3300 mem_tras = ((temp >> 11) & 0xf) + 6;
3301 } else if (rdev->family == CHIP_R420 ||
3302 rdev->family == CHIP_R423 ||
3303 rdev->family == CHIP_RV410) {
3305 mem_trcd = (temp & 0xf) + 3;
3308 mem_trp = ((temp >> 8) & 0xf) + 3;
3311 mem_tras = ((temp >> 12) & 0x1f) + 6;
3314 } else { /* RV200, R200 */
3315 mem_trcd = (temp & 0x7) + 1;
3316 mem_trp = ((temp >> 8) & 0x7) + 1;
3317 mem_tras = ((temp >> 12) & 0xf) + 4;
3320 trcd_ff.full = dfixed_const(mem_trcd);
3321 trp_ff.full = dfixed_const(mem_trp);
3322 tras_ff.full = dfixed_const(mem_tras);
3324 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3325 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3326 data = (temp & (7 << 20)) >> 20;
3327 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3328 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3329 tcas_ff = memtcas_rs480_ff[data];
3331 tcas_ff = memtcas_ff[data];
3333 tcas_ff = memtcas2_ff[data];
3335 if (rdev->family == CHIP_RS400 ||
3336 rdev->family == CHIP_RS480) {
3337 /* extra cas latency stored in bits 23-25 0-4 clocks */
3338 data = (temp >> 23) & 0x7;
3340 tcas_ff.full += dfixed_const(data);
3343 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3344 /* on the R300, Tcas is included in Trbs.
3346 temp = RREG32(RADEON_MEM_CNTL);
3347 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3349 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3350 temp = RREG32(R300_MC_IND_INDEX);
3351 temp &= ~R300_MC_IND_ADDR_MASK;
3352 temp |= R300_MC_READ_CNTL_CD_mcind;
3353 WREG32(R300_MC_IND_INDEX, temp);
3354 temp = RREG32(R300_MC_IND_DATA);
3355 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3357 temp = RREG32(R300_MC_READ_CNTL_AB);
3358 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3361 temp = RREG32(R300_MC_READ_CNTL_AB);
3362 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3364 if (rdev->family == CHIP_RV410 ||
3365 rdev->family == CHIP_R420 ||
3366 rdev->family == CHIP_R423)
3367 trbs_ff = memtrbs_r4xx[data];
3369 trbs_ff = memtrbs[data];
3370 tcas_ff.full += trbs_ff.full;
3373 sclk_eff_ff.full = sclk_ff.full;
3375 if (rdev->flags & RADEON_IS_AGP) {
3376 fixed20_12 agpmode_ff;
3377 agpmode_ff.full = dfixed_const(radeon_agpmode);
3378 temp_ff.full = dfixed_const_666(16);
3379 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3381 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3383 if (ASIC_IS_R300(rdev)) {
3384 sclk_delay_ff.full = dfixed_const(250);
3386 if ((rdev->family == CHIP_RV100) ||
3387 rdev->flags & RADEON_IS_IGP) {
3388 if (rdev->mc.vram_is_ddr)
3389 sclk_delay_ff.full = dfixed_const(41);
3391 sclk_delay_ff.full = dfixed_const(33);
3393 if (rdev->mc.vram_width == 128)
3394 sclk_delay_ff.full = dfixed_const(57);
3396 sclk_delay_ff.full = dfixed_const(41);
3400 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3402 if (rdev->mc.vram_is_ddr) {
3403 if (rdev->mc.vram_width == 32) {
3404 k1.full = dfixed_const(40);
3407 k1.full = dfixed_const(20);
3411 k1.full = dfixed_const(40);
3415 temp_ff.full = dfixed_const(2);
3416 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3417 temp_ff.full = dfixed_const(c);
3418 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3419 temp_ff.full = dfixed_const(4);
3420 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3421 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3422 mc_latency_mclk.full += k1.full;
3424 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3425 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3428 HW cursor time assuming worst case of full size colour cursor.
3430 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3431 temp_ff.full += trcd_ff.full;
3432 if (temp_ff.full < tras_ff.full)
3433 temp_ff.full = tras_ff.full;
3434 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3436 temp_ff.full = dfixed_const(cur_size);
3437 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3439 Find the total latency for the display data.
3441 disp_latency_overhead.full = dfixed_const(8);
3442 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3443 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3444 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3446 if (mc_latency_mclk.full > mc_latency_sclk.full)
3447 disp_latency.full = mc_latency_mclk.full;
3449 disp_latency.full = mc_latency_sclk.full;
3451 /* setup Max GRPH_STOP_REQ default value */
3452 if (ASIC_IS_RV100(rdev))
3453 max_stop_req = 0x5c;
3455 max_stop_req = 0x7c;
3459 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3460 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3462 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3464 if (stop_req > max_stop_req)
3465 stop_req = max_stop_req;
3468 Find the drain rate of the display buffer.
3470 temp_ff.full = dfixed_const((16/pixel_bytes1));
3471 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3474 Find the critical point of the display buffer.
3476 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3477 crit_point_ff.full += dfixed_const_half(0);
3479 critical_point = dfixed_trunc(crit_point_ff);
3481 if (rdev->disp_priority == 2) {
3486 The critical point should never be above max_stop_req-4. Setting
3487 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3489 if (max_stop_req - critical_point < 4)
3492 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3493 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3494 critical_point = 0x10;
3497 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3498 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3499 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3500 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3501 if ((rdev->family == CHIP_R350) &&
3502 (stop_req > 0x15)) {
3505 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3506 temp |= RADEON_GRPH_BUFFER_SIZE;
3507 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3508 RADEON_GRPH_CRITICAL_AT_SOF |
3509 RADEON_GRPH_STOP_CNTL);
3511 Write the result into the register.
3513 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3514 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3517 if ((rdev->family == CHIP_RS400) ||
3518 (rdev->family == CHIP_RS480)) {
3519 /* attempt to program RS400 disp regs correctly ??? */
3520 temp = RREG32(RS400_DISP1_REG_CNTL);
3521 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3522 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3523 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3524 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3525 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3526 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3527 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3528 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3529 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3530 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3531 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3535 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3536 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3537 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3542 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3544 if (stop_req > max_stop_req)
3545 stop_req = max_stop_req;
3548 Find the drain rate of the display buffer.
3550 temp_ff.full = dfixed_const((16/pixel_bytes2));
3551 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3553 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3554 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3555 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3556 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3557 if ((rdev->family == CHIP_R350) &&
3558 (stop_req > 0x15)) {
3561 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3562 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3563 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3564 RADEON_GRPH_CRITICAL_AT_SOF |
3565 RADEON_GRPH_STOP_CNTL);
3567 if ((rdev->family == CHIP_RS100) ||
3568 (rdev->family == CHIP_RS200))
3569 critical_point2 = 0;
3571 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3572 temp_ff.full = dfixed_const(temp);
3573 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3574 if (sclk_ff.full < temp_ff.full)
3575 temp_ff.full = sclk_ff.full;
3577 read_return_rate.full = temp_ff.full;
3580 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3581 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3583 time_disp1_drop_priority.full = 0;
3585 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3586 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3587 crit_point_ff.full += dfixed_const_half(0);
3589 critical_point2 = dfixed_trunc(crit_point_ff);
3591 if (rdev->disp_priority == 2) {
3592 critical_point2 = 0;
3595 if (max_stop_req - critical_point2 < 4)
3596 critical_point2 = 0;
3600 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3601 /* some R300 cards have problem with this set to 0 */
3602 critical_point2 = 0x10;
3605 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3606 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3608 if ((rdev->family == CHIP_RS400) ||
3609 (rdev->family == CHIP_RS480)) {
3611 /* attempt to program RS400 disp2 regs correctly ??? */
3612 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3613 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3614 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3615 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3616 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3617 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3618 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3619 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3620 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3621 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3622 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3623 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3625 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3626 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3627 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3628 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3631 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3632 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3636 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3643 r = radeon_scratch_get(rdev, &scratch);
3645 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3648 WREG32(scratch, 0xCAFEDEAD);
3649 r = radeon_ring_lock(rdev, ring, 2);
3651 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3652 radeon_scratch_free(rdev, scratch);
3655 radeon_ring_write(ring, PACKET0(scratch, 0));
3656 radeon_ring_write(ring, 0xDEADBEEF);
3657 radeon_ring_unlock_commit(rdev, ring);
3658 for (i = 0; i < rdev->usec_timeout; i++) {
3659 tmp = RREG32(scratch);
3660 if (tmp == 0xDEADBEEF) {
3665 if (i < rdev->usec_timeout) {
3666 DRM_INFO("ring test succeeded in %d usecs\n", i);
3668 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3672 radeon_scratch_free(rdev, scratch);
3676 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3678 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3680 if (ring->rptr_save_reg) {
3681 u32 next_rptr = ring->wptr + 2 + 3;
3682 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3683 radeon_ring_write(ring, next_rptr);
3686 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3687 radeon_ring_write(ring, ib->gpu_addr);
3688 radeon_ring_write(ring, ib->length_dw);
3691 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3693 struct radeon_ib ib;
3699 r = radeon_scratch_get(rdev, &scratch);
3701 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3704 WREG32(scratch, 0xCAFEDEAD);
3705 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3707 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3710 ib.ptr[0] = PACKET0(scratch, 0);
3711 ib.ptr[1] = 0xDEADBEEF;
3712 ib.ptr[2] = PACKET2(0);
3713 ib.ptr[3] = PACKET2(0);
3714 ib.ptr[4] = PACKET2(0);
3715 ib.ptr[5] = PACKET2(0);
3716 ib.ptr[6] = PACKET2(0);
3717 ib.ptr[7] = PACKET2(0);
3719 r = radeon_ib_schedule(rdev, &ib, NULL);
3721 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3724 r = radeon_fence_wait(ib.fence, false);
3726 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3729 for (i = 0; i < rdev->usec_timeout; i++) {
3730 tmp = RREG32(scratch);
3731 if (tmp == 0xDEADBEEF) {
3736 if (i < rdev->usec_timeout) {
3737 DRM_INFO("ib test succeeded in %u usecs\n", i);
3739 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3744 radeon_ib_free(rdev, &ib);
3746 radeon_scratch_free(rdev, scratch);
3750 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3752 /* Shutdown CP we shouldn't need to do that but better be safe than
3755 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3756 WREG32(R_000740_CP_CSQ_CNTL, 0);
3758 /* Save few CRTC registers */
3759 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3760 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3761 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3762 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3763 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3764 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3765 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3768 /* Disable VGA aperture access */
3769 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3770 /* Disable cursor, overlay, crtc */
3771 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3772 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3773 S_000054_CRTC_DISPLAY_DIS(1));
3774 WREG32(R_000050_CRTC_GEN_CNTL,
3775 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3776 S_000050_CRTC_DISP_REQ_EN_B(1));
3777 WREG32(R_000420_OV0_SCALE_CNTL,
3778 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3779 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3780 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3781 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3782 S_000360_CUR2_LOCK(1));
3783 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3784 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3785 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3786 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3787 WREG32(R_000360_CUR2_OFFSET,
3788 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3792 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3794 /* Update base address for crtc */
3795 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3796 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3797 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3799 /* Restore CRTC registers */
3800 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3801 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3802 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3803 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3804 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3808 void r100_vga_render_disable(struct radeon_device *rdev)
3812 tmp = RREG8(R_0003C2_GENMO_WT);
3813 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3816 static void r100_debugfs(struct radeon_device *rdev)
3820 r = r100_debugfs_mc_info_init(rdev);
3822 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3825 static void r100_mc_program(struct radeon_device *rdev)
3827 struct r100_mc_save save;
3829 /* Stops all mc clients */
3830 r100_mc_stop(rdev, &save);
3831 if (rdev->flags & RADEON_IS_AGP) {
3832 WREG32(R_00014C_MC_AGP_LOCATION,
3833 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3834 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3835 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3836 if (rdev->family > CHIP_RV200)
3837 WREG32(R_00015C_AGP_BASE_2,
3838 upper_32_bits(rdev->mc.agp_base) & 0xff);
3840 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3841 WREG32(R_000170_AGP_BASE, 0);
3842 if (rdev->family > CHIP_RV200)
3843 WREG32(R_00015C_AGP_BASE_2, 0);
3845 /* Wait for mc idle */
3846 if (r100_mc_wait_for_idle(rdev))
3847 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3848 /* Program MC, should be a 32bits limited address space */
3849 WREG32(R_000148_MC_FB_LOCATION,
3850 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3851 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3852 r100_mc_resume(rdev, &save);
3855 static void r100_clock_startup(struct radeon_device *rdev)
3859 if (radeon_dynclks != -1 && radeon_dynclks)
3860 radeon_legacy_set_clock_gating(rdev, 1);
3861 /* We need to force on some of the block */
3862 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3863 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3864 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3865 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3866 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3869 static int r100_startup(struct radeon_device *rdev)
3873 /* set common regs */
3874 r100_set_common_regs(rdev);
3876 r100_mc_program(rdev);
3878 r100_clock_startup(rdev);
3879 /* Initialize GART (initialize after TTM so we can allocate
3880 * memory through TTM but finalize after TTM) */
3881 r100_enable_bm(rdev);
3882 if (rdev->flags & RADEON_IS_PCI) {
3883 r = r100_pci_gart_enable(rdev);
3888 /* allocate wb buffer */
3889 r = radeon_wb_init(rdev);
3893 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3895 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3900 if (!rdev->irq.installed) {
3901 r = radeon_irq_kms_init(rdev);
3907 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3908 /* 1M ring buffer */
3909 r = r100_cp_init(rdev, 1024 * 1024);
3911 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3915 r = radeon_ib_pool_init(rdev);
3917 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3924 int r100_resume(struct radeon_device *rdev)
3928 /* Make sur GART are not working */
3929 if (rdev->flags & RADEON_IS_PCI)
3930 r100_pci_gart_disable(rdev);
3931 /* Resume clock before doing reset */
3932 r100_clock_startup(rdev);
3933 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3934 if (radeon_asic_reset(rdev)) {
3935 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3936 RREG32(R_000E40_RBBM_STATUS),
3937 RREG32(R_0007C0_CP_STAT));
3940 radeon_combios_asic_init(rdev->ddev);
3941 /* Resume clock after posting */
3942 r100_clock_startup(rdev);
3943 /* Initialize surface registers */
3944 radeon_surface_init(rdev);
3946 rdev->accel_working = true;
3947 r = r100_startup(rdev);
3949 rdev->accel_working = false;
3954 int r100_suspend(struct radeon_device *rdev)
3956 radeon_pm_suspend(rdev);
3957 r100_cp_disable(rdev);
3958 radeon_wb_disable(rdev);
3959 r100_irq_disable(rdev);
3960 if (rdev->flags & RADEON_IS_PCI)
3961 r100_pci_gart_disable(rdev);
3965 void r100_fini(struct radeon_device *rdev)
3967 radeon_pm_fini(rdev);
3969 radeon_wb_fini(rdev);
3970 radeon_ib_pool_fini(rdev);
3971 radeon_gem_fini(rdev);
3972 if (rdev->flags & RADEON_IS_PCI)
3973 r100_pci_gart_fini(rdev);
3974 radeon_agp_fini(rdev);
3975 radeon_irq_kms_fini(rdev);
3976 radeon_fence_driver_fini(rdev);
3977 radeon_bo_fini(rdev);
3978 radeon_atombios_fini(rdev);
3984 * Due to how kexec works, it can leave the hw fully initialised when it
3985 * boots the new kernel. However doing our init sequence with the CP and
3986 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3987 * do some quick sanity checks and restore sane values to avoid this
3990 void r100_restore_sanity(struct radeon_device *rdev)
3994 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3996 WREG32(RADEON_CP_CSQ_CNTL, 0);
3998 tmp = RREG32(RADEON_CP_RB_CNTL);
4000 WREG32(RADEON_CP_RB_CNTL, 0);
4002 tmp = RREG32(RADEON_SCRATCH_UMSK);
4004 WREG32(RADEON_SCRATCH_UMSK, 0);
4008 int r100_init(struct radeon_device *rdev)
4012 /* Register debugfs file specific to this group of asics */
4015 r100_vga_render_disable(rdev);
4016 /* Initialize scratch registers */
4017 radeon_scratch_init(rdev);
4018 /* Initialize surface registers */
4019 radeon_surface_init(rdev);
4020 /* sanity check some register to avoid hangs like after kexec */
4021 r100_restore_sanity(rdev);
4022 /* TODO: disable VGA need to use VGA request */
4024 if (!radeon_get_bios(rdev)) {
4025 if (ASIC_IS_AVIVO(rdev))
4028 if (rdev->is_atom_bios) {
4029 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4032 r = radeon_combios_init(rdev);
4036 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4037 if (radeon_asic_reset(rdev)) {
4039 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4040 RREG32(R_000E40_RBBM_STATUS),
4041 RREG32(R_0007C0_CP_STAT));
4043 /* check if cards are posted or not */
4044 if (radeon_boot_test_post_card(rdev) == false)
4046 /* Set asic errata */
4048 /* Initialize clocks */
4049 radeon_get_clock_info(rdev->ddev);
4050 /* initialize AGP */
4051 if (rdev->flags & RADEON_IS_AGP) {
4052 r = radeon_agp_init(rdev);
4054 radeon_agp_disable(rdev);
4057 /* initialize VRAM */
4060 r = radeon_fence_driver_init(rdev);
4063 /* Memory manager */
4064 r = radeon_bo_init(rdev);
4067 if (rdev->flags & RADEON_IS_PCI) {
4068 r = r100_pci_gart_init(rdev);
4072 r100_set_safe_registers(rdev);
4074 /* Initialize power management */
4075 radeon_pm_init(rdev);
4077 rdev->accel_working = true;
4078 r = r100_startup(rdev);
4080 /* Somethings want wront with the accel init stop accel */
4081 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4083 radeon_wb_fini(rdev);
4084 radeon_ib_pool_fini(rdev);
4085 radeon_irq_kms_fini(rdev);
4086 if (rdev->flags & RADEON_IS_PCI)
4087 r100_pci_gart_fini(rdev);
4088 rdev->accel_working = false;
4093 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4094 bool always_indirect)
4096 if (reg < rdev->rmmio_size && !always_indirect)
4097 return readl(((void __iomem *)rdev->rmmio) + reg);
4099 unsigned long flags;
4102 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4103 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4104 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4105 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4111 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4112 bool always_indirect)
4114 if (reg < rdev->rmmio_size && !always_indirect)
4115 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4117 unsigned long flags;
4119 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4120 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4121 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4122 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4126 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4128 if (reg < rdev->rio_mem_size)
4129 return ioread32(rdev->rio_mem + reg);
4131 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4132 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4136 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4138 if (reg < rdev->rio_mem_size)
4139 iowrite32(v, rdev->rio_mem + reg);
4141 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4142 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);