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24 #include "changk104.h"
27 #include <core/gpuobj.h>
29 #include <nvif/class.h>
32 gv100_fifo_runlist_chan(struct gk104_fifo_chan *chan,
33 struct nvkm_memory *memory, u32 offset)
35 struct nvkm_memory *usermem = chan->fifo->user.mem;
36 const u64 user = nvkm_memory_addr(usermem) + (chan->base.chid * 0x200);
37 const u64 inst = chan->base.inst->addr;
39 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user));
40 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user));
41 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->base.chid);
42 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst));
46 gv100_fifo_runlist_cgrp(struct nvkm_fifo_cgrp *cgrp,
47 struct nvkm_memory *memory, u32 offset)
49 nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001);
50 nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr);
51 nvkm_wo32(memory, offset + 0x8, cgrp->id);
52 nvkm_wo32(memory, offset + 0xc, 0x00000000);
55 const struct gk104_fifo_runlist_func
56 gv100_fifo_runlist = {
58 .cgrp = gv100_fifo_runlist_cgrp,
59 .chan = gv100_fifo_runlist_chan,
60 .commit = gk104_fifo_runlist_commit,
63 const struct nvkm_enum
64 gv100_fifo_fault_gpcclient[] = {
89 { 0x18, "LTP_UTLB_0" },
90 { 0x19, "LTP_UTLB_1" },
91 { 0x1a, "LTP_UTLB_2" },
92 { 0x1b, "LTP_UTLB_3" },
93 { 0x1c, "LTP_UTLB_4" },
94 { 0x1d, "LTP_UTLB_5" },
95 { 0x1e, "LTP_UTLB_6" },
96 { 0x1f, "LTP_UTLB_7" },
124 { 0x3b, "TPCCS_10" },
125 { 0x3c, "TPCCS_11" },
132 { 0x43, "TPCCS_12" },
133 { 0x44, "TPCCS_13" },
140 { 0x4b, "TPCCS_14" },
141 { 0x4c, "TPCCS_15" },
148 { 0x53, "TPCCS_16" },
149 { 0x54, "TPCCS_17" },
156 { 0x5b, "TPCCS_18" },
157 { 0x5c, "TPCCS_19" },
165 const struct nvkm_enum
166 gv100_fifo_fault_hubclient[] = {
174 { 0x07, "HOST_CPU" },
175 { 0x08, "HOST_CPU_NB" },
185 { 0x13, "RASTERTWOD" },
197 { 0x1f, "DONT_CARE" },
218 { 0x34, "VPR_SCRUBBER0" },
219 { 0x35, "VPR_SCRUBBER1" },
221 { 0x37, "FBFALCON" },
227 const struct nvkm_enum
228 gv100_fifo_fault_reason[] = {
230 { 0x01, "PDE_SIZE" },
232 { 0x03, "VA_LIMIT_VIOLATION" },
233 { 0x04, "UNBOUND_INST_BLOCK" },
234 { 0x05, "PRIV_VIOLATION" },
235 { 0x06, "RO_VIOLATION" },
236 { 0x07, "WO_VIOLATION" },
237 { 0x08, "PITCH_MASK_VIOLATION" },
238 { 0x09, "WORK_CREATION" },
239 { 0x0a, "UNSUPPORTED_APERTURE" },
240 { 0x0b, "COMPRESSION_FAILURE" },
241 { 0x0c, "UNSUPPORTED_KIND" },
242 { 0x0d, "REGION_VIOLATION" },
243 { 0x0e, "POISONED" },
244 { 0x0f, "ATOMIC_VIOLATION" },
248 static const struct nvkm_enum
249 gv100_fifo_fault_engine[] = {
252 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
253 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
255 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
257 { 0x1f, "PHYSICAL" },
275 const struct nvkm_enum
276 gv100_fifo_fault_access[] = {
277 { 0x0, "VIRT_READ" },
278 { 0x1, "VIRT_WRITE" },
279 { 0x2, "VIRT_ATOMIC" },
280 { 0x3, "VIRT_PREFETCH" },
281 { 0x4, "VIRT_ATOMIC_WEAK" },
282 { 0x8, "PHYS_READ" },
283 { 0x9, "PHYS_WRITE" },
284 { 0xa, "PHYS_ATOMIC" },
285 { 0xb, "PHYS_PREFETCH" },
289 static const struct gk104_fifo_func
291 .pbdma = &gm200_fifo_pbdma,
292 .fault.access = gv100_fifo_fault_access,
293 .fault.engine = gv100_fifo_fault_engine,
294 .fault.reason = gv100_fifo_fault_reason,
295 .fault.hubclient = gv100_fifo_fault_hubclient,
296 .fault.gpcclient = gv100_fifo_fault_gpcclient,
297 .runlist = &gv100_fifo_runlist,
298 .user = {{-1,-1,VOLTA_USERMODE_A }, gv100_fifo_user_new },
299 .chan = {{ 0, 0,VOLTA_CHANNEL_GPFIFO_A}, gv100_fifo_gpfifo_new },
304 gv100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
306 return gk104_fifo_new_(&gv100_fifo, device, index, 4096, pfifo);