2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include <core/ramht.h>
31 #include <subdev/timer.h>
34 gf119_disp_super(struct work_struct *work)
36 struct nv50_disp *disp =
37 container_of(work, struct nv50_disp, supervisor);
38 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
39 struct nvkm_device *device = subdev->device;
40 struct nvkm_head *head;
43 nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super));
44 list_for_each_entry(head, &disp->base.head, head) {
45 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800));
46 HEAD_DBG(head, "%08x", mask[head->id]);
49 if (disp->super & 0x00000001) {
50 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
51 nv50_disp_super_1(disp);
52 list_for_each_entry(head, &disp->base.head, head) {
53 if (!(mask[head->id] & 0x00001000))
55 nv50_disp_super_1_0(disp, head);
58 if (disp->super & 0x00000002) {
59 list_for_each_entry(head, &disp->base.head, head) {
60 if (!(mask[head->id] & 0x00001000))
62 nv50_disp_super_2_0(disp, head);
64 nvkm_outp_route(&disp->base);
65 list_for_each_entry(head, &disp->base.head, head) {
66 if (!(mask[head->id] & 0x00010000))
68 nv50_disp_super_2_1(disp, head);
70 list_for_each_entry(head, &disp->base.head, head) {
71 if (!(mask[head->id] & 0x00001000))
73 nv50_disp_super_2_2(disp, head);
76 if (disp->super & 0x00000004) {
77 list_for_each_entry(head, &disp->base.head, head) {
78 if (!(mask[head->id] & 0x00001000))
80 nv50_disp_super_3_0(disp, head);
84 list_for_each_entry(head, &disp->base.head, head)
85 nvkm_wr32(device, 0x6101d4 + (head->id * 0x800), 0x00000000);
86 nvkm_wr32(device, 0x6101d0, 0x80000000);
90 gf119_disp_intr_error(struct nv50_disp *disp, int chid)
92 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
93 struct nvkm_device *device = subdev->device;
94 u32 stat = nvkm_rd32(device, 0x6101f0 + (chid * 12));
95 u32 type = (stat & 0x00007000) >> 12;
96 u32 mthd = (stat & 0x00000ffc);
97 u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12));
98 u32 code = nvkm_rd32(device, 0x6101f8 + (chid * 12));
99 const struct nvkm_enum *reason =
100 nvkm_enum_find(nv50_disp_intr_error_type, type);
102 nvkm_error(subdev, "chid %d stat %08x reason %d [%s] mthd %04x "
103 "data %08x code %08x\n",
104 chid, stat, type, reason ? reason->name : "",
107 if (chid < ARRAY_SIZE(disp->chan)) {
110 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
117 nvkm_wr32(device, 0x61009c, (1 << chid));
118 nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000);
122 gf119_disp_intr(struct nv50_disp *disp)
124 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
125 struct nvkm_device *device = subdev->device;
126 struct nvkm_head *head;
127 u32 intr = nvkm_rd32(device, 0x610088);
129 if (intr & 0x00000001) {
130 u32 stat = nvkm_rd32(device, 0x61008c);
132 int chid = __ffs(stat); stat &= ~(1 << chid);
133 nv50_disp_chan_uevent_send(disp, chid);
134 nvkm_wr32(device, 0x61008c, 1 << chid);
139 if (intr & 0x00000002) {
140 u32 stat = nvkm_rd32(device, 0x61009c);
141 int chid = ffs(stat) - 1;
143 disp->func->intr_error(disp, chid);
147 if (intr & 0x00100000) {
148 u32 stat = nvkm_rd32(device, 0x6100ac);
149 if (stat & 0x00000007) {
150 disp->super = (stat & 0x00000007);
151 queue_work(disp->wq, &disp->supervisor);
152 nvkm_wr32(device, 0x6100ac, disp->super);
157 nvkm_warn(subdev, "intr24 %08x\n", stat);
158 nvkm_wr32(device, 0x6100ac, stat);
164 list_for_each_entry(head, &disp->base.head, head) {
165 const u32 hoff = head->id * 0x800;
166 u32 mask = 0x01000000 << head->id;
168 u32 stat = nvkm_rd32(device, 0x6100bc + hoff);
169 if (stat & 0x00000001)
170 nvkm_disp_vblank(&disp->base, head->id);
171 nvkm_mask(device, 0x6100bc + hoff, 0, 0);
172 nvkm_rd32(device, 0x6100c0 + hoff);
178 gf119_disp_fini(struct nv50_disp *disp)
180 struct nvkm_device *device = disp->base.engine.subdev.device;
181 /* disable all interrupts */
182 nvkm_wr32(device, 0x6100b0, 0x00000000);
186 gf119_disp_init(struct nv50_disp *disp)
188 struct nvkm_device *device = disp->base.engine.subdev.device;
189 struct nvkm_head *head;
193 /* The below segments of code copying values from one register to
194 * another appear to inform EVO of the display capabilities or
199 list_for_each_entry(head, &disp->base.head, head) {
200 const u32 hoff = head->id * 0x800;
201 tmp = nvkm_rd32(device, 0x616104 + hoff);
202 nvkm_wr32(device, 0x6101b4 + hoff, tmp);
203 tmp = nvkm_rd32(device, 0x616108 + hoff);
204 nvkm_wr32(device, 0x6101b8 + hoff, tmp);
205 tmp = nvkm_rd32(device, 0x61610c + hoff);
206 nvkm_wr32(device, 0x6101bc + hoff, tmp);
210 for (i = 0; i < disp->dac.nr; i++) {
211 tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
212 nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
216 for (i = 0; i < disp->sor.nr; i++) {
217 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
218 nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
221 /* steal display away from vbios, or something like that */
222 if (nvkm_rd32(device, 0x6100ac) & 0x00000100) {
223 nvkm_wr32(device, 0x6100ac, 0x00000100);
224 nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
225 if (nvkm_msec(device, 2000,
226 if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
232 /* point at display engine memory area (hash table, objects) */
233 nvkm_wr32(device, 0x610010, (disp->inst->addr >> 8) | 9);
235 /* enable supervisor interrupts, disable everything else */
236 nvkm_wr32(device, 0x610090, 0x00000000);
237 nvkm_wr32(device, 0x6100a0, 0x00000000);
238 nvkm_wr32(device, 0x6100b0, 0x00000307);
240 /* disable underflow reporting, preventing an intermittent issue
241 * on some gk104 boards where the production vbios left this
242 * setting enabled by default.
244 * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
246 list_for_each_entry(head, &disp->base.head, head) {
247 const u32 hoff = head->id * 0x800;
248 nvkm_mask(device, 0x616308 + hoff, 0x00000111, 0x00000010);
254 static const struct nv50_disp_func
256 .init = gf119_disp_init,
257 .fini = gf119_disp_fini,
258 .intr = gf119_disp_intr,
259 .intr_error = gf119_disp_intr_error,
260 .uevent = &gf119_disp_chan_uevent,
261 .super = gf119_disp_super,
262 .root = &gf119_disp_root_oclass,
263 .head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
264 .dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
265 .sor = { .cnt = gf119_sor_cnt, .new = gf119_sor_new },
269 gf119_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
271 return nv50_disp_new_(&gf119_disp, device, index, pdisp);