2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 /******************************************************************************
28 * instmem object implementation
29 *****************************************************************************/
32 nv04_instobj_rd32(struct nouveau_object *object, u64 addr)
34 struct nv04_instobj_priv *node = (void *)object;
35 return nv_ro32(object->engine, node->mem->offset + addr);
39 nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
41 struct nv04_instobj_priv *node = (void *)object;
42 nv_wo32(object->engine, node->mem->offset + addr, data);
46 nv04_instobj_dtor(struct nouveau_object *object)
48 struct nv04_instmem_priv *priv = (void *)object->engine;
49 struct nv04_instobj_priv *node = (void *)object;
50 nouveau_mm_free(&priv->heap, &node->mem);
51 nouveau_instobj_destroy(&node->base);
55 nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
56 struct nouveau_oclass *oclass, void *data, u32 size,
57 struct nouveau_object **pobject)
59 struct nv04_instmem_priv *priv = (void *)engine;
60 struct nv04_instobj_priv *node;
61 struct nouveau_instobj_args *args = data;
67 ret = nouveau_instobj_create(parent, engine, oclass, &node);
68 *pobject = nv_object(node);
72 ret = nouveau_mm_head(&priv->heap, 1, args->size, args->size,
73 args->align, &node->mem);
77 node->base.addr = node->mem->offset;
78 node->base.size = node->mem->length;
82 struct nouveau_instobj_impl
83 nv04_instobj_oclass = {
84 .base.ofuncs = &(struct nouveau_ofuncs) {
85 .ctor = nv04_instobj_ctor,
86 .dtor = nv04_instobj_dtor,
87 .init = _nouveau_instobj_init,
88 .fini = _nouveau_instobj_fini,
89 .rd32 = nv04_instobj_rd32,
90 .wr32 = nv04_instobj_wr32,
94 /******************************************************************************
95 * instmem subdev implementation
96 *****************************************************************************/
99 nv04_instmem_rd32(struct nouveau_object *object, u64 addr)
101 return nv_rd32(object, 0x700000 + addr);
105 nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data)
107 return nv_wr32(object, 0x700000 + addr, data);
111 nv04_instmem_dtor(struct nouveau_object *object)
113 struct nv04_instmem_priv *priv = (void *)object;
114 nouveau_gpuobj_ref(NULL, &priv->ramfc);
115 nouveau_gpuobj_ref(NULL, &priv->ramro);
116 nouveau_ramht_ref(NULL, &priv->ramht);
117 nouveau_gpuobj_ref(NULL, &priv->vbios);
118 nouveau_mm_fini(&priv->heap);
120 iounmap(priv->iomem);
121 nouveau_instmem_destroy(&priv->base);
125 nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
126 struct nouveau_oclass *oclass, void *data, u32 size,
127 struct nouveau_object **pobject)
129 struct nv04_instmem_priv *priv;
132 ret = nouveau_instmem_create(parent, engine, oclass, &priv);
133 *pobject = nv_object(priv);
137 /* PRAMIN aperture maps over the end of VRAM, reserve it */
138 priv->base.reserved = 512 * 1024;
140 ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1);
144 /* 0x00000-0x10000: reserve for probable vbios image */
145 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
150 /* 0x10000-0x18000: reserve for RAMHT */
151 ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht);
155 /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */
156 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00800, 0,
157 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
161 /* 0x18800-0x18a00: reserve for RAMRO */
162 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0,
170 struct nouveau_oclass *
171 nv04_instmem_oclass = &(struct nouveau_instmem_impl) {
172 .base.handle = NV_SUBDEV(INSTMEM, 0x04),
173 .base.ofuncs = &(struct nouveau_ofuncs) {
174 .ctor = nv04_instmem_ctor,
175 .dtor = nv04_instmem_dtor,
176 .init = _nouveau_instmem_init,
177 .fini = _nouveau_instmem_fini,
178 .rd32 = nv04_instmem_rd32,
179 .wr32 = nv04_instmem_wr32,
181 .instobj = &nv04_instobj_oclass.base,