drivers/gpu/drm/nouveau/core/engine/graph/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/os.h>
  27 #include <core/class.h>
  28 #include <core/handle.h>
  29 #include <core/engctx.h>
  30
  31 #include <subdev/fb.h>
  32 #include <subdev/timer.h>
  33
  34 #include <engine/graph.h>
  35 #include <engine/fifo.h>
  36
  37 #include "nv40.h"
  38 #include "regs.h"
  39
  40 struct nv40_graph_priv {
  41         struct nouveau_graph base;
  42         u32 size;
  43 };
  44
  45 struct nv40_graph_chan {
  46         struct nouveau_graph_chan base;
  47 };
  48
  49 static u64
  50 nv40_graph_units(struct nouveau_graph *graph)
  51 {
  52         struct nv40_graph_priv *priv = (void *)graph;
  53
  54         return nv_rd32(priv, 0x1540);
  55 }
  56
  57 /*******************************************************************************
  58  * Graphics object classes
  59  ******************************************************************************/
  60
  61 static int
  62 nv40_graph_object_ctor(struct nouveau_object *parent,
  63                        struct nouveau_object *engine,
  64                        struct nouveau_oclass *oclass, void *data, u32 size,
  65                        struct nouveau_object **pobject)
  66 {
  67         struct nouveau_gpuobj *obj;
  68         int ret;
  69
  70         ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
  71                                     20, 16, 0, &obj);
  72         *pobject = nv_object(obj);
  73         if (ret)
  74                 return ret;
  75
  76         nv_wo32(obj, 0x00, nv_mclass(obj));
  77         nv_wo32(obj, 0x04, 0x00000000);
  78         nv_wo32(obj, 0x08, 0x00000000);
  79 #ifdef __BIG_ENDIAN
  80         nv_mo32(obj, 0x08, 0x01000000, 0x01000000);
  81 #endif
  82         nv_wo32(obj, 0x0c, 0x00000000);
  83         nv_wo32(obj, 0x10, 0x00000000);
  84         return 0;
  85 }
  86
  87 static struct nouveau_ofuncs
  88 nv40_graph_ofuncs = {
  89         .ctor = nv40_graph_object_ctor,
  90         .dtor = _nouveau_gpuobj_dtor,
  91         .init = _nouveau_gpuobj_init,
  92         .fini = _nouveau_gpuobj_fini,
  93         .rd32 = _nouveau_gpuobj_rd32,
  94         .wr32 = _nouveau_gpuobj_wr32,
  95 };
  96
  97 static struct nouveau_oclass
  98 nv40_graph_sclass[] = {
  99         { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
 100         { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
 101         { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
 102         { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
 103         { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
 104         { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
 105         { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
 106         { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
 107         { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
 108         { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
 109         { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
 110         { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
 111         { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
 112         { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
 113         { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
 114         { 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
 115         {},
 116 };
 117
 118 static struct nouveau_oclass
 119 nv44_graph_sclass[] = {
 120         { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
 121         { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
 122         { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
 123         { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
 124         { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
 125         { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
 126         { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
 127         { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
 128         { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
 129         { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
 130         { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
 131         { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
 132         { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
 133         { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
 134         { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
 135         { 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
 136         {},
 137 };
 138
 139 /*******************************************************************************
 140  * PGRAPH context
 141  ******************************************************************************/
 142
 143 static int
 144 nv40_graph_context_ctor(struct nouveau_object *parent,
 145                         struct nouveau_object *engine,
 146                         struct nouveau_oclass *oclass, void *data, u32 size,
 147                         struct nouveau_object **pobject)
 148 {
 149         struct nv40_graph_priv *priv = (void *)engine;
 150         struct nv40_graph_chan *chan;
 151         int ret;
 152
 153         ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
 154                                            priv->size, 16,
 155                                            NVOBJ_FLAG_ZERO_ALLOC, &chan);
 156         *pobject = nv_object(chan);
 157         if (ret)
 158                 return ret;
 159
 160         nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
 161         nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
 162         return 0;
 163 }
 164
 165 static int
 166 nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
 167 {
 168         struct nv40_graph_priv *priv = (void *)object->engine;
 169         struct nv40_graph_chan *chan = (void *)object;
 170         u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
 171         int ret = 0;
 172
 173         nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
 174
 175         if (nv_rd32(priv, 0x40032c) == inst) {
 176                 if (suspend) {
 177                         nv_wr32(priv, 0x400720, 0x00000000);
 178                         nv_wr32(priv, 0x400784, inst);
 179                         nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
 180                         nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
 181                         if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
 182                                 u32 insn = nv_rd32(priv, 0x400308);
 183                                 nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
 184                                 ret = -EBUSY;
 185                         }
 186                 }
 187
 188                 nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
 189         }
 190
 191         if (nv_rd32(priv, 0x400330) == inst)
 192                 nv_mask(priv, 0x400330, 0x01000000, 0x00000000);
 193
 194         nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
 195         return ret;
 196 }
 197
 198 static struct nouveau_oclass
 199 nv40_graph_cclass = {
 200         .handle = NV_ENGCTX(GR, 0x40),
 201         .ofuncs = &(struct nouveau_ofuncs) {
 202                 .ctor = nv40_graph_context_ctor,
 203                 .dtor = _nouveau_graph_context_dtor,
 204                 .init = _nouveau_graph_context_init,
 205                 .fini = nv40_graph_context_fini,
 206                 .rd32 = _nouveau_graph_context_rd32,
 207                 .wr32 = _nouveau_graph_context_wr32,
 208         },
 209 };
 210
 211 /*******************************************************************************
 212  * PGRAPH engine/subdev functions
 213  ******************************************************************************/
 214
 215 static void
 216 nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
 217 {
 218         struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
 219         struct nouveau_fifo *pfifo = nouveau_fifo(engine);
 220         struct nv40_graph_priv *priv = (void *)engine;
 221         unsigned long flags;
 222
 223         pfifo->pause(pfifo, &flags);
 224         nv04_graph_idle(priv);
 225
 226         switch (nv_device(priv)->chipset) {
 227         case 0x40:
 228         case 0x41:
 229         case 0x42:
 230         case 0x43:
 231         case 0x45:
 232         case 0x4e:
 233                 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
 234                 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
 235                 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
 236                 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 237                 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 238                 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
 239                 switch (nv_device(priv)->chipset) {
 240                 case 0x40:
 241                 case 0x45:
 242                         nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
 243                         nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
 244                         break;
 245                 case 0x41:
 246                 case 0x42:
 247                 case 0x43:
 248                         nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
 249                         nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
 250                         break;
 251                 default:
 252                         break;
 253                 }
 254                 break;
 255         case 0x44:
 256         case 0x4a:
 257                 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
 258                 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
 259                 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
 260                 break;
 261         case 0x46:
 262         case 0x4c:
 263         case 0x47:
 264         case 0x49:
 265         case 0x4b:
 266         case 0x63:
 267         case 0x67:
 268         case 0x68:
 269                 nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
 270                 nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
 271                 nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
 272                 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 273                 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 274                 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
 275                 switch (nv_device(priv)->chipset) {
 276                 case 0x47:
 277                 case 0x49:
 278                 case 0x4b:
 279                         nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
 280                         nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
 281                         break;
 282                 default:
 283                         break;
 284                 }
 285                 break;
 286         default:
 287                 break;
 288         }
 289
 290         pfifo->start(pfifo, &flags);
 291 }
 292
 293 static void
 294 nv40_graph_intr(struct nouveau_subdev *subdev)
 295 {
 296         struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
 297         struct nouveau_engine *engine = nv_engine(subdev);
 298         struct nouveau_object *engctx;
 299         struct nouveau_handle *handle = NULL;
 300         struct nv40_graph_priv *priv = (void *)subdev;
 301         u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
 302         u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
 303         u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
 304         u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
 305         u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
 306         u32 subc = (addr & 0x00070000) >> 16;
 307         u32 mthd = (addr & 0x00001ffc);
 308         u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
 309         u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
 310         u32 show = stat;
 311         int chid;
 312
 313         engctx = nouveau_engctx_get(engine, inst);
 314         chid   = pfifo->chid(pfifo, engctx);
 315
 316         if (stat & NV_PGRAPH_INTR_ERROR) {
 317                 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 318                         handle = nouveau_handle_get_class(engctx, class);
 319                         if (handle && !nv_call(handle->object, mthd, data))
 320                                 show &= ~NV_PGRAPH_INTR_ERROR;
 321                         nouveau_handle_put(handle);
 322                 }
 323
 324                 if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
 325                         nv_mask(priv, 0x402000, 0, 0);
 326                 }
 327         }
 328
 329         nv_wr32(priv, NV03_PGRAPH_INTR, stat);
 330         nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
 331
 332         if (show) {
 333                 nv_error(priv, "%s", "");
 334                 nouveau_bitfield_print(nv10_graph_intr_name, show);
 335                 pr_cont(" nsource:");
 336                 nouveau_bitfield_print(nv04_graph_nsource, nsource);
 337                 pr_cont(" nstatus:");
 338                 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
 339                 pr_cont("\n");
 340                 nv_error(priv,
 341                          "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 342                          chid, inst << 4, nouveau_client_name(engctx), subc,
 343                          class, mthd, data);
 344         }
 345
 346         nouveau_engctx_put(engctx);
 347 }
 348
 349 static int
 350 nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 351                struct nouveau_oclass *oclass, void *data, u32 size,
 352                struct nouveau_object **pobject)
 353 {
 354         struct nv40_graph_priv *priv;
 355         int ret;
 356
 357         ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
 358         *pobject = nv_object(priv);
 359         if (ret)
 360                 return ret;
 361
 362         nv_subdev(priv)->unit = 0x00001000;
 363         nv_subdev(priv)->intr = nv40_graph_intr;
 364         nv_engine(priv)->cclass = &nv40_graph_cclass;
 365         if (nv44_graph_class(priv))
 366                 nv_engine(priv)->sclass = nv44_graph_sclass;
 367         else
 368                 nv_engine(priv)->sclass = nv40_graph_sclass;
 369         nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
 370
 371         priv->base.units = nv40_graph_units;
 372         return 0;
 373 }
 374
 375 static int
 376 nv40_graph_init(struct nouveau_object *object)
 377 {
 378         struct nouveau_engine *engine = nv_engine(object);
 379         struct nouveau_fb *pfb = nouveau_fb(object);
 380         struct nv40_graph_priv *priv = (void *)engine;
 381         int ret, i, j;
 382         u32 vramsz;
 383
 384         ret = nouveau_graph_init(&priv->base);
 385         if (ret)
 386                 return ret;
 387
 388         /* generate and upload context program */
 389         ret = nv40_grctx_init(nv_device(priv), &priv->size);
 390         if (ret)
 391                 return ret;
 392
 393         /* No context present currently */
 394         nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 395
 396         nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 397         nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 398
 399         nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 400         nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
 401         nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
 402         nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
 403         nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
 404         nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 405
 406         nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 407         nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 408
 409         j = nv_rd32(priv, 0x1540) & 0xff;
 410         if (j) {
 411                 for (i = 0; !(j & 1); j >>= 1, i++)
 412                         ;
 413                 nv_wr32(priv, 0x405000, i);
 414         }
 415
 416         if (nv_device(priv)->chipset == 0x40) {
 417                 nv_wr32(priv, 0x4009b0, 0x83280fff);
 418                 nv_wr32(priv, 0x4009b4, 0x000000a0);
 419         } else {
 420                 nv_wr32(priv, 0x400820, 0x83280eff);
 421                 nv_wr32(priv, 0x400824, 0x000000a0);
 422         }
 423
 424         switch (nv_device(priv)->chipset) {
 425         case 0x40:
 426         case 0x45:
 427                 nv_wr32(priv, 0x4009b8, 0x0078e366);
 428                 nv_wr32(priv, 0x4009bc, 0x0000014c);
 429                 break;
 430         case 0x41:
 431         case 0x42: /* pciid also 0x00Cx */
 432         /* case 0x0120: XXX (pciid) */
 433                 nv_wr32(priv, 0x400828, 0x007596ff);
 434                 nv_wr32(priv, 0x40082c, 0x00000108);
 435                 break;
 436         case 0x43:
 437                 nv_wr32(priv, 0x400828, 0x0072cb77);
 438                 nv_wr32(priv, 0x40082c, 0x00000108);
 439                 break;
 440         case 0x44:
 441         case 0x46: /* G72 */
 442         case 0x4a:
 443         case 0x4c: /* G7x-based C51 */
 444         case 0x4e:
 445                 nv_wr32(priv, 0x400860, 0);
 446                 nv_wr32(priv, 0x400864, 0);
 447                 break;
 448         case 0x47: /* G70 */
 449         case 0x49: /* G71 */
 450         case 0x4b: /* G73 */
 451                 nv_wr32(priv, 0x400828, 0x07830610);
 452                 nv_wr32(priv, 0x40082c, 0x0000016A);
 453                 break;
 454         default:
 455                 break;
 456         }
 457
 458         nv_wr32(priv, 0x400b38, 0x2ffff800);
 459         nv_wr32(priv, 0x400b3c, 0x00006000);
 460
 461         /* Tiling related stuff. */
 462         switch (nv_device(priv)->chipset) {
 463         case 0x44:
 464         case 0x4a:
 465                 nv_wr32(priv, 0x400bc4, 0x1003d888);
 466                 nv_wr32(priv, 0x400bbc, 0xb7a7b500);
 467                 break;
 468         case 0x46:
 469                 nv_wr32(priv, 0x400bc4, 0x0000e024);
 470                 nv_wr32(priv, 0x400bbc, 0xb7a7b520);
 471                 break;
 472         case 0x4c:
 473         case 0x4e:
 474         case 0x67:
 475                 nv_wr32(priv, 0x400bc4, 0x1003d888);
 476                 nv_wr32(priv, 0x400bbc, 0xb7a7b540);
 477                 break;
 478         default:
 479                 break;
 480         }
 481
 482         /* Turn all the tiling regions off. */
 483         for (i = 0; i < pfb->tile.regions; i++)
 484                 engine->tile_prog(engine, i);
 485
 486         /* begin RAM config */
 487         vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
 488         switch (nv_device(priv)->chipset) {
 489         case 0x40:
 490                 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
 491                 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
 492                 nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
 493                 nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
 494                 nv_wr32(priv, 0x400820, 0);
 495                 nv_wr32(priv, 0x400824, 0);
 496                 nv_wr32(priv, 0x400864, vramsz);
 497                 nv_wr32(priv, 0x400868, vramsz);
 498                 break;
 499         default:
 500                 switch (nv_device(priv)->chipset) {
 501                 case 0x41:
 502                 case 0x42:
 503                 case 0x43:
 504                 case 0x45:
 505                 case 0x4e:
 506                 case 0x44:
 507                 case 0x4a:
 508                         nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
 509                         nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
 510                         break;
 511                 default:
 512                         nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
 513                         nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
 514                         break;
 515                 }
 516                 nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
 517                 nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
 518                 nv_wr32(priv, 0x400840, 0);
 519                 nv_wr32(priv, 0x400844, 0);
 520                 nv_wr32(priv, 0x4008A0, vramsz);
 521                 nv_wr32(priv, 0x4008A4, vramsz);
 522                 break;
 523         }
 524
 525         return 0;
 526 }
 527
 528 struct nouveau_oclass
 529 nv40_graph_oclass = {
 530         .handle = NV_ENGINE(GR, 0x40),
 531         .ofuncs = &(struct nouveau_ofuncs) {
 532                 .ctor = nv40_graph_ctor,
 533                 .dtor = _nouveau_graph_dtor,
 534                 .init = nv40_graph_init,
 535                 .fini = _nouveau_graph_fini,
 536         },
 537 };