drivers/gpu/drm/msm/adreno/adreno_device.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013-2014 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
   7  */
   8
   9 #include "adreno_gpu.h"
  10
  11 #define ANY_ID 0xff
  12
  13 bool hang_debug = false;
  14 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  15 module_param_named(hang_debug, hang_debug, bool, 0600);
  16
  17 static const struct adreno_info gpulist[] = {
  18         {
  19                 .rev   = ADRENO_REV(2, 0, 0, 0),
  20                 .revn  = 200,
  21                 .name  = "A200",
  22                 .fw = {
  23                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  24                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  25                 },
  26                 .gmem  = SZ_256K,
  27                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  28                 .init  = a2xx_gpu_init,
  29         }, { /* a200 on i.mx51 has only 128kib gmem */
  30                 .rev   = ADRENO_REV(2, 0, 0, 1),
  31                 .revn  = 201,
  32                 .name  = "A200",
  33                 .fw = {
  34                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  35                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  36                 },
  37                 .gmem  = SZ_128K,
  38                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  39                 .init  = a2xx_gpu_init,
  40         }, {
  41                 .rev   = ADRENO_REV(2, 2, 0, ANY_ID),
  42                 .revn  = 220,
  43                 .name  = "A220",
  44                 .fw = {
  45                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  46                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  47                 },
  48                 .gmem  = SZ_512K,
  49                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  50                 .init  = a2xx_gpu_init,
  51         }, {
  52                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  53                 .revn  = 305,
  54                 .name  = "A305",
  55                 .fw = {
  56                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  57                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  58                 },
  59                 .gmem  = SZ_256K,
  60                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  61                 .init  = a3xx_gpu_init,
  62         }, {
  63                 .rev   = ADRENO_REV(3, 0, 6, 0),
  64                 .revn  = 307,        /* because a305c is revn==306 */
  65                 .name  = "A306",
  66                 .fw = {
  67                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  68                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  69                 },
  70                 .gmem  = SZ_128K,
  71                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  72                 .init  = a3xx_gpu_init,
  73         }, {
  74                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  75                 .revn  = 320,
  76                 .name  = "A320",
  77                 .fw = {
  78                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  79                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  80                 },
  81                 .gmem  = SZ_512K,
  82                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  83                 .init  = a3xx_gpu_init,
  84         }, {
  85                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  86                 .revn  = 330,
  87                 .name  = "A330",
  88                 .fw = {
  89                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
  90                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
  91                 },
  92                 .gmem  = SZ_1M,
  93                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  94                 .init  = a3xx_gpu_init,
  95         }, {
  96                 .rev   = ADRENO_REV(4, 2, 0, ANY_ID),
  97                 .revn  = 420,
  98                 .name  = "A420",
  99                 .fw = {
 100                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 101                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 102                 },
 103                 .gmem  = (SZ_1M + SZ_512K),
 104                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 105                 .init  = a4xx_gpu_init,
 106         }, {
 107                 .rev   = ADRENO_REV(4, 3, 0, ANY_ID),
 108                 .revn  = 430,
 109                 .name  = "A430",
 110                 .fw = {
 111                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 112                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 113                 },
 114                 .gmem  = (SZ_1M + SZ_512K),
 115                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 116                 .init  = a4xx_gpu_init,
 117         }, {
 118                 .rev = ADRENO_REV(5, 3, 0, 2),
 119                 .revn = 530,
 120                 .name = "A530",
 121                 .fw = {
 122                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 123                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 124                         [ADRENO_FW_GPMU] = "/*(DEBLOBBED)*/",
 125                 },
 126                 .gmem = SZ_1M,
 127                 /*
 128                  * Increase inactive period to 250 to avoid bouncing
 129                  * the GDSC which appears to make it grumpy
 130                  */
 131                 .inactive_period = 250,
 132                 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
 133                         ADRENO_QUIRK_FAULT_DETECT_MASK,
 134                 .init = a5xx_gpu_init,
 135                 .zapfw = "/*(DEBLOBBED)*/",
 136         }, {
 137                 .rev = ADRENO_REV(5, 4, 0, 2),
 138                 .revn = 540,
 139                 .name = "A540",
 140                 .fw = {
 141                         [ADRENO_FW_PM4] = "/*(DEBLOBBED)*/",
 142                         [ADRENO_FW_PFP] = "/*(DEBLOBBED)*/",
 143                         [ADRENO_FW_GPMU] = "/*(DEBLOBBED)*/",
 144                 },
 145                 .gmem = SZ_1M,
 146                 /*
 147                  * Increase inactive period to 250 to avoid bouncing
 148                  * the GDSC which appears to make it grumpy
 149                  */
 150                 .inactive_period = 250,
 151                 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
 152                 .init = a5xx_gpu_init,
 153                 .zapfw = "/*(DEBLOBBED)*/",
 154         }, {
 155                 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
 156                 .revn = 630,
 157                 .name = "A630",
 158                 .fw = {
 159                         [ADRENO_FW_SQE] = "/*(DEBLOBBED)*/",
 160                         [ADRENO_FW_GMU] = "/*(DEBLOBBED)*/",
 161                 },
 162                 .gmem = SZ_1M,
 163                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
 164                 .init = a6xx_gpu_init,
 165                 .zapfw = "/*(DEBLOBBED)*/",
 166         },
 167 };
 168
 169 /*(DEBLOBBED)*/
 170
 171 static inline bool _rev_match(uint8_t entry, uint8_t id)
 172 {
 173         return (entry == ANY_ID) || (entry == id);
 174 }
 175
 176 const struct adreno_info *adreno_info(struct adreno_rev rev)
 177 {
 178         int i;
 179
 180         /* identify gpu: */
 181         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
 182                 const struct adreno_info *info = &gpulist[i];
 183                 if (_rev_match(info->rev.core, rev.core) &&
 184                                 _rev_match(info->rev.major, rev.major) &&
 185                                 _rev_match(info->rev.minor, rev.minor) &&
 186                                 _rev_match(info->rev.patchid, rev.patchid))
 187                         return info;
 188         }
 189
 190         return NULL;
 191 }
 192
 193 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 194 {
 195         struct msm_drm_private *priv = dev->dev_private;
 196         struct platform_device *pdev = priv->gpu_pdev;
 197         struct msm_gpu *gpu = NULL;
 198         struct adreno_gpu *adreno_gpu;
 199         int ret;
 200
 201         if (pdev)
 202                 gpu = platform_get_drvdata(pdev);
 203
 204         if (!gpu) {
 205                 dev_err_once(dev->dev, "no GPU device was found\n");
 206                 return NULL;
 207         }
 208
 209         adreno_gpu = to_adreno_gpu(gpu);
 210
 211         /*
 212          * The number one reason for HW init to fail is if the firmware isn't
 213          * loaded yet. Try that first and don't bother continuing on
 214          * otherwise
 215          */
 216
 217         ret = adreno_load_fw(adreno_gpu);
 218         if (ret)
 219                 return NULL;
 220
 221         /* Make sure pm runtime is active and reset any previous errors */
 222         pm_runtime_set_active(&pdev->dev);
 223
 224         ret = pm_runtime_get_sync(&pdev->dev);
 225         if (ret < 0) {
 226                 pm_runtime_put_sync(&pdev->dev);
 227                 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
 228                 return NULL;
 229         }
 230
 231         mutex_lock(&dev->struct_mutex);
 232         ret = msm_gpu_hw_init(gpu);
 233         mutex_unlock(&dev->struct_mutex);
 234         pm_runtime_put_autosuspend(&pdev->dev);
 235         if (ret) {
 236                 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
 237                 return NULL;
 238         }
 239
 240 #ifdef CONFIG_DEBUG_FS
 241         if (gpu->funcs->debugfs_init) {
 242                 gpu->funcs->debugfs_init(gpu, dev->primary);
 243                 gpu->funcs->debugfs_init(gpu, dev->render);
 244         }
 245 #endif
 246
 247         return gpu;
 248 }
 249
 250 static void set_gpu_pdev(struct drm_device *dev,
 251                 struct platform_device *pdev)
 252 {
 253         struct msm_drm_private *priv = dev->dev_private;
 254         priv->gpu_pdev = pdev;
 255 }
 256
 257 static int find_chipid(struct device *dev, struct adreno_rev *rev)
 258 {
 259         struct device_node *node = dev->of_node;
 260         const char *compat;
 261         int ret;
 262         u32 chipid;
 263
 264         /* first search the compat strings for qcom,adreno-XYZ.W: */
 265         ret = of_property_read_string_index(node, "compatible", 0, &compat);
 266         if (ret == 0) {
 267                 unsigned int r, patch;
 268
 269                 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
 270                     sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
 271                         rev->core = r / 100;
 272                         r %= 100;
 273                         rev->major = r / 10;
 274                         r %= 10;
 275                         rev->minor = r;
 276                         rev->patchid = patch;
 277
 278                         return 0;
 279                 }
 280         }
 281
 282         /* and if that fails, fall back to legacy "qcom,chipid" property: */
 283         ret = of_property_read_u32(node, "qcom,chipid", &chipid);
 284         if (ret) {
 285                 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
 286                 return ret;
 287         }
 288
 289         rev->core = (chipid >> 24) & 0xff;
 290         rev->major = (chipid >> 16) & 0xff;
 291         rev->minor = (chipid >> 8) & 0xff;
 292         rev->patchid = (chipid & 0xff);
 293
 294         dev_warn(dev, "Using legacy qcom,chipid binding!\n");
 295         dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
 296                 rev->core, rev->major, rev->minor, rev->patchid);
 297
 298         return 0;
 299 }
 300
 301 static int adreno_bind(struct device *dev, struct device *master, void *data)
 302 {
 303         static struct adreno_platform_config config = {};
 304         const struct adreno_info *info;
 305         struct drm_device *drm = dev_get_drvdata(master);
 306         struct msm_drm_private *priv = drm->dev_private;
 307         struct msm_gpu *gpu;
 308         int ret;
 309
 310         ret = find_chipid(dev, &config.rev);
 311         if (ret)
 312                 return ret;
 313
 314         dev->platform_data = &config;
 315         set_gpu_pdev(drm, to_platform_device(dev));
 316
 317         info = adreno_info(config.rev);
 318
 319         if (!info) {
 320                 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 321                         config.rev.core, config.rev.major,
 322                         config.rev.minor, config.rev.patchid);
 323                 return -ENXIO;
 324         }
 325
 326         DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
 327                 config.rev.minor, config.rev.patchid);
 328
 329         priv->is_a2xx = config.rev.core == 2;
 330
 331         gpu = info->init(drm);
 332         if (IS_ERR(gpu)) {
 333                 dev_warn(drm->dev, "failed to load adreno gpu\n");
 334                 return PTR_ERR(gpu);
 335         }
 336
 337         dev_set_drvdata(dev, gpu);
 338
 339         return 0;
 340 }
 341
 342 static void adreno_unbind(struct device *dev, struct device *master,
 343                 void *data)
 344 {
 345         struct msm_gpu *gpu = dev_get_drvdata(dev);
 346
 347         pm_runtime_force_suspend(dev);
 348         gpu->funcs->destroy(gpu);
 349
 350         set_gpu_pdev(dev_get_drvdata(master), NULL);
 351 }
 352
 353 static const struct component_ops a3xx_ops = {
 354                 .bind   = adreno_bind,
 355                 .unbind = adreno_unbind,
 356 };
 357
 358 static void adreno_device_register_headless(void)
 359 {
 360         /* on imx5, we don't have a top-level mdp/dpu node
 361          * this creates a dummy node for the driver for that case
 362          */
 363         struct platform_device_info dummy_info = {
 364                 .parent = NULL,
 365                 .name = "msm",
 366                 .id = -1,
 367                 .res = NULL,
 368                 .num_res = 0,
 369                 .data = NULL,
 370                 .size_data = 0,
 371                 .dma_mask = ~0,
 372         };
 373         platform_device_register_full(&dummy_info);
 374 }
 375
 376 static int adreno_probe(struct platform_device *pdev)
 377 {
 378
 379         int ret;
 380
 381         ret = component_add(&pdev->dev, &a3xx_ops);
 382         if (ret)
 383                 return ret;
 384
 385         if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
 386                 adreno_device_register_headless();
 387
 388         return 0;
 389 }
 390
 391 static int adreno_remove(struct platform_device *pdev)
 392 {
 393         component_del(&pdev->dev, &a3xx_ops);
 394         return 0;
 395 }
 396
 397 static const struct of_device_id dt_match[] = {
 398         { .compatible = "qcom,adreno" },
 399         { .compatible = "qcom,adreno-3xx" },
 400         /* for compatibility with imx5 gpu: */
 401         { .compatible = "amd,imageon" },
 402         /* for backwards compat w/ downstream kgsl DT files: */
 403         { .compatible = "qcom,kgsl-3d0" },
 404         {}
 405 };
 406
 407 #ifdef CONFIG_PM
 408 static int adreno_resume(struct device *dev)
 409 {
 410         struct platform_device *pdev = to_platform_device(dev);
 411         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 412
 413         return gpu->funcs->pm_resume(gpu);
 414 }
 415
 416 static int adreno_suspend(struct device *dev)
 417 {
 418         struct platform_device *pdev = to_platform_device(dev);
 419         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 420
 421         return gpu->funcs->pm_suspend(gpu);
 422 }
 423 #endif
 424
 425 static const struct dev_pm_ops adreno_pm_ops = {
 426         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
 427         SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
 428 };
 429
 430 static struct platform_driver adreno_driver = {
 431         .probe = adreno_probe,
 432         .remove = adreno_remove,
 433         .driver = {
 434                 .name = "adreno",
 435                 .of_match_table = dt_match,
 436                 .pm = &adreno_pm_ops,
 437         },
 438 };
 439
 440 void __init adreno_register(void)
 441 {
 442         platform_driver_register(&adreno_driver);
 443 }
 444
 445 void __exit adreno_unregister(void)
 446 {
 447         platform_driver_unregister(&adreno_driver);
 448 }