drivers/gpu/drm/msm/adreno/adreno_device.c

   1 /*
   2  * Copyright (C) 2013-2014 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/pm_opp.h>
  21 #include "adreno_gpu.h"
  22
  23 #define ANY_ID 0xff
  24
  25 bool hang_debug = false;
  26 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  27 module_param_named(hang_debug, hang_debug, bool, 0600);
  28
  29 static const struct adreno_info gpulist[] = {
  30         {
  31                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  32                 .revn  = 305,
  33                 .name  = "A305",
  34                 .pm4fw = "/*(DEBLOBBED)*/",
  35                 .pfpfw = "/*(DEBLOBBED)*/",
  36                 .gmem  = SZ_256K,
  37                 .init  = a3xx_gpu_init,
  38         }, {
  39                 .rev   = ADRENO_REV(3, 0, 6, 0),
  40                 .revn  = 307,        /* because a305c is revn==306 */
  41                 .name  = "A306",
  42                 .pm4fw = "/*(DEBLOBBED)*/",
  43                 .pfpfw = "/*(DEBLOBBED)*/",
  44                 .gmem  = SZ_128K,
  45                 .init  = a3xx_gpu_init,
  46         }, {
  47                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  48                 .revn  = 320,
  49                 .name  = "A320",
  50                 .pm4fw = "/*(DEBLOBBED)*/",
  51                 .pfpfw = "/*(DEBLOBBED)*/",
  52                 .gmem  = SZ_512K,
  53                 .init  = a3xx_gpu_init,
  54         }, {
  55                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  56                 .revn  = 330,
  57                 .name  = "A330",
  58                 .pm4fw = "/*(DEBLOBBED)*/",
  59                 .pfpfw = "/*(DEBLOBBED)*/",
  60                 .gmem  = SZ_1M,
  61                 .init  = a3xx_gpu_init,
  62         }, {
  63                 .rev   = ADRENO_REV(4, 2, 0, ANY_ID),
  64                 .revn  = 420,
  65                 .name  = "A420",
  66                 .pm4fw = "/*(DEBLOBBED)*/",
  67                 .pfpfw = "/*(DEBLOBBED)*/",
  68                 .gmem  = (SZ_1M + SZ_512K),
  69                 .init  = a4xx_gpu_init,
  70         }, {
  71                 .rev   = ADRENO_REV(4, 3, 0, ANY_ID),
  72                 .revn  = 430,
  73                 .name  = "A430",
  74                 .pm4fw = "/*(DEBLOBBED)*/",
  75                 .pfpfw = "/*(DEBLOBBED)*/",
  76                 .gmem  = (SZ_1M + SZ_512K),
  77                 .init  = a4xx_gpu_init,
  78         }, {
  79                 .rev = ADRENO_REV(5, 3, 0, 2),
  80                 .revn = 530,
  81                 .name = "A530",
  82                 .pm4fw = "/*(DEBLOBBED)*/",
  83                 .pfpfw = "/*(DEBLOBBED)*/",
  84                 .gmem = SZ_1M,
  85                 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
  86                         ADRENO_QUIRK_FAULT_DETECT_MASK,
  87                 .init = a5xx_gpu_init,
  88                 .gpmufw = "/*(DEBLOBBED)*/",
  89                 .zapfw = "/*(DEBLOBBED)*/",
  90         },
  91 };
  92
  93 /*(DEBLOBBED)*/
  94
  95 static inline bool _rev_match(uint8_t entry, uint8_t id)
  96 {
  97         return (entry == ANY_ID) || (entry == id);
  98 }
  99
 100 const struct adreno_info *adreno_info(struct adreno_rev rev)
 101 {
 102         int i;
 103
 104         /* identify gpu: */
 105         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
 106                 const struct adreno_info *info = &gpulist[i];
 107                 if (_rev_match(info->rev.core, rev.core) &&
 108                                 _rev_match(info->rev.major, rev.major) &&
 109                                 _rev_match(info->rev.minor, rev.minor) &&
 110                                 _rev_match(info->rev.patchid, rev.patchid))
 111                         return info;
 112         }
 113
 114         return NULL;
 115 }
 116
 117 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 118 {
 119         struct msm_drm_private *priv = dev->dev_private;
 120         struct platform_device *pdev = priv->gpu_pdev;
 121         struct adreno_platform_config *config;
 122         struct adreno_rev rev;
 123         const struct adreno_info *info;
 124         struct msm_gpu *gpu = NULL;
 125
 126         if (!pdev) {
 127                 dev_err(dev->dev, "no adreno device\n");
 128                 return NULL;
 129         }
 130
 131         config = pdev->dev.platform_data;
 132         rev = config->rev;
 133         info = adreno_info(config->rev);
 134
 135         if (!info) {
 136                 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 137                                 rev.core, rev.major, rev.minor, rev.patchid);
 138                 return NULL;
 139         }
 140
 141         DBG("Found GPU: %u.%u.%u.%u",  rev.core, rev.major,
 142                         rev.minor, rev.patchid);
 143
 144         gpu = info->init(dev);
 145         if (IS_ERR(gpu)) {
 146                 dev_warn(dev->dev, "failed to load adreno gpu\n");
 147                 gpu = NULL;
 148                 /* not fatal */
 149         }
 150
 151         if (gpu) {
 152                 int ret;
 153
 154                 pm_runtime_get_sync(&pdev->dev);
 155                 mutex_lock(&dev->struct_mutex);
 156                 ret = msm_gpu_hw_init(gpu);
 157                 mutex_unlock(&dev->struct_mutex);
 158                 pm_runtime_put_sync(&pdev->dev);
 159                 if (ret) {
 160                         dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
 161                         gpu->funcs->destroy(gpu);
 162                         gpu = NULL;
 163                 }
 164         }
 165
 166         return gpu;
 167 }
 168
 169 static void set_gpu_pdev(struct drm_device *dev,
 170                 struct platform_device *pdev)
 171 {
 172         struct msm_drm_private *priv = dev->dev_private;
 173         priv->gpu_pdev = pdev;
 174 }
 175
 176 static int find_chipid(struct device *dev, u32 *chipid)
 177 {
 178         struct device_node *node = dev->of_node;
 179         const char *compat;
 180         int ret;
 181
 182         /* first search the compat strings for qcom,adreno-XYZ.W: */
 183         ret = of_property_read_string_index(node, "compatible", 0, &compat);
 184         if (ret == 0) {
 185                 unsigned rev, patch;
 186
 187                 if (sscanf(compat, "qcom,adreno-%u.%u", &rev, &patch) == 2) {
 188                         *chipid = 0;
 189                         *chipid |= (rev / 100) << 24;  /* core */
 190                         rev %= 100;
 191                         *chipid |= (rev / 10) << 16;   /* major */
 192                         rev %= 10;
 193                         *chipid |= rev << 8;           /* minor */
 194                         *chipid |= patch;
 195
 196                         return 0;
 197                 }
 198         }
 199
 200         /* and if that fails, fall back to legacy "qcom,chipid" property: */
 201         ret = of_property_read_u32(node, "qcom,chipid", chipid);
 202         if (ret)
 203                 return ret;
 204
 205         dev_warn(dev, "Using legacy qcom,chipid binding!\n");
 206         dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
 207                         (*chipid >> 24) & 0xff, (*chipid >> 16) & 0xff,
 208                         (*chipid >> 8) & 0xff, *chipid & 0xff);
 209
 210         return 0;
 211 }
 212
 213 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
 214 static int adreno_get_legacy_pwrlevels(struct device *dev)
 215 {
 216         struct device_node *child, *node;
 217         int ret;
 218
 219         node = of_find_compatible_node(dev->of_node, NULL,
 220                 "qcom,gpu-pwrlevels");
 221         if (!node) {
 222                 dev_err(dev, "Could not find the GPU powerlevels\n");
 223                 return -ENXIO;
 224         }
 225
 226         for_each_child_of_node(node, child) {
 227                 unsigned int val;
 228
 229                 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
 230                 if (ret)
 231                         continue;
 232
 233                 /*
 234                  * Skip the intentionally bogus clock value found at the bottom
 235                  * of most legacy frequency tables
 236                  */
 237                 if (val != 27000000)
 238                         dev_pm_opp_add(dev, val, 0);
 239         }
 240
 241         return 0;
 242 }
 243
 244 static int adreno_get_pwrlevels(struct device *dev,
 245                 struct adreno_platform_config *config)
 246 {
 247         unsigned long freq = ULONG_MAX;
 248         struct dev_pm_opp *opp;
 249         int ret;
 250
 251         /* You down with OPP? */
 252         if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
 253                 ret = adreno_get_legacy_pwrlevels(dev);
 254         else
 255                 ret = dev_pm_opp_of_add_table(dev);
 256
 257         if (ret)
 258                 return ret;
 259
 260         /* Find the fastest defined rate */
 261         opp = dev_pm_opp_find_freq_floor(dev, &freq);
 262         if (!IS_ERR(opp))
 263                 config->fast_rate = dev_pm_opp_get_freq(opp);
 264
 265         if (!config->fast_rate) {
 266                 DRM_DEV_INFO(dev,
 267                         "Could not find clock rate. Using default\n");
 268                 /* Pick a suitably safe clock speed for any target */
 269                 config->fast_rate = 200000000;
 270         }
 271
 272         return 0;
 273 }
 274
 275 static int adreno_bind(struct device *dev, struct device *master, void *data)
 276 {
 277         static struct adreno_platform_config config = {};
 278         u32 val;
 279         int ret;
 280
 281         ret = find_chipid(dev, &val);
 282         if (ret) {
 283                 dev_err(dev, "could not find chipid: %d\n", ret);
 284                 return ret;
 285         }
 286
 287         config.rev = ADRENO_REV((val >> 24) & 0xff,
 288                         (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
 289
 290         /* find clock rates: */
 291         config.fast_rate = 0;
 292
 293         ret = adreno_get_pwrlevels(dev, &config);
 294         if (ret)
 295                 return ret;
 296
 297         dev->platform_data = &config;
 298         set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
 299         return 0;
 300 }
 301
 302 static void adreno_unbind(struct device *dev, struct device *master,
 303                 void *data)
 304 {
 305         set_gpu_pdev(dev_get_drvdata(master), NULL);
 306 }
 307
 308 static const struct component_ops a3xx_ops = {
 309                 .bind   = adreno_bind,
 310                 .unbind = adreno_unbind,
 311 };
 312
 313 static int adreno_probe(struct platform_device *pdev)
 314 {
 315         return component_add(&pdev->dev, &a3xx_ops);
 316 }
 317
 318 static int adreno_remove(struct platform_device *pdev)
 319 {
 320         component_del(&pdev->dev, &a3xx_ops);
 321         return 0;
 322 }
 323
 324 static const struct of_device_id dt_match[] = {
 325         { .compatible = "qcom,adreno" },
 326         { .compatible = "qcom,adreno-3xx" },
 327         /* for backwards compat w/ downstream kgsl DT files: */
 328         { .compatible = "qcom,kgsl-3d0" },
 329         {}
 330 };
 331
 332 #ifdef CONFIG_PM
 333 static int adreno_resume(struct device *dev)
 334 {
 335         struct platform_device *pdev = to_platform_device(dev);
 336         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 337
 338         return gpu->funcs->pm_resume(gpu);
 339 }
 340
 341 static int adreno_suspend(struct device *dev)
 342 {
 343         struct platform_device *pdev = to_platform_device(dev);
 344         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 345
 346         return gpu->funcs->pm_suspend(gpu);
 347 }
 348 #endif
 349
 350 static const struct dev_pm_ops adreno_pm_ops = {
 351         SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
 352 };
 353
 354 static struct platform_driver adreno_driver = {
 355         .probe = adreno_probe,
 356         .remove = adreno_remove,
 357         .driver = {
 358                 .name = "adreno",
 359                 .of_match_table = dt_match,
 360                 .pm = &adreno_pm_ops,
 361         },
 362 };
 363
 364 void __init adreno_register(void)
 365 {
 366         platform_driver_register(&adreno_driver);
 367 }
 368
 369 void __exit adreno_unregister(void)
 370 {
 371         platform_driver_unregister(&adreno_driver);
 372 }