drivers/gpu/drm/msm/adreno/a2xx.xml.h

   1 #ifndef A2XX_XML
   2 #define A2XX_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10755 bytes, from 2015-09-14 20:46:55)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67771 bytes, from 2015-09-14 20:46:55)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63970 bytes, from 2015-09-14 20:50:12)
  18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
  19
  20 Copyright (C) 2013-2015 by the following authors:
  21 - Rob Clark <robdclark@gmail.com> (robclark)
  22
  23 Permission is hereby granted, free of charge, to any person obtaining
  24 a copy of this software and associated documentation files (the
  25 "Software"), to deal in the Software without restriction, including
  26 without limitation the rights to use, copy, modify, merge, publish,
  27 distribute, sublicense, and/or sell copies of the Software, and to
  28 permit persons to whom the Software is furnished to do so, subject to
  29 the following conditions:
  30
  31 The above copyright notice and this permission notice (including the
  32 next paragraph) shall be included in all copies or substantial
  33 portions of the Software.
  34
  35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */
  43
  44
  45 enum a2xx_rb_dither_type {
  46         DITHER_PIXEL = 0,
  47         DITHER_SUBPIXEL = 1,
  48 };
  49
  50 enum a2xx_colorformatx {
  51         COLORX_4_4_4_4 = 0,
  52         COLORX_1_5_5_5 = 1,
  53         COLORX_5_6_5 = 2,
  54         COLORX_8 = 3,
  55         COLORX_8_8 = 4,
  56         COLORX_8_8_8_8 = 5,
  57         COLORX_S8_8_8_8 = 6,
  58         COLORX_16_FLOAT = 7,
  59         COLORX_16_16_FLOAT = 8,
  60         COLORX_16_16_16_16_FLOAT = 9,
  61         COLORX_32_FLOAT = 10,
  62         COLORX_32_32_FLOAT = 11,
  63         COLORX_32_32_32_32_FLOAT = 12,
  64         COLORX_2_3_3 = 13,
  65         COLORX_8_8_8 = 14,
  66 };
  67
  68 enum a2xx_sq_surfaceformat {
  69         FMT_1_REVERSE = 0,
  70         FMT_1 = 1,
  71         FMT_8 = 2,
  72         FMT_1_5_5_5 = 3,
  73         FMT_5_6_5 = 4,
  74         FMT_6_5_5 = 5,
  75         FMT_8_8_8_8 = 6,
  76         FMT_2_10_10_10 = 7,
  77         FMT_8_A = 8,
  78         FMT_8_B = 9,
  79         FMT_8_8 = 10,
  80         FMT_Cr_Y1_Cb_Y0 = 11,
  81         FMT_Y1_Cr_Y0_Cb = 12,
  82         FMT_5_5_5_1 = 13,
  83         FMT_8_8_8_8_A = 14,
  84         FMT_4_4_4_4 = 15,
  85         FMT_10_11_11 = 16,
  86         FMT_11_11_10 = 17,
  87         FMT_DXT1 = 18,
  88         FMT_DXT2_3 = 19,
  89         FMT_DXT4_5 = 20,
  90         FMT_24_8 = 22,
  91         FMT_24_8_FLOAT = 23,
  92         FMT_16 = 24,
  93         FMT_16_16 = 25,
  94         FMT_16_16_16_16 = 26,
  95         FMT_16_EXPAND = 27,
  96         FMT_16_16_EXPAND = 28,
  97         FMT_16_16_16_16_EXPAND = 29,
  98         FMT_16_FLOAT = 30,
  99         FMT_16_16_FLOAT = 31,
 100         FMT_16_16_16_16_FLOAT = 32,
 101         FMT_32 = 33,
 102         FMT_32_32 = 34,
 103         FMT_32_32_32_32 = 35,
 104         FMT_32_FLOAT = 36,
 105         FMT_32_32_FLOAT = 37,
 106         FMT_32_32_32_32_FLOAT = 38,
 107         FMT_32_AS_8 = 39,
 108         FMT_32_AS_8_8 = 40,
 109         FMT_16_MPEG = 41,
 110         FMT_16_16_MPEG = 42,
 111         FMT_8_INTERLACED = 43,
 112         FMT_32_AS_8_INTERLACED = 44,
 113         FMT_32_AS_8_8_INTERLACED = 45,
 114         FMT_16_INTERLACED = 46,
 115         FMT_16_MPEG_INTERLACED = 47,
 116         FMT_16_16_MPEG_INTERLACED = 48,
 117         FMT_DXN = 49,
 118         FMT_8_8_8_8_AS_16_16_16_16 = 50,
 119         FMT_DXT1_AS_16_16_16_16 = 51,
 120         FMT_DXT2_3_AS_16_16_16_16 = 52,
 121         FMT_DXT4_5_AS_16_16_16_16 = 53,
 122         FMT_2_10_10_10_AS_16_16_16_16 = 54,
 123         FMT_10_11_11_AS_16_16_16_16 = 55,
 124         FMT_11_11_10_AS_16_16_16_16 = 56,
 125         FMT_32_32_32_FLOAT = 57,
 126         FMT_DXT3A = 58,
 127         FMT_DXT5A = 59,
 128         FMT_CTX1 = 60,
 129         FMT_DXT3A_AS_1_1_1_1 = 61,
 130 };
 131
 132 enum a2xx_sq_ps_vtx_mode {
 133         POSITION_1_VECTOR = 0,
 134         POSITION_2_VECTORS_UNUSED = 1,
 135         POSITION_2_VECTORS_SPRITE = 2,
 136         POSITION_2_VECTORS_EDGE = 3,
 137         POSITION_2_VECTORS_KILL = 4,
 138         POSITION_2_VECTORS_SPRITE_KILL = 5,
 139         POSITION_2_VECTORS_EDGE_KILL = 6,
 140         MULTIPASS = 7,
 141 };
 142
 143 enum a2xx_sq_sample_cntl {
 144         CENTROIDS_ONLY = 0,
 145         CENTERS_ONLY = 1,
 146         CENTROIDS_AND_CENTERS = 2,
 147 };
 148
 149 enum a2xx_dx_clip_space {
 150         DXCLIP_OPENGL = 0,
 151         DXCLIP_DIRECTX = 1,
 152 };
 153
 154 enum a2xx_pa_su_sc_polymode {
 155         POLY_DISABLED = 0,
 156         POLY_DUALMODE = 1,
 157 };
 158
 159 enum a2xx_rb_edram_mode {
 160         EDRAM_NOP = 0,
 161         COLOR_DEPTH = 4,
 162         DEPTH_ONLY = 5,
 163         EDRAM_COPY = 6,
 164 };
 165
 166 enum a2xx_pa_sc_pattern_bit_order {
 167         LITTLE = 0,
 168         BIG = 1,
 169 };
 170
 171 enum a2xx_pa_sc_auto_reset_cntl {
 172         NEVER = 0,
 173         EACH_PRIMITIVE = 1,
 174         EACH_PACKET = 2,
 175 };
 176
 177 enum a2xx_pa_pixcenter {
 178         PIXCENTER_D3D = 0,
 179         PIXCENTER_OGL = 1,
 180 };
 181
 182 enum a2xx_pa_roundmode {
 183         TRUNCATE = 0,
 184         ROUND = 1,
 185         ROUNDTOEVEN = 2,
 186         ROUNDTOODD = 3,
 187 };
 188
 189 enum a2xx_pa_quantmode {
 190         ONE_SIXTEENTH = 0,
 191         ONE_EIGTH = 1,
 192         ONE_QUARTER = 2,
 193         ONE_HALF = 3,
 194         ONE = 4,
 195 };
 196
 197 enum a2xx_rb_copy_sample_select {
 198         SAMPLE_0 = 0,
 199         SAMPLE_1 = 1,
 200         SAMPLE_2 = 2,
 201         SAMPLE_3 = 3,
 202         SAMPLE_01 = 4,
 203         SAMPLE_23 = 5,
 204         SAMPLE_0123 = 6,
 205 };
 206
 207 enum a2xx_rb_blend_opcode {
 208         BLEND_DST_PLUS_SRC = 0,
 209         BLEND_SRC_MINUS_DST = 1,
 210         BLEND_MIN_DST_SRC = 2,
 211         BLEND_MAX_DST_SRC = 3,
 212         BLEND_DST_MINUS_SRC = 4,
 213         BLEND_DST_PLUS_SRC_BIAS = 5,
 214 };
 215
 216 enum adreno_mmu_clnt_beh {
 217         BEH_NEVR = 0,
 218         BEH_TRAN_RNG = 1,
 219         BEH_TRAN_FLT = 2,
 220 };
 221
 222 enum sq_tex_clamp {
 223         SQ_TEX_WRAP = 0,
 224         SQ_TEX_MIRROR = 1,
 225         SQ_TEX_CLAMP_LAST_TEXEL = 2,
 226         SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3,
 227         SQ_TEX_CLAMP_HALF_BORDER = 4,
 228         SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5,
 229         SQ_TEX_CLAMP_BORDER = 6,
 230         SQ_TEX_MIRROR_ONCE_BORDER = 7,
 231 };
 232
 233 enum sq_tex_swiz {
 234         SQ_TEX_X = 0,
 235         SQ_TEX_Y = 1,
 236         SQ_TEX_Z = 2,
 237         SQ_TEX_W = 3,
 238         SQ_TEX_ZERO = 4,
 239         SQ_TEX_ONE = 5,
 240 };
 241
 242 enum sq_tex_filter {
 243         SQ_TEX_FILTER_POINT = 0,
 244         SQ_TEX_FILTER_BILINEAR = 1,
 245         SQ_TEX_FILTER_BICUBIC = 2,
 246 };
 247
 248 #define REG_A2XX_RBBM_PATCH_RELEASE                             0x00000001
 249
 250 #define REG_A2XX_RBBM_CNTL                                      0x0000003b
 251
 252 #define REG_A2XX_RBBM_SOFT_RESET                                0x0000003c
 253
 254 #define REG_A2XX_CP_PFP_UCODE_ADDR                              0x000000c0
 255
 256 #define REG_A2XX_CP_PFP_UCODE_DATA                              0x000000c1
 257
 258 #define REG_A2XX_MH_MMU_CONFIG                                  0x00000040
 259 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE                           0x00000001
 260 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE                    0x00000002
 261 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK             0x00000030
 262 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT            4
 263 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 264 {
 265         return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
 266 }
 267 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK             0x000000c0
 268 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT            6
 269 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 270 {
 271         return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
 272 }
 273 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK            0x00000300
 274 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT           8
 275 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 276 {
 277         return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
 278 }
 279 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK            0x00000c00
 280 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT           10
 281 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 282 {
 283         return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
 284 }
 285 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK            0x00003000
 286 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT           12
 287 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 288 {
 289         return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
 290 }
 291 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK            0x0000c000
 292 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT           14
 293 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 294 {
 295         return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
 296 }
 297 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK            0x00030000
 298 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT           16
 299 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 300 {
 301         return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
 302 }
 303 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK           0x000c0000
 304 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT          18
 305 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 306 {
 307         return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
 308 }
 309 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK           0x00300000
 310 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT          20
 311 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 312 {
 313         return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
 314 }
 315 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK             0x00c00000
 316 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT            22
 317 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 318 {
 319         return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
 320 }
 321 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK             0x03000000
 322 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT            24
 323 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
 324 {
 325         return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
 326 }
 327
 328 #define REG_A2XX_MH_MMU_VA_RANGE                                0x00000041
 329
 330 #define REG_A2XX_MH_MMU_PT_BASE                                 0x00000042
 331
 332 #define REG_A2XX_MH_MMU_PAGE_FAULT                              0x00000043
 333
 334 #define REG_A2XX_MH_MMU_TRAN_ERROR                              0x00000044
 335
 336 #define REG_A2XX_MH_MMU_INVALIDATE                              0x00000045
 337
 338 #define REG_A2XX_MH_MMU_MPU_BASE                                0x00000046
 339
 340 #define REG_A2XX_MH_MMU_MPU_END                                 0x00000047
 341
 342 #define REG_A2XX_NQWAIT_UNTIL                                   0x00000394
 343
 344 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT                       0x00000395
 345
 346 #define REG_A2XX_RBBM_PERFCOUNTER1_LO                           0x00000397
 347
 348 #define REG_A2XX_RBBM_PERFCOUNTER1_HI                           0x00000398
 349
 350 #define REG_A2XX_RBBM_DEBUG                                     0x0000039b
 351
 352 #define REG_A2XX_RBBM_PM_OVERRIDE1                              0x0000039c
 353
 354 #define REG_A2XX_RBBM_PM_OVERRIDE2                              0x0000039d
 355
 356 #define REG_A2XX_RBBM_DEBUG_OUT                                 0x000003a0
 357
 358 #define REG_A2XX_RBBM_DEBUG_CNTL                                0x000003a1
 359
 360 #define REG_A2XX_RBBM_READ_ERROR                                0x000003b3
 361
 362 #define REG_A2XX_RBBM_INT_CNTL                                  0x000003b4
 363
 364 #define REG_A2XX_RBBM_INT_STATUS                                0x000003b5
 365
 366 #define REG_A2XX_RBBM_INT_ACK                                   0x000003b6
 367
 368 #define REG_A2XX_MASTER_INT_SIGNAL                              0x000003b7
 369
 370 #define REG_A2XX_RBBM_PERIPHID1                                 0x000003f9
 371
 372 #define REG_A2XX_RBBM_PERIPHID2                                 0x000003fa
 373
 374 #define REG_A2XX_CP_PERFMON_CNTL                                0x00000444
 375
 376 #define REG_A2XX_CP_PERFCOUNTER_SELECT                          0x00000445
 377
 378 #define REG_A2XX_CP_PERFCOUNTER_LO                              0x00000446
 379
 380 #define REG_A2XX_CP_PERFCOUNTER_HI                              0x00000447
 381
 382 #define REG_A2XX_RBBM_STATUS                                    0x000005d0
 383 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK                    0x0000001f
 384 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT                   0
 385 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
 386 {
 387         return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
 388 }
 389 #define A2XX_RBBM_STATUS_TC_BUSY                                0x00000020
 390 #define A2XX_RBBM_STATUS_HIRQ_PENDING                           0x00000100
 391 #define A2XX_RBBM_STATUS_CPRQ_PENDING                           0x00000200
 392 #define A2XX_RBBM_STATUS_CFRQ_PENDING                           0x00000400
 393 #define A2XX_RBBM_STATUS_PFRQ_PENDING                           0x00000800
 394 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA                        0x00001000
 395 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY                           0x00004000
 396 #define A2XX_RBBM_STATUS_CP_NRT_BUSY                            0x00010000
 397 #define A2XX_RBBM_STATUS_MH_BUSY                                0x00040000
 398 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY                      0x00080000
 399 #define A2XX_RBBM_STATUS_SX_BUSY                                0x00200000
 400 #define A2XX_RBBM_STATUS_TPC_BUSY                               0x00400000
 401 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY                           0x01000000
 402 #define A2XX_RBBM_STATUS_PA_BUSY                                0x02000000
 403 #define A2XX_RBBM_STATUS_VGT_BUSY                               0x04000000
 404 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY                         0x08000000
 405 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY                          0x10000000
 406 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY                           0x40000000
 407 #define A2XX_RBBM_STATUS_GUI_ACTIVE                             0x80000000
 408
 409 #define REG_A2XX_MH_ARBITER_CONFIG                              0x00000a40
 410 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK            0x0000003f
 411 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT           0
 412 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
 413 {
 414         return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK;
 415 }
 416 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY            0x00000040
 417 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE                    0x00000080
 418 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE               0x00000100
 419 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL                   0x00000200
 420 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK                  0x00001c00
 421 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT                 10
 422 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
 423 {
 424         return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK;
 425 }
 426 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE                0x00002000
 427 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE               0x00004000
 428 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE           0x00008000
 429 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK            0x003f0000
 430 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT           16
 431 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
 432 {
 433         return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK;
 434 }
 435 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE                   0x00400000
 436 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE                  0x00800000
 437 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE                   0x01000000
 438 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE                   0x02000000
 439 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE                   0x04000000
 440
 441 #define REG_A2XX_A220_VSC_BIN_SIZE                              0x00000c01
 442 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK                      0x0000001f
 443 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT                     0
 444 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
 445 {
 446         return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
 447 }
 448 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK                     0x000003e0
 449 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT                    5
 450 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
 451 {
 452         return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
 453 }
 454
 455 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
 456
 457 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
 458
 459 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
 460
 461 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
 462
 463 #define REG_A2XX_PC_DEBUG_CNTL                                  0x00000c38
 464
 465 #define REG_A2XX_PC_DEBUG_DATA                                  0x00000c39
 466
 467 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS                         0x00000c44
 468
 469 #define REG_A2XX_GRAS_DEBUG_CNTL                                0x00000c80
 470
 471 #define REG_A2XX_PA_SU_DEBUG_CNTL                               0x00000c80
 472
 473 #define REG_A2XX_GRAS_DEBUG_DATA                                0x00000c81
 474
 475 #define REG_A2XX_PA_SU_DEBUG_DATA                               0x00000c81
 476
 477 #define REG_A2XX_PA_SU_FACE_DATA                                0x00000c86
 478
 479 #define REG_A2XX_SQ_GPR_MANAGEMENT                              0x00000d00
 480
 481 #define REG_A2XX_SQ_FLOW_CONTROL                                0x00000d01
 482
 483 #define REG_A2XX_SQ_INST_STORE_MANAGMENT                        0x00000d02
 484
 485 #define REG_A2XX_SQ_DEBUG_MISC                                  0x00000d05
 486
 487 #define REG_A2XX_SQ_INT_CNTL                                    0x00000d34
 488
 489 #define REG_A2XX_SQ_INT_STATUS                                  0x00000d35
 490
 491 #define REG_A2XX_SQ_INT_ACK                                     0x00000d36
 492
 493 #define REG_A2XX_SQ_DEBUG_INPUT_FSM                             0x00000dae
 494
 495 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM                         0x00000daf
 496
 497 #define REG_A2XX_SQ_DEBUG_TP_FSM                                0x00000db0
 498
 499 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0                             0x00000db1
 500
 501 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1                             0x00000db2
 502
 503 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC                             0x00000db3
 504
 505 #define REG_A2XX_SQ_DEBUG_PTR_BUFF                              0x00000db4
 506
 507 #define REG_A2XX_SQ_DEBUG_GPR_VTX                               0x00000db5
 508
 509 #define REG_A2XX_SQ_DEBUG_GPR_PIX                               0x00000db6
 510
 511 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL                         0x00000db7
 512
 513 #define REG_A2XX_SQ_DEBUG_VTX_TB_0                              0x00000db8
 514
 515 #define REG_A2XX_SQ_DEBUG_VTX_TB_1                              0x00000db9
 516
 517 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG                     0x00000dba
 518
 519 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM                      0x00000dbb
 520
 521 #define REG_A2XX_SQ_DEBUG_PIX_TB_0                              0x00000dbc
 522
 523 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0                   0x00000dbd
 524
 525 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1                   0x00000dbe
 526
 527 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2                   0x00000dbf
 528
 529 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3                   0x00000dc0
 530
 531 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM                      0x00000dc1
 532
 533 #define REG_A2XX_TC_CNTL_STATUS                                 0x00000e00
 534 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE                       0x00000001
 535
 536 #define REG_A2XX_TP0_CHICKEN                                    0x00000e1e
 537
 538 #define REG_A2XX_RB_BC_CONTROL                                  0x00000f01
 539 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE             0x00000001
 540 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK           0x00000006
 541 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT          1
 542 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
 543 {
 544         return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK;
 545 }
 546 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM                    0x00000008
 547 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH       0x00000010
 548 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP            0x00000020
 549 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP            0x00000040
 550 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE                   0x00000080
 551 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK              0x00001f00
 552 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT             8
 553 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
 554 {
 555         return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK;
 556 }
 557 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE                    0x00004000
 558 #define A2XX_RB_BC_CONTROL_CRC_MODE                             0x00008000
 559 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS              0x00010000
 560 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM                        0x00020000
 561 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK               0x003c0000
 562 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT              18
 563 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
 564 {
 565         return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK;
 566 }
 567 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE            0x00400000
 568 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK          0x07800000
 569 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT         23
 570 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
 571 {
 572         return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK;
 573 }
 574 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK      0x18000000
 575 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT     27
 576 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
 577 {
 578         return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK;
 579 }
 580 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE        0x20000000
 581 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM                           0x40000000
 582 #define A2XX_RB_BC_CONTROL_RESERVED6                            0x80000000
 583
 584 #define REG_A2XX_RB_EDRAM_INFO                                  0x00000f02
 585
 586 #define REG_A2XX_RB_DEBUG_CNTL                                  0x00000f26
 587
 588 #define REG_A2XX_RB_DEBUG_DATA                                  0x00000f27
 589
 590 #define REG_A2XX_RB_SURFACE_INFO                                0x00002000
 591
 592 #define REG_A2XX_RB_COLOR_INFO                                  0x00002001
 593 #define A2XX_RB_COLOR_INFO_FORMAT__MASK                         0x0000000f
 594 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT                        0
 595 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
 596 {
 597         return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK;
 598 }
 599 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK                     0x00000030
 600 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT                    4
 601 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
 602 {
 603         return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK;
 604 }
 605 #define A2XX_RB_COLOR_INFO_LINEAR                               0x00000040
 606 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK                         0x00000180
 607 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT                        7
 608 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
 609 {
 610         return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK;
 611 }
 612 #define A2XX_RB_COLOR_INFO_SWAP__MASK                           0x00000600
 613 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT                          9
 614 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
 615 {
 616         return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK;
 617 }
 618 #define A2XX_RB_COLOR_INFO_BASE__MASK                           0xfffff000
 619 #define A2XX_RB_COLOR_INFO_BASE__SHIFT                          12
 620 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
 621 {
 622         return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
 623 }
 624
 625 #define REG_A2XX_RB_DEPTH_INFO                                  0x00002002
 626 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000001
 627 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                  0
 628 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
 629 {
 630         return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
 631 }
 632 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                     0xfffff000
 633 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                    12
 634 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
 635 {
 636         return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
 637 }
 638
 639 #define REG_A2XX_A225_RB_COLOR_INFO3                            0x00002005
 640
 641 #define REG_A2XX_COHER_DEST_BASE_0                              0x00002006
 642
 643 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL                        0x0000200e
 644 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE      0x80000000
 645 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK                    0x00007fff
 646 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT                   0
 647 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
 648 {
 649         return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK;
 650 }
 651 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK                    0x7fff0000
 652 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT                   16
 653 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
 654 {
 655         return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK;
 656 }
 657
 658 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR                        0x0000200f
 659 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE      0x80000000
 660 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK                    0x00007fff
 661 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT                   0
 662 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
 663 {
 664         return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK;
 665 }
 666 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK                    0x7fff0000
 667 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT                   16
 668 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
 669 {
 670         return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK;
 671 }
 672
 673 #define REG_A2XX_PA_SC_WINDOW_OFFSET                            0x00002080
 674 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK                        0x00007fff
 675 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT                       0
 676 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
 677 {
 678         return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK;
 679 }
 680 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK                        0x7fff0000
 681 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT                       16
 682 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
 683 {
 684         return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK;
 685 }
 686 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE                        0x80000000
 687
 688 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL                        0x00002081
 689 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE      0x80000000
 690 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK                    0x00007fff
 691 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT                   0
 692 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
 693 {
 694         return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK;
 695 }
 696 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK                    0x7fff0000
 697 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT                   16
 698 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
 699 {
 700         return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK;
 701 }
 702
 703 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR                        0x00002082
 704 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE      0x80000000
 705 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK                    0x00007fff
 706 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT                   0
 707 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
 708 {
 709         return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK;
 710 }
 711 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK                    0x7fff0000
 712 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT                   16
 713 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
 714 {
 715         return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK;
 716 }
 717
 718 #define REG_A2XX_UNKNOWN_2010                                   0x00002010
 719
 720 #define REG_A2XX_VGT_MAX_VTX_INDX                               0x00002100
 721
 722 #define REG_A2XX_VGT_MIN_VTX_INDX                               0x00002101
 723
 724 #define REG_A2XX_VGT_INDX_OFFSET                                0x00002102
 725
 726 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX               0x00002103
 727
 728 #define REG_A2XX_RB_COLOR_MASK                                  0x00002104
 729 #define A2XX_RB_COLOR_MASK_WRITE_RED                            0x00000001
 730 #define A2XX_RB_COLOR_MASK_WRITE_GREEN                          0x00000002
 731 #define A2XX_RB_COLOR_MASK_WRITE_BLUE                           0x00000004
 732 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA                          0x00000008
 733
 734 #define REG_A2XX_RB_BLEND_RED                                   0x00002105
 735
 736 #define REG_A2XX_RB_BLEND_GREEN                                 0x00002106
 737
 738 #define REG_A2XX_RB_BLEND_BLUE                                  0x00002107
 739
 740 #define REG_A2XX_RB_BLEND_ALPHA                                 0x00002108
 741
 742 #define REG_A2XX_RB_FOG_COLOR                                   0x00002109
 743
 744 #define REG_A2XX_RB_STENCILREFMASK_BF                           0x0000210c
 745 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
 746 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
 747 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
 748 {
 749         return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
 750 }
 751 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
 752 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
 753 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
 754 {
 755         return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
 756 }
 757 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
 758 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
 759 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
 760 {
 761         return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
 762 }
 763
 764 #define REG_A2XX_RB_STENCILREFMASK                              0x0000210d
 765 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
 766 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
 767 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
 768 {
 769         return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK;
 770 }
 771 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
 772 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
 773 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
 774 {
 775         return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK;
 776 }
 777 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
 778 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
 779 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
 780 {
 781         return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
 782 }
 783
 784 #define REG_A2XX_RB_ALPHA_REF                                   0x0000210e
 785
 786 #define REG_A2XX_PA_CL_VPORT_XSCALE                             0x0000210f
 787 #define A2XX_PA_CL_VPORT_XSCALE__MASK                           0xffffffff
 788 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT                          0
 789 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
 790 {
 791         return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK;
 792 }
 793
 794 #define REG_A2XX_PA_CL_VPORT_XOFFSET                            0x00002110
 795 #define A2XX_PA_CL_VPORT_XOFFSET__MASK                          0xffffffff
 796 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT                         0
 797 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
 798 {
 799         return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK;
 800 }
 801
 802 #define REG_A2XX_PA_CL_VPORT_YSCALE                             0x00002111
 803 #define A2XX_PA_CL_VPORT_YSCALE__MASK                           0xffffffff
 804 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT                          0
 805 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
 806 {
 807         return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK;
 808 }
 809
 810 #define REG_A2XX_PA_CL_VPORT_YOFFSET                            0x00002112
 811 #define A2XX_PA_CL_VPORT_YOFFSET__MASK                          0xffffffff
 812 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT                         0
 813 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
 814 {
 815         return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK;
 816 }
 817
 818 #define REG_A2XX_PA_CL_VPORT_ZSCALE                             0x00002113
 819 #define A2XX_PA_CL_VPORT_ZSCALE__MASK                           0xffffffff
 820 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT                          0
 821 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
 822 {
 823         return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK;
 824 }
 825
 826 #define REG_A2XX_PA_CL_VPORT_ZOFFSET                            0x00002114
 827 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK                          0xffffffff
 828 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT                         0
 829 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
 830 {
 831         return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK;
 832 }
 833
 834 #define REG_A2XX_SQ_PROGRAM_CNTL                                0x00002180
 835 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK                      0x000000ff
 836 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT                     0
 837 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
 838 {
 839         return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK;
 840 }
 841 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK                      0x0000ff00
 842 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT                     8
 843 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
 844 {
 845         return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK;
 846 }
 847 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE                        0x00010000
 848 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE                        0x00020000
 849 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN                          0x00040000
 850 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX                      0x00080000
 851 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK              0x00f00000
 852 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT             20
 853 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
 854 {
 855         return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK;
 856 }
 857 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK               0x07000000
 858 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT              24
 859 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
 860 {
 861         return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK;
 862 }
 863 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK               0x78000000
 864 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT              27
 865 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
 866 {
 867         return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK;
 868 }
 869 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX                      0x80000000
 870
 871 #define REG_A2XX_SQ_CONTEXT_MISC                                0x00002181
 872 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE                 0x00000001
 873 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY                0x00000002
 874 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK               0x0000000c
 875 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT              2
 876 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
 877 {
 878         return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK;
 879 }
 880 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK                0x0000ff00
 881 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT               8
 882 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
 883 {
 884         return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK;
 885 }
 886 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF                    0x00010000
 887 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE                     0x00020000
 888 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL                       0x00040000
 889
 890 #define REG_A2XX_SQ_INTERPOLATOR_CNTL                           0x00002182
 891
 892 #define REG_A2XX_SQ_WRAPPING_0                                  0x00002183
 893
 894 #define REG_A2XX_SQ_WRAPPING_1                                  0x00002184
 895
 896 #define REG_A2XX_SQ_PS_PROGRAM                                  0x000021f6
 897
 898 #define REG_A2XX_SQ_VS_PROGRAM                                  0x000021f7
 899
 900 #define REG_A2XX_VGT_EVENT_INITIATOR                            0x000021f9
 901
 902 #define REG_A2XX_VGT_DRAW_INITIATOR                             0x000021fc
 903 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK                 0x0000003f
 904 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT                0
 905 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
 906 {
 907         return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
 908 }
 909 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK             0x000000c0
 910 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT            6
 911 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
 912 {
 913         return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
 914 }
 915 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK                  0x00000600
 916 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT                 9
 917 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
 918 {
 919         return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
 920 }
 921 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK                0x00000800
 922 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT               11
 923 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
 924 {
 925         return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
 926 }
 927 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP                         0x00001000
 928 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX                     0x00002000
 929 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE       0x00004000
 930 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK             0xff000000
 931 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT            24
 932 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
 933 {
 934         return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
 935 }
 936
 937 #define REG_A2XX_VGT_IMMED_DATA                                 0x000021fd
 938
 939 #define REG_A2XX_RB_DEPTHCONTROL                                0x00002200
 940 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE                     0x00000001
 941 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE                           0x00000002
 942 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE                     0x00000004
 943 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE                     0x00000008
 944 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK                        0x00000070
 945 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT                       4
 946 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
 947 {
 948         return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK;
 949 }
 950 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE                    0x00000080
 951 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK                  0x00000700
 952 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT                 8
 953 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
 954 {
 955         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK;
 956 }
 957 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK                  0x00003800
 958 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT                 11
 959 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
 960 {
 961         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK;
 962 }
 963 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK                 0x0001c000
 964 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT                14
 965 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
 966 {
 967         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK;
 968 }
 969 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK                 0x000e0000
 970 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT                17
 971 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
 972 {
 973         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK;
 974 }
 975 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK               0x00700000
 976 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT              20
 977 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
 978 {
 979         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK;
 980 }
 981 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK               0x03800000
 982 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT              23
 983 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
 984 {
 985         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK;
 986 }
 987 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK              0x1c000000
 988 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT             26
 989 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
 990 {
 991         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK;
 992 }
 993 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK              0xe0000000
 994 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT             29
 995 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
 996 {
 997         return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK;
 998 }
 999
1000 #define REG_A2XX_RB_BLEND_CONTROL                               0x00002201
1001 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK              0x0000001f
1002 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT             0
1003 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
1004 {
1005         return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK;
1006 }
1007 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK              0x000000e0
1008 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT             5
1009 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
1010 {
1011         return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
1012 }
1013 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK             0x00001f00
1014 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT            8
1015 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
1016 {
1017         return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK;
1018 }
1019 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK              0x001f0000
1020 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT             16
1021 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
1022 {
1023         return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK;
1024 }
1025 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK              0x00e00000
1026 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT             21
1027 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
1028 {
1029         return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
1030 }
1031 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK             0x1f000000
1032 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT            24
1033 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
1034 {
1035         return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK;
1036 }
1037 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE                0x20000000
1038 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE                       0x40000000
1039
1040 #define REG_A2XX_RB_COLORCONTROL                                0x00002202
1041 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK                   0x00000007
1042 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT                  0
1043 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
1044 {
1045         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK;
1046 }
1047 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE                  0x00000008
1048 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE               0x00000010
1049 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE                      0x00000020
1050 #define A2XX_RB_COLORCONTROL_VOB_ENABLE                         0x00000040
1051 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG                     0x00000080
1052 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK                     0x00000f00
1053 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT                    8
1054 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
1055 {
1056         return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK;
1057 }
1058 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK                  0x00003000
1059 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT                 12
1060 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
1061 {
1062         return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK;
1063 }
1064 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK                  0x0000c000
1065 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT                 14
1066 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
1067 {
1068         return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK;
1069 }
1070 #define A2XX_RB_COLORCONTROL_PIXEL_FOG                          0x00010000
1071 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK        0x03000000
1072 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT       24
1073 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
1074 {
1075         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK;
1076 }
1077 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK        0x0c000000
1078 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT       26
1079 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
1080 {
1081         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK;
1082 }
1083 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK        0x30000000
1084 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT       28
1085 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
1086 {
1087         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK;
1088 }
1089 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK        0xc0000000
1090 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT       30
1091 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
1092 {
1093         return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK;
1094 }
1095
1096 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX                         0x00002203
1097 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK                0x00000007
1098 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT               0
1099 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
1100 {
1101         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK;
1102 }
1103 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK                   0x00000038
1104 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT                  3
1105 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
1106 {
1107         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK;
1108 }
1109 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK       0x000001c0
1110 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT      6
1111 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
1112 {
1113         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK;
1114 }
1115
1116 #define REG_A2XX_PA_CL_CLIP_CNTL                                0x00002204
1117 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE                       0x00010000
1118 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA             0x00040000
1119 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK            0x00080000
1120 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT           19
1121 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
1122 {
1123         return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK;
1124 }
1125 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT                0x00100000
1126 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR                        0x00200000
1127 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN                      0x00400000
1128 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN                       0x00800000
1129 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN                       0x01000000
1130
1131 #define REG_A2XX_PA_SU_SC_MODE_CNTL                             0x00002205
1132 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT                      0x00000001
1133 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK                       0x00000002
1134 #define A2XX_PA_SU_SC_MODE_CNTL_FACE                            0x00000004
1135 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK                  0x00000018
1136 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT                 3
1137 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val)
1138 {
1139         return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK;
1140 }
1141 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK               0x000000e0
1142 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT              5
1143 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
1144 {
1145         return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK;
1146 }
1147 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK                0x00000700
1148 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT               8
1149 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
1150 {
1151         return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK;
1152 }
1153 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE        0x00000800
1154 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE         0x00001000
1155 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE         0x00002000
1156 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE                     0x00008000
1157 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE        0x00010000
1158 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE             0x00040000
1159 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST              0x00080000
1160 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS                  0x00100000
1161 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA               0x00200000
1162 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE               0x00800000
1163 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI            0x02000000
1164 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE        0x04000000
1165 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS                0x10000000
1166 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS              0x20000000
1167 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE                0x40000000
1168 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE               0x80000000
1169
1170 #define REG_A2XX_PA_CL_VTE_CNTL                                 0x00002206
1171 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA                   0x00000001
1172 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA                  0x00000002
1173 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA                   0x00000004
1174 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA                  0x00000008
1175 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA                   0x00000010
1176 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA                  0x00000020
1177 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT                          0x00000100
1178 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT                           0x00000200
1179 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT                          0x00000400
1180 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF                     0x00000800
1181
1182 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN                         0x00002207
1183 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK                0x00000007
1184 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT               0
1185 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val)
1186 {
1187         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK;
1188 }
1189 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK                   0x00000038
1190 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT                  3
1191 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val)
1192 {
1193         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK;
1194 }
1195 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK       0x000001c0
1196 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT      6
1197 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val)
1198 {
1199         return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK;
1200 }
1201
1202 #define REG_A2XX_RB_MODECONTROL                                 0x00002208
1203 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK                    0x00000007
1204 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT                   0
1205 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val)
1206 {
1207         return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK;
1208 }
1209
1210 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL                        0x00002209
1211
1212 #define REG_A2XX_RB_SAMPLE_POS                                  0x0000220a
1213
1214 #define REG_A2XX_CLEAR_COLOR                                    0x0000220b
1215 #define A2XX_CLEAR_COLOR_RED__MASK                              0x000000ff
1216 #define A2XX_CLEAR_COLOR_RED__SHIFT                             0
1217 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val)
1218 {
1219         return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK;
1220 }
1221 #define A2XX_CLEAR_COLOR_GREEN__MASK                            0x0000ff00
1222 #define A2XX_CLEAR_COLOR_GREEN__SHIFT                           8
1223 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val)
1224 {
1225         return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK;
1226 }
1227 #define A2XX_CLEAR_COLOR_BLUE__MASK                             0x00ff0000
1228 #define A2XX_CLEAR_COLOR_BLUE__SHIFT                            16
1229 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val)
1230 {
1231         return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK;
1232 }
1233 #define A2XX_CLEAR_COLOR_ALPHA__MASK                            0xff000000
1234 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT                           24
1235 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val)
1236 {
1237         return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK;
1238 }
1239
1240 #define REG_A2XX_A220_GRAS_CONTROL                              0x00002210
1241
1242 #define REG_A2XX_PA_SU_POINT_SIZE                               0x00002280
1243 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK                      0x0000ffff
1244 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT                     0
1245 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)
1246 {
1247         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;
1248 }
1249 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK                       0xffff0000
1250 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT                      16
1251 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)
1252 {
1253         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;
1254 }
1255
1256 #define REG_A2XX_PA_SU_POINT_MINMAX                             0x00002281
1257 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK                       0x0000ffff
1258 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT                      0
1259 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)
1260 {
1261         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;
1262 }
1263 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK                       0xffff0000
1264 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT                      16
1265 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)
1266 {
1267         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;
1268 }
1269
1270 #define REG_A2XX_PA_SU_LINE_CNTL                                0x00002282
1271 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK                        0x0000ffff
1272 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT                       0
1273 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)
1274 {
1275         return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;
1276 }
1277
1278 #define REG_A2XX_PA_SC_LINE_STIPPLE                             0x00002283
1279 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK              0x0000ffff
1280 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT             0
1281 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val)
1282 {
1283         return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK;
1284 }
1285 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK              0x00ff0000
1286 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT             16
1287 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val)
1288 {
1289         return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK;
1290 }
1291 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK         0x10000000
1292 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT        28
1293 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val)
1294 {
1295         return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK;
1296 }
1297 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK           0x60000000
1298 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT          29
1299 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val)
1300 {
1301         return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK;
1302 }
1303
1304 #define REG_A2XX_PA_SC_VIZ_QUERY                                0x00002293
1305
1306 #define REG_A2XX_VGT_ENHANCE                                    0x00002294
1307
1308 #define REG_A2XX_PA_SC_LINE_CNTL                                0x00002300
1309 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK                    0x0000ffff
1310 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT                   0
1311 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
1312 {
1313         return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK;
1314 }
1315 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL                      0x00000100
1316 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH                  0x00000200
1317 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL                         0x00000400
1318
1319 #define REG_A2XX_PA_SC_AA_CONFIG                                0x00002301
1320
1321 #define REG_A2XX_PA_SU_VTX_CNTL                                 0x00002302
1322 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK                    0x00000001
1323 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT                   0
1324 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val)
1325 {
1326         return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK;
1327 }
1328 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK                    0x00000006
1329 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT                   1
1330 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val)
1331 {
1332         return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK;
1333 }
1334 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK                    0x00000380
1335 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT                   7
1336 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val)
1337 {
1338         return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK;
1339 }
1340
1341 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ                         0x00002303
1342 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK                       0xffffffff
1343 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT                      0
1344 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val)
1345 {
1346         return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK;
1347 }
1348
1349 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ                         0x00002304
1350 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK                       0xffffffff
1351 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT                      0
1352 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val)
1353 {
1354         return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK;
1355 }
1356
1357 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ                         0x00002305
1358 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK                       0xffffffff
1359 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT                      0
1360 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val)
1361 {
1362         return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK;
1363 }
1364
1365 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ                         0x00002306
1366 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK                       0xffffffff
1367 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT                      0
1368 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val)
1369 {
1370         return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK;
1371 }
1372
1373 #define REG_A2XX_SQ_VS_CONST                                    0x00002307
1374 #define A2XX_SQ_VS_CONST_BASE__MASK                             0x000001ff
1375 #define A2XX_SQ_VS_CONST_BASE__SHIFT                            0
1376 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val)
1377 {
1378         return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK;
1379 }
1380 #define A2XX_SQ_VS_CONST_SIZE__MASK                             0x001ff000
1381 #define A2XX_SQ_VS_CONST_SIZE__SHIFT                            12
1382 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val)
1383 {
1384         return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK;
1385 }
1386
1387 #define REG_A2XX_SQ_PS_CONST                                    0x00002308
1388 #define A2XX_SQ_PS_CONST_BASE__MASK                             0x000001ff
1389 #define A2XX_SQ_PS_CONST_BASE__SHIFT                            0
1390 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val)
1391 {
1392         return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK;
1393 }
1394 #define A2XX_SQ_PS_CONST_SIZE__MASK                             0x001ff000
1395 #define A2XX_SQ_PS_CONST_SIZE__SHIFT                            12
1396 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
1397 {
1398         return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK;
1399 }
1400
1401 #define REG_A2XX_SQ_DEBUG_MISC_0                                0x00002309
1402
1403 #define REG_A2XX_SQ_DEBUG_MISC_1                                0x0000230a
1404
1405 #define REG_A2XX_PA_SC_AA_MASK                                  0x00002312
1406
1407 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL                    0x00002316
1408
1409 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL                           0x00002317
1410
1411 #define REG_A2XX_RB_COPY_CONTROL                                0x00002318
1412 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK           0x00000007
1413 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT          0
1414 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val)
1415 {
1416         return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK;
1417 }
1418 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE                 0x00000008
1419 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK                   0x000000f0
1420 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT                  4
1421 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val)
1422 {
1423         return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK;
1424 }
1425
1426 #define REG_A2XX_RB_COPY_DEST_BASE                              0x00002319
1427
1428 #define REG_A2XX_RB_COPY_DEST_PITCH                             0x0000231a
1429 #define A2XX_RB_COPY_DEST_PITCH__MASK                           0xffffffff
1430 #define A2XX_RB_COPY_DEST_PITCH__SHIFT                          0
1431 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
1432 {
1433         return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
1434 }
1435
1436 #define REG_A2XX_RB_COPY_DEST_INFO                              0x0000231b
1437 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK                0x00000007
1438 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT               0
1439 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val)
1440 {
1441         return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK;
1442 }
1443 #define A2XX_RB_COPY_DEST_INFO_LINEAR                           0x00000008
1444 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK                     0x000000f0
1445 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                    4
1446 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val)
1447 {
1448         return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1449 }
1450 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK                       0x00000300
1451 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT                      8
1452 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val)
1453 {
1454         return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK;
1455 }
1456 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK                0x00000c00
1457 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT               10
1458 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1459 {
1460         return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1461 }
1462 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK                0x00003000
1463 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT               12
1464 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val)
1465 {
1466         return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK;
1467 }
1468 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED                        0x00004000
1469 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN                      0x00008000
1470 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE                       0x00010000
1471 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA                      0x00020000
1472
1473 #define REG_A2XX_RB_COPY_DEST_OFFSET                            0x0000231c
1474 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK                        0x00001fff
1475 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT                       0
1476 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val)
1477 {
1478         return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK;
1479 }
1480 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK                        0x03ffe000
1481 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT                       13
1482 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
1483 {
1484         return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK;
1485 }
1486
1487 #define REG_A2XX_RB_DEPTH_CLEAR                                 0x0000231d
1488
1489 #define REG_A2XX_RB_SAMPLE_COUNT_CTL                            0x00002324
1490
1491 #define REG_A2XX_RB_COLOR_DEST_MASK                             0x00002326
1492
1493 #define REG_A2XX_A225_GRAS_UCP0X                                0x00002340
1494
1495 #define REG_A2XX_A225_GRAS_UCP5W                                0x00002357
1496
1497 #define REG_A2XX_A225_GRAS_UCP_ENABLED                          0x00002360
1498
1499 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE                  0x00002380
1500
1501 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET                  0x00002383
1502
1503 #define REG_A2XX_SQ_CONSTANT_0                                  0x00004000
1504
1505 #define REG_A2XX_SQ_FETCH_0                                     0x00004800
1506
1507 #define REG_A2XX_SQ_CF_BOOLEANS                                 0x00004900
1508
1509 #define REG_A2XX_SQ_CF_LOOP                                     0x00004908
1510
1511 #define REG_A2XX_COHER_SIZE_PM4                                 0x00000a29
1512
1513 #define REG_A2XX_COHER_BASE_PM4                                 0x00000a2a
1514
1515 #define REG_A2XX_COHER_STATUS_PM4                               0x00000a2b
1516
1517 #define REG_A2XX_SQ_TEX_0                                       0x00000000
1518 #define A2XX_SQ_TEX_0_CLAMP_X__MASK                             0x00001c00
1519 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT                            10
1520 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
1521 {
1522         return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK;
1523 }
1524 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK                             0x0000e000
1525 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT                            13
1526 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val)
1527 {
1528         return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK;
1529 }
1530 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK                             0x00070000
1531 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT                            16
1532 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
1533 {
1534         return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
1535 }
1536 #define A2XX_SQ_TEX_0_PITCH__MASK                               0xffc00000
1537 #define A2XX_SQ_TEX_0_PITCH__SHIFT                              22
1538 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
1539 {
1540         return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
1541 }
1542
1543 #define REG_A2XX_SQ_TEX_1                                       0x00000001
1544
1545 #define REG_A2XX_SQ_TEX_2                                       0x00000002
1546 #define A2XX_SQ_TEX_2_WIDTH__MASK                               0x00001fff
1547 #define A2XX_SQ_TEX_2_WIDTH__SHIFT                              0
1548 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val)
1549 {
1550         return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK;
1551 }
1552 #define A2XX_SQ_TEX_2_HEIGHT__MASK                              0x03ffe000
1553 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT                             13
1554 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
1555 {
1556         return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
1557 }
1558
1559 #define REG_A2XX_SQ_TEX_3                                       0x00000003
1560 #define A2XX_SQ_TEX_3_SWIZ_X__MASK                              0x0000000e
1561 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT                             1
1562 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
1563 {
1564         return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK;
1565 }
1566 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK                              0x00000070
1567 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT                             4
1568 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val)
1569 {
1570         return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK;
1571 }
1572 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK                              0x00000380
1573 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT                             7
1574 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val)
1575 {
1576         return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK;
1577 }
1578 #define A2XX_SQ_TEX_3_SWIZ_W__MASK                              0x00001c00
1579 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT                             10
1580 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
1581 {
1582         return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
1583 }
1584 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK                       0x00180000
1585 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT                      19
1586 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
1587 {
1588         return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK;
1589 }
1590 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK                       0x00600000
1591 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT                      21
1592 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
1593 {
1594         return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
1595 }
1596
1597
1598 #endif /* A2XX_XML */