drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 static inline int ring_space(struct intel_ring_buffer *ring)
  38 {
  39         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  40         if (space < 0)
  41                 space += ring->size;
  42         return space;
  43 }
  44
  45 static u32 i915_gem_get_seqno(struct drm_device *dev)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         u32 seqno;
  49
  50         seqno = dev_priv->next_seqno;
  51
  52         /* reserve 0 for non-seqno */
  53         if (++dev_priv->next_seqno == 0)
  54                 dev_priv->next_seqno = 1;
  55
  56         return seqno;
  57 }
  58
  59 static int
  60 render_ring_flush(struct intel_ring_buffer *ring,
  61                   u32   invalidate_domains,
  62                   u32   flush_domains)
  63 {
  64         struct drm_device *dev = ring->dev;
  65         u32 cmd;
  66         int ret;
  67
  68         /*
  69          * read/write caches:
  70          *
  71          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  72          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  73          * also flushed at 2d versus 3d pipeline switches.
  74          *
  75          * read-only caches:
  76          *
  77          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  78          * MI_READ_FLUSH is set, and is always flushed on 965.
  79          *
  80          * I915_GEM_DOMAIN_COMMAND may not exist?
  81          *
  82          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  83          * invalidated when MI_EXE_FLUSH is set.
  84          *
  85          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  86          * invalidated with every MI_FLUSH.
  87          *
  88          * TLBs:
  89          *
  90          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  91          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  92          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  93          * are flushed at any MI_FLUSH.
  94          */
  95
  96         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  97         if ((invalidate_domains|flush_domains) &
  98             I915_GEM_DOMAIN_RENDER)
  99                 cmd &= ~MI_NO_WRITE_FLUSH;
 100         if (INTEL_INFO(dev)->gen < 4) {
 101                 /*
 102                  * On the 965, the sampler cache always gets flushed
 103                  * and this bit is reserved.
 104                  */
 105                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 106                         cmd |= MI_READ_FLUSH;
 107         }
 108         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 109                 cmd |= MI_EXE_FLUSH;
 110
 111         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 112             (IS_G4X(dev) || IS_GEN5(dev)))
 113                 cmd |= MI_INVALIDATE_ISP;
 114
 115         ret = intel_ring_begin(ring, 2);
 116         if (ret)
 117                 return ret;
 118
 119         intel_ring_emit(ring, cmd);
 120         intel_ring_emit(ring, MI_NOOP);
 121         intel_ring_advance(ring);
 122
 123         return 0;
 124 }
 125
 126 static void ring_write_tail(struct intel_ring_buffer *ring,
 127                             u32 value)
 128 {
 129         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 130         I915_WRITE_TAIL(ring, value);
 131 }
 132
 133 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 134 {
 135         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 136         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 137                         RING_ACTHD(ring->mmio_base) : ACTHD;
 138
 139         return I915_READ(acthd_reg);
 140 }
 141
 142 static int init_ring_common(struct intel_ring_buffer *ring)
 143 {
 144         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 145         struct drm_i915_gem_object *obj = ring->obj;
 146         u32 head;
 147
 148         /* Stop the ring if it's running. */
 149         I915_WRITE_CTL(ring, 0);
 150         I915_WRITE_HEAD(ring, 0);
 151         ring->write_tail(ring, 0);
 152
 153         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 154
 155         /* G45 ring initialization fails to reset head to zero */
 156         if (head != 0) {
 157                 DRM_DEBUG_KMS("%s head not reset to zero "
 158                               "ctl %08x head %08x tail %08x start %08x\n",
 159                               ring->name,
 160                               I915_READ_CTL(ring),
 161                               I915_READ_HEAD(ring),
 162                               I915_READ_TAIL(ring),
 163                               I915_READ_START(ring));
 164
 165                 I915_WRITE_HEAD(ring, 0);
 166
 167                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 168                         DRM_ERROR("failed to set %s head to zero "
 169                                   "ctl %08x head %08x tail %08x start %08x\n",
 170                                   ring->name,
 171                                   I915_READ_CTL(ring),
 172                                   I915_READ_HEAD(ring),
 173                                   I915_READ_TAIL(ring),
 174                                   I915_READ_START(ring));
 175                 }
 176         }
 177
 178         /* Initialize the ring. This must happen _after_ we've cleared the ring
 179          * registers with the above sequence (the readback of the HEAD registers
 180          * also enforces ordering), otherwise the hw might lose the new ring
 181          * register values. */
 182         I915_WRITE_START(ring, obj->gtt_offset);
 183         I915_WRITE_CTL(ring,
 184                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 185                         | RING_REPORT_64K | RING_VALID);
 186
 187         /* If the head is still not zero, the ring is dead */
 188         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 189             I915_READ_START(ring) != obj->gtt_offset ||
 190             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 191                 DRM_ERROR("%s initialization failed "
 192                                 "ctl %08x head %08x tail %08x start %08x\n",
 193                                 ring->name,
 194                                 I915_READ_CTL(ring),
 195                                 I915_READ_HEAD(ring),
 196                                 I915_READ_TAIL(ring),
 197                                 I915_READ_START(ring));
 198                 return -EIO;
 199         }
 200
 201         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 202                 i915_kernel_lost_context(ring->dev);
 203         else {
 204                 ring->head = I915_READ_HEAD(ring);
 205                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 206                 ring->space = ring_space(ring);
 207         }
 208
 209         return 0;
 210 }
 211
 212 /*
 213  * 965+ support PIPE_CONTROL commands, which provide finer grained control
 214  * over cache flushing.
 215  */
 216 struct pipe_control {
 217         struct drm_i915_gem_object *obj;
 218         volatile u32 *cpu_page;
 219         u32 gtt_offset;
 220 };
 221
 222 static int
 223 init_pipe_control(struct intel_ring_buffer *ring)
 224 {
 225         struct pipe_control *pc;
 226         struct drm_i915_gem_object *obj;
 227         int ret;
 228
 229         if (ring->private)
 230                 return 0;
 231
 232         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 233         if (!pc)
 234                 return -ENOMEM;
 235
 236         obj = i915_gem_alloc_object(ring->dev, 4096);
 237         if (obj == NULL) {
 238                 DRM_ERROR("Failed to allocate seqno page\n");
 239                 ret = -ENOMEM;
 240                 goto err;
 241         }
 242         obj->cache_level = I915_CACHE_LLC;
 243
 244         ret = i915_gem_object_pin(obj, 4096, true);
 245         if (ret)
 246                 goto err_unref;
 247
 248         pc->gtt_offset = obj->gtt_offset;
 249         pc->cpu_page =  kmap(obj->pages[0]);
 250         if (pc->cpu_page == NULL)
 251                 goto err_unpin;
 252
 253         pc->obj = obj;
 254         ring->private = pc;
 255         return 0;
 256
 257 err_unpin:
 258         i915_gem_object_unpin(obj);
 259 err_unref:
 260         drm_gem_object_unreference(&obj->base);
 261 err:
 262         kfree(pc);
 263         return ret;
 264 }
 265
 266 static void
 267 cleanup_pipe_control(struct intel_ring_buffer *ring)
 268 {
 269         struct pipe_control *pc = ring->private;
 270         struct drm_i915_gem_object *obj;
 271
 272         if (!ring->private)
 273                 return;
 274
 275         obj = pc->obj;
 276         kunmap(obj->pages[0]);
 277         i915_gem_object_unpin(obj);
 278         drm_gem_object_unreference(&obj->base);
 279
 280         kfree(pc);
 281         ring->private = NULL;
 282 }
 283
 284 static int init_render_ring(struct intel_ring_buffer *ring)
 285 {
 286         struct drm_device *dev = ring->dev;
 287         struct drm_i915_private *dev_priv = dev->dev_private;
 288         int ret = init_ring_common(ring);
 289
 290         if (INTEL_INFO(dev)->gen > 3) {
 291                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 292                 if (IS_GEN6(dev) || IS_GEN7(dev))
 293                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 294                 I915_WRITE(MI_MODE, mode);
 295         }
 296
 297         if (INTEL_INFO(dev)->gen >= 6) {
 298         } else if (IS_GEN5(dev)) {
 299                 ret = init_pipe_control(ring);
 300                 if (ret)
 301                         return ret;
 302         }
 303
 304         return ret;
 305 }
 306
 307 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 308 {
 309         if (!ring->private)
 310                 return;
 311
 312         cleanup_pipe_control(ring);
 313 }
 314
 315 static void
 316 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
 317 {
 318         struct drm_device *dev = ring->dev;
 319         struct drm_i915_private *dev_priv = dev->dev_private;
 320         int id;
 321
 322         /*
 323          * cs -> 1 = vcs, 0 = bcs
 324          * vcs -> 1 = bcs, 0 = cs,
 325          * bcs -> 1 = cs, 0 = vcs.
 326          */
 327         id = ring - dev_priv->ring;
 328         id += 2 - i;
 329         id %= 3;
 330
 331         intel_ring_emit(ring,
 332                         MI_SEMAPHORE_MBOX |
 333                         MI_SEMAPHORE_REGISTER |
 334                         MI_SEMAPHORE_UPDATE);
 335         intel_ring_emit(ring, seqno);
 336         intel_ring_emit(ring,
 337                         RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
 338 }
 339
 340 static int
 341 gen6_add_request(struct intel_ring_buffer *ring,
 342                  u32 *result)
 343 {
 344         u32 seqno;
 345         int ret;
 346
 347         ret = intel_ring_begin(ring, 10);
 348         if (ret)
 349                 return ret;
 350
 351         seqno = i915_gem_get_seqno(ring->dev);
 352         update_semaphore(ring, 0, seqno);
 353         update_semaphore(ring, 1, seqno);
 354
 355         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 356         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 357         intel_ring_emit(ring, seqno);
 358         intel_ring_emit(ring, MI_USER_INTERRUPT);
 359         intel_ring_advance(ring);
 360
 361         *result = seqno;
 362         return 0;
 363 }
 364
 365 int
 366 intel_ring_sync(struct intel_ring_buffer *ring,
 367                 struct intel_ring_buffer *to,
 368                 u32 seqno)
 369 {
 370         int ret;
 371
 372         ret = intel_ring_begin(ring, 4);
 373         if (ret)
 374                 return ret;
 375
 376         intel_ring_emit(ring,
 377                         MI_SEMAPHORE_MBOX |
 378                         MI_SEMAPHORE_REGISTER |
 379                         intel_ring_sync_index(ring, to) << 17 |
 380                         MI_SEMAPHORE_COMPARE);
 381         intel_ring_emit(ring, seqno);
 382         intel_ring_emit(ring, 0);
 383         intel_ring_emit(ring, MI_NOOP);
 384         intel_ring_advance(ring);
 385
 386         return 0;
 387 }
 388
 389 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 390 do {                                                                    \
 391         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |           \
 392                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
 393         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 394         intel_ring_emit(ring__, 0);                                                     \
 395         intel_ring_emit(ring__, 0);                                                     \
 396 } while (0)
 397
 398 static int
 399 pc_render_add_request(struct intel_ring_buffer *ring,
 400                       u32 *result)
 401 {
 402         struct drm_device *dev = ring->dev;
 403         u32 seqno = i915_gem_get_seqno(dev);
 404         struct pipe_control *pc = ring->private;
 405         u32 scratch_addr = pc->gtt_offset + 128;
 406         int ret;
 407
 408         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 409          * incoherent with writes to memory, i.e. completely fubar,
 410          * so we need to use PIPE_NOTIFY instead.
 411          *
 412          * However, we also need to workaround the qword write
 413          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 414          * memory before requesting an interrupt.
 415          */
 416         ret = intel_ring_begin(ring, 32);
 417         if (ret)
 418                 return ret;
 419
 420         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 421                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
 422         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 423         intel_ring_emit(ring, seqno);
 424         intel_ring_emit(ring, 0);
 425         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 426         scratch_addr += 128; /* write to separate cachelines */
 427         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 428         scratch_addr += 128;
 429         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 430         scratch_addr += 128;
 431         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 432         scratch_addr += 128;
 433         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 434         scratch_addr += 128;
 435         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 436         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
 437                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
 438                         PIPE_CONTROL_NOTIFY);
 439         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 440         intel_ring_emit(ring, seqno);
 441         intel_ring_emit(ring, 0);
 442         intel_ring_advance(ring);
 443
 444         *result = seqno;
 445         return 0;
 446 }
 447
 448 static int
 449 render_ring_add_request(struct intel_ring_buffer *ring,
 450                         u32 *result)
 451 {
 452         struct drm_device *dev = ring->dev;
 453         u32 seqno = i915_gem_get_seqno(dev);
 454         int ret;
 455
 456         ret = intel_ring_begin(ring, 4);
 457         if (ret)
 458                 return ret;
 459
 460         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 461         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 462         intel_ring_emit(ring, seqno);
 463         intel_ring_emit(ring, MI_USER_INTERRUPT);
 464         intel_ring_advance(ring);
 465
 466         *result = seqno;
 467         return 0;
 468 }
 469
 470 static u32
 471 ring_get_seqno(struct intel_ring_buffer *ring)
 472 {
 473         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 474 }
 475
 476 static u32
 477 pc_render_get_seqno(struct intel_ring_buffer *ring)
 478 {
 479         struct pipe_control *pc = ring->private;
 480         return pc->cpu_page[0];
 481 }
 482
 483 static void
 484 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 485 {
 486         dev_priv->gt_irq_mask &= ~mask;
 487         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 488         POSTING_READ(GTIMR);
 489 }
 490
 491 static void
 492 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 493 {
 494         dev_priv->gt_irq_mask |= mask;
 495         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 496         POSTING_READ(GTIMR);
 497 }
 498
 499 static void
 500 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 501 {
 502         dev_priv->irq_mask &= ~mask;
 503         I915_WRITE(IMR, dev_priv->irq_mask);
 504         POSTING_READ(IMR);
 505 }
 506
 507 static void
 508 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 509 {
 510         dev_priv->irq_mask |= mask;
 511         I915_WRITE(IMR, dev_priv->irq_mask);
 512         POSTING_READ(IMR);
 513 }
 514
 515 static bool
 516 render_ring_get_irq(struct intel_ring_buffer *ring)
 517 {
 518         struct drm_device *dev = ring->dev;
 519         drm_i915_private_t *dev_priv = dev->dev_private;
 520
 521         if (!dev->irq_enabled)
 522                 return false;
 523
 524         spin_lock(&ring->irq_lock);
 525         if (ring->irq_refcount++ == 0) {
 526                 if (HAS_PCH_SPLIT(dev))
 527                         ironlake_enable_irq(dev_priv,
 528                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 529                 else
 530                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 531         }
 532         spin_unlock(&ring->irq_lock);
 533
 534         return true;
 535 }
 536
 537 static void
 538 render_ring_put_irq(struct intel_ring_buffer *ring)
 539 {
 540         struct drm_device *dev = ring->dev;
 541         drm_i915_private_t *dev_priv = dev->dev_private;
 542
 543         spin_lock(&ring->irq_lock);
 544         if (--ring->irq_refcount == 0) {
 545                 if (HAS_PCH_SPLIT(dev))
 546                         ironlake_disable_irq(dev_priv,
 547                                              GT_USER_INTERRUPT |
 548                                              GT_PIPE_NOTIFY);
 549                 else
 550                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 551         }
 552         spin_unlock(&ring->irq_lock);
 553 }
 554
 555 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 556 {
 557         struct drm_device *dev = ring->dev;
 558         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 559         u32 mmio = 0;
 560
 561         /* The ring status page addresses are no longer next to the rest of
 562          * the ring registers as of gen7.
 563          */
 564         if (IS_GEN7(dev)) {
 565                 switch (ring->id) {
 566                 case RING_RENDER:
 567                         mmio = RENDER_HWS_PGA_GEN7;
 568                         break;
 569                 case RING_BLT:
 570                         mmio = BLT_HWS_PGA_GEN7;
 571                         break;
 572                 case RING_BSD:
 573                         mmio = BSD_HWS_PGA_GEN7;
 574                         break;
 575                 }
 576         } else if (IS_GEN6(ring->dev)) {
 577                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 578         } else {
 579                 mmio = RING_HWS_PGA(ring->mmio_base);
 580         }
 581
 582         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 583         POSTING_READ(mmio);
 584 }
 585
 586 static int
 587 bsd_ring_flush(struct intel_ring_buffer *ring,
 588                u32     invalidate_domains,
 589                u32     flush_domains)
 590 {
 591         int ret;
 592
 593         ret = intel_ring_begin(ring, 2);
 594         if (ret)
 595                 return ret;
 596
 597         intel_ring_emit(ring, MI_FLUSH);
 598         intel_ring_emit(ring, MI_NOOP);
 599         intel_ring_advance(ring);
 600         return 0;
 601 }
 602
 603 static int
 604 ring_add_request(struct intel_ring_buffer *ring,
 605                  u32 *result)
 606 {
 607         u32 seqno;
 608         int ret;
 609
 610         ret = intel_ring_begin(ring, 4);
 611         if (ret)
 612                 return ret;
 613
 614         seqno = i915_gem_get_seqno(ring->dev);
 615
 616         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 617         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 618         intel_ring_emit(ring, seqno);
 619         intel_ring_emit(ring, MI_USER_INTERRUPT);
 620         intel_ring_advance(ring);
 621
 622         *result = seqno;
 623         return 0;
 624 }
 625
 626 static bool
 627 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 628 {
 629         struct drm_device *dev = ring->dev;
 630         drm_i915_private_t *dev_priv = dev->dev_private;
 631
 632         if (!dev->irq_enabled)
 633                return false;
 634
 635         spin_lock(&ring->irq_lock);
 636         if (ring->irq_refcount++ == 0) {
 637                 ring->irq_mask &= ~rflag;
 638                 I915_WRITE_IMR(ring, ring->irq_mask);
 639                 ironlake_enable_irq(dev_priv, gflag);
 640         }
 641         spin_unlock(&ring->irq_lock);
 642
 643         return true;
 644 }
 645
 646 static void
 647 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 648 {
 649         struct drm_device *dev = ring->dev;
 650         drm_i915_private_t *dev_priv = dev->dev_private;
 651
 652         spin_lock(&ring->irq_lock);
 653         if (--ring->irq_refcount == 0) {
 654                 ring->irq_mask |= rflag;
 655                 I915_WRITE_IMR(ring, ring->irq_mask);
 656                 ironlake_disable_irq(dev_priv, gflag);
 657         }
 658         spin_unlock(&ring->irq_lock);
 659 }
 660
 661 static bool
 662 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 663 {
 664         struct drm_device *dev = ring->dev;
 665         drm_i915_private_t *dev_priv = dev->dev_private;
 666
 667         if (!dev->irq_enabled)
 668                 return false;
 669
 670         spin_lock(&ring->irq_lock);
 671         if (ring->irq_refcount++ == 0) {
 672                 if (IS_G4X(dev))
 673                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 674                 else
 675                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 676         }
 677         spin_unlock(&ring->irq_lock);
 678
 679         return true;
 680 }
 681 static void
 682 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 683 {
 684         struct drm_device *dev = ring->dev;
 685         drm_i915_private_t *dev_priv = dev->dev_private;
 686
 687         spin_lock(&ring->irq_lock);
 688         if (--ring->irq_refcount == 0) {
 689                 if (IS_G4X(dev))
 690                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 691                 else
 692                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 693         }
 694         spin_unlock(&ring->irq_lock);
 695 }
 696
 697 static int
 698 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 699 {
 700         int ret;
 701
 702         ret = intel_ring_begin(ring, 2);
 703         if (ret)
 704                 return ret;
 705
 706         intel_ring_emit(ring,
 707                         MI_BATCH_BUFFER_START | (2 << 6) |
 708                         MI_BATCH_NON_SECURE_I965);
 709         intel_ring_emit(ring, offset);
 710         intel_ring_advance(ring);
 711
 712         return 0;
 713 }
 714
 715 static int
 716 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 717                                 u32 offset, u32 len)
 718 {
 719         struct drm_device *dev = ring->dev;
 720         int ret;
 721
 722         if (IS_I830(dev) || IS_845G(dev)) {
 723                 ret = intel_ring_begin(ring, 4);
 724                 if (ret)
 725                         return ret;
 726
 727                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 728                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 729                 intel_ring_emit(ring, offset + len - 8);
 730                 intel_ring_emit(ring, 0);
 731         } else {
 732                 ret = intel_ring_begin(ring, 2);
 733                 if (ret)
 734                         return ret;
 735
 736                 if (INTEL_INFO(dev)->gen >= 4) {
 737                         intel_ring_emit(ring,
 738                                         MI_BATCH_BUFFER_START | (2 << 6) |
 739                                         MI_BATCH_NON_SECURE_I965);
 740                         intel_ring_emit(ring, offset);
 741                 } else {
 742                         intel_ring_emit(ring,
 743                                         MI_BATCH_BUFFER_START | (2 << 6));
 744                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 745                 }
 746         }
 747         intel_ring_advance(ring);
 748
 749         return 0;
 750 }
 751
 752 static void cleanup_status_page(struct intel_ring_buffer *ring)
 753 {
 754         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 755         struct drm_i915_gem_object *obj;
 756
 757         obj = ring->status_page.obj;
 758         if (obj == NULL)
 759                 return;
 760
 761         kunmap(obj->pages[0]);
 762         i915_gem_object_unpin(obj);
 763         drm_gem_object_unreference(&obj->base);
 764         ring->status_page.obj = NULL;
 765
 766         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 767 }
 768
 769 static int init_status_page(struct intel_ring_buffer *ring)
 770 {
 771         struct drm_device *dev = ring->dev;
 772         drm_i915_private_t *dev_priv = dev->dev_private;
 773         struct drm_i915_gem_object *obj;
 774         int ret;
 775
 776         obj = i915_gem_alloc_object(dev, 4096);
 777         if (obj == NULL) {
 778                 DRM_ERROR("Failed to allocate status page\n");
 779                 ret = -ENOMEM;
 780                 goto err;
 781         }
 782         obj->cache_level = I915_CACHE_LLC;
 783
 784         ret = i915_gem_object_pin(obj, 4096, true);
 785         if (ret != 0) {
 786                 goto err_unref;
 787         }
 788
 789         ring->status_page.gfx_addr = obj->gtt_offset;
 790         ring->status_page.page_addr = kmap(obj->pages[0]);
 791         if (ring->status_page.page_addr == NULL) {
 792                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 793                 goto err_unpin;
 794         }
 795         ring->status_page.obj = obj;
 796         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 797
 798         intel_ring_setup_status_page(ring);
 799         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 800                         ring->name, ring->status_page.gfx_addr);
 801
 802         return 0;
 803
 804 err_unpin:
 805         i915_gem_object_unpin(obj);
 806 err_unref:
 807         drm_gem_object_unreference(&obj->base);
 808 err:
 809         return ret;
 810 }
 811
 812 int intel_init_ring_buffer(struct drm_device *dev,
 813                            struct intel_ring_buffer *ring)
 814 {
 815         struct drm_i915_gem_object *obj;
 816         int ret;
 817
 818         ring->dev = dev;
 819         INIT_LIST_HEAD(&ring->active_list);
 820         INIT_LIST_HEAD(&ring->request_list);
 821         INIT_LIST_HEAD(&ring->gpu_write_list);
 822
 823         init_waitqueue_head(&ring->irq_queue);
 824         spin_lock_init(&ring->irq_lock);
 825         ring->irq_mask = ~0;
 826
 827         if (I915_NEED_GFX_HWS(dev)) {
 828                 ret = init_status_page(ring);
 829                 if (ret)
 830                         return ret;
 831         }
 832
 833         obj = i915_gem_alloc_object(dev, ring->size);
 834         if (obj == NULL) {
 835                 DRM_ERROR("Failed to allocate ringbuffer\n");
 836                 ret = -ENOMEM;
 837                 goto err_hws;
 838         }
 839
 840         ring->obj = obj;
 841
 842         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
 843         if (ret)
 844                 goto err_unref;
 845
 846         ring->map.size = ring->size;
 847         ring->map.offset = dev->agp->base + obj->gtt_offset;
 848         ring->map.type = 0;
 849         ring->map.flags = 0;
 850         ring->map.mtrr = 0;
 851
 852         drm_core_ioremap_wc(&ring->map, dev);
 853         if (ring->map.handle == NULL) {
 854                 DRM_ERROR("Failed to map ringbuffer.\n");
 855                 ret = -EINVAL;
 856                 goto err_unpin;
 857         }
 858
 859         ring->virtual_start = ring->map.handle;
 860         ret = ring->init(ring);
 861         if (ret)
 862                 goto err_unmap;
 863
 864         /* Workaround an erratum on the i830 which causes a hang if
 865          * the TAIL pointer points to within the last 2 cachelines
 866          * of the buffer.
 867          */
 868         ring->effective_size = ring->size;
 869         if (IS_I830(ring->dev) || IS_845G(ring->dev))
 870                 ring->effective_size -= 128;
 871
 872         return 0;
 873
 874 err_unmap:
 875         drm_core_ioremapfree(&ring->map, dev);
 876 err_unpin:
 877         i915_gem_object_unpin(obj);
 878 err_unref:
 879         drm_gem_object_unreference(&obj->base);
 880         ring->obj = NULL;
 881 err_hws:
 882         cleanup_status_page(ring);
 883         return ret;
 884 }
 885
 886 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
 887 {
 888         struct drm_i915_private *dev_priv;
 889         int ret;
 890
 891         if (ring->obj == NULL)
 892                 return;
 893
 894         /* Disable the ring buffer. The ring must be idle at this point */
 895         dev_priv = ring->dev->dev_private;
 896         ret = intel_wait_ring_idle(ring);
 897         if (ret)
 898                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 899                           ring->name, ret);
 900
 901         I915_WRITE_CTL(ring, 0);
 902
 903         drm_core_ioremapfree(&ring->map, ring->dev);
 904
 905         i915_gem_object_unpin(ring->obj);
 906         drm_gem_object_unreference(&ring->obj->base);
 907         ring->obj = NULL;
 908
 909         if (ring->cleanup)
 910                 ring->cleanup(ring);
 911
 912         cleanup_status_page(ring);
 913 }
 914
 915 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
 916 {
 917         unsigned int *virt;
 918         int rem = ring->size - ring->tail;
 919
 920         if (ring->space < rem) {
 921                 int ret = intel_wait_ring_buffer(ring, rem);
 922                 if (ret)
 923                         return ret;
 924         }
 925
 926         virt = (unsigned int *)(ring->virtual_start + ring->tail);
 927         rem /= 8;
 928         while (rem--) {
 929                 *virt++ = MI_NOOP;
 930                 *virt++ = MI_NOOP;
 931         }
 932
 933         ring->tail = 0;
 934         ring->space = ring_space(ring);
 935
 936         return 0;
 937 }
 938
 939 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
 940 {
 941         struct drm_device *dev = ring->dev;
 942         struct drm_i915_private *dev_priv = dev->dev_private;
 943         unsigned long end;
 944         u32 head;
 945
 946         /* If the reported head position has wrapped or hasn't advanced,
 947          * fallback to the slow and accurate path.
 948          */
 949         head = intel_read_status_page(ring, 4);
 950         if (head > ring->head) {
 951                 ring->head = head;
 952                 ring->space = ring_space(ring);
 953                 if (ring->space >= n)
 954                         return 0;
 955         }
 956
 957         trace_i915_ring_wait_begin(ring);
 958         end = jiffies + 3 * HZ;
 959         do {
 960                 ring->head = I915_READ_HEAD(ring);
 961                 ring->space = ring_space(ring);
 962                 if (ring->space >= n) {
 963                         trace_i915_ring_wait_end(ring);
 964                         return 0;
 965                 }
 966
 967                 if (dev->primary->master) {
 968                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 969                         if (master_priv->sarea_priv)
 970                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 971                 }
 972
 973                 msleep(1);
 974                 if (atomic_read(&dev_priv->mm.wedged))
 975                         return -EAGAIN;
 976         } while (!time_after(jiffies, end));
 977         trace_i915_ring_wait_end(ring);
 978         return -EBUSY;
 979 }
 980
 981 int intel_ring_begin(struct intel_ring_buffer *ring,
 982                      int num_dwords)
 983 {
 984         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 985         int n = 4*num_dwords;
 986         int ret;
 987
 988         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
 989                 return -EIO;
 990
 991         if (unlikely(ring->tail + n > ring->effective_size)) {
 992                 ret = intel_wrap_ring_buffer(ring);
 993                 if (unlikely(ret))
 994                         return ret;
 995         }
 996
 997         if (unlikely(ring->space < n)) {
 998                 ret = intel_wait_ring_buffer(ring, n);
 999                 if (unlikely(ret))
1000                         return ret;
1001         }
1002
1003         ring->space -= n;
1004         return 0;
1005 }
1006
1007 void intel_ring_advance(struct intel_ring_buffer *ring)
1008 {
1009         ring->tail &= ring->size - 1;
1010         ring->write_tail(ring, ring->tail);
1011 }
1012
1013 static const struct intel_ring_buffer render_ring = {
1014         .name                   = "render ring",
1015         .id                     = RING_RENDER,
1016         .mmio_base              = RENDER_RING_BASE,
1017         .size                   = 32 * PAGE_SIZE,
1018         .init                   = init_render_ring,
1019         .write_tail             = ring_write_tail,
1020         .flush                  = render_ring_flush,
1021         .add_request            = render_ring_add_request,
1022         .get_seqno              = ring_get_seqno,
1023         .irq_get                = render_ring_get_irq,
1024         .irq_put                = render_ring_put_irq,
1025         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1026        .cleanup                 = render_ring_cleanup,
1027 };
1028
1029 /* ring buffer for bit-stream decoder */
1030
1031 static const struct intel_ring_buffer bsd_ring = {
1032         .name                   = "bsd ring",
1033         .id                     = RING_BSD,
1034         .mmio_base              = BSD_RING_BASE,
1035         .size                   = 32 * PAGE_SIZE,
1036         .init                   = init_ring_common,
1037         .write_tail             = ring_write_tail,
1038         .flush                  = bsd_ring_flush,
1039         .add_request            = ring_add_request,
1040         .get_seqno              = ring_get_seqno,
1041         .irq_get                = bsd_ring_get_irq,
1042         .irq_put                = bsd_ring_put_irq,
1043         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1044 };
1045
1046
1047 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1048                                      u32 value)
1049 {
1050        drm_i915_private_t *dev_priv = ring->dev->dev_private;
1051
1052        /* Every tail move must follow the sequence below */
1053        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1054                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1055                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1056        I915_WRITE(GEN6_BSD_RNCID, 0x0);
1057
1058        if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1059                                GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1060                        50))
1061                DRM_ERROR("timed out waiting for IDLE Indicator\n");
1062
1063        I915_WRITE_TAIL(ring, value);
1064        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1065                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1066                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1067 }
1068
1069 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1070                            u32 invalidate, u32 flush)
1071 {
1072         uint32_t cmd;
1073         int ret;
1074
1075         ret = intel_ring_begin(ring, 4);
1076         if (ret)
1077                 return ret;
1078
1079         cmd = MI_FLUSH_DW;
1080         if (invalidate & I915_GEM_GPU_DOMAINS)
1081                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1082         intel_ring_emit(ring, cmd);
1083         intel_ring_emit(ring, 0);
1084         intel_ring_emit(ring, 0);
1085         intel_ring_emit(ring, MI_NOOP);
1086         intel_ring_advance(ring);
1087         return 0;
1088 }
1089
1090 static int
1091 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1092                               u32 offset, u32 len)
1093 {
1094        int ret;
1095
1096        ret = intel_ring_begin(ring, 2);
1097        if (ret)
1098                return ret;
1099
1100        intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1101        /* bit0-7 is the length on GEN6+ */
1102        intel_ring_emit(ring, offset);
1103        intel_ring_advance(ring);
1104
1105        return 0;
1106 }
1107
1108 static bool
1109 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1110 {
1111         return gen6_ring_get_irq(ring,
1112                                  GT_USER_INTERRUPT,
1113                                  GEN6_RENDER_USER_INTERRUPT);
1114 }
1115
1116 static void
1117 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1118 {
1119         return gen6_ring_put_irq(ring,
1120                                  GT_USER_INTERRUPT,
1121                                  GEN6_RENDER_USER_INTERRUPT);
1122 }
1123
1124 static bool
1125 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1126 {
1127         return gen6_ring_get_irq(ring,
1128                                  GT_GEN6_BSD_USER_INTERRUPT,
1129                                  GEN6_BSD_USER_INTERRUPT);
1130 }
1131
1132 static void
1133 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1134 {
1135         return gen6_ring_put_irq(ring,
1136                                  GT_GEN6_BSD_USER_INTERRUPT,
1137                                  GEN6_BSD_USER_INTERRUPT);
1138 }
1139
1140 /* ring buffer for Video Codec for Gen6+ */
1141 static const struct intel_ring_buffer gen6_bsd_ring = {
1142         .name                   = "gen6 bsd ring",
1143         .id                     = RING_BSD,
1144         .mmio_base              = GEN6_BSD_RING_BASE,
1145         .size                   = 32 * PAGE_SIZE,
1146         .init                   = init_ring_common,
1147         .write_tail             = gen6_bsd_ring_write_tail,
1148         .flush                  = gen6_ring_flush,
1149         .add_request            = gen6_add_request,
1150         .get_seqno              = ring_get_seqno,
1151         .irq_get                = gen6_bsd_ring_get_irq,
1152         .irq_put                = gen6_bsd_ring_put_irq,
1153         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1154 };
1155
1156 /* Blitter support (SandyBridge+) */
1157
1158 static bool
1159 blt_ring_get_irq(struct intel_ring_buffer *ring)
1160 {
1161         return gen6_ring_get_irq(ring,
1162                                  GT_BLT_USER_INTERRUPT,
1163                                  GEN6_BLITTER_USER_INTERRUPT);
1164 }
1165
1166 static void
1167 blt_ring_put_irq(struct intel_ring_buffer *ring)
1168 {
1169         gen6_ring_put_irq(ring,
1170                           GT_BLT_USER_INTERRUPT,
1171                           GEN6_BLITTER_USER_INTERRUPT);
1172 }
1173
1174
1175 /* Workaround for some stepping of SNB,
1176  * each time when BLT engine ring tail moved,
1177  * the first command in the ring to be parsed
1178  * should be MI_BATCH_BUFFER_START
1179  */
1180 #define NEED_BLT_WORKAROUND(dev) \
1181         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1182
1183 static inline struct drm_i915_gem_object *
1184 to_blt_workaround(struct intel_ring_buffer *ring)
1185 {
1186         return ring->private;
1187 }
1188
1189 static int blt_ring_init(struct intel_ring_buffer *ring)
1190 {
1191         if (NEED_BLT_WORKAROUND(ring->dev)) {
1192                 struct drm_i915_gem_object *obj;
1193                 u32 *ptr;
1194                 int ret;
1195
1196                 obj = i915_gem_alloc_object(ring->dev, 4096);
1197                 if (obj == NULL)
1198                         return -ENOMEM;
1199
1200                 ret = i915_gem_object_pin(obj, 4096, true);
1201                 if (ret) {
1202                         drm_gem_object_unreference(&obj->base);
1203                         return ret;
1204                 }
1205
1206                 ptr = kmap(obj->pages[0]);
1207                 *ptr++ = MI_BATCH_BUFFER_END;
1208                 *ptr++ = MI_NOOP;
1209                 kunmap(obj->pages[0]);
1210
1211                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1212                 if (ret) {
1213                         i915_gem_object_unpin(obj);
1214                         drm_gem_object_unreference(&obj->base);
1215                         return ret;
1216                 }
1217
1218                 ring->private = obj;
1219         }
1220
1221         return init_ring_common(ring);
1222 }
1223
1224 static int blt_ring_begin(struct intel_ring_buffer *ring,
1225                           int num_dwords)
1226 {
1227         if (ring->private) {
1228                 int ret = intel_ring_begin(ring, num_dwords+2);
1229                 if (ret)
1230                         return ret;
1231
1232                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1233                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1234
1235                 return 0;
1236         } else
1237                 return intel_ring_begin(ring, 4);
1238 }
1239
1240 static int blt_ring_flush(struct intel_ring_buffer *ring,
1241                           u32 invalidate, u32 flush)
1242 {
1243         uint32_t cmd;
1244         int ret;
1245
1246         ret = blt_ring_begin(ring, 4);
1247         if (ret)
1248                 return ret;
1249
1250         cmd = MI_FLUSH_DW;
1251         if (invalidate & I915_GEM_DOMAIN_RENDER)
1252                 cmd |= MI_INVALIDATE_TLB;
1253         intel_ring_emit(ring, cmd);
1254         intel_ring_emit(ring, 0);
1255         intel_ring_emit(ring, 0);
1256         intel_ring_emit(ring, MI_NOOP);
1257         intel_ring_advance(ring);
1258         return 0;
1259 }
1260
1261 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1262 {
1263         if (!ring->private)
1264                 return;
1265
1266         i915_gem_object_unpin(ring->private);
1267         drm_gem_object_unreference(ring->private);
1268         ring->private = NULL;
1269 }
1270
1271 static const struct intel_ring_buffer gen6_blt_ring = {
1272        .name                    = "blt ring",
1273        .id                      = RING_BLT,
1274        .mmio_base               = BLT_RING_BASE,
1275        .size                    = 32 * PAGE_SIZE,
1276        .init                    = blt_ring_init,
1277        .write_tail              = ring_write_tail,
1278        .flush                   = blt_ring_flush,
1279        .add_request             = gen6_add_request,
1280        .get_seqno               = ring_get_seqno,
1281        .irq_get                 = blt_ring_get_irq,
1282        .irq_put                 = blt_ring_put_irq,
1283        .dispatch_execbuffer     = gen6_ring_dispatch_execbuffer,
1284        .cleanup                 = blt_ring_cleanup,
1285 };
1286
1287 int intel_init_render_ring_buffer(struct drm_device *dev)
1288 {
1289         drm_i915_private_t *dev_priv = dev->dev_private;
1290         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1291
1292         *ring = render_ring;
1293         if (INTEL_INFO(dev)->gen >= 6) {
1294                 ring->add_request = gen6_add_request;
1295                 ring->irq_get = gen6_render_ring_get_irq;
1296                 ring->irq_put = gen6_render_ring_put_irq;
1297         } else if (IS_GEN5(dev)) {
1298                 ring->add_request = pc_render_add_request;
1299                 ring->get_seqno = pc_render_get_seqno;
1300         }
1301
1302         if (!I915_NEED_GFX_HWS(dev)) {
1303                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1304                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1305         }
1306
1307         return intel_init_ring_buffer(dev, ring);
1308 }
1309
1310 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1311 {
1312         drm_i915_private_t *dev_priv = dev->dev_private;
1313         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1314
1315         *ring = render_ring;
1316         if (INTEL_INFO(dev)->gen >= 6) {
1317                 ring->add_request = gen6_add_request;
1318                 ring->irq_get = gen6_render_ring_get_irq;
1319                 ring->irq_put = gen6_render_ring_put_irq;
1320         } else if (IS_GEN5(dev)) {
1321                 ring->add_request = pc_render_add_request;
1322                 ring->get_seqno = pc_render_get_seqno;
1323         }
1324
1325         if (!I915_NEED_GFX_HWS(dev))
1326                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1327
1328         ring->dev = dev;
1329         INIT_LIST_HEAD(&ring->active_list);
1330         INIT_LIST_HEAD(&ring->request_list);
1331         INIT_LIST_HEAD(&ring->gpu_write_list);
1332
1333         ring->size = size;
1334         ring->effective_size = ring->size;
1335         if (IS_I830(ring->dev))
1336                 ring->effective_size -= 128;
1337
1338         ring->map.offset = start;
1339         ring->map.size = size;
1340         ring->map.type = 0;
1341         ring->map.flags = 0;
1342         ring->map.mtrr = 0;
1343
1344         drm_core_ioremap_wc(&ring->map, dev);
1345         if (ring->map.handle == NULL) {
1346                 DRM_ERROR("can not ioremap virtual address for"
1347                           " ring buffer\n");
1348                 return -ENOMEM;
1349         }
1350
1351         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1352         return 0;
1353 }
1354
1355 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1356 {
1357         drm_i915_private_t *dev_priv = dev->dev_private;
1358         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1359
1360         if (IS_GEN6(dev) || IS_GEN7(dev))
1361                 *ring = gen6_bsd_ring;
1362         else
1363                 *ring = bsd_ring;
1364
1365         return intel_init_ring_buffer(dev, ring);
1366 }
1367
1368 int intel_init_blt_ring_buffer(struct drm_device *dev)
1369 {
1370         drm_i915_private_t *dev_priv = dev->dev_private;
1371         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1372
1373         *ring = gen6_blt_ring;
1374
1375         return intel_init_ring_buffer(dev, ring);
1376 }