2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define RING_EXECLIST_QFULL (1 << 0x2)
142 #define RING_EXECLIST1_VALID (1 << 0x3)
143 #define RING_EXECLIST0_VALID (1 << 0x4)
144 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
145 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
146 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
148 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
149 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
150 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
151 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
152 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
153 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
155 #define GEN8_CTX_STATUS_COMPLETED_MASK \
156 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
157 GEN8_CTX_STATUS_PREEMPTED | \
158 GEN8_CTX_STATUS_ELEMENT_SWITCH)
160 #define CTX_LRI_HEADER_0 0x01
161 #define CTX_CONTEXT_CONTROL 0x02
162 #define CTX_RING_HEAD 0x04
163 #define CTX_RING_TAIL 0x06
164 #define CTX_RING_BUFFER_START 0x08
165 #define CTX_RING_BUFFER_CONTROL 0x0a
166 #define CTX_BB_HEAD_U 0x0c
167 #define CTX_BB_HEAD_L 0x0e
168 #define CTX_BB_STATE 0x10
169 #define CTX_SECOND_BB_HEAD_U 0x12
170 #define CTX_SECOND_BB_HEAD_L 0x14
171 #define CTX_SECOND_BB_STATE 0x16
172 #define CTX_BB_PER_CTX_PTR 0x18
173 #define CTX_RCS_INDIRECT_CTX 0x1a
174 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
175 #define CTX_LRI_HEADER_1 0x21
176 #define CTX_CTX_TIMESTAMP 0x22
177 #define CTX_PDP3_UDW 0x24
178 #define CTX_PDP3_LDW 0x26
179 #define CTX_PDP2_UDW 0x28
180 #define CTX_PDP2_LDW 0x2a
181 #define CTX_PDP1_UDW 0x2c
182 #define CTX_PDP1_LDW 0x2e
183 #define CTX_PDP0_UDW 0x30
184 #define CTX_PDP0_LDW 0x32
185 #define CTX_LRI_HEADER_2 0x41
186 #define CTX_R_PWR_CLK_STATE 0x42
187 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
189 #define CTX_REG(reg_state, pos, reg, val) do { \
190 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
191 (reg_state)[(pos)+1] = (val); \
194 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
195 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
200 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
201 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
202 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
206 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
207 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19
209 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
210 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
212 #define WA_TAIL_DWORDS 2
214 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
215 struct intel_engine_cs *engine);
216 static void execlists_init_reg_state(u32 *reg_state,
217 struct i915_gem_context *ctx,
218 struct intel_engine_cs *engine,
219 struct intel_ring *ring);
222 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
223 * @dev_priv: i915 device private
224 * @enable_execlists: value of i915.enable_execlists module parameter.
226 * Only certain platforms support Execlists (the prerequisites being
227 * support for Logical Ring Contexts and Aliasing PPGTT or better).
229 * Return: 1 if Execlists is supported and has to be enabled.
231 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
233 /* On platforms with execlist available, vGPU will only
234 * support execlist mode, no ring buffer mode.
236 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
239 if (INTEL_GEN(dev_priv) >= 9)
242 if (enable_execlists == 0)
245 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
246 USES_PPGTT(dev_priv) &&
247 i915.use_mmio_flip >= 0)
254 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
255 * descriptor for a pinned context
256 * @ctx: Context to work on
257 * @engine: Engine the descriptor will be used with
259 * The context descriptor encodes various attributes of a context,
260 * including its GTT address and some flags. Because it's fairly
261 * expensive to calculate, we'll just do it once and cache the result,
262 * which remains valid until the context is unpinned.
264 * This is what a descriptor looks like, from LSB to MSB::
266 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
267 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
268 * bits 32-52: ctx ID, a globally unique tag
269 * bits 53-54: mbz, reserved for use by hardware
270 * bits 55-63: group ID, currently unused and set to 0
273 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
274 struct intel_engine_cs *engine)
276 struct intel_context *ce = &ctx->engine[engine->id];
279 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
281 desc = ctx->desc_template; /* bits 0-11 */
282 desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
284 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
289 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
290 struct intel_engine_cs *engine)
292 return ctx->engine[engine->id].lrc_desc;
296 execlists_context_status_change(struct drm_i915_gem_request *rq,
297 unsigned long status)
300 * Only used when GVT-g is enabled now. When GVT-g is disabled,
301 * The compiler should eliminate this function as dead-code.
303 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
306 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
311 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
313 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
314 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
315 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
316 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
319 static u64 execlists_update_context(struct drm_i915_gem_request *rq)
321 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
322 struct i915_hw_ppgtt *ppgtt =
323 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
324 u32 *reg_state = ce->lrc_reg_state;
326 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
329 * True 32b PPGTT with dynamic page allocation: update PDP
330 * registers and point the unallocated PDPs to scratch page.
331 * PML4 is allocated during ppgtt init, so this is not needed
334 if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
335 execlists_update_context_pdps(ppgtt, reg_state);
338 * Make sure the context image is complete before we submit it to HW.
340 * Ostensibly, writes (including the WCB) should be flushed prior to
341 * an uncached write such as our mmio register access, the empirical
342 * evidence (esp. on Braswell) suggests that the WC write into memory
343 * may not be visible to the HW prior to the completion of the UC
344 * register write and that we may begin execution from the context
345 * before its image is complete leading to invalid PD chasing.
347 * Furthermore, Braswell, at least, wants a full mb to be sure that
348 * the writes are coherent in memory (visible to the GPU) prior to
349 * execution, and not just visible to other CPUs (as is the result of
356 static void execlists_submit_ports(struct intel_engine_cs *engine)
358 struct execlist_port *port = engine->execlist_port;
360 engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
363 for (n = ARRAY_SIZE(engine->execlist_port); n--; ) {
364 struct drm_i915_gem_request *rq;
368 rq = port_unpack(&port[n], &count);
370 GEM_BUG_ON(count > !n);
372 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
373 port_set(&port[n], port_pack(rq, count));
374 desc = execlists_update_context(rq);
375 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
381 writel(upper_32_bits(desc), elsp);
382 writel(lower_32_bits(desc), elsp);
386 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
388 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
389 i915_gem_context_force_single_submission(ctx));
392 static bool can_merge_ctx(const struct i915_gem_context *prev,
393 const struct i915_gem_context *next)
398 if (ctx_single_port_submission(prev))
404 static void port_assign(struct execlist_port *port,
405 struct drm_i915_gem_request *rq)
407 GEM_BUG_ON(rq == port_request(port));
409 if (port_isset(port))
410 i915_gem_request_put(port_request(port));
412 port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
415 static void execlists_dequeue(struct intel_engine_cs *engine)
417 struct drm_i915_gem_request *last;
418 struct execlist_port *port = engine->execlist_port;
422 last = port_request(port);
424 /* WaIdleLiteRestore:bdw,skl
425 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
426 * as we resubmit the request. See gen8_emit_breadcrumb()
427 * for where we prepare the padding after the end of the
430 last->tail = last->wa_tail;
432 GEM_BUG_ON(port_isset(&port[1]));
434 /* Hardware submission is through 2 ports. Conceptually each port
435 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
436 * static for a context, and unique to each, so we only execute
437 * requests belonging to a single context from each ring. RING_HEAD
438 * is maintained by the CS in the context image, it marks the place
439 * where it got up to last time, and through RING_TAIL we tell the CS
440 * where we want to execute up to this time.
442 * In this list the requests are in order of execution. Consecutive
443 * requests from the same context are adjacent in the ringbuffer. We
444 * can combine these requests into a single RING_TAIL update:
446 * RING_HEAD...req1...req2
448 * since to execute req2 the CS must first execute req1.
450 * Our goal then is to point each port to the end of a consecutive
451 * sequence of requests as being the most optimal (fewest wake ups
452 * and context switches) submission.
455 spin_lock_irq(&engine->timeline->lock);
456 rb = engine->execlist_first;
457 GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb);
459 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
460 struct drm_i915_gem_request *rq, *rn;
462 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
464 * Can we combine this request with the current port?
465 * It has to be the same context/ringbuffer and not
466 * have any exceptions (e.g. GVT saying never to
469 * If we can combine the requests, we can execute both
470 * by updating the RING_TAIL to point to the end of the
471 * second request, and so we never need to tell the
472 * hardware about the first.
474 if (last && !can_merge_ctx(rq->ctx, last->ctx)) {
476 * If we are on the second port and cannot
477 * combine this request with the last, then we
480 if (port != engine->execlist_port) {
481 __list_del_many(&p->requests,
487 * If GVT overrides us we only ever submit
488 * port[0], leaving port[1] empty. Note that we
489 * also have to be careful that we don't queue
490 * the same context (even though a different
491 * request) to the second port.
493 if (ctx_single_port_submission(last->ctx) ||
494 ctx_single_port_submission(rq->ctx)) {
495 __list_del_many(&p->requests,
500 GEM_BUG_ON(last->ctx == rq->ctx);
503 port_assign(port, last);
507 INIT_LIST_HEAD(&rq->priotree.link);
508 rq->priotree.priority = INT_MAX;
510 __i915_gem_request_submit(rq);
511 trace_i915_gem_request_in(rq, port_index(port, engine));
517 rb_erase(&p->node, &engine->execlist_queue);
518 INIT_LIST_HEAD(&p->requests);
519 if (p->priority != I915_PRIORITY_NORMAL)
520 kmem_cache_free(engine->i915->priorities, p);
523 engine->execlist_first = rb;
525 port_assign(port, last);
526 spin_unlock_irq(&engine->timeline->lock);
529 execlists_submit_ports(engine);
532 static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
534 const struct execlist_port *port = engine->execlist_port;
536 return port_count(&port[0]) + port_count(&port[1]) < 2;
540 * Check the unread Context Status Buffers and manage the submission of new
541 * contexts to the ELSP accordingly.
543 static void intel_lrc_irq_handler(unsigned long data)
545 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
546 struct execlist_port *port = engine->execlist_port;
547 struct drm_i915_private *dev_priv = engine->i915;
549 /* We can skip acquiring intel_runtime_pm_get() here as it was taken
550 * on our behalf by the request (see i915_gem_mark_busy()) and it will
551 * not be relinquished until the device is idle (see
552 * i915_gem_idle_work_handler()). As a precaution, we make sure
553 * that all ELSP are drained i.e. we have processed the CSB,
554 * before allowing ourselves to idle and calling intel_runtime_pm_put().
556 GEM_BUG_ON(!dev_priv->gt.awake);
558 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
560 /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
561 * imposing the cost of a locked atomic transaction when submitting a
562 * new request (outside of the context-switch interrupt).
564 while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
565 u32 __iomem *csb_mmio =
566 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
568 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
569 unsigned int head, tail;
571 /* The write will be ordered by the uncached read (itself
572 * a memory barrier), so we do not need another in the form
573 * of a locked instruction. The race between the interrupt
574 * handler and the split test/clear is harmless as we order
575 * our clear before the CSB read. If the interrupt arrived
576 * first between the test and the clear, we read the updated
577 * CSB and clear the bit. If the interrupt arrives as we read
578 * the CSB or later (i.e. after we had cleared the bit) the bit
579 * is set and we do a new loop.
581 __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
582 head = readl(csb_mmio);
583 tail = GEN8_CSB_WRITE_PTR(head);
584 head = GEN8_CSB_READ_PTR(head);
585 while (head != tail) {
586 struct drm_i915_gem_request *rq;
590 if (++head == GEN8_CSB_ENTRIES)
593 /* We are flying near dragons again.
595 * We hold a reference to the request in execlist_port[]
596 * but no more than that. We are operating in softirq
597 * context and so cannot hold any mutex or sleep. That
598 * prevents us stopping the requests we are processing
599 * in port[] from being retired simultaneously (the
600 * breadcrumb will be complete before we see the
601 * context-switch). As we only hold the reference to the
602 * request, any pointer chasing underneath the request
603 * is subject to a potential use-after-free. Thus we
604 * store all of the bookkeeping within port[] as
605 * required, and avoid using unguarded pointers beneath
606 * request itself. The same applies to the atomic
610 status = readl(buf + 2 * head);
611 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
614 /* Check the context/desc id for this event matches */
615 GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) !=
618 rq = port_unpack(port, &count);
619 GEM_BUG_ON(count == 0);
621 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
622 GEM_BUG_ON(!i915_gem_request_completed(rq));
623 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
625 trace_i915_gem_request_out(rq);
626 i915_gem_request_put(rq);
629 memset(&port[1], 0, sizeof(port[1]));
631 port_set(port, port_pack(rq, count));
634 /* After the final element, the hw should be idle */
635 GEM_BUG_ON(port_count(port) == 0 &&
636 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
639 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
643 if (execlists_elsp_ready(engine))
644 execlists_dequeue(engine);
646 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
650 insert_request(struct intel_engine_cs *engine,
651 struct i915_priotree *pt,
654 struct i915_priolist *p;
655 struct rb_node **parent, *rb;
658 if (unlikely(engine->no_priolist))
659 prio = I915_PRIORITY_NORMAL;
662 /* most positive priority is scheduled first, equal priorities fifo */
664 parent = &engine->execlist_queue.rb_node;
667 p = rb_entry(rb, typeof(*p), node);
668 if (prio > p->priority) {
669 parent = &rb->rb_left;
670 } else if (prio < p->priority) {
671 parent = &rb->rb_right;
674 list_add_tail(&pt->link, &p->requests);
679 if (prio == I915_PRIORITY_NORMAL) {
680 p = &engine->default_priolist;
682 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
683 /* Convert an allocation failure to a priority bump */
685 prio = I915_PRIORITY_NORMAL; /* recurses just once */
687 /* To maintain ordering with all rendering, after an
688 * allocation failure we have to disable all scheduling.
689 * Requests will then be executed in fifo, and schedule
690 * will ensure that dependencies are emitted in fifo.
691 * There will be still some reordering with existing
692 * requests, so if userspace lied about their
693 * dependencies that reordering may be visible.
695 engine->no_priolist = true;
701 rb_link_node(&p->node, rb, parent);
702 rb_insert_color(&p->node, &engine->execlist_queue);
704 INIT_LIST_HEAD(&p->requests);
705 list_add_tail(&pt->link, &p->requests);
708 engine->execlist_first = &p->node;
713 static void execlists_submit_request(struct drm_i915_gem_request *request)
715 struct intel_engine_cs *engine = request->engine;
718 /* Will be called from irq-context when using foreign fences. */
719 spin_lock_irqsave(&engine->timeline->lock, flags);
721 if (insert_request(engine,
723 request->priotree.priority)) {
724 if (execlists_elsp_ready(engine))
725 tasklet_hi_schedule(&engine->irq_tasklet);
728 GEM_BUG_ON(!engine->execlist_first);
729 GEM_BUG_ON(list_empty(&request->priotree.link));
731 spin_unlock_irqrestore(&engine->timeline->lock, flags);
734 static struct intel_engine_cs *
735 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
737 struct intel_engine_cs *engine =
738 container_of(pt, struct drm_i915_gem_request, priotree)->engine;
742 if (engine != locked) {
743 spin_unlock(&locked->timeline->lock);
744 spin_lock(&engine->timeline->lock);
750 static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
752 struct intel_engine_cs *engine;
753 struct i915_dependency *dep, *p;
754 struct i915_dependency stack;
757 if (prio <= READ_ONCE(request->priotree.priority))
760 /* Need BKL in order to use the temporary link inside i915_dependency */
761 lockdep_assert_held(&request->i915->drm.struct_mutex);
763 stack.signaler = &request->priotree;
764 list_add(&stack.dfs_link, &dfs);
766 /* Recursively bump all dependent priorities to match the new request.
768 * A naive approach would be to use recursion:
769 * static void update_priorities(struct i915_priotree *pt, prio) {
770 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
771 * update_priorities(dep->signal, prio)
772 * insert_request(pt);
774 * but that may have unlimited recursion depth and so runs a very
775 * real risk of overunning the kernel stack. Instead, we build
776 * a flat list of all dependencies starting with the current request.
777 * As we walk the list of dependencies, we add all of its dependencies
778 * to the end of the list (this may include an already visited
779 * request) and continue to walk onwards onto the new dependencies. The
780 * end result is a topological list of requests in reverse order, the
781 * last element in the list is the request we must execute first.
783 list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
784 struct i915_priotree *pt = dep->signaler;
786 /* Within an engine, there can be no cycle, but we may
787 * refer to the same dependency chain multiple times
788 * (redundant dependencies are not eliminated) and across
791 list_for_each_entry(p, &pt->signalers_list, signal_link) {
792 GEM_BUG_ON(p->signaler->priority < pt->priority);
793 if (prio > READ_ONCE(p->signaler->priority))
794 list_move_tail(&p->dfs_link, &dfs);
797 list_safe_reset_next(dep, p, dfs_link);
800 /* If we didn't need to bump any existing priorities, and we haven't
801 * yet submitted this request (i.e. there is no potential race with
802 * execlists_submit_request()), we can set our own priority and skip
803 * acquiring the engine locks.
805 if (request->priotree.priority == INT_MIN) {
806 GEM_BUG_ON(!list_empty(&request->priotree.link));
807 request->priotree.priority = prio;
808 if (stack.dfs_link.next == stack.dfs_link.prev)
810 __list_del_entry(&stack.dfs_link);
813 engine = request->engine;
814 spin_lock_irq(&engine->timeline->lock);
816 /* Fifo and depth-first replacement ensure our deps execute before us */
817 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
818 struct i915_priotree *pt = dep->signaler;
820 INIT_LIST_HEAD(&dep->dfs_link);
822 engine = pt_lock_engine(pt, engine);
824 if (prio <= pt->priority)
828 if (!list_empty(&pt->link)) {
829 __list_del_entry(&pt->link);
830 insert_request(engine, pt, prio);
834 spin_unlock_irq(&engine->timeline->lock);
836 /* XXX Do we need to preempt to make room for us and our deps? */
839 static struct intel_ring *
840 execlists_context_pin(struct intel_engine_cs *engine,
841 struct i915_gem_context *ctx)
843 struct intel_context *ce = &ctx->engine[engine->id];
848 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
850 if (likely(ce->pin_count++))
852 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
855 ret = execlists_context_deferred_alloc(ctx, engine);
859 GEM_BUG_ON(!ce->state);
861 flags = PIN_GLOBAL | PIN_HIGH;
862 if (ctx->ggtt_offset_bias)
863 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
865 ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
869 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
871 ret = PTR_ERR(vaddr);
875 ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
879 intel_lr_context_descriptor_update(ctx, engine);
881 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
882 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
883 i915_ggtt_offset(ce->ring->vma);
885 ce->state->obj->mm.dirty = true;
887 i915_gem_context_get(ctx);
892 i915_gem_object_unpin_map(ce->state->obj);
894 __i915_vma_unpin(ce->state);
900 static void execlists_context_unpin(struct intel_engine_cs *engine,
901 struct i915_gem_context *ctx)
903 struct intel_context *ce = &ctx->engine[engine->id];
905 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
906 GEM_BUG_ON(ce->pin_count == 0);
911 intel_ring_unpin(ce->ring);
913 i915_gem_object_unpin_map(ce->state->obj);
914 i915_vma_unpin(ce->state);
916 i915_gem_context_put(ctx);
919 static int execlists_request_alloc(struct drm_i915_gem_request *request)
921 struct intel_engine_cs *engine = request->engine;
922 struct intel_context *ce = &request->ctx->engine[engine->id];
926 GEM_BUG_ON(!ce->pin_count);
928 /* Flush enough space to reduce the likelihood of waiting after
929 * we start building the request - in which case we will just
930 * have to repeat work.
932 request->reserved_space += EXECLISTS_REQUEST_SIZE;
934 if (i915.enable_guc_submission) {
936 * Check that the GuC has space for the request before
937 * going any further, as the i915_add_request() call
938 * later on mustn't fail ...
940 ret = i915_guc_wq_reserve(request);
945 cs = intel_ring_begin(request, 0);
951 if (!ce->initialised) {
952 ret = engine->init_context(request);
956 ce->initialised = true;
959 /* Note that after this point, we have committed to using
960 * this request as it is being used to both track the
961 * state of engine initialisation and liveness of the
962 * golden renderstate above. Think twice before you try
963 * to cancel/unwind this request now.
966 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
970 if (i915.enable_guc_submission)
971 i915_guc_wq_unreserve(request);
977 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
978 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
979 * but there is a slight complication as this is applied in WA batch where the
980 * values are only initialized once so we cannot take register value at the
981 * beginning and reuse it further; hence we save its value to memory, upload a
982 * constant value with bit21 set and then we restore it back with the saved value.
983 * To simplify the WA, a constant value is formed by using the default value
984 * of this register. This shouldn't be a problem because we are only modifying
985 * it for a short period and this batch in non-premptible. We can ofcourse
986 * use additional instructions that read the actual value of the register
987 * at that time and set our bit of interest but it makes the WA complicated.
989 * This WA is also required for Gen9 so extracting as a function avoids
993 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
995 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
996 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
997 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1000 *batch++ = MI_LOAD_REGISTER_IMM(1);
1001 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1002 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1004 batch = gen8_emit_pipe_control(batch,
1005 PIPE_CONTROL_CS_STALL |
1006 PIPE_CONTROL_DC_FLUSH_ENABLE,
1009 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1010 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1011 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1018 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1019 * initialized at the beginning and shared across all contexts but this field
1020 * helps us to have multiple batches at different offsets and select them based
1021 * on a criteria. At the moment this batch always start at the beginning of the page
1022 * and at this point we don't have multiple wa_ctx batch buffers.
1024 * The number of WA applied are not known at the beginning; we use this field
1025 * to return the no of DWORDS written.
1027 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1028 * so it adds NOOPs as padding to make it cacheline aligned.
1029 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1030 * makes a complete batch buffer.
1032 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1034 /* WaDisableCtxRestoreArbitration:bdw,chv */
1035 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1037 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1038 if (IS_BROADWELL(engine->i915))
1039 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1041 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1042 /* Actual scratch location is at 128 bytes offset */
1043 batch = gen8_emit_pipe_control(batch,
1044 PIPE_CONTROL_FLUSH_L3 |
1045 PIPE_CONTROL_GLOBAL_GTT_IVB |
1046 PIPE_CONTROL_CS_STALL |
1047 PIPE_CONTROL_QW_WRITE,
1048 i915_ggtt_offset(engine->scratch) +
1049 2 * CACHELINE_BYTES);
1051 /* Pad to end of cacheline */
1052 while ((unsigned long)batch % CACHELINE_BYTES)
1056 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1057 * execution depends on the length specified in terms of cache lines
1058 * in the register CTX_RCS_INDIRECT_CTX
1065 * This batch is started immediately after indirect_ctx batch. Since we ensure
1066 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1068 * The number of DWORDS written are returned using this field.
1070 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1071 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1073 static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
1075 /* WaDisableCtxRestoreArbitration:bdw,chv */
1076 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1077 *batch++ = MI_BATCH_BUFFER_END;
1082 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1084 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1085 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1087 *batch++ = MI_LOAD_REGISTER_IMM(3);
1089 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1090 *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
1091 *batch++ = _MASKED_BIT_DISABLE(
1092 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
1095 *batch++ = i915_mmio_reg_offset(FF_SLICE_CHICKEN);
1096 *batch++ = _MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX);
1099 *batch++ = i915_mmio_reg_offset(_3D_CHICKEN3);
1100 *batch++ = _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX);
1104 /* WaClearSlmSpaceAtContextSwitch:kbl */
1105 /* Actual scratch location is at 128 bytes offset */
1106 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1107 batch = gen8_emit_pipe_control(batch,
1108 PIPE_CONTROL_FLUSH_L3 |
1109 PIPE_CONTROL_GLOBAL_GTT_IVB |
1110 PIPE_CONTROL_CS_STALL |
1111 PIPE_CONTROL_QW_WRITE,
1112 i915_ggtt_offset(engine->scratch)
1113 + 2 * CACHELINE_BYTES);
1116 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1117 if (HAS_POOLED_EU(engine->i915)) {
1119 * EU pool configuration is setup along with golden context
1120 * during context initialization. This value depends on
1121 * device type (2x6 or 3x6) and needs to be updated based
1122 * on which subslice is disabled especially for 2x6
1123 * devices, however it is safe to load default
1124 * configuration of 3x6 device instead of masking off
1125 * corresponding bits because HW ignores bits of a disabled
1126 * subslice and drops down to appropriate config. Please
1127 * see render_state_setup() in i915_gem_render_state.c for
1128 * possible configurations, to avoid duplication they are
1129 * not shown here again.
1131 *batch++ = GEN9_MEDIA_POOL_STATE;
1132 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1133 *batch++ = 0x00777000;
1139 /* Pad to end of cacheline */
1140 while ((unsigned long)batch % CACHELINE_BYTES)
1146 static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
1148 *batch++ = MI_BATCH_BUFFER_END;
1153 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1155 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1157 struct drm_i915_gem_object *obj;
1158 struct i915_vma *vma;
1161 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1163 return PTR_ERR(obj);
1165 vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
1171 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1175 engine->wa_ctx.vma = vma;
1179 i915_gem_object_put(obj);
1183 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1185 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1188 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1190 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1192 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1193 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1195 wa_bb_func_t wa_bb_fn[2];
1197 void *batch, *batch_ptr;
1201 if (WARN_ON(engine->id != RCS || !engine->scratch))
1204 switch (INTEL_GEN(engine->i915)) {
1206 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1207 wa_bb_fn[1] = gen9_init_perctx_bb;
1210 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1211 wa_bb_fn[1] = gen8_init_perctx_bb;
1214 MISSING_CASE(INTEL_GEN(engine->i915));
1218 ret = lrc_setup_wa_ctx(engine);
1220 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1224 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1225 batch = batch_ptr = kmap_atomic(page);
1228 * Emit the two workaround batch buffers, recording the offset from the
1229 * start of the workaround batch buffer object for each and their
1232 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1233 wa_bb[i]->offset = batch_ptr - batch;
1234 if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) {
1238 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1239 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1242 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1244 kunmap_atomic(batch);
1246 lrc_destroy_wa_ctx(engine);
1251 static u8 gtiir[] = {
1259 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1261 struct drm_i915_private *dev_priv = engine->i915;
1262 struct execlist_port *port = engine->execlist_port;
1267 ret = intel_mocs_init_engine(engine);
1271 intel_engine_reset_breadcrumbs(engine);
1272 intel_engine_init_hangcheck(engine);
1274 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1275 I915_WRITE(RING_MODE_GEN7(engine),
1276 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1277 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1278 engine->status_page.ggtt_offset);
1279 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1281 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1283 GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
1286 * Clear any pending interrupt state.
1288 * We do it twice out of paranoia that some of the IIR are double
1289 * buffered, and if we only reset it once there may still be
1290 * an interrupt pending.
1292 I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1293 GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
1294 I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1295 GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
1296 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1298 /* After a GPU reset, we may have requests to replay */
1300 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
1301 if (!port_isset(&port[n]))
1304 DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n",
1306 port_request(&port[n])->global_seqno);
1308 /* Discard the current inflight count */
1309 port_set(&port[n], port_request(&port[n]));
1313 if (submit && !i915.enable_guc_submission)
1314 execlists_submit_ports(engine);
1319 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1321 struct drm_i915_private *dev_priv = engine->i915;
1324 ret = gen8_init_common_ring(engine);
1328 /* We need to disable the AsyncFlip performance optimisations in order
1329 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1330 * programmed to '1' on all products.
1332 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1334 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1336 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1338 return init_workarounds_ring(engine);
1341 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1345 ret = gen8_init_common_ring(engine);
1349 return init_workarounds_ring(engine);
1352 static void reset_common_ring(struct intel_engine_cs *engine,
1353 struct drm_i915_gem_request *request)
1355 struct execlist_port *port = engine->execlist_port;
1356 struct intel_context *ce;
1360 * Catch up with any missed context-switch interrupts.
1362 * Ideally we would just read the remaining CSB entries now that we
1363 * know the gpu is idle. However, the CSB registers are sometimes^W
1364 * often trashed across a GPU reset! Instead we have to rely on
1365 * guessing the missed context-switch events by looking at what
1366 * requests were completed.
1369 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
1370 i915_gem_request_put(port_request(&port[n]));
1371 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
1375 if (request->ctx != port_request(port)->ctx) {
1376 i915_gem_request_put(port_request(port));
1378 memset(&port[1], 0, sizeof(port[1]));
1381 GEM_BUG_ON(request->ctx != port_request(port)->ctx);
1383 /* If the request was innocent, we leave the request in the ELSP
1384 * and will try to replay it on restarting. The context image may
1385 * have been corrupted by the reset, in which case we may have
1386 * to service a new GPU hang, but more likely we can continue on
1389 * If the request was guilty, we presume the context is corrupt
1390 * and have to at least restore the RING register in the context
1391 * image back to the expected values to skip over the guilty request.
1393 if (request->fence.error != -EIO)
1396 /* We want a simple context + ring to execute the breadcrumb update.
1397 * We cannot rely on the context being intact across the GPU hang,
1398 * so clear it and rebuild just what we need for the breadcrumb.
1399 * All pending requests for this context will be zapped, and any
1400 * future request will be after userspace has had the opportunity
1401 * to recreate its own state.
1403 ce = &request->ctx->engine[engine->id];
1404 execlists_init_reg_state(ce->lrc_reg_state,
1405 request->ctx, engine, ce->ring);
1407 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1408 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1409 i915_ggtt_offset(ce->ring->vma);
1410 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1412 request->ring->head = request->postfix;
1413 intel_ring_update_space(request->ring);
1415 /* Reset WaIdleLiteRestore:bdw,skl as well */
1417 intel_ring_wrap(request->ring,
1418 request->wa_tail - WA_TAIL_DWORDS*sizeof(u32));
1419 assert_ring_tail_valid(request->ring, request->tail);
1422 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1424 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1425 struct intel_engine_cs *engine = req->engine;
1426 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
1430 cs = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1434 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1435 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
1436 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1438 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1439 *cs++ = upper_32_bits(pd_daddr);
1440 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1441 *cs++ = lower_32_bits(pd_daddr);
1445 intel_ring_advance(req, cs);
1450 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1451 u64 offset, u32 len,
1452 const unsigned int flags)
1457 /* Don't rely in hw updating PDPs, specially in lite-restore.
1458 * Ideally, we should set Force PD Restore in ctx descriptor,
1459 * but we can't. Force Restore would be a second option, but
1460 * it is unsafe in case of lite-restore (because the ctx is
1461 * not idle). PML4 is allocated during ppgtt init so this is
1462 * not needed in 48-bit.*/
1463 if (req->ctx->ppgtt &&
1464 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) &&
1465 !i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
1466 !intel_vgpu_active(req->i915)) {
1467 ret = intel_logical_ring_emit_pdps(req);
1471 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1474 cs = intel_ring_begin(req, 4);
1478 /* FIXME(BDW): Address space and security selectors. */
1479 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
1480 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
1481 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
1482 *cs++ = lower_32_bits(offset);
1483 *cs++ = upper_32_bits(offset);
1485 intel_ring_advance(req, cs);
1490 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1492 struct drm_i915_private *dev_priv = engine->i915;
1493 I915_WRITE_IMR(engine,
1494 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1495 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1498 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1500 struct drm_i915_private *dev_priv = engine->i915;
1501 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1504 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1508 cs = intel_ring_begin(request, 4);
1512 cmd = MI_FLUSH_DW + 1;
1514 /* We always require a command barrier so that subsequent
1515 * commands, such as breadcrumb interrupts, are strictly ordered
1516 * wrt the contents of the write cache being flushed to memory
1517 * (and thus being coherent from the CPU).
1519 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1521 if (mode & EMIT_INVALIDATE) {
1522 cmd |= MI_INVALIDATE_TLB;
1523 if (request->engine->id == VCS)
1524 cmd |= MI_INVALIDATE_BSD;
1528 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1529 *cs++ = 0; /* upper addr */
1530 *cs++ = 0; /* value */
1531 intel_ring_advance(request, cs);
1536 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1539 struct intel_engine_cs *engine = request->engine;
1541 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1542 bool vf_flush_wa = false, dc_flush_wa = false;
1546 flags |= PIPE_CONTROL_CS_STALL;
1548 if (mode & EMIT_FLUSH) {
1549 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1550 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1551 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1552 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1555 if (mode & EMIT_INVALIDATE) {
1556 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1557 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1558 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1559 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1560 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1561 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1562 flags |= PIPE_CONTROL_QW_WRITE;
1563 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1566 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1569 if (IS_GEN9(request->i915))
1572 /* WaForGAMHang:kbl */
1573 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1585 cs = intel_ring_begin(request, len);
1590 cs = gen8_emit_pipe_control(cs, 0, 0);
1593 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
1596 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
1599 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
1601 intel_ring_advance(request, cs);
1607 * Reserve space for 2 NOOPs at the end of each request to be
1608 * used as a workaround for not being allowed to do lite
1609 * restore with HEAD==TAIL (WaIdleLiteRestore).
1611 static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs)
1615 request->wa_tail = intel_ring_offset(request, cs);
1618 static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs)
1620 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1621 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1623 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1624 *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;
1626 *cs++ = request->global_seqno;
1627 *cs++ = MI_USER_INTERRUPT;
1629 request->tail = intel_ring_offset(request, cs);
1630 assert_ring_tail_valid(request->ring, request->tail);
1632 gen8_emit_wa_tail(request, cs);
1635 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1637 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
1640 /* We're using qword write, seqno should be aligned to 8 bytes. */
1641 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1643 /* w/a for post sync ops following a GPGPU operation we
1644 * need a prior CS_STALL, which is emitted by the flush
1645 * following the batch.
1647 *cs++ = GFX_OP_PIPE_CONTROL(6);
1648 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
1649 PIPE_CONTROL_QW_WRITE;
1650 *cs++ = intel_hws_seqno_address(request->engine);
1652 *cs++ = request->global_seqno;
1653 /* We're thrashing one dword of HWS. */
1655 *cs++ = MI_USER_INTERRUPT;
1657 request->tail = intel_ring_offset(request, cs);
1658 assert_ring_tail_valid(request->ring, request->tail);
1660 gen8_emit_wa_tail(request, cs);
1663 static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;
1665 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1669 ret = intel_ring_workarounds_emit(req);
1673 ret = intel_rcs_context_init_mocs(req);
1675 * Failing to program the MOCS is non-fatal.The system will not
1676 * run at peak performance. So generate an error and carry on.
1679 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1681 return i915_gem_render_state_emit(req);
1685 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1686 * @engine: Engine Command Streamer.
1688 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1690 struct drm_i915_private *dev_priv;
1693 * Tasklet cannot be active at this point due intel_mark_active/idle
1694 * so this is just for documentation.
1696 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1697 tasklet_kill(&engine->irq_tasklet);
1699 dev_priv = engine->i915;
1701 if (engine->buffer) {
1702 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1705 if (engine->cleanup)
1706 engine->cleanup(engine);
1708 if (engine->status_page.vma) {
1709 i915_gem_object_unpin_map(engine->status_page.vma->obj);
1710 engine->status_page.vma = NULL;
1713 intel_engine_cleanup_common(engine);
1715 lrc_destroy_wa_ctx(engine);
1716 engine->i915 = NULL;
1717 dev_priv->engine[engine->id] = NULL;
1721 static void execlists_set_default_submission(struct intel_engine_cs *engine)
1723 engine->submit_request = execlists_submit_request;
1724 engine->schedule = execlists_schedule;
1725 engine->irq_tasklet.func = intel_lrc_irq_handler;
1729 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1731 /* Default vfuncs which can be overriden by each engine. */
1732 engine->init_hw = gen8_init_common_ring;
1733 engine->reset_hw = reset_common_ring;
1735 engine->context_pin = execlists_context_pin;
1736 engine->context_unpin = execlists_context_unpin;
1738 engine->request_alloc = execlists_request_alloc;
1740 engine->emit_flush = gen8_emit_flush;
1741 engine->emit_breadcrumb = gen8_emit_breadcrumb;
1742 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1744 engine->set_default_submission = execlists_set_default_submission;
1746 engine->irq_enable = gen8_logical_ring_enable_irq;
1747 engine->irq_disable = gen8_logical_ring_disable_irq;
1748 engine->emit_bb_start = gen8_emit_bb_start;
1752 logical_ring_default_irqs(struct intel_engine_cs *engine)
1754 unsigned shift = engine->irq_shift;
1755 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1756 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1760 lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
1762 const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
1765 /* The HWSP is part of the default context object in LRC mode. */
1766 hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1768 return PTR_ERR(hws);
1770 engine->status_page.page_addr = hws + hws_offset;
1771 engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
1772 engine->status_page.vma = vma;
1778 logical_ring_setup(struct intel_engine_cs *engine)
1780 struct drm_i915_private *dev_priv = engine->i915;
1781 enum forcewake_domains fw_domains;
1783 intel_engine_setup_common(engine);
1785 /* Intentionally left blank. */
1786 engine->buffer = NULL;
1788 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1792 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1793 RING_CONTEXT_STATUS_PTR(engine),
1794 FW_REG_READ | FW_REG_WRITE);
1796 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1797 RING_CONTEXT_STATUS_BUF_BASE(engine),
1800 engine->fw_domains = fw_domains;
1802 tasklet_init(&engine->irq_tasklet,
1803 intel_lrc_irq_handler, (unsigned long)engine);
1805 logical_ring_default_vfuncs(engine);
1806 logical_ring_default_irqs(engine);
1810 logical_ring_init(struct intel_engine_cs *engine)
1812 struct i915_gem_context *dctx = engine->i915->kernel_context;
1815 ret = intel_engine_init_common(engine);
1819 /* And setup the hardware status page. */
1820 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
1822 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
1829 intel_logical_ring_cleanup(engine);
1833 int logical_render_ring_init(struct intel_engine_cs *engine)
1835 struct drm_i915_private *dev_priv = engine->i915;
1838 logical_ring_setup(engine);
1840 if (HAS_L3_DPF(dev_priv))
1841 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1843 /* Override some for render ring. */
1844 if (INTEL_GEN(dev_priv) >= 9)
1845 engine->init_hw = gen9_init_render_ring;
1847 engine->init_hw = gen8_init_render_ring;
1848 engine->init_context = gen8_init_rcs_context;
1849 engine->emit_flush = gen8_emit_flush_render;
1850 engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
1851 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
1853 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
1857 ret = intel_init_workaround_bb(engine);
1860 * We continue even if we fail to initialize WA batch
1861 * because we only expect rare glitches but nothing
1862 * critical to prevent us from using GPU
1864 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1868 return logical_ring_init(engine);
1871 int logical_xcs_ring_init(struct intel_engine_cs *engine)
1873 logical_ring_setup(engine);
1875 return logical_ring_init(engine);
1879 make_rpcs(struct drm_i915_private *dev_priv)
1884 * No explicit RPCS request is needed to ensure full
1885 * slice/subslice/EU enablement prior to Gen9.
1887 if (INTEL_GEN(dev_priv) < 9)
1891 * Starting in Gen9, render power gating can leave
1892 * slice/subslice/EU in a partially enabled state. We
1893 * must make an explicit request through RPCS for full
1896 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
1897 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1898 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
1899 GEN8_RPCS_S_CNT_SHIFT;
1900 rpcs |= GEN8_RPCS_ENABLE;
1903 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
1904 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1905 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
1906 GEN8_RPCS_SS_CNT_SHIFT;
1907 rpcs |= GEN8_RPCS_ENABLE;
1910 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
1911 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1912 GEN8_RPCS_EU_MIN_SHIFT;
1913 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1914 GEN8_RPCS_EU_MAX_SHIFT;
1915 rpcs |= GEN8_RPCS_ENABLE;
1921 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
1923 u32 indirect_ctx_offset;
1925 switch (INTEL_GEN(engine->i915)) {
1927 MISSING_CASE(INTEL_GEN(engine->i915));
1930 indirect_ctx_offset =
1931 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1934 indirect_ctx_offset =
1935 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1938 indirect_ctx_offset =
1939 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1943 return indirect_ctx_offset;
1946 static void execlists_init_reg_state(u32 *regs,
1947 struct i915_gem_context *ctx,
1948 struct intel_engine_cs *engine,
1949 struct intel_ring *ring)
1951 struct drm_i915_private *dev_priv = engine->i915;
1952 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
1953 u32 base = engine->mmio_base;
1954 bool rcs = engine->id == RCS;
1956 /* A context is actually a big batch buffer with several
1957 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
1958 * values we are setting here are only for the first context restore:
1959 * on a subsequent save, the GPU will recreate this batchbuffer with new
1960 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
1961 * we are not initializing here).
1963 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
1964 MI_LRI_FORCE_POSTED;
1966 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
1967 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1968 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
1969 (HAS_RESOURCE_STREAMER(dev_priv) ?
1970 CTX_CTRL_RS_CTX_ENABLE : 0)));
1971 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
1972 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
1973 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
1974 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
1975 RING_CTL_SIZE(ring->size) | RING_VALID);
1976 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
1977 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
1978 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
1979 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
1980 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
1981 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
1983 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
1984 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
1985 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
1986 RING_INDIRECT_CTX_OFFSET(base), 0);
1988 if (engine->wa_ctx.vma) {
1989 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1990 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
1992 regs[CTX_RCS_INDIRECT_CTX + 1] =
1993 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
1994 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
1996 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
1997 intel_lr_indirect_ctx_offset(engine) << 6;
1999 regs[CTX_BB_PER_CTX_PTR + 1] =
2000 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2004 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2006 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2007 /* PDP values well be assigned later if needed */
2008 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2009 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2010 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2011 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2012 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2013 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2014 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2015 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2017 if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
2018 /* 64b PPGTT (48bit canonical)
2019 * PDP0_DESCRIPTOR contains the base address to PML4 and
2020 * other PDP Descriptors are ignored.
2022 ASSIGN_CTX_PML4(ppgtt, regs);
2026 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2027 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2028 make_rpcs(dev_priv));
2030 i915_oa_init_reg_state(engine, ctx, regs);
2035 populate_lr_context(struct i915_gem_context *ctx,
2036 struct drm_i915_gem_object *ctx_obj,
2037 struct intel_engine_cs *engine,
2038 struct intel_ring *ring)
2043 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2045 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2049 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2050 if (IS_ERR(vaddr)) {
2051 ret = PTR_ERR(vaddr);
2052 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2055 ctx_obj->mm.dirty = true;
2057 /* The second page of the context object contains some fields which must
2058 * be set up prior to the first execution. */
2060 execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
2063 i915_gem_object_unpin_map(ctx_obj);
2068 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2069 struct intel_engine_cs *engine)
2071 struct drm_i915_gem_object *ctx_obj;
2072 struct intel_context *ce = &ctx->engine[engine->id];
2073 struct i915_vma *vma;
2074 uint32_t context_size;
2075 struct intel_ring *ring;
2080 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2082 /* One extra page as the sharing data between driver and GuC */
2083 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2085 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2086 if (IS_ERR(ctx_obj)) {
2087 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2088 return PTR_ERR(ctx_obj);
2091 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
2094 goto error_deref_obj;
2097 ring = intel_engine_create_ring(engine, ctx->ring_size);
2099 ret = PTR_ERR(ring);
2100 goto error_deref_obj;
2103 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2105 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2106 goto error_ring_free;
2111 ce->initialised |= engine->init_context == NULL;
2116 intel_ring_free(ring);
2118 i915_gem_object_put(ctx_obj);
2122 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2124 struct intel_engine_cs *engine;
2125 struct i915_gem_context *ctx;
2126 enum intel_engine_id id;
2128 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2129 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2130 * that stored in context. As we only write new commands from
2131 * ce->ring->tail onwards, everything before that is junk. If the GPU
2132 * starts reading from its RING_HEAD from the context, it may try to
2133 * execute that junk and die.
2135 * So to avoid that we reset the context images upon resume. For
2136 * simplicity, we just zero everything out.
2138 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
2139 for_each_engine(engine, dev_priv, id) {
2140 struct intel_context *ce = &ctx->engine[engine->id];
2146 reg = i915_gem_object_pin_map(ce->state->obj,
2148 if (WARN_ON(IS_ERR(reg)))
2151 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2152 reg[CTX_RING_HEAD+1] = 0;
2153 reg[CTX_RING_TAIL+1] = 0;
2155 ce->state->obj->mm.dirty = true;
2156 i915_gem_object_unpin_map(ce->state->obj);
2158 intel_ring_reset(ce->ring, 0);