drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_uc.h"
  32
  33 /**
  34  * DOC: GuC-specific firmware loader
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  */
  55
  56 #define SKL_FW_MAJOR 6
  57 #define SKL_FW_MINOR 1
  58
  59 #define BXT_FW_MAJOR 8
  60 #define BXT_FW_MINOR 7
  61
  62 #define KBL_FW_MAJOR 9
  63 #define KBL_FW_MINOR 14
  64
  65 #define GUC_FW_PATH(platform, major, minor) \
  66        "/*(DEBLOBBED)*/"
  67
  68 #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
  69 /*(DEBLOBBED)*/
  70
  71 #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
  72 /*(DEBLOBBED)*/
  73
  74 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
  75 /*(DEBLOBBED)*/
  76
  77 /* User-friendly representation of an enum */
  78 const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
  79 {
  80         switch (status) {
  81         case INTEL_UC_FIRMWARE_FAIL:
  82                 return "FAIL";
  83         case INTEL_UC_FIRMWARE_NONE:
  84                 return "NONE";
  85         case INTEL_UC_FIRMWARE_PENDING:
  86                 return "PENDING";
  87         case INTEL_UC_FIRMWARE_SUCCESS:
  88                 return "SUCCESS";
  89         default:
  90                 return "UNKNOWN!";
  91         }
  92 };
  93
  94 static void guc_interrupts_release(struct drm_i915_private *dev_priv)
  95 {
  96         struct intel_engine_cs *engine;
  97         enum intel_engine_id id;
  98         int irqs;
  99
 100         /* tell all command streamers NOT to forward interrupts or vblank to GuC */
 101         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
 102         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
 103         for_each_engine(engine, dev_priv, id)
 104                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 105
 106         /* route all GT interrupts to the host */
 107         I915_WRITE(GUC_BCS_RCS_IER, 0);
 108         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
 109         I915_WRITE(GUC_WD_VECS_IER, 0);
 110 }
 111
 112 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
 113 {
 114         struct intel_engine_cs *engine;
 115         enum intel_engine_id id;
 116         int irqs;
 117         u32 tmp;
 118
 119         /* tell all command streamers to forward interrupts (but not vblank) to GuC */
 120         irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 121         for_each_engine(engine, dev_priv, id)
 122                 I915_WRITE(RING_MODE_GEN7(engine), irqs);
 123
 124         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
 125         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
 126                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
 127         /* These three registers have the same bit definitions */
 128         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
 129         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
 130         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
 131
 132         /*
 133          * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
 134          * (unmasked) PM interrupts to the GuC. All other bits of this
 135          * register *disable* generation of a specific interrupt.
 136          *
 137          * 'pm_intr_keep' indicates bits that are NOT to be set when
 138          * writing to the PM interrupt mask register, i.e. interrupts
 139          * that must not be disabled.
 140          *
 141          * If the GuC is handling these interrupts, then we must not let
 142          * the PM code disable ANY interrupt that the GuC is expecting.
 143          * So for each ENABLED (0) bit in this register, we must SET the
 144          * bit in pm_intr_keep so that it's left enabled for the GuC.
 145          *
 146          * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep
 147          * (so interrupts go to the DISPLAY unit at first); but here we
 148          * need to CLEAR that bit, which will result in the register bit
 149          * being left SET!
 150          */
 151         tmp = I915_READ(GEN6_PMINTRMSK);
 152         if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) {
 153                 dev_priv->rps.pm_intr_keep |= ~tmp;
 154                 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
 155         }
 156 }
 157
 158 static u32 get_gttype(struct drm_i915_private *dev_priv)
 159 {
 160         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 161         return 0;
 162 }
 163
 164 static u32 get_core_family(struct drm_i915_private *dev_priv)
 165 {
 166         u32 gen = INTEL_GEN(dev_priv);
 167
 168         switch (gen) {
 169         case 9:
 170                 return GFXCORE_FAMILY_GEN9;
 171
 172         default:
 173                 WARN(1, "GEN%d does not support GuC operation!\n", gen);
 174                 return GFXCORE_FAMILY_UNKNOWN;
 175         }
 176 }
 177
 178 /*
 179  * Initialise the GuC parameter block before starting the firmware
 180  * transfer. These parameters are read by the firmware on startup
 181  * and cannot be changed thereafter.
 182  */
 183 static void guc_params_init(struct drm_i915_private *dev_priv)
 184 {
 185         struct intel_guc *guc = &dev_priv->guc;
 186         u32 params[GUC_CTL_MAX_DWORDS];
 187         int i;
 188
 189         memset(&params, 0, sizeof(params));
 190
 191         params[GUC_CTL_DEVICE_INFO] |=
 192                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 193                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 194
 195         /*
 196          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 197          * second. This ARAR is calculated by:
 198          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 199          */
 200         params[GUC_CTL_ARAT_HIGH] = 0;
 201         params[GUC_CTL_ARAT_LOW] = 100000000;
 202
 203         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 204
 205         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 206                         GUC_CTL_VCS2_ENABLED;
 207
 208         params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 209
 210         if (i915.guc_log_level >= 0) {
 211                 params[GUC_CTL_DEBUG] =
 212                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 213         } else
 214                 params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
 215
 216         if (guc->ads_vma) {
 217                 u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
 218                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 219                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 220         }
 221
 222         /* If GuC submission is enabled, set up additional parameters here */
 223         if (i915.enable_guc_submission) {
 224                 u32 pgs = guc_ggtt_offset(dev_priv->guc.ctx_pool_vma);
 225                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 226
 227                 pgs >>= PAGE_SHIFT;
 228                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 229                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 230
 231                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 232
 233                 /* Unmask this bit to enable the GuC's internal scheduler */
 234                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 235         }
 236
 237         I915_WRITE(SOFT_SCRATCH(0), 0);
 238
 239         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 240                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 241 }
 242
 243 /*
 244  * Read the GuC status register (GUC_STATUS) and store it in the
 245  * specified location; then return a boolean indicating whether
 246  * the value matches either of two values representing completion
 247  * of the GuC boot process.
 248  *
 249  * This is used for polling the GuC status in a wait_for()
 250  * loop below.
 251  */
 252 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 253                                       u32 *status)
 254 {
 255         u32 val = I915_READ(GUC_STATUS);
 256         u32 uk_val = val & GS_UKERNEL_MASK;
 257         *status = val;
 258         return (uk_val == GS_UKERNEL_READY ||
 259                 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
 260 }
 261
 262 /*
 263  * Transfer the firmware image to RAM for execution by the microcontroller.
 264  *
 265  * Architecturally, the DMA engine is bidirectional, and can potentially even
 266  * transfer between GTT locations. This functionality is left out of the API
 267  * for now as there is no need for it.
 268  *
 269  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 270  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 271  */
 272 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 273                               struct i915_vma *vma)
 274 {
 275         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 276         unsigned long offset;
 277         struct sg_table *sg = vma->pages;
 278         u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 279         int i, ret = 0;
 280
 281         /* where RSA signature starts */
 282         offset = guc_fw->rsa_offset;
 283
 284         /* Copy RSA signature from the fw image to HW for verification */
 285         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
 286         for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
 287                 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
 288
 289         /* The header plus uCode will be copied to WOPCM via DMA, excluding any
 290          * other components */
 291         I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 292
 293         /* Set the source address for the new blob */
 294         offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
 295         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 296         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 297
 298         /*
 299          * Set the DMA destination. Current uCode expects the code to be
 300          * loaded at 8k; locations below this are used for the stack.
 301          */
 302         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 303         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 304
 305         /* Finally start the DMA */
 306         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 307
 308         /*
 309          * Wait for the DMA to complete & the GuC to start up.
 310          * NB: Docs recommend not using the interrupt for completion.
 311          * Measurements indicate this should take no more than 20ms, so a
 312          * timeout here indicates that the GuC has failed and is unusable.
 313          * (Higher levels of the driver will attempt to fall back to
 314          * execlist mode if this happens.)
 315          */
 316         ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 317
 318         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 319                         I915_READ(DMA_CTRL), status);
 320
 321         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 322                 DRM_ERROR("GuC firmware signature verification failed\n");
 323                 ret = -ENOEXEC;
 324         }
 325
 326         DRM_DEBUG_DRIVER("returning %d\n", ret);
 327
 328         return ret;
 329 }
 330
 331 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
 332 {
 333         u32 wopcm_size = GUC_WOPCM_TOP;
 334
 335         /* On BXT, the top of WOPCM is reserved for RC6 context */
 336         if (IS_GEN9_LP(dev_priv))
 337                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 338
 339         return wopcm_size;
 340 }
 341
 342 /*
 343  * Load the GuC firmware blob into the MinuteIA.
 344  */
 345 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 346 {
 347         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 348         struct i915_vma *vma;
 349         int ret;
 350
 351         ret = i915_gem_object_set_to_gtt_domain(guc_fw->obj, false);
 352         if (ret) {
 353                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 354                 return ret;
 355         }
 356
 357         vma = i915_gem_object_ggtt_pin(guc_fw->obj, NULL, 0, 0,
 358                                        PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
 359         if (IS_ERR(vma)) {
 360                 DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
 361                 return PTR_ERR(vma);
 362         }
 363
 364         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 365
 366         /* init WOPCM */
 367         I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
 368         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 369
 370         /* Enable MIA caching. GuC clock gating is disabled. */
 371         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 372
 373         /* WaDisableMinuteIaClockGating:bxt */
 374         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
 375                 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
 376                                               ~GUC_ENABLE_MIA_CLOCK_GATING));
 377         }
 378
 379         /* WaC6DisallowByGfxPause:bxt */
 380         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
 381                 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 382
 383         if (IS_GEN9_LP(dev_priv))
 384                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 385         else
 386                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 387
 388         if (IS_GEN9(dev_priv)) {
 389                 /* DOP Clock Gating Enable for GuC clocks */
 390                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 391                                             I915_READ(GEN7_MISCCPCTL)));
 392
 393                 /* allows for 5us (in 10ns units) before GT can go to RC6 */
 394                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 395         }
 396
 397         guc_params_init(dev_priv);
 398
 399         ret = guc_ucode_xfer_dma(dev_priv, vma);
 400
 401         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 402
 403         /*
 404          * We keep the object pages for reuse during resume. But we can unpin it
 405          * now that DMA has completed, so it doesn't continue to take up space.
 406          */
 407         i915_vma_unpin(vma);
 408
 409         return ret;
 410 }
 411
 412 static int guc_hw_reset(struct drm_i915_private *dev_priv)
 413 {
 414         int ret;
 415         u32 guc_status;
 416
 417         ret = intel_guc_reset(dev_priv);
 418         if (ret) {
 419                 DRM_ERROR("GuC reset failed, ret = %d\n", ret);
 420                 return ret;
 421         }
 422
 423         guc_status = I915_READ(GUC_STATUS);
 424         WARN(!(guc_status & GS_MIA_IN_RESET),
 425              "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status);
 426
 427         return ret;
 428 }
 429
 430 /**
 431  * intel_guc_setup() - finish preparing the GuC for activity
 432  * @dev_priv:   i915 device private
 433  *
 434  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 435  *
 436  * The main action required here it to load the GuC uCode into the device.
 437  * The firmware image should have already been fetched into memory by the
 438  * earlier call to intel_guc_init(), so here we need only check that worked,
 439  * and then transfer the image to the h/w.
 440  *
 441  * Return:      non-zero code on error
 442  */
 443 int intel_guc_setup(struct drm_i915_private *dev_priv)
 444 {
 445         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 446         const char *fw_path = guc_fw->path;
 447         int retries, ret, err;
 448
 449         DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
 450                 fw_path,
 451                 intel_uc_fw_status_repr(guc_fw->fetch_status),
 452                 intel_uc_fw_status_repr(guc_fw->load_status));
 453
 454         /* Loading forbidden, or no firmware to load? */
 455         if (!i915.enable_guc_loading) {
 456                 err = 0;
 457                 goto fail;
 458         } else if (fw_path == NULL) {
 459                 /* Device is known to have no uCode (e.g. no GuC) */
 460                 err = -ENXIO;
 461                 goto fail;
 462         } else if (*fw_path == '\0') {
 463                 /* Device has a GuC but we don't know what f/w to load? */
 464                 WARN(1, "No GuC firmware known for this platform!\n");
 465                 err = -ENODEV;
 466                 goto fail;
 467         }
 468
 469         /* Fetch failed, or already fetched but failed to load? */
 470         if (guc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS) {
 471                 err = -EIO;
 472                 goto fail;
 473         } else if (guc_fw->load_status == INTEL_UC_FIRMWARE_FAIL) {
 474                 err = -ENOEXEC;
 475                 goto fail;
 476         }
 477
 478         guc_interrupts_release(dev_priv);
 479         gen9_reset_guc_interrupts(dev_priv);
 480
 481         /* We need to notify the guc whenever we change the GGTT */
 482         i915_ggtt_enable_guc(dev_priv);
 483
 484         guc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
 485
 486         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 487                 intel_uc_fw_status_repr(guc_fw->fetch_status),
 488                 intel_uc_fw_status_repr(guc_fw->load_status));
 489
 490         err = i915_guc_submission_init(dev_priv);
 491         if (err)
 492                 goto fail;
 493
 494         /*
 495          * WaEnableuKernelHeaderValidFix:skl,bxt
 496          * For BXT, this is only upto B0 but below WA is required for later
 497          * steppings also so this is extended as well.
 498          */
 499         /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
 500         for (retries = 3; ; ) {
 501                 /*
 502                  * Always reset the GuC just before (re)loading, so
 503                  * that the state and timing are fairly predictable
 504                  */
 505                 err = guc_hw_reset(dev_priv);
 506                 if (err)
 507                         goto fail;
 508
 509                 intel_huc_load(dev_priv);
 510                 err = guc_ucode_xfer(dev_priv);
 511                 if (!err)
 512                         break;
 513
 514                 if (--retries == 0)
 515                         goto fail;
 516
 517                 DRM_INFO("GuC fw load failed: %d; will reset and "
 518                          "retry %d more time(s)\n", err, retries);
 519         }
 520
 521         guc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
 522
 523         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 524                 intel_uc_fw_status_repr(guc_fw->fetch_status),
 525                 intel_uc_fw_status_repr(guc_fw->load_status));
 526
 527         intel_guc_auth_huc(dev_priv);
 528
 529         if (i915.enable_guc_submission) {
 530                 if (i915.guc_log_level >= 0)
 531                         gen9_enable_guc_interrupts(dev_priv);
 532
 533                 err = i915_guc_submission_enable(dev_priv);
 534                 if (err)
 535                         goto fail;
 536                 guc_interrupts_capture(dev_priv);
 537         }
 538
 539         return 0;
 540
 541 fail:
 542         if (guc_fw->load_status == INTEL_UC_FIRMWARE_PENDING)
 543                 guc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
 544
 545         guc_interrupts_release(dev_priv);
 546         i915_guc_submission_disable(dev_priv);
 547         i915_guc_submission_fini(dev_priv);
 548         i915_ggtt_disable_guc(dev_priv);
 549
 550         /*
 551          * We've failed to load the firmware :(
 552          *
 553          * Decide whether to disable GuC submission and fall back to
 554          * execlist mode, and whether to hide the error by returning
 555          * zero or to return -EIO, which the caller will treat as a
 556          * nonfatal error (i.e. it doesn't prevent driver load, but
 557          * marks the GPU as wedged until reset).
 558          */
 559         if (i915.enable_guc_loading > 1) {
 560                 ret = -EIO;
 561         } else if (i915.enable_guc_submission > 1) {
 562                 ret = -EIO;
 563         } else {
 564                 ret = 0;
 565         }
 566
 567         if (err == 0 && !HAS_GUC_UCODE(dev_priv))
 568                 ;       /* Don't mention the GuC! */
 569         else if (err == 0)
 570                 DRM_INFO("GuC firmware load skipped\n");
 571         else if (ret != -EIO)
 572                 DRM_NOTE("GuC firmware load failed: %d\n", err);
 573         else
 574                 DRM_WARN("GuC firmware load failed: %d\n", err);
 575
 576         if (i915.enable_guc_submission) {
 577                 if (fw_path == NULL)
 578                         DRM_INFO("GuC submission without firmware not supported\n");
 579                 if (ret == 0)
 580                         DRM_NOTE("Falling back from GuC submission to execlist mode\n");
 581                 else
 582                         DRM_ERROR("GuC init failed: %d\n", ret);
 583         }
 584         i915.enable_guc_submission = 0;
 585
 586         return ret;
 587 }
 588
 589 void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 590                          struct intel_uc_fw *uc_fw)
 591 {
 592         struct pci_dev *pdev = dev_priv->drm.pdev;
 593         struct drm_i915_gem_object *obj;
 594         const struct firmware *fw = NULL;
 595         struct uc_css_header *css;
 596         size_t size;
 597         int err;
 598
 599         DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
 600                 intel_uc_fw_status_repr(uc_fw->fetch_status));
 601
 602         err = reject_firmware(&fw, uc_fw->path, &pdev->dev);
 603         if (err)
 604                 goto fail;
 605         if (!fw)
 606                 goto fail;
 607
 608         DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
 609                 uc_fw->path, fw);
 610
 611         /* Check the size of the blob before examining buffer contents */
 612         if (fw->size < sizeof(struct uc_css_header)) {
 613                 DRM_NOTE("Firmware header is missing\n");
 614                 goto fail;
 615         }
 616
 617         css = (struct uc_css_header *)fw->data;
 618
 619         /* Firmware bits always start from header */
 620         uc_fw->header_offset = 0;
 621         uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
 622                 css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
 623
 624         if (uc_fw->header_size != sizeof(struct uc_css_header)) {
 625                 DRM_NOTE("CSS header definition mismatch\n");
 626                 goto fail;
 627         }
 628
 629         /* then, uCode */
 630         uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
 631         uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 632
 633         /* now RSA */
 634         if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
 635                 DRM_NOTE("RSA key size is bad\n");
 636                 goto fail;
 637         }
 638         uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
 639         uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
 640
 641         /* At least, it should have header, uCode and RSA. Size of all three. */
 642         size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
 643         if (fw->size < size) {
 644                 DRM_NOTE("Missing firmware components\n");
 645                 goto fail;
 646         }
 647
 648         /*
 649          * The GuC firmware image has the version number embedded at a well-known
 650          * offset within the firmware blob; note that major / minor version are
 651          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 652          * in terms of bytes (u8).
 653          */
 654         switch (uc_fw->fw) {
 655         case INTEL_UC_FW_TYPE_GUC:
 656                 /* Header and uCode will be loaded to WOPCM. Size of the two. */
 657                 size = uc_fw->header_size + uc_fw->ucode_size;
 658
 659                 /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
 660                 if (size > intel_guc_wopcm_size(dev_priv)) {
 661                         DRM_ERROR("Firmware is too large to fit in WOPCM\n");
 662                         goto fail;
 663                 }
 664                 uc_fw->major_ver_found = css->guc.sw_version >> 16;
 665                 uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
 666                 break;
 667
 668         case INTEL_UC_FW_TYPE_HUC:
 669                 uc_fw->major_ver_found = css->huc.sw_version >> 16;
 670                 uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
 671                 break;
 672
 673         default:
 674                 DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw);
 675                 err = -ENOEXEC;
 676                 goto fail;
 677         }
 678
 679         if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
 680             uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
 681                 DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
 682                         uc_fw->major_ver_found, uc_fw->minor_ver_found,
 683                         uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 684                 err = -ENOEXEC;
 685                 goto fail;
 686         }
 687
 688         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 689                         uc_fw->major_ver_found, uc_fw->minor_ver_found,
 690                         uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
 691
 692         mutex_lock(&dev_priv->drm.struct_mutex);
 693         obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->size);
 694         mutex_unlock(&dev_priv->drm.struct_mutex);
 695         if (IS_ERR_OR_NULL(obj)) {
 696                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 697                 goto fail;
 698         }
 699
 700         uc_fw->obj = obj;
 701         uc_fw->size = fw->size;
 702
 703         DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
 704                         uc_fw->obj);
 705
 706         release_firmware(fw);
 707         uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
 708         return;
 709
 710 fail:
 711         DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
 712                  uc_fw->path, err);
 713         DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 714                 err, fw, uc_fw->obj);
 715
 716         mutex_lock(&dev_priv->drm.struct_mutex);
 717         obj = uc_fw->obj;
 718         if (obj)
 719                 i915_gem_object_put(obj);
 720         uc_fw->obj = NULL;
 721         mutex_unlock(&dev_priv->drm.struct_mutex);
 722
 723         release_firmware(fw);           /* OK even if fw is NULL */
 724         uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL;
 725 }
 726
 727 /**
 728  * intel_guc_init() - define parameters and fetch firmware
 729  * @dev_priv:   i915 device private
 730  *
 731  * Called early during driver load, but after GEM is initialised.
 732  *
 733  * The firmware will be transferred to the GuC's memory later,
 734  * when intel_guc_setup() is called.
 735  */
 736 void intel_guc_init(struct drm_i915_private *dev_priv)
 737 {
 738         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 739         const char *fw_path;
 740
 741         if (!HAS_GUC(dev_priv)) {
 742                 i915.enable_guc_loading = 0;
 743                 i915.enable_guc_submission = 0;
 744         } else {
 745                 /* A negative value means "use platform default" */
 746                 if (i915.enable_guc_loading < 0)
 747                         i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
 748                 if (i915.enable_guc_submission < 0)
 749                         i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
 750         }
 751
 752         if (!HAS_GUC_UCODE(dev_priv)) {
 753                 fw_path = NULL;
 754         } else if (IS_SKYLAKE(dev_priv)) {
 755                 fw_path = I915_SKL_GUC_UCODE;
 756                 guc_fw->major_ver_wanted = SKL_FW_MAJOR;
 757                 guc_fw->minor_ver_wanted = SKL_FW_MINOR;
 758         } else if (IS_BROXTON(dev_priv)) {
 759                 fw_path = I915_BXT_GUC_UCODE;
 760                 guc_fw->major_ver_wanted = BXT_FW_MAJOR;
 761                 guc_fw->minor_ver_wanted = BXT_FW_MINOR;
 762         } else if (IS_KABYLAKE(dev_priv)) {
 763                 fw_path = I915_KBL_GUC_UCODE;
 764                 guc_fw->major_ver_wanted = KBL_FW_MAJOR;
 765                 guc_fw->minor_ver_wanted = KBL_FW_MINOR;
 766         } else {
 767                 fw_path = "";   /* unknown device */
 768         }
 769
 770         guc_fw->path = fw_path;
 771         guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 772         guc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
 773
 774         /* Early (and silent) return if GuC loading is disabled */
 775         if (!i915.enable_guc_loading)
 776                 return;
 777         if (fw_path == NULL)
 778                 return;
 779         if (*fw_path == '\0')
 780                 return;
 781
 782         guc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
 783         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 784         intel_uc_fw_fetch(dev_priv, guc_fw);
 785         /* status must now be FAIL or SUCCESS */
 786 }
 787
 788 /**
 789  * intel_guc_fini() - clean up all allocated resources
 790  * @dev_priv:   i915 device private
 791  */
 792 void intel_guc_fini(struct drm_i915_private *dev_priv)
 793 {
 794         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 795
 796         mutex_lock(&dev_priv->drm.struct_mutex);
 797         guc_interrupts_release(dev_priv);
 798         i915_guc_submission_disable(dev_priv);
 799         i915_guc_submission_fini(dev_priv);
 800
 801         if (guc_fw->obj)
 802                 i915_gem_object_put(guc_fw->obj);
 803         guc_fw->obj = NULL;
 804         mutex_unlock(&dev_priv->drm.struct_mutex);
 805
 806         guc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
 807 }