drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 908000, .max = 1512000 },
  94         .n = { .min = 2, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 908000, .max = 1512000 },
 107         .n = { .min = 2, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 908000, .max = 1512000 },
 120         .n = { .min = 2, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         if (WARN_ON(clock->n == 0 || clock->p == 0))
 333                 return;
 334         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 335         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 336 }
 337
 338 /**
 339  * Returns whether any output on the specified pipe is of the specified type
 340  */
 341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 342 {
 343         struct drm_device *dev = crtc->dev;
 344         struct intel_encoder *encoder;
 345
 346         for_each_encoder_on_crtc(dev, crtc, encoder)
 347                 if (encoder->type == type)
 348                         return true;
 349
 350         return false;
 351 }
 352
 353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 354                                                 int refclk)
 355 {
 356         struct drm_device *dev = crtc->dev;
 357         const intel_limit_t *limit;
 358
 359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 360                 if (intel_is_dual_link_lvds(dev)) {
 361                         if (refclk == 100000)
 362                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 363                         else
 364                                 limit = &intel_limits_ironlake_dual_lvds;
 365                 } else {
 366                         if (refclk == 100000)
 367                                 limit = &intel_limits_ironlake_single_lvds_100m;
 368                         else
 369                                 limit = &intel_limits_ironlake_single_lvds;
 370                 }
 371         } else
 372                 limit = &intel_limits_ironlake_dac;
 373
 374         return limit;
 375 }
 376
 377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 378 {
 379         struct drm_device *dev = crtc->dev;
 380         const intel_limit_t *limit;
 381
 382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 383                 if (intel_is_dual_link_lvds(dev))
 384                         limit = &intel_limits_g4x_dual_channel_lvds;
 385                 else
 386                         limit = &intel_limits_g4x_single_channel_lvds;
 387         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 388                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 389                 limit = &intel_limits_g4x_hdmi;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 391                 limit = &intel_limits_g4x_sdvo;
 392         } else /* The option is for other outputs */
 393                 limit = &intel_limits_i9xx_sdvo;
 394
 395         return limit;
 396 }
 397
 398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 399 {
 400         struct drm_device *dev = crtc->dev;
 401         const intel_limit_t *limit;
 402
 403         if (HAS_PCH_SPLIT(dev))
 404                 limit = intel_ironlake_limit(crtc, refclk);
 405         else if (IS_G4X(dev)) {
 406                 limit = intel_g4x_limit(crtc);
 407         } else if (IS_PINEVIEW(dev)) {
 408                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 409                         limit = &intel_limits_pineview_lvds;
 410                 else
 411                         limit = &intel_limits_pineview_sdvo;
 412         } else if (IS_VALLEYVIEW(dev)) {
 413                 limit = &intel_limits_vlv;
 414         } else if (!IS_GEN2(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 416                         limit = &intel_limits_i9xx_lvds;
 417                 else
 418                         limit = &intel_limits_i9xx_sdvo;
 419         } else {
 420                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 421                         limit = &intel_limits_i8xx_lvds;
 422                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 423                         limit = &intel_limits_i8xx_dvo;
 424                 else
 425                         limit = &intel_limits_i8xx_dac;
 426         }
 427         return limit;
 428 }
 429
 430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 431 static void pineview_clock(int refclk, intel_clock_t *clock)
 432 {
 433         clock->m = clock->m2 + 2;
 434         clock->p = clock->p1 * clock->p2;
 435         if (WARN_ON(clock->n == 0 || clock->p == 0))
 436                 return;
 437         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 438         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 439 }
 440
 441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 442 {
 443         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 444 }
 445
 446 static void i9xx_clock(int refclk, intel_clock_t *clock)
 447 {
 448         clock->m = i9xx_dpll_compute_m(clock);
 449         clock->p = clock->p1 * clock->p2;
 450         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 451                 return;
 452         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 453         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 467                 INTELPllInvalid("n out of range\n");
 468         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 469                 INTELPllInvalid("p1 out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474
 475         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 476                 if (clock->m1 <= clock->m2)
 477                         INTELPllInvalid("m1 <= m2\n");
 478
 479         if (!IS_VALLEYVIEW(dev)) {
 480                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 481                         INTELPllInvalid("p out of range\n");
 482                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 483                         INTELPllInvalid("m out of range\n");
 484         }
 485
 486         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 487                 INTELPllInvalid("vco out of range\n");
 488         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 489          * connector, etc., rather than just a single range.
 490          */
 491         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 492                 INTELPllInvalid("dot out of range\n");
 493
 494         return true;
 495 }
 496
 497 static bool
 498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 499                     int target, int refclk, intel_clock_t *match_clock,
 500                     intel_clock_t *best_clock)
 501 {
 502         struct drm_device *dev = crtc->dev;
 503         intel_clock_t clock;
 504         int err = target;
 505
 506         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 507                 /*
 508                  * For LVDS just rely on its current settings for dual-channel.
 509                  * We haven't figured out how to reliably set up different
 510                  * single/dual channel state, if we even can.
 511                  */
 512                 if (intel_is_dual_link_lvds(dev))
 513                         clock.p2 = limit->p2.p2_fast;
 514                 else
 515                         clock.p2 = limit->p2.p2_slow;
 516         } else {
 517                 if (target < limit->p2.dot_limit)
 518                         clock.p2 = limit->p2.p2_slow;
 519                 else
 520                         clock.p2 = limit->p2.p2_fast;
 521         }
 522
 523         memset(best_clock, 0, sizeof(*best_clock));
 524
 525         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 526              clock.m1++) {
 527                 for (clock.m2 = limit->m2.min;
 528                      clock.m2 <= limit->m2.max; clock.m2++) {
 529                         if (clock.m2 >= clock.m1)
 530                                 break;
 531                         for (clock.n = limit->n.min;
 532                              clock.n <= limit->n.max; clock.n++) {
 533                                 for (clock.p1 = limit->p1.min;
 534                                         clock.p1 <= limit->p1.max; clock.p1++) {
 535                                         int this_err;
 536
 537                                         i9xx_clock(refclk, &clock);
 538                                         if (!intel_PLL_is_valid(dev, limit,
 539                                                                 &clock))
 540                                                 continue;
 541                                         if (match_clock &&
 542                                             clock.p != match_clock->p)
 543                                                 continue;
 544
 545                                         this_err = abs(clock.dot - target);
 546                                         if (this_err < err) {
 547                                                 *best_clock = clock;
 548                                                 err = this_err;
 549                                         }
 550                                 }
 551                         }
 552                 }
 553         }
 554
 555         return (err != target);
 556 }
 557
 558 static bool
 559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 560                    int target, int refclk, intel_clock_t *match_clock,
 561                    intel_clock_t *best_clock)
 562 {
 563         struct drm_device *dev = crtc->dev;
 564         intel_clock_t clock;
 565         int err = target;
 566
 567         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 568                 /*
 569                  * For LVDS just rely on its current settings for dual-channel.
 570                  * We haven't figured out how to reliably set up different
 571                  * single/dual channel state, if we even can.
 572                  */
 573                 if (intel_is_dual_link_lvds(dev))
 574                         clock.p2 = limit->p2.p2_fast;
 575                 else
 576                         clock.p2 = limit->p2.p2_slow;
 577         } else {
 578                 if (target < limit->p2.dot_limit)
 579                         clock.p2 = limit->p2.p2_slow;
 580                 else
 581                         clock.p2 = limit->p2.p2_fast;
 582         }
 583
 584         memset(best_clock, 0, sizeof(*best_clock));
 585
 586         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 587              clock.m1++) {
 588                 for (clock.m2 = limit->m2.min;
 589                      clock.m2 <= limit->m2.max; clock.m2++) {
 590                         for (clock.n = limit->n.min;
 591                              clock.n <= limit->n.max; clock.n++) {
 592                                 for (clock.p1 = limit->p1.min;
 593                                         clock.p1 <= limit->p1.max; clock.p1++) {
 594                                         int this_err;
 595
 596                                         pineview_clock(refclk, &clock);
 597                                         if (!intel_PLL_is_valid(dev, limit,
 598                                                                 &clock))
 599                                                 continue;
 600                                         if (match_clock &&
 601                                             clock.p != match_clock->p)
 602                                                 continue;
 603
 604                                         this_err = abs(clock.dot - target);
 605                                         if (this_err < err) {
 606                                                 *best_clock = clock;
 607                                                 err = this_err;
 608                                         }
 609                                 }
 610                         }
 611                 }
 612         }
 613
 614         return (err != target);
 615 }
 616
 617 static bool
 618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 619                    int target, int refclk, intel_clock_t *match_clock,
 620                    intel_clock_t *best_clock)
 621 {
 622         struct drm_device *dev = crtc->dev;
 623         intel_clock_t clock;
 624         int max_n;
 625         bool found;
 626         /* approximately equals target * 0.00585 */
 627         int err_most = (target >> 8) + (target >> 9);
 628         found = false;
 629
 630         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 631                 if (intel_is_dual_link_lvds(dev))
 632                         clock.p2 = limit->p2.p2_fast;
 633                 else
 634                         clock.p2 = limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         clock.p2 = limit->p2.p2_slow;
 638                 else
 639                         clock.p2 = limit->p2.p2_fast;
 640         }
 641
 642         memset(best_clock, 0, sizeof(*best_clock));
 643         max_n = limit->n.max;
 644         /* based on hardware requirement, prefer smaller n to precision */
 645         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 646                 /* based on hardware requirement, prefere larger m1,m2 */
 647                 for (clock.m1 = limit->m1.max;
 648                      clock.m1 >= limit->m1.min; clock.m1--) {
 649                         for (clock.m2 = limit->m2.max;
 650                              clock.m2 >= limit->m2.min; clock.m2--) {
 651                                 for (clock.p1 = limit->p1.max;
 652                                      clock.p1 >= limit->p1.min; clock.p1--) {
 653                                         int this_err;
 654
 655                                         i9xx_clock(refclk, &clock);
 656                                         if (!intel_PLL_is_valid(dev, limit,
 657                                                                 &clock))
 658                                                 continue;
 659
 660                                         this_err = abs(clock.dot - target);
 661                                         if (this_err < err_most) {
 662                                                 *best_clock = clock;
 663                                                 err_most = this_err;
 664                                                 max_n = clock.n;
 665                                                 found = true;
 666                                         }
 667                                 }
 668                         }
 669                 }
 670         }
 671         return found;
 672 }
 673
 674 static bool
 675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                    int target, int refclk, intel_clock_t *match_clock,
 677                    intel_clock_t *best_clock)
 678 {
 679         struct drm_device *dev = crtc->dev;
 680         intel_clock_t clock;
 681         unsigned int bestppm = 1000000;
 682         /* min update 19.2 MHz */
 683         int max_n = min(limit->n.max, refclk / 19200);
 684         bool found = false;
 685
 686         target *= 5; /* fast clock */
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         /* based on hardware requirement, prefer smaller n to precision */
 691         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 692                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 693                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 694                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 695                                 clock.p = clock.p1 * clock.p2;
 696                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 697                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 698                                         unsigned int ppm, diff;
 699
 700                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 701                                                                      refclk * clock.m1);
 702
 703                                         vlv_clock(refclk, &clock);
 704
 705                                         if (!intel_PLL_is_valid(dev, limit,
 706                                                                 &clock))
 707                                                 continue;
 708
 709                                         diff = abs(clock.dot - target);
 710                                         ppm = div_u64(1000000ULL * diff, target);
 711
 712                                         if (ppm < 100 && clock.p > best_clock->p) {
 713                                                 bestppm = 0;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717
 718                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 719                                                 bestppm = ppm;
 720                                                 *best_clock = clock;
 721                                                 found = true;
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727
 728         return found;
 729 }
 730
 731 bool intel_crtc_active(struct drm_crtc *crtc)
 732 {
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         /* Be paranoid as we can arrive here with only partial
 736          * state retrieved from the hardware during setup.
 737          *
 738          * We can ditch the adjusted_mode.crtc_clock check as soon
 739          * as Haswell has gained clock readout/fastboot support.
 740          *
 741          * We can ditch the crtc->fb check as soon as we can
 742          * properly reconstruct framebuffers.
 743          */
 744         return intel_crtc->active && crtc->fb &&
 745                 intel_crtc->config.adjusted_mode.crtc_clock;
 746 }
 747
 748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 749                                              enum pipe pipe)
 750 {
 751         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 753
 754         return intel_crtc->config.cpu_transcoder;
 755 }
 756
 757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 761
 762         frame = I915_READ(frame_reg);
 763
 764         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 765                 DRM_DEBUG_KMS("vblank wait timed out\n");
 766 }
 767
 768 /**
 769  * intel_wait_for_vblank - wait for vblank on a given pipe
 770  * @dev: drm device
 771  * @pipe: pipe to wait for
 772  *
 773  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 774  * mode setting code.
 775  */
 776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         int pipestat_reg = PIPESTAT(pipe);
 780
 781         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 782                 g4x_wait_for_vblank(dev, pipe);
 783                 return;
 784         }
 785
 786         /* Clear existing vblank status. Note this will clear any other
 787          * sticky status fields as well.
 788          *
 789          * This races with i915_driver_irq_handler() with the result
 790          * that either function could miss a vblank event.  Here it is not
 791          * fatal, as we will either wait upon the next vblank interrupt or
 792          * timeout.  Generally speaking intel_wait_for_vblank() is only
 793          * called during modeset at which time the GPU should be idle and
 794          * should *not* be performing page flips and thus not waiting on
 795          * vblanks...
 796          * Currently, the result of us stealing a vblank from the irq
 797          * handler is that a single frame will be skipped during swapbuffers.
 798          */
 799         I915_WRITE(pipestat_reg,
 800                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 801
 802         /* Wait for vblank interrupt bit to set */
 803         if (wait_for(I915_READ(pipestat_reg) &
 804                      PIPE_VBLANK_INTERRUPT_STATUS,
 805                      50))
 806                 DRM_DEBUG_KMS("vblank wait timed out\n");
 807 }
 808
 809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         u32 reg = PIPEDSL(pipe);
 813         u32 line1, line2;
 814         u32 line_mask;
 815
 816         if (IS_GEN2(dev))
 817                 line_mask = DSL_LINEMASK_GEN2;
 818         else
 819                 line_mask = DSL_LINEMASK_GEN3;
 820
 821         line1 = I915_READ(reg) & line_mask;
 822         mdelay(5);
 823         line2 = I915_READ(reg) & line_mask;
 824
 825         return line1 == line2;
 826 }
 827
 828 /*
 829  * intel_wait_for_pipe_off - wait for pipe to turn off
 830  * @dev: drm device
 831  * @pipe: pipe to wait for
 832  *
 833  * After disabling a pipe, we can't wait for vblank in the usual way,
 834  * spinning on the vblank interrupt status bit, since we won't actually
 835  * see an interrupt when the pipe is disabled.
 836  *
 837  * On Gen4 and above:
 838  *   wait for the pipe register state bit to turn off
 839  *
 840  * Otherwise:
 841  *   wait for the display line value to settle (it usually
 842  *   ends up stopping at the start of the next frame).
 843  *
 844  */
 845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 849                                                                       pipe);
 850
 851         if (INTEL_INFO(dev)->gen >= 4) {
 852                 int reg = PIPECONF(cpu_transcoder);
 853
 854                 /* Wait for the Pipe State to go off */
 855                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 856                              100))
 857                         WARN(1, "pipe_off wait timed out\n");
 858         } else {
 859                 /* Wait for the display line to settle */
 860                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 861                         WARN(1, "pipe_off wait timed out\n");
 862         }
 863 }
 864
 865 /*
 866  * ibx_digital_port_connected - is the specified port connected?
 867  * @dev_priv: i915 private structure
 868  * @port: the port to test
 869  *
 870  * Returns true if @port is connected, false otherwise.
 871  */
 872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 873                                 struct intel_digital_port *port)
 874 {
 875         u32 bit;
 876
 877         if (HAS_PCH_IBX(dev_priv->dev)) {
 878                 switch(port->port) {
 879                 case PORT_B:
 880                         bit = SDE_PORTB_HOTPLUG;
 881                         break;
 882                 case PORT_C:
 883                         bit = SDE_PORTC_HOTPLUG;
 884                         break;
 885                 case PORT_D:
 886                         bit = SDE_PORTD_HOTPLUG;
 887                         break;
 888                 default:
 889                         return true;
 890                 }
 891         } else {
 892                 switch(port->port) {
 893                 case PORT_B:
 894                         bit = SDE_PORTB_HOTPLUG_CPT;
 895                         break;
 896                 case PORT_C:
 897                         bit = SDE_PORTC_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_D:
 900                         bit = SDE_PORTD_HOTPLUG_CPT;
 901                         break;
 902                 default:
 903                         return true;
 904                 }
 905         }
 906
 907         return I915_READ(SDEISR) & bit;
 908 }
 909
 910 static const char *state_string(bool enabled)
 911 {
 912         return enabled ? "on" : "off";
 913 }
 914
 915 /* Only for pre-ILK configs */
 916 void assert_pll(struct drm_i915_private *dev_priv,
 917                 enum pipe pipe, bool state)
 918 {
 919         int reg;
 920         u32 val;
 921         bool cur_state;
 922
 923         reg = DPLL(pipe);
 924         val = I915_READ(reg);
 925         cur_state = !!(val & DPLL_VCO_ENABLE);
 926         WARN(cur_state != state,
 927              "PLL state assertion failure (expected %s, current %s)\n",
 928              state_string(state), state_string(cur_state));
 929 }
 930
 931 /* XXX: the dsi pll is shared between MIPI DSI ports */
 932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 933 {
 934         u32 val;
 935         bool cur_state;
 936
 937         mutex_lock(&dev_priv->dpio_lock);
 938         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 939         mutex_unlock(&dev_priv->dpio_lock);
 940
 941         cur_state = val & DSI_PLL_VCO_EN;
 942         WARN(cur_state != state,
 943              "DSI PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 948
 949 struct intel_shared_dpll *
 950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (crtc->config.shared_dpll < 0)
 955                 return NULL;
 956
 957         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 958 }
 959
 960 /* For ILK+ */
 961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 962                         struct intel_shared_dpll *pll,
 963                         bool state)
 964 {
 965         bool cur_state;
 966         struct intel_dpll_hw_state hw_state;
 967
 968         if (HAS_PCH_LPT(dev_priv->dev)) {
 969                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 970                 return;
 971         }
 972
 973         if (WARN (!pll,
 974                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 975                 return;
 976
 977         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 978         WARN(cur_state != state,
 979              "%s assertion failure (expected %s, current %s)\n",
 980              pll->name, state_string(state), state_string(cur_state));
 981 }
 982
 983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 984                           enum pipe pipe, bool state)
 985 {
 986         int reg;
 987         u32 val;
 988         bool cur_state;
 989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 990                                                                       pipe);
 991
 992         if (HAS_DDI(dev_priv->dev)) {
 993                 /* DDI does not have a specific FDI_TX register */
 994                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 995                 val = I915_READ(reg);
 996                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 997         } else {
 998                 reg = FDI_TX_CTL(pipe);
 999                 val = I915_READ(reg);
1000                 cur_state = !!(val & FDI_TX_ENABLE);
1001         }
1002         WARN(cur_state != state,
1003              "FDI TX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010                           enum pipe pipe, bool state)
1011 {
1012         int reg;
1013         u32 val;
1014         bool cur_state;
1015
1016         reg = FDI_RX_CTL(pipe);
1017         val = I915_READ(reg);
1018         cur_state = !!(val & FDI_RX_ENABLE);
1019         WARN(cur_state != state,
1020              "FDI RX state assertion failure (expected %s, current %s)\n",
1021              state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027                                       enum pipe pipe)
1028 {
1029         int reg;
1030         u32 val;
1031
1032         /* ILK FDI PLL is always enabled */
1033         if (dev_priv->info->gen == 5)
1034                 return;
1035
1036         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037         if (HAS_DDI(dev_priv->dev))
1038                 return;
1039
1040         reg = FDI_TX_CTL(pipe);
1041         val = I915_READ(reg);
1042         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046                        enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = FDI_RX_CTL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055         WARN(cur_state != state,
1056              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061                                   enum pipe pipe)
1062 {
1063         int pp_reg, lvds_reg;
1064         u32 val;
1065         enum pipe panel_pipe = PIPE_A;
1066         bool locked = true;
1067
1068         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069                 pp_reg = PCH_PP_CONTROL;
1070                 lvds_reg = PCH_LVDS;
1071         } else {
1072                 pp_reg = PP_CONTROL;
1073                 lvds_reg = LVDS;
1074         }
1075
1076         val = I915_READ(pp_reg);
1077         if (!(val & PANEL_POWER_ON) ||
1078             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079                 locked = false;
1080
1081         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082                 panel_pipe = PIPE_B;
1083
1084         WARN(panel_pipe == pipe && locked,
1085              "panel assertion failure, pipe %c regs locked\n",
1086              pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090                           enum pipe pipe, bool state)
1091 {
1092         struct drm_device *dev = dev_priv->dev;
1093         bool cur_state;
1094
1095         if (IS_845G(dev) || IS_I865G(dev))
1096                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1097         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1098                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1099         else
1100                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1101
1102         WARN(cur_state != state,
1103              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104              pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110                  enum pipe pipe, bool state)
1111 {
1112         int reg;
1113         u32 val;
1114         bool cur_state;
1115         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116                                                                       pipe);
1117
1118         /* if we need the pipe A quirk it must be always on */
1119         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120                 state = true;
1121
1122         if (!intel_display_power_enabled(dev_priv->dev,
1123                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124                 cur_state = false;
1125         } else {
1126                 reg = PIPECONF(cpu_transcoder);
1127                 val = I915_READ(reg);
1128                 cur_state = !!(val & PIPECONF_ENABLE);
1129         }
1130
1131         WARN(cur_state != state,
1132              "pipe %c assertion failure (expected %s, current %s)\n",
1133              pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137                          enum plane plane, bool state)
1138 {
1139         int reg;
1140         u32 val;
1141         bool cur_state;
1142
1143         reg = DSPCNTR(plane);
1144         val = I915_READ(reg);
1145         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146         WARN(cur_state != state,
1147              "plane %c assertion failure (expected %s, current %s)\n",
1148              plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155                                    enum pipe pipe)
1156 {
1157         struct drm_device *dev = dev_priv->dev;
1158         int reg, i;
1159         u32 val;
1160         int cur_pipe;
1161
1162         /* Primary planes are fixed to pipes on gen4+ */
1163         if (INTEL_INFO(dev)->gen >= 4) {
1164                 reg = DSPCNTR(pipe);
1165                 val = I915_READ(reg);
1166                 WARN((val & DISPLAY_PLANE_ENABLE),
1167                      "plane %c assertion failure, should be disabled but not\n",
1168                      plane_name(pipe));
1169                 return;
1170         }
1171
1172         /* Need to check both planes against the pipe */
1173         for_each_pipe(i) {
1174                 reg = DSPCNTR(i);
1175                 val = I915_READ(reg);
1176                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177                         DISPPLANE_SEL_PIPE_SHIFT;
1178                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180                      plane_name(i), pipe_name(pipe));
1181         }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185                                     enum pipe pipe)
1186 {
1187         struct drm_device *dev = dev_priv->dev;
1188         int reg, i;
1189         u32 val;
1190
1191         if (IS_VALLEYVIEW(dev)) {
1192                 for (i = 0; i < dev_priv->num_plane; i++) {
1193                         reg = SPCNTR(pipe, i);
1194                         val = I915_READ(reg);
1195                         WARN((val & SP_ENABLE),
1196                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197                              sprite_name(pipe, i), pipe_name(pipe));
1198                 }
1199         } else if (INTEL_INFO(dev)->gen >= 7) {
1200                 reg = SPRCTL(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & SPRITE_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         } else if (INTEL_INFO(dev)->gen >= 5) {
1206                 reg = DVSCNTR(pipe);
1207                 val = I915_READ(reg);
1208                 WARN((val & DVS_ENABLE),
1209                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210                      plane_name(pipe), pipe_name(pipe));
1211         }
1212 }
1213
1214 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216         u32 val;
1217         bool enabled;
1218
1219         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1220
1221         val = I915_READ(PCH_DREF_CONTROL);
1222         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1223                             DREF_SUPERSPREAD_SOURCE_MASK));
1224         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1225 }
1226
1227 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1228                                            enum pipe pipe)
1229 {
1230         int reg;
1231         u32 val;
1232         bool enabled;
1233
1234         reg = PCH_TRANSCONF(pipe);
1235         val = I915_READ(reg);
1236         enabled = !!(val & TRANS_ENABLE);
1237         WARN(enabled,
1238              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239              pipe_name(pipe));
1240 }
1241
1242 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1243                             enum pipe pipe, u32 port_sel, u32 val)
1244 {
1245         if ((val & DP_PORT_EN) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1250                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1251                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1252                         return false;
1253         } else {
1254                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1255                         return false;
1256         }
1257         return true;
1258 }
1259
1260 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1261                               enum pipe pipe, u32 val)
1262 {
1263         if ((val & SDVO_ENABLE) == 0)
1264                 return false;
1265
1266         if (HAS_PCH_CPT(dev_priv->dev)) {
1267                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1268                         return false;
1269         } else {
1270                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1271                         return false;
1272         }
1273         return true;
1274 }
1275
1276 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1277                               enum pipe pipe, u32 val)
1278 {
1279         if ((val & LVDS_PORT_EN) == 0)
1280                 return false;
1281
1282         if (HAS_PCH_CPT(dev_priv->dev)) {
1283                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284                         return false;
1285         } else {
1286                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1287                         return false;
1288         }
1289         return true;
1290 }
1291
1292 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1293                               enum pipe pipe, u32 val)
1294 {
1295         if ((val & ADPA_DAC_ENABLE) == 0)
1296                 return false;
1297         if (HAS_PCH_CPT(dev_priv->dev)) {
1298                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1299                         return false;
1300         } else {
1301                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1302                         return false;
1303         }
1304         return true;
1305 }
1306
1307 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1308                                    enum pipe pipe, int reg, u32 port_sel)
1309 {
1310         u32 val = I915_READ(reg);
1311         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1312              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1313              reg, pipe_name(pipe));
1314
1315         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1316              && (val & DP_PIPEB_SELECT),
1317              "IBX PCH dp port still using transcoder B\n");
1318 }
1319
1320 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1321                                      enum pipe pipe, int reg)
1322 {
1323         u32 val = I915_READ(reg);
1324         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1325              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1326              reg, pipe_name(pipe));
1327
1328         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1329              && (val & SDVO_PIPE_B_SELECT),
1330              "IBX PCH hdmi port still using transcoder B\n");
1331 }
1332
1333 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1334                                       enum pipe pipe)
1335 {
1336         int reg;
1337         u32 val;
1338
1339         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1340         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1341         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1342
1343         reg = PCH_ADPA;
1344         val = I915_READ(reg);
1345         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1346              "PCH VGA enabled on transcoder %c, should be disabled\n",
1347              pipe_name(pipe));
1348
1349         reg = PCH_LVDS;
1350         val = I915_READ(reg);
1351         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1352              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1353              pipe_name(pipe));
1354
1355         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1356         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1357         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1358 }
1359
1360 static void intel_init_dpio(struct drm_device *dev)
1361 {
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363
1364         if (!IS_VALLEYVIEW(dev))
1365                 return;
1366
1367         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1368 }
1369
1370 static void intel_reset_dpio(struct drm_device *dev)
1371 {
1372         struct drm_i915_private *dev_priv = dev->dev_private;
1373
1374         if (!IS_VALLEYVIEW(dev))
1375                 return;
1376
1377         /*
1378          * Enable the CRI clock source so we can get at the display and the
1379          * reference clock for VGA hotplug / manual detection.
1380          */
1381         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1382                    DPLL_REFA_CLK_ENABLE_VLV |
1383                    DPLL_INTEGRATED_CRI_CLK_VLV);
1384
1385         /*
1386          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1387          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1388          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1389          *   b. The other bits such as sfr settings / modesel may all be set
1390          *      to 0.
1391          *
1392          * This should only be done on init and resume from S3 with both
1393          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1394          */
1395         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1396 }
1397
1398 static void vlv_enable_pll(struct intel_crtc *crtc)
1399 {
1400         struct drm_device *dev = crtc->base.dev;
1401         struct drm_i915_private *dev_priv = dev->dev_private;
1402         int reg = DPLL(crtc->pipe);
1403         u32 dpll = crtc->config.dpll_hw_state.dpll;
1404
1405         assert_pipe_disabled(dev_priv, crtc->pipe);
1406
1407         /* No really, not for ILK+ */
1408         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1409
1410         /* PLL is protected by panel, make sure we can write it */
1411         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1412                 assert_panel_unlocked(dev_priv, crtc->pipe);
1413
1414         I915_WRITE(reg, dpll);
1415         POSTING_READ(reg);
1416         udelay(150);
1417
1418         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1419                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1420
1421         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1422         POSTING_READ(DPLL_MD(crtc->pipe));
1423
1424         /* We do this three times for luck */
1425         I915_WRITE(reg, dpll);
1426         POSTING_READ(reg);
1427         udelay(150); /* wait for warmup */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434 }
1435
1436 static void i9xx_enable_pll(struct intel_crtc *crtc)
1437 {
1438         struct drm_device *dev = crtc->base.dev;
1439         struct drm_i915_private *dev_priv = dev->dev_private;
1440         int reg = DPLL(crtc->pipe);
1441         u32 dpll = crtc->config.dpll_hw_state.dpll;
1442
1443         assert_pipe_disabled(dev_priv, crtc->pipe);
1444
1445         /* No really, not for ILK+ */
1446         BUG_ON(dev_priv->info->gen >= 5);
1447
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev) && !IS_I830(dev))
1450                 assert_panel_unlocked(dev_priv, crtc->pipe);
1451
1452         I915_WRITE(reg, dpll);
1453
1454         /* Wait for the clocks to stabilize. */
1455         POSTING_READ(reg);
1456         udelay(150);
1457
1458         if (INTEL_INFO(dev)->gen >= 4) {
1459                 I915_WRITE(DPLL_MD(crtc->pipe),
1460                            crtc->config.dpll_hw_state.dpll_md);
1461         } else {
1462                 /* The pixel multiplier can only be updated once the
1463                  * DPLL is enabled and the clocks are stable.
1464                  *
1465                  * So write it again.
1466                  */
1467                 I915_WRITE(reg, dpll);
1468         }
1469
1470         /* We do this three times for luck */
1471         I915_WRITE(reg, dpll);
1472         POSTING_READ(reg);
1473         udelay(150); /* wait for warmup */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480 }
1481
1482 /**
1483  * i9xx_disable_pll - disable a PLL
1484  * @dev_priv: i915 private structure
1485  * @pipe: pipe PLL to disable
1486  *
1487  * Disable the PLL for @pipe, making sure the pipe is off first.
1488  *
1489  * Note!  This is for pre-ILK only.
1490  */
1491 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1492 {
1493         /* Don't disable pipe A or pipe A PLLs if needed */
1494         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495                 return;
1496
1497         /* Make sure the pipe isn't still relying on us */
1498         assert_pipe_disabled(dev_priv, pipe);
1499
1500         I915_WRITE(DPLL(pipe), 0);
1501         POSTING_READ(DPLL(pipe));
1502 }
1503
1504 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1505 {
1506         u32 val = 0;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         /*
1512          * Leave integrated clock source and reference clock enabled for pipe B.
1513          * The latter is needed for VGA hotplug / manual detection.
1514          */
1515         if (pipe == PIPE_B)
1516                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1517         I915_WRITE(DPLL(pipe), val);
1518         POSTING_READ(DPLL(pipe));
1519 }
1520
1521 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1522                 struct intel_digital_port *dport)
1523 {
1524         u32 port_mask;
1525
1526         switch (dport->port) {
1527         case PORT_B:
1528                 port_mask = DPLL_PORTB_READY_MASK;
1529                 break;
1530         case PORT_C:
1531                 port_mask = DPLL_PORTC_READY_MASK;
1532                 break;
1533         default:
1534                 BUG();
1535         }
1536
1537         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1538                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1539                      port_name(dport->port), I915_READ(DPLL(0)));
1540 }
1541
1542 /**
1543  * ironlake_enable_shared_dpll - enable PCH PLL
1544  * @dev_priv: i915 private structure
1545  * @pipe: pipe PLL to enable
1546  *
1547  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1548  * drives the transcoder clock.
1549  */
1550 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1551 {
1552         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1553         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1554
1555         /* PCH PLLs only available on ILK, SNB and IVB */
1556         BUG_ON(dev_priv->info->gen < 5);
1557         if (WARN_ON(pll == NULL))
1558                 return;
1559
1560         if (WARN_ON(pll->refcount == 0))
1561                 return;
1562
1563         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1564                       pll->name, pll->active, pll->on,
1565                       crtc->base.base.id);
1566
1567         if (pll->active++) {
1568                 WARN_ON(!pll->on);
1569                 assert_shared_dpll_enabled(dev_priv, pll);
1570                 return;
1571         }
1572         WARN_ON(pll->on);
1573
1574         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1575         pll->enable(dev_priv, pll);
1576         pll->on = true;
1577 }
1578
1579 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1580 {
1581         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1582         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1583
1584         /* PCH only available on ILK+ */
1585         BUG_ON(dev_priv->info->gen < 5);
1586         if (WARN_ON(pll == NULL))
1587                return;
1588
1589         if (WARN_ON(pll->refcount == 0))
1590                 return;
1591
1592         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1593                       pll->name, pll->active, pll->on,
1594                       crtc->base.base.id);
1595
1596         if (WARN_ON(pll->active == 0)) {
1597                 assert_shared_dpll_disabled(dev_priv, pll);
1598                 return;
1599         }
1600
1601         assert_shared_dpll_enabled(dev_priv, pll);
1602         WARN_ON(!pll->on);
1603         if (--pll->active)
1604                 return;
1605
1606         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1607         pll->disable(dev_priv, pll);
1608         pll->on = false;
1609 }
1610
1611 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1612                                            enum pipe pipe)
1613 {
1614         struct drm_device *dev = dev_priv->dev;
1615         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1617         uint32_t reg, val, pipeconf_val;
1618
1619         /* PCH only available on ILK+ */
1620         BUG_ON(dev_priv->info->gen < 5);
1621
1622         /* Make sure PCH DPLL is enabled */
1623         assert_shared_dpll_enabled(dev_priv,
1624                                    intel_crtc_to_shared_dpll(intel_crtc));
1625
1626         /* FDI must be feeding us bits for PCH ports */
1627         assert_fdi_tx_enabled(dev_priv, pipe);
1628         assert_fdi_rx_enabled(dev_priv, pipe);
1629
1630         if (HAS_PCH_CPT(dev)) {
1631                 /* Workaround: Set the timing override bit before enabling the
1632                  * pch transcoder. */
1633                 reg = TRANS_CHICKEN2(pipe);
1634                 val = I915_READ(reg);
1635                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1636                 I915_WRITE(reg, val);
1637         }
1638
1639         reg = PCH_TRANSCONF(pipe);
1640         val = I915_READ(reg);
1641         pipeconf_val = I915_READ(PIPECONF(pipe));
1642
1643         if (HAS_PCH_IBX(dev_priv->dev)) {
1644                 /*
1645                  * make the BPC in transcoder be consistent with
1646                  * that in pipeconf reg.
1647                  */
1648                 val &= ~PIPECONF_BPC_MASK;
1649                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1650         }
1651
1652         val &= ~TRANS_INTERLACE_MASK;
1653         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1654                 if (HAS_PCH_IBX(dev_priv->dev) &&
1655                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1656                         val |= TRANS_LEGACY_INTERLACED_ILK;
1657                 else
1658                         val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(reg, val | TRANS_ENABLE);
1663         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1665 }
1666
1667 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                       enum transcoder cpu_transcoder)
1669 {
1670         u32 val, pipeconf_val;
1671
1672         /* PCH only available on ILK+ */
1673         BUG_ON(dev_priv->info->gen < 5);
1674
1675         /* FDI must be feeding us bits for PCH ports */
1676         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1677         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1678
1679         /* Workaround: set timing override bit. */
1680         val = I915_READ(_TRANSA_CHICKEN2);
1681         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1682         I915_WRITE(_TRANSA_CHICKEN2, val);
1683
1684         val = TRANS_ENABLE;
1685         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1686
1687         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1688             PIPECONF_INTERLACED_ILK)
1689                 val |= TRANS_INTERLACED;
1690         else
1691                 val |= TRANS_PROGRESSIVE;
1692
1693         I915_WRITE(LPT_TRANSCONF, val);
1694         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1695                 DRM_ERROR("Failed to enable PCH transcoder\n");
1696 }
1697
1698 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1699                                             enum pipe pipe)
1700 {
1701         struct drm_device *dev = dev_priv->dev;
1702         uint32_t reg, val;
1703
1704         /* FDI relies on the transcoder */
1705         assert_fdi_tx_disabled(dev_priv, pipe);
1706         assert_fdi_rx_disabled(dev_priv, pipe);
1707
1708         /* Ports must be off as well */
1709         assert_pch_ports_disabled(dev_priv, pipe);
1710
1711         reg = PCH_TRANSCONF(pipe);
1712         val = I915_READ(reg);
1713         val &= ~TRANS_ENABLE;
1714         I915_WRITE(reg, val);
1715         /* wait for PCH transcoder off, transcoder state */
1716         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1717                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1718
1719         if (!HAS_PCH_IBX(dev)) {
1720                 /* Workaround: Clear the timing override chicken bit again. */
1721                 reg = TRANS_CHICKEN2(pipe);
1722                 val = I915_READ(reg);
1723                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1724                 I915_WRITE(reg, val);
1725         }
1726 }
1727
1728 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1729 {
1730         u32 val;
1731
1732         val = I915_READ(LPT_TRANSCONF);
1733         val &= ~TRANS_ENABLE;
1734         I915_WRITE(LPT_TRANSCONF, val);
1735         /* wait for PCH transcoder off, transcoder state */
1736         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1737                 DRM_ERROR("Failed to disable PCH transcoder\n");
1738
1739         /* Workaround: clear timing override bit. */
1740         val = I915_READ(_TRANSA_CHICKEN2);
1741         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1742         I915_WRITE(_TRANSA_CHICKEN2, val);
1743 }
1744
1745 /**
1746  * intel_enable_pipe - enable a pipe, asserting requirements
1747  * @dev_priv: i915 private structure
1748  * @pipe: pipe to enable
1749  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1750  *
1751  * Enable @pipe, making sure that various hardware specific requirements
1752  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1753  *
1754  * @pipe should be %PIPE_A or %PIPE_B.
1755  *
1756  * Will wait until the pipe is actually running (i.e. first vblank) before
1757  * returning.
1758  */
1759 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1760                               bool pch_port, bool dsi)
1761 {
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (dsi)
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (pch_port) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE)
1800                 return;
1801
1802         I915_WRITE(reg, val | PIPECONF_ENABLE);
1803         intel_wait_for_vblank(dev_priv->dev, pipe);
1804 }
1805
1806 /**
1807  * intel_disable_pipe - disable a pipe, asserting requirements
1808  * @dev_priv: i915 private structure
1809  * @pipe: pipe to disable
1810  *
1811  * Disable @pipe, making sure that various hardware specific requirements
1812  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1813  *
1814  * @pipe should be %PIPE_A or %PIPE_B.
1815  *
1816  * Will wait until the pipe has shut down before returning.
1817  */
1818 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1819                                enum pipe pipe)
1820 {
1821         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1822                                                                       pipe);
1823         int reg;
1824         u32 val;
1825
1826         /*
1827          * Make sure planes won't keep trying to pump pixels to us,
1828          * or we might hang the display.
1829          */
1830         assert_planes_disabled(dev_priv, pipe);
1831         assert_cursor_disabled(dev_priv, pipe);
1832         assert_sprites_disabled(dev_priv, pipe);
1833
1834         /* Don't disable pipe A or pipe A PLLs if needed */
1835         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1836                 return;
1837
1838         reg = PIPECONF(cpu_transcoder);
1839         val = I915_READ(reg);
1840         if ((val & PIPECONF_ENABLE) == 0)
1841                 return;
1842
1843         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1844         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1845 }
1846
1847 /*
1848  * Plane regs are double buffered, going from enabled->disabled needs a
1849  * trigger in order to latch.  The display address reg provides this.
1850  */
1851 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1852                                enum plane plane)
1853 {
1854         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1855
1856         I915_WRITE(reg, I915_READ(reg));
1857         POSTING_READ(reg);
1858 }
1859
1860 /**
1861  * intel_enable_primary_plane - enable the primary plane on a given pipe
1862  * @dev_priv: i915 private structure
1863  * @plane: plane to enable
1864  * @pipe: pipe being fed
1865  *
1866  * Enable @plane on @pipe, making sure that @pipe is running first.
1867  */
1868 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1869                                        enum plane plane, enum pipe pipe)
1870 {
1871         struct intel_crtc *intel_crtc =
1872                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1873         int reg;
1874         u32 val;
1875
1876         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1877         assert_pipe_enabled(dev_priv, pipe);
1878
1879         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1880
1881         intel_crtc->primary_enabled = true;
1882
1883         reg = DSPCNTR(plane);
1884         val = I915_READ(reg);
1885         if (val & DISPLAY_PLANE_ENABLE)
1886                 return;
1887
1888         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1889         intel_flush_primary_plane(dev_priv, plane);
1890         intel_wait_for_vblank(dev_priv->dev, pipe);
1891 }
1892
1893 /**
1894  * intel_disable_primary_plane - disable the primary plane
1895  * @dev_priv: i915 private structure
1896  * @plane: plane to disable
1897  * @pipe: pipe consuming the data
1898  *
1899  * Disable @plane; should be an independent operation.
1900  */
1901 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1902                                         enum plane plane, enum pipe pipe)
1903 {
1904         struct intel_crtc *intel_crtc =
1905                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1906         int reg;
1907         u32 val;
1908
1909         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1910
1911         intel_crtc->primary_enabled = false;
1912
1913         reg = DSPCNTR(plane);
1914         val = I915_READ(reg);
1915         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1916                 return;
1917
1918         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1919         intel_flush_primary_plane(dev_priv, plane);
1920         intel_wait_for_vblank(dev_priv->dev, pipe);
1921 }
1922
1923 static bool need_vtd_wa(struct drm_device *dev)
1924 {
1925 #ifdef CONFIG_INTEL_IOMMU
1926         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1927                 return true;
1928 #endif
1929         return false;
1930 }
1931
1932 int
1933 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1934                            struct drm_i915_gem_object *obj,
1935                            struct intel_ring_buffer *pipelined)
1936 {
1937         struct drm_i915_private *dev_priv = dev->dev_private;
1938         u32 alignment;
1939         int ret;
1940
1941         switch (obj->tiling_mode) {
1942         case I915_TILING_NONE:
1943                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1944                         alignment = 128 * 1024;
1945                 else if (INTEL_INFO(dev)->gen >= 4)
1946                         alignment = 4 * 1024;
1947                 else
1948                         alignment = 64 * 1024;
1949                 break;
1950         case I915_TILING_X:
1951                 /* pin() will align the object as required by fence */
1952                 alignment = 0;
1953                 break;
1954         case I915_TILING_Y:
1955                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1956                 return -EINVAL;
1957         default:
1958                 BUG();
1959         }
1960
1961         /* Note that the w/a also requires 64 PTE of padding following the
1962          * bo. We currently fill all unused PTE with the shadow page and so
1963          * we should always have valid PTE following the scanout preventing
1964          * the VT-d warning.
1965          */
1966         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1967                 alignment = 256 * 1024;
1968
1969         dev_priv->mm.interruptible = false;
1970         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1971         if (ret)
1972                 goto err_interruptible;
1973
1974         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1975          * fence, whereas 965+ only requires a fence if using
1976          * framebuffer compression.  For simplicity, we always install
1977          * a fence as the cost is not that onerous.
1978          */
1979         ret = i915_gem_object_get_fence(obj);
1980         if (ret)
1981                 goto err_unpin;
1982
1983         i915_gem_object_pin_fence(obj);
1984
1985         dev_priv->mm.interruptible = true;
1986         return 0;
1987
1988 err_unpin:
1989         i915_gem_object_unpin_from_display_plane(obj);
1990 err_interruptible:
1991         dev_priv->mm.interruptible = true;
1992         return ret;
1993 }
1994
1995 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1996 {
1997         i915_gem_object_unpin_fence(obj);
1998         i915_gem_object_unpin_from_display_plane(obj);
1999 }
2000
2001 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2002  * is assumed to be a power-of-two. */
2003 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2004                                              unsigned int tiling_mode,
2005                                              unsigned int cpp,
2006                                              unsigned int pitch)
2007 {
2008         if (tiling_mode != I915_TILING_NONE) {
2009                 unsigned int tile_rows, tiles;
2010
2011                 tile_rows = *y / 8;
2012                 *y %= 8;
2013
2014                 tiles = *x / (512/cpp);
2015                 *x %= 512/cpp;
2016
2017                 return tile_rows * pitch * 8 + tiles * 4096;
2018         } else {
2019                 unsigned int offset;
2020
2021                 offset = *y * pitch + *x * cpp;
2022                 *y = 0;
2023                 *x = (offset & 4095) / cpp;
2024                 return offset & -4096;
2025         }
2026 }
2027
2028 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2029                              int x, int y)
2030 {
2031         struct drm_device *dev = crtc->dev;
2032         struct drm_i915_private *dev_priv = dev->dev_private;
2033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2034         struct intel_framebuffer *intel_fb;
2035         struct drm_i915_gem_object *obj;
2036         int plane = intel_crtc->plane;
2037         unsigned long linear_offset;
2038         u32 dspcntr;
2039         u32 reg;
2040
2041         switch (plane) {
2042         case 0:
2043         case 1:
2044                 break;
2045         default:
2046                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2047                 return -EINVAL;
2048         }
2049
2050         intel_fb = to_intel_framebuffer(fb);
2051         obj = intel_fb->obj;
2052
2053         reg = DSPCNTR(plane);
2054         dspcntr = I915_READ(reg);
2055         /* Mask out pixel format bits in case we change it */
2056         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2057         switch (fb->pixel_format) {
2058         case DRM_FORMAT_C8:
2059                 dspcntr |= DISPPLANE_8BPP;
2060                 break;
2061         case DRM_FORMAT_XRGB1555:
2062         case DRM_FORMAT_ARGB1555:
2063                 dspcntr |= DISPPLANE_BGRX555;
2064                 break;
2065         case DRM_FORMAT_RGB565:
2066                 dspcntr |= DISPPLANE_BGRX565;
2067                 break;
2068         case DRM_FORMAT_XRGB8888:
2069         case DRM_FORMAT_ARGB8888:
2070                 dspcntr |= DISPPLANE_BGRX888;
2071                 break;
2072         case DRM_FORMAT_XBGR8888:
2073         case DRM_FORMAT_ABGR8888:
2074                 dspcntr |= DISPPLANE_RGBX888;
2075                 break;
2076         case DRM_FORMAT_XRGB2101010:
2077         case DRM_FORMAT_ARGB2101010:
2078                 dspcntr |= DISPPLANE_BGRX101010;
2079                 break;
2080         case DRM_FORMAT_XBGR2101010:
2081         case DRM_FORMAT_ABGR2101010:
2082                 dspcntr |= DISPPLANE_RGBX101010;
2083                 break;
2084         default:
2085                 BUG();
2086         }
2087
2088         if (INTEL_INFO(dev)->gen >= 4) {
2089                 if (obj->tiling_mode != I915_TILING_NONE)
2090                         dspcntr |= DISPPLANE_TILED;
2091                 else
2092                         dspcntr &= ~DISPPLANE_TILED;
2093         }
2094
2095         if (IS_G4X(dev))
2096                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101
2102         if (INTEL_INFO(dev)->gen >= 4) {
2103                 intel_crtc->dspaddr_offset =
2104                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2105                                                        fb->bits_per_pixel / 8,
2106                                                        fb->pitches[0]);
2107                 linear_offset -= intel_crtc->dspaddr_offset;
2108         } else {
2109                 intel_crtc->dspaddr_offset = linear_offset;
2110         }
2111
2112         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2113                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2114                       fb->pitches[0]);
2115         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2116         if (INTEL_INFO(dev)->gen >= 4) {
2117                 I915_WRITE(DSPSURF(plane),
2118                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2119                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2120                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2121         } else
2122                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2123         POSTING_READ(reg);
2124
2125         return 0;
2126 }
2127
2128 static int ironlake_update_plane(struct drm_crtc *crtc,
2129                                  struct drm_framebuffer *fb, int x, int y)
2130 {
2131         struct drm_device *dev = crtc->dev;
2132         struct drm_i915_private *dev_priv = dev->dev_private;
2133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134         struct intel_framebuffer *intel_fb;
2135         struct drm_i915_gem_object *obj;
2136         int plane = intel_crtc->plane;
2137         unsigned long linear_offset;
2138         u32 dspcntr;
2139         u32 reg;
2140
2141         switch (plane) {
2142         case 0:
2143         case 1:
2144         case 2:
2145                 break;
2146         default:
2147                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2148                 return -EINVAL;
2149         }
2150
2151         intel_fb = to_intel_framebuffer(fb);
2152         obj = intel_fb->obj;
2153
2154         reg = DSPCNTR(plane);
2155         dspcntr = I915_READ(reg);
2156         /* Mask out pixel format bits in case we change it */
2157         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2158         switch (fb->pixel_format) {
2159         case DRM_FORMAT_C8:
2160                 dspcntr |= DISPPLANE_8BPP;
2161                 break;
2162         case DRM_FORMAT_RGB565:
2163                 dspcntr |= DISPPLANE_BGRX565;
2164                 break;
2165         case DRM_FORMAT_XRGB8888:
2166         case DRM_FORMAT_ARGB8888:
2167                 dspcntr |= DISPPLANE_BGRX888;
2168                 break;
2169         case DRM_FORMAT_XBGR8888:
2170         case DRM_FORMAT_ABGR8888:
2171                 dspcntr |= DISPPLANE_RGBX888;
2172                 break;
2173         case DRM_FORMAT_XRGB2101010:
2174         case DRM_FORMAT_ARGB2101010:
2175                 dspcntr |= DISPPLANE_BGRX101010;
2176                 break;
2177         case DRM_FORMAT_XBGR2101010:
2178         case DRM_FORMAT_ABGR2101010:
2179                 dspcntr |= DISPPLANE_RGBX101010;
2180                 break;
2181         default:
2182                 BUG();
2183         }
2184
2185         if (obj->tiling_mode != I915_TILING_NONE)
2186                 dspcntr |= DISPPLANE_TILED;
2187         else
2188                 dspcntr &= ~DISPPLANE_TILED;
2189
2190         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2191                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2192         else
2193                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2194
2195         I915_WRITE(reg, dspcntr);
2196
2197         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2198         intel_crtc->dspaddr_offset =
2199                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2200                                                fb->bits_per_pixel / 8,
2201                                                fb->pitches[0]);
2202         linear_offset -= intel_crtc->dspaddr_offset;
2203
2204         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2206                       fb->pitches[0]);
2207         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2208         I915_WRITE(DSPSURF(plane),
2209                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2210         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2211                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2212         } else {
2213                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2215         }
2216         POSTING_READ(reg);
2217
2218         return 0;
2219 }
2220
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2222 static int
2223 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224                            int x, int y, enum mode_set_atomic state)
2225 {
2226         struct drm_device *dev = crtc->dev;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228
2229         if (dev_priv->display.disable_fbc)
2230                 dev_priv->display.disable_fbc(dev);
2231         intel_increase_pllclock(crtc);
2232
2233         return dev_priv->display.update_plane(crtc, fb, x, y);
2234 }
2235
2236 void intel_display_handle_reset(struct drm_device *dev)
2237 {
2238         struct drm_i915_private *dev_priv = dev->dev_private;
2239         struct drm_crtc *crtc;
2240
2241         /*
2242          * Flips in the rings have been nuked by the reset,
2243          * so complete all pending flips so that user space
2244          * will get its events and not get stuck.
2245          *
2246          * Also update the base address of all primary
2247          * planes to the the last fb to make sure we're
2248          * showing the correct fb after a reset.
2249          *
2250          * Need to make two loops over the crtcs so that we
2251          * don't try to grab a crtc mutex before the
2252          * pending_flip_queue really got woken up.
2253          */
2254
2255         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2256                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257                 enum plane plane = intel_crtc->plane;
2258
2259                 intel_prepare_page_flip(dev, plane);
2260                 intel_finish_page_flip_plane(dev, plane);
2261         }
2262
2263         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2264                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266                 mutex_lock(&crtc->mutex);
2267                 /*
2268                  * FIXME: Once we have proper support for primary planes (and
2269                  * disabling them without disabling the entire crtc) allow again
2270                  * a NULL crtc->fb.
2271                  */
2272                 if (intel_crtc->active && crtc->fb)
2273                         dev_priv->display.update_plane(crtc, crtc->fb,
2274                                                        crtc->x, crtc->y);
2275                 mutex_unlock(&crtc->mutex);
2276         }
2277 }
2278
2279 static int
2280 intel_finish_fb(struct drm_framebuffer *old_fb)
2281 {
2282         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2283         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2284         bool was_interruptible = dev_priv->mm.interruptible;
2285         int ret;
2286
2287         /* Big Hammer, we also need to ensure that any pending
2288          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2289          * current scanout is retired before unpinning the old
2290          * framebuffer.
2291          *
2292          * This should only fail upon a hung GPU, in which case we
2293          * can safely continue.
2294          */
2295         dev_priv->mm.interruptible = false;
2296         ret = i915_gem_object_finish_gpu(obj);
2297         dev_priv->mm.interruptible = was_interruptible;
2298
2299         return ret;
2300 }
2301
2302 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2303 {
2304         struct drm_device *dev = crtc->dev;
2305         struct drm_i915_master_private *master_priv;
2306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307
2308         if (!dev->primary->master)
2309                 return;
2310
2311         master_priv = dev->primary->master->driver_priv;
2312         if (!master_priv->sarea_priv)
2313                 return;
2314
2315         switch (intel_crtc->pipe) {
2316         case 0:
2317                 master_priv->sarea_priv->pipeA_x = x;
2318                 master_priv->sarea_priv->pipeA_y = y;
2319                 break;
2320         case 1:
2321                 master_priv->sarea_priv->pipeB_x = x;
2322                 master_priv->sarea_priv->pipeB_y = y;
2323                 break;
2324         default:
2325                 break;
2326         }
2327 }
2328
2329 static int
2330 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2331                     struct drm_framebuffer *fb)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         struct drm_framebuffer *old_fb;
2337         int ret;
2338
2339         /* no fb bound */
2340         if (!fb) {
2341                 DRM_ERROR("No FB bound\n");
2342                 return 0;
2343         }
2344
2345         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2346                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2347                           plane_name(intel_crtc->plane),
2348                           INTEL_INFO(dev)->num_pipes);
2349                 return -EINVAL;
2350         }
2351
2352         mutex_lock(&dev->struct_mutex);
2353         ret = intel_pin_and_fence_fb_obj(dev,
2354                                          to_intel_framebuffer(fb)->obj,
2355                                          NULL);
2356         if (ret != 0) {
2357                 mutex_unlock(&dev->struct_mutex);
2358                 DRM_ERROR("pin & fence failed\n");
2359                 return ret;
2360         }
2361
2362         /*
2363          * Update pipe size and adjust fitter if needed: the reason for this is
2364          * that in compute_mode_changes we check the native mode (not the pfit
2365          * mode) to see if we can flip rather than do a full mode set. In the
2366          * fastboot case, we'll flip, but if we don't update the pipesrc and
2367          * pfit state, we'll end up with a big fb scanned out into the wrong
2368          * sized surface.
2369          *
2370          * To fix this properly, we need to hoist the checks up into
2371          * compute_mode_changes (or above), check the actual pfit state and
2372          * whether the platform allows pfit disable with pipe active, and only
2373          * then update the pipesrc and pfit state, even on the flip path.
2374          */
2375         if (i915_fastboot) {
2376                 const struct drm_display_mode *adjusted_mode =
2377                         &intel_crtc->config.adjusted_mode;
2378
2379                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2380                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2381                            (adjusted_mode->crtc_vdisplay - 1));
2382                 if (!intel_crtc->config.pch_pfit.enabled &&
2383                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2384                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2385                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2386                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2387                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2388                 }
2389                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2390                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2391         }
2392
2393         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2394         if (ret) {
2395                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2396                 mutex_unlock(&dev->struct_mutex);
2397                 DRM_ERROR("failed to update base address\n");
2398                 return ret;
2399         }
2400
2401         old_fb = crtc->fb;
2402         crtc->fb = fb;
2403         crtc->x = x;
2404         crtc->y = y;
2405
2406         if (old_fb) {
2407                 if (intel_crtc->active && old_fb != fb)
2408                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2409                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2410         }
2411
2412         intel_update_fbc(dev);
2413         intel_edp_psr_update(dev);
2414         mutex_unlock(&dev->struct_mutex);
2415
2416         intel_crtc_update_sarea_pos(crtc, x, y);
2417
2418         return 0;
2419 }
2420
2421 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2422 {
2423         struct drm_device *dev = crtc->dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426         int pipe = intel_crtc->pipe;
2427         u32 reg, temp;
2428
2429         /* enable normal train */
2430         reg = FDI_TX_CTL(pipe);
2431         temp = I915_READ(reg);
2432         if (IS_IVYBRIDGE(dev)) {
2433                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2434                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2435         } else {
2436                 temp &= ~FDI_LINK_TRAIN_NONE;
2437                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2438         }
2439         I915_WRITE(reg, temp);
2440
2441         reg = FDI_RX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         if (HAS_PCH_CPT(dev)) {
2444                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2446         } else {
2447                 temp &= ~FDI_LINK_TRAIN_NONE;
2448                 temp |= FDI_LINK_TRAIN_NONE;
2449         }
2450         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2451
2452         /* wait one idle pattern time */
2453         POSTING_READ(reg);
2454         udelay(1000);
2455
2456         /* IVB wants error correction enabled */
2457         if (IS_IVYBRIDGE(dev))
2458                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2459                            FDI_FE_ERRC_ENABLE);
2460 }
2461
2462 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2463 {
2464         return crtc->base.enabled && crtc->active &&
2465                 crtc->config.has_pch_encoder;
2466 }
2467
2468 static void ivb_modeset_global_resources(struct drm_device *dev)
2469 {
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct intel_crtc *pipe_B_crtc =
2472                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473         struct intel_crtc *pipe_C_crtc =
2474                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475         uint32_t temp;
2476
2477         /*
2478          * When everything is off disable fdi C so that we could enable fdi B
2479          * with all lanes. Note that we don't care about enabled pipes without
2480          * an enabled pch encoder.
2481          */
2482         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2483             !pipe_has_enabled_pch(pipe_C_crtc)) {
2484                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2485                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2486
2487                 temp = I915_READ(SOUTH_CHICKEN1);
2488                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2489                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2490                 I915_WRITE(SOUTH_CHICKEN1, temp);
2491         }
2492 }
2493
2494 /* The FDI link training functions for ILK/Ibexpeak. */
2495 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2496 {
2497         struct drm_device *dev = crtc->dev;
2498         struct drm_i915_private *dev_priv = dev->dev_private;
2499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500         int pipe = intel_crtc->pipe;
2501         int plane = intel_crtc->plane;
2502         u32 reg, temp, tries;
2503
2504         /* FDI needs bits from pipe & plane first */
2505         assert_pipe_enabled(dev_priv, pipe);
2506         assert_plane_enabled(dev_priv, plane);
2507
2508         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509            for train result */
2510         reg = FDI_RX_IMR(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_RX_SYMBOL_LOCK;
2513         temp &= ~FDI_RX_BIT_LOCK;
2514         I915_WRITE(reg, temp);
2515         I915_READ(reg);
2516         udelay(150);
2517
2518         /* enable CPU FDI TX and PCH FDI RX */
2519         reg = FDI_TX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2522         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2523         temp &= ~FDI_LINK_TRAIN_NONE;
2524         temp |= FDI_LINK_TRAIN_PATTERN_1;
2525         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2526
2527         reg = FDI_RX_CTL(pipe);
2528         temp = I915_READ(reg);
2529         temp &= ~FDI_LINK_TRAIN_NONE;
2530         temp |= FDI_LINK_TRAIN_PATTERN_1;
2531         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2532
2533         POSTING_READ(reg);
2534         udelay(150);
2535
2536         /* Ironlake workaround, enable clock pointer after FDI enable*/
2537         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2538         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2539                    FDI_RX_PHASE_SYNC_POINTER_EN);
2540
2541         reg = FDI_RX_IIR(pipe);
2542         for (tries = 0; tries < 5; tries++) {
2543                 temp = I915_READ(reg);
2544                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545
2546                 if ((temp & FDI_RX_BIT_LOCK)) {
2547                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2548                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2549                         break;
2550                 }
2551         }
2552         if (tries == 5)
2553                 DRM_ERROR("FDI train 1 fail!\n");
2554
2555         /* Train 2 */
2556         reg = FDI_TX_CTL(pipe);
2557         temp = I915_READ(reg);
2558         temp &= ~FDI_LINK_TRAIN_NONE;
2559         temp |= FDI_LINK_TRAIN_PATTERN_2;
2560         I915_WRITE(reg, temp);
2561
2562         reg = FDI_RX_CTL(pipe);
2563         temp = I915_READ(reg);
2564         temp &= ~FDI_LINK_TRAIN_NONE;
2565         temp |= FDI_LINK_TRAIN_PATTERN_2;
2566         I915_WRITE(reg, temp);
2567
2568         POSTING_READ(reg);
2569         udelay(150);
2570
2571         reg = FDI_RX_IIR(pipe);
2572         for (tries = 0; tries < 5; tries++) {
2573                 temp = I915_READ(reg);
2574                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575
2576                 if (temp & FDI_RX_SYMBOL_LOCK) {
2577                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2578                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2579                         break;
2580                 }
2581         }
2582         if (tries == 5)
2583                 DRM_ERROR("FDI train 2 fail!\n");
2584
2585         DRM_DEBUG_KMS("FDI train done\n");
2586
2587 }
2588
2589 static const int snb_b_fdi_train_param[] = {
2590         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2591         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2592         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2593         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2594 };
2595
2596 /* The FDI link training functions for SNB/Cougarpoint. */
2597 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2598 {
2599         struct drm_device *dev = crtc->dev;
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602         int pipe = intel_crtc->pipe;
2603         u32 reg, temp, i, retry;
2604
2605         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606            for train result */
2607         reg = FDI_RX_IMR(pipe);
2608         temp = I915_READ(reg);
2609         temp &= ~FDI_RX_SYMBOL_LOCK;
2610         temp &= ~FDI_RX_BIT_LOCK;
2611         I915_WRITE(reg, temp);
2612
2613         POSTING_READ(reg);
2614         udelay(150);
2615
2616         /* enable CPU FDI TX and PCH FDI RX */
2617         reg = FDI_TX_CTL(pipe);
2618         temp = I915_READ(reg);
2619         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2620         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2621         temp &= ~FDI_LINK_TRAIN_NONE;
2622         temp |= FDI_LINK_TRAIN_PATTERN_1;
2623         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624         /* SNB-B */
2625         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2626         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627
2628         I915_WRITE(FDI_RX_MISC(pipe),
2629                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2630
2631         reg = FDI_RX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         if (HAS_PCH_CPT(dev)) {
2634                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636         } else {
2637                 temp &= ~FDI_LINK_TRAIN_NONE;
2638                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2639         }
2640         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642         POSTING_READ(reg);
2643         udelay(150);
2644
2645         for (i = 0; i < 4; i++) {
2646                 reg = FDI_TX_CTL(pipe);
2647                 temp = I915_READ(reg);
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 temp |= snb_b_fdi_train_param[i];
2650                 I915_WRITE(reg, temp);
2651
2652                 POSTING_READ(reg);
2653                 udelay(500);
2654
2655                 for (retry = 0; retry < 5; retry++) {
2656                         reg = FDI_RX_IIR(pipe);
2657                         temp = I915_READ(reg);
2658                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2659                         if (temp & FDI_RX_BIT_LOCK) {
2660                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662                                 break;
2663                         }
2664                         udelay(50);
2665                 }
2666                 if (retry < 5)
2667                         break;
2668         }
2669         if (i == 4)
2670                 DRM_ERROR("FDI train 1 fail!\n");
2671
2672         /* Train 2 */
2673         reg = FDI_TX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_LINK_TRAIN_NONE;
2676         temp |= FDI_LINK_TRAIN_PATTERN_2;
2677         if (IS_GEN6(dev)) {
2678                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679                 /* SNB-B */
2680                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2681         }
2682         I915_WRITE(reg, temp);
2683
2684         reg = FDI_RX_CTL(pipe);
2685         temp = I915_READ(reg);
2686         if (HAS_PCH_CPT(dev)) {
2687                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2688                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2689         } else {
2690                 temp &= ~FDI_LINK_TRAIN_NONE;
2691                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2692         }
2693         I915_WRITE(reg, temp);
2694
2695         POSTING_READ(reg);
2696         udelay(150);
2697
2698         for (i = 0; i < 4; i++) {
2699                 reg = FDI_TX_CTL(pipe);
2700                 temp = I915_READ(reg);
2701                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2702                 temp |= snb_b_fdi_train_param[i];
2703                 I915_WRITE(reg, temp);
2704
2705                 POSTING_READ(reg);
2706                 udelay(500);
2707
2708                 for (retry = 0; retry < 5; retry++) {
2709                         reg = FDI_RX_IIR(pipe);
2710                         temp = I915_READ(reg);
2711                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2712                         if (temp & FDI_RX_SYMBOL_LOCK) {
2713                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2714                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2715                                 break;
2716                         }
2717                         udelay(50);
2718                 }
2719                 if (retry < 5)
2720                         break;
2721         }
2722         if (i == 4)
2723                 DRM_ERROR("FDI train 2 fail!\n");
2724
2725         DRM_DEBUG_KMS("FDI train done.\n");
2726 }
2727
2728 /* Manual link training for Ivy Bridge A0 parts */
2729 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2730 {
2731         struct drm_device *dev = crtc->dev;
2732         struct drm_i915_private *dev_priv = dev->dev_private;
2733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2734         int pipe = intel_crtc->pipe;
2735         u32 reg, temp, i, j;
2736
2737         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2738            for train result */
2739         reg = FDI_RX_IMR(pipe);
2740         temp = I915_READ(reg);
2741         temp &= ~FDI_RX_SYMBOL_LOCK;
2742         temp &= ~FDI_RX_BIT_LOCK;
2743         I915_WRITE(reg, temp);
2744
2745         POSTING_READ(reg);
2746         udelay(150);
2747
2748         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2749                       I915_READ(FDI_RX_IIR(pipe)));
2750
2751         /* Try each vswing and preemphasis setting twice before moving on */
2752         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2753                 /* disable first in case we need to retry */
2754                 reg = FDI_TX_CTL(pipe);
2755                 temp = I915_READ(reg);
2756                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2757                 temp &= ~FDI_TX_ENABLE;
2758                 I915_WRITE(reg, temp);
2759
2760                 reg = FDI_RX_CTL(pipe);
2761                 temp = I915_READ(reg);
2762                 temp &= ~FDI_LINK_TRAIN_AUTO;
2763                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2764                 temp &= ~FDI_RX_ENABLE;
2765                 I915_WRITE(reg, temp);
2766
2767                 /* enable CPU FDI TX and PCH FDI RX */
2768                 reg = FDI_TX_CTL(pipe);
2769                 temp = I915_READ(reg);
2770                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2771                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2772                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2773                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2774                 temp |= snb_b_fdi_train_param[j/2];
2775                 temp |= FDI_COMPOSITE_SYNC;
2776                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2777
2778                 I915_WRITE(FDI_RX_MISC(pipe),
2779                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2780
2781                 reg = FDI_RX_CTL(pipe);
2782                 temp = I915_READ(reg);
2783                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2784                 temp |= FDI_COMPOSITE_SYNC;
2785                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2786
2787                 POSTING_READ(reg);
2788                 udelay(1); /* should be 0.5us */
2789
2790                 for (i = 0; i < 4; i++) {
2791                         reg = FDI_RX_IIR(pipe);
2792                         temp = I915_READ(reg);
2793                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794
2795                         if (temp & FDI_RX_BIT_LOCK ||
2796                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2797                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2798                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2799                                               i);
2800                                 break;
2801                         }
2802                         udelay(1); /* should be 0.5us */
2803                 }
2804                 if (i == 4) {
2805                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2806                         continue;
2807                 }
2808
2809                 /* Train 2 */
2810                 reg = FDI_TX_CTL(pipe);
2811                 temp = I915_READ(reg);
2812                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2813                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2814                 I915_WRITE(reg, temp);
2815
2816                 reg = FDI_RX_CTL(pipe);
2817                 temp = I915_READ(reg);
2818                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2820                 I915_WRITE(reg, temp);
2821
2822                 POSTING_READ(reg);
2823                 udelay(2); /* should be 1.5us */
2824
2825                 for (i = 0; i < 4; i++) {
2826                         reg = FDI_RX_IIR(pipe);
2827                         temp = I915_READ(reg);
2828                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830                         if (temp & FDI_RX_SYMBOL_LOCK ||
2831                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2832                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2833                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2834                                               i);
2835                                 goto train_done;
2836                         }
2837                         udelay(2); /* should be 1.5us */
2838                 }
2839                 if (i == 4)
2840                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2841         }
2842
2843 train_done:
2844         DRM_DEBUG_KMS("FDI train done.\n");
2845 }
2846
2847 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2848 {
2849         struct drm_device *dev = intel_crtc->base.dev;
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         int pipe = intel_crtc->pipe;
2852         u32 reg, temp;
2853
2854
2855         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2856         reg = FDI_RX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2859         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2860         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2862
2863         POSTING_READ(reg);
2864         udelay(200);
2865
2866         /* Switch from Rawclk to PCDclk */
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp | FDI_PCDCLK);
2869
2870         POSTING_READ(reg);
2871         udelay(200);
2872
2873         /* Enable CPU FDI TX PLL, always on for Ironlake */
2874         reg = FDI_TX_CTL(pipe);
2875         temp = I915_READ(reg);
2876         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2877                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2878
2879                 POSTING_READ(reg);
2880                 udelay(100);
2881         }
2882 }
2883
2884 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2885 {
2886         struct drm_device *dev = intel_crtc->base.dev;
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         int pipe = intel_crtc->pipe;
2889         u32 reg, temp;
2890
2891         /* Switch from PCDclk to Rawclk */
2892         reg = FDI_RX_CTL(pipe);
2893         temp = I915_READ(reg);
2894         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2895
2896         /* Disable CPU FDI TX PLL */
2897         reg = FDI_TX_CTL(pipe);
2898         temp = I915_READ(reg);
2899         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2900
2901         POSTING_READ(reg);
2902         udelay(100);
2903
2904         reg = FDI_RX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2907
2908         /* Wait for the clocks to turn off. */
2909         POSTING_READ(reg);
2910         udelay(100);
2911 }
2912
2913 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2914 {
2915         struct drm_device *dev = crtc->dev;
2916         struct drm_i915_private *dev_priv = dev->dev_private;
2917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918         int pipe = intel_crtc->pipe;
2919         u32 reg, temp;
2920
2921         /* disable CPU FDI tx and PCH FDI rx */
2922         reg = FDI_TX_CTL(pipe);
2923         temp = I915_READ(reg);
2924         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2925         POSTING_READ(reg);
2926
2927         reg = FDI_RX_CTL(pipe);
2928         temp = I915_READ(reg);
2929         temp &= ~(0x7 << 16);
2930         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2931         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2932
2933         POSTING_READ(reg);
2934         udelay(100);
2935
2936         /* Ironlake workaround, disable clock pointer after downing FDI */
2937         if (HAS_PCH_IBX(dev)) {
2938                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2939         }
2940
2941         /* still set train pattern 1 */
2942         reg = FDI_TX_CTL(pipe);
2943         temp = I915_READ(reg);
2944         temp &= ~FDI_LINK_TRAIN_NONE;
2945         temp |= FDI_LINK_TRAIN_PATTERN_1;
2946         I915_WRITE(reg, temp);
2947
2948         reg = FDI_RX_CTL(pipe);
2949         temp = I915_READ(reg);
2950         if (HAS_PCH_CPT(dev)) {
2951                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2952                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2953         } else {
2954                 temp &= ~FDI_LINK_TRAIN_NONE;
2955                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2956         }
2957         /* BPC in FDI rx is consistent with that in PIPECONF */
2958         temp &= ~(0x07 << 16);
2959         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2960         I915_WRITE(reg, temp);
2961
2962         POSTING_READ(reg);
2963         udelay(100);
2964 }
2965
2966 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2967 {
2968         struct drm_device *dev = crtc->dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971         unsigned long flags;
2972         bool pending;
2973
2974         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2975             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2976                 return false;
2977
2978         spin_lock_irqsave(&dev->event_lock, flags);
2979         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2980         spin_unlock_irqrestore(&dev->event_lock, flags);
2981
2982         return pending;
2983 }
2984
2985 bool intel_has_pending_fb_unpin(struct drm_device *dev)
2986 {
2987         struct intel_crtc *crtc;
2988
2989         /* Note that we don't need to be called with mode_config.lock here
2990          * as our list of CRTC objects is static for the lifetime of the
2991          * device and so cannot disappear as we iterate. Similarly, we can
2992          * happily treat the predicates as racy, atomic checks as userspace
2993          * cannot claim and pin a new fb without at least acquring the
2994          * struct_mutex and so serialising with us.
2995          */
2996         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2997                 if (atomic_read(&crtc->unpin_work_count) == 0)
2998                         continue;
2999
3000                 if (crtc->unpin_work)
3001                         intel_wait_for_vblank(dev, crtc->pipe);
3002
3003                 return true;
3004         }
3005
3006         return false;
3007 }
3008
3009 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3010 {
3011         struct drm_device *dev = crtc->dev;
3012         struct drm_i915_private *dev_priv = dev->dev_private;
3013
3014         if (crtc->fb == NULL)
3015                 return;
3016
3017         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3018
3019         wait_event(dev_priv->pending_flip_queue,
3020                    !intel_crtc_has_pending_flip(crtc));
3021
3022         mutex_lock(&dev->struct_mutex);
3023         intel_finish_fb(crtc->fb);
3024         mutex_unlock(&dev->struct_mutex);
3025 }
3026
3027 /* Program iCLKIP clock to the desired frequency */
3028 static void lpt_program_iclkip(struct drm_crtc *crtc)
3029 {
3030         struct drm_device *dev = crtc->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3033         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3034         u32 temp;
3035
3036         mutex_lock(&dev_priv->dpio_lock);
3037
3038         /* It is necessary to ungate the pixclk gate prior to programming
3039          * the divisors, and gate it back when it is done.
3040          */
3041         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3042
3043         /* Disable SSCCTL */
3044         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3045                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3046                                 SBI_SSCCTL_DISABLE,
3047                         SBI_ICLK);
3048
3049         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3050         if (clock == 20000) {
3051                 auxdiv = 1;
3052                 divsel = 0x41;
3053                 phaseinc = 0x20;
3054         } else {
3055                 /* The iCLK virtual clock root frequency is in MHz,
3056                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3057                  * divisors, it is necessary to divide one by another, so we
3058                  * convert the virtual clock precision to KHz here for higher
3059                  * precision.
3060                  */
3061                 u32 iclk_virtual_root_freq = 172800 * 1000;
3062                 u32 iclk_pi_range = 64;
3063                 u32 desired_divisor, msb_divisor_value, pi_value;
3064
3065                 desired_divisor = (iclk_virtual_root_freq / clock);
3066                 msb_divisor_value = desired_divisor / iclk_pi_range;
3067                 pi_value = desired_divisor % iclk_pi_range;
3068
3069                 auxdiv = 0;
3070                 divsel = msb_divisor_value - 2;
3071                 phaseinc = pi_value;
3072         }
3073
3074         /* This should not happen with any sane values */
3075         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3076                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3077         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3078                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3079
3080         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3081                         clock,
3082                         auxdiv,
3083                         divsel,
3084                         phasedir,
3085                         phaseinc);
3086
3087         /* Program SSCDIVINTPHASE6 */
3088         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3089         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3090         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3091         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3092         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3093         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3094         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3095         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3096
3097         /* Program SSCAUXDIV */
3098         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3099         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3100         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3101         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3102
3103         /* Enable modulator and associated divider */
3104         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3105         temp &= ~SBI_SSCCTL_DISABLE;
3106         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3107
3108         /* Wait for initialization time */
3109         udelay(24);
3110
3111         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3112
3113         mutex_unlock(&dev_priv->dpio_lock);
3114 }
3115
3116 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3117                                                 enum pipe pch_transcoder)
3118 {
3119         struct drm_device *dev = crtc->base.dev;
3120         struct drm_i915_private *dev_priv = dev->dev_private;
3121         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3122
3123         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3124                    I915_READ(HTOTAL(cpu_transcoder)));
3125         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3126                    I915_READ(HBLANK(cpu_transcoder)));
3127         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3128                    I915_READ(HSYNC(cpu_transcoder)));
3129
3130         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3131                    I915_READ(VTOTAL(cpu_transcoder)));
3132         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3133                    I915_READ(VBLANK(cpu_transcoder)));
3134         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3135                    I915_READ(VSYNC(cpu_transcoder)));
3136         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3137                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3138 }
3139
3140 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3141 {
3142         struct drm_i915_private *dev_priv = dev->dev_private;
3143         uint32_t temp;
3144
3145         temp = I915_READ(SOUTH_CHICKEN1);
3146         if (temp & FDI_BC_BIFURCATION_SELECT)
3147                 return;
3148
3149         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3150         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3151
3152         temp |= FDI_BC_BIFURCATION_SELECT;
3153         DRM_DEBUG_KMS("enabling fdi C rx\n");
3154         I915_WRITE(SOUTH_CHICKEN1, temp);
3155         POSTING_READ(SOUTH_CHICKEN1);
3156 }
3157
3158 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3159 {
3160         struct drm_device *dev = intel_crtc->base.dev;
3161         struct drm_i915_private *dev_priv = dev->dev_private;
3162
3163         switch (intel_crtc->pipe) {
3164         case PIPE_A:
3165                 break;
3166         case PIPE_B:
3167                 if (intel_crtc->config.fdi_lanes > 2)
3168                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3169                 else
3170                         cpt_enable_fdi_bc_bifurcation(dev);
3171
3172                 break;
3173         case PIPE_C:
3174                 cpt_enable_fdi_bc_bifurcation(dev);
3175
3176                 break;
3177         default:
3178                 BUG();
3179         }
3180 }
3181
3182 /*
3183  * Enable PCH resources required for PCH ports:
3184  *   - PCH PLLs
3185  *   - FDI training & RX/TX
3186  *   - update transcoder timings
3187  *   - DP transcoding bits
3188  *   - transcoder
3189  */
3190 static void ironlake_pch_enable(struct drm_crtc *crtc)
3191 {
3192         struct drm_device *dev = crtc->dev;
3193         struct drm_i915_private *dev_priv = dev->dev_private;
3194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3195         int pipe = intel_crtc->pipe;
3196         u32 reg, temp;
3197
3198         assert_pch_transcoder_disabled(dev_priv, pipe);
3199
3200         if (IS_IVYBRIDGE(dev))
3201                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3202
3203         /* Write the TU size bits before fdi link training, so that error
3204          * detection works. */
3205         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3206                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3207
3208         /* For PCH output, training FDI link */
3209         dev_priv->display.fdi_link_train(crtc);
3210
3211         /* We need to program the right clock selection before writing the pixel
3212          * mutliplier into the DPLL. */
3213         if (HAS_PCH_CPT(dev)) {
3214                 u32 sel;
3215
3216                 temp = I915_READ(PCH_DPLL_SEL);
3217                 temp |= TRANS_DPLL_ENABLE(pipe);
3218                 sel = TRANS_DPLLB_SEL(pipe);
3219                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3220                         temp |= sel;
3221                 else
3222                         temp &= ~sel;
3223                 I915_WRITE(PCH_DPLL_SEL, temp);
3224         }
3225
3226         /* XXX: pch pll's can be enabled any time before we enable the PCH
3227          * transcoder, and we actually should do this to not upset any PCH
3228          * transcoder that already use the clock when we share it.
3229          *
3230          * Note that enable_shared_dpll tries to do the right thing, but
3231          * get_shared_dpll unconditionally resets the pll - we need that to have
3232          * the right LVDS enable sequence. */
3233         ironlake_enable_shared_dpll(intel_crtc);
3234
3235         /* set transcoder timing, panel must allow it */
3236         assert_panel_unlocked(dev_priv, pipe);
3237         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3238
3239         intel_fdi_normal_train(crtc);
3240
3241         /* For PCH DP, enable TRANS_DP_CTL */
3242         if (HAS_PCH_CPT(dev) &&
3243             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3244              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3245                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3246                 reg = TRANS_DP_CTL(pipe);
3247                 temp = I915_READ(reg);
3248                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3249                           TRANS_DP_SYNC_MASK |
3250                           TRANS_DP_BPC_MASK);
3251                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3252                          TRANS_DP_ENH_FRAMING);
3253                 temp |= bpc << 9; /* same format but at 11:9 */
3254
3255                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3256                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3257                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3258                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3259
3260                 switch (intel_trans_dp_port_sel(crtc)) {
3261                 case PCH_DP_B:
3262                         temp |= TRANS_DP_PORT_SEL_B;
3263                         break;
3264                 case PCH_DP_C:
3265                         temp |= TRANS_DP_PORT_SEL_C;
3266                         break;
3267                 case PCH_DP_D:
3268                         temp |= TRANS_DP_PORT_SEL_D;
3269                         break;
3270                 default:
3271                         BUG();
3272                 }
3273
3274                 I915_WRITE(reg, temp);
3275         }
3276
3277         ironlake_enable_pch_transcoder(dev_priv, pipe);
3278 }
3279
3280 static void lpt_pch_enable(struct drm_crtc *crtc)
3281 {
3282         struct drm_device *dev = crtc->dev;
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3286
3287         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3288
3289         lpt_program_iclkip(crtc);
3290
3291         /* Set transcoder timing. */
3292         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3293
3294         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3295 }
3296
3297 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3298 {
3299         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3300
3301         if (pll == NULL)
3302                 return;
3303
3304         if (pll->refcount == 0) {
3305                 WARN(1, "bad %s refcount\n", pll->name);
3306                 return;
3307         }
3308
3309         if (--pll->refcount == 0) {
3310                 WARN_ON(pll->on);
3311                 WARN_ON(pll->active);
3312         }
3313
3314         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3315 }
3316
3317 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3318 {
3319         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3320         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3321         enum intel_dpll_id i;
3322
3323         if (pll) {
3324                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3325                               crtc->base.base.id, pll->name);
3326                 intel_put_shared_dpll(crtc);
3327         }
3328
3329         if (HAS_PCH_IBX(dev_priv->dev)) {
3330                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3331                 i = (enum intel_dpll_id) crtc->pipe;
3332                 pll = &dev_priv->shared_dplls[i];
3333
3334                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3335                               crtc->base.base.id, pll->name);
3336
3337                 goto found;
3338         }
3339
3340         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3341                 pll = &dev_priv->shared_dplls[i];
3342
3343                 /* Only want to check enabled timings first */
3344                 if (pll->refcount == 0)
3345                         continue;
3346
3347                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3348                            sizeof(pll->hw_state)) == 0) {
3349                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3350                                       crtc->base.base.id,
3351                                       pll->name, pll->refcount, pll->active);
3352
3353                         goto found;
3354                 }
3355         }
3356
3357         /* Ok no matching timings, maybe there's a free one? */
3358         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3359                 pll = &dev_priv->shared_dplls[i];
3360                 if (pll->refcount == 0) {
3361                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3362                                       crtc->base.base.id, pll->name);
3363                         goto found;
3364                 }
3365         }
3366
3367         return NULL;
3368
3369 found:
3370         crtc->config.shared_dpll = i;
3371         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3372                          pipe_name(crtc->pipe));
3373
3374         if (pll->active == 0) {
3375                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3376                        sizeof(pll->hw_state));
3377
3378                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3379                 WARN_ON(pll->on);
3380                 assert_shared_dpll_disabled(dev_priv, pll);
3381
3382                 pll->mode_set(dev_priv, pll);
3383         }
3384         pll->refcount++;
3385
3386         return pll;
3387 }
3388
3389 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3390 {
3391         struct drm_i915_private *dev_priv = dev->dev_private;
3392         int dslreg = PIPEDSL(pipe);
3393         u32 temp;
3394
3395         temp = I915_READ(dslreg);
3396         udelay(500);
3397         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3398                 if (wait_for(I915_READ(dslreg) != temp, 5))
3399                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3400         }
3401 }
3402
3403 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3404 {
3405         struct drm_device *dev = crtc->base.dev;
3406         struct drm_i915_private *dev_priv = dev->dev_private;
3407         int pipe = crtc->pipe;
3408
3409         if (crtc->config.pch_pfit.enabled) {
3410                 /* Force use of hard-coded filter coefficients
3411                  * as some pre-programmed values are broken,
3412                  * e.g. x201.
3413                  */
3414                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3415                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3416                                                  PF_PIPE_SEL_IVB(pipe));
3417                 else
3418                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3419                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3420                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3421         }
3422 }
3423
3424 static void intel_enable_planes(struct drm_crtc *crtc)
3425 {
3426         struct drm_device *dev = crtc->dev;
3427         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3428         struct intel_plane *intel_plane;
3429
3430         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3431                 if (intel_plane->pipe == pipe)
3432                         intel_plane_restore(&intel_plane->base);
3433 }
3434
3435 static void intel_disable_planes(struct drm_crtc *crtc)
3436 {
3437         struct drm_device *dev = crtc->dev;
3438         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3439         struct intel_plane *intel_plane;
3440
3441         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3442                 if (intel_plane->pipe == pipe)
3443                         intel_plane_disable(&intel_plane->base);
3444 }
3445
3446 void hsw_enable_ips(struct intel_crtc *crtc)
3447 {
3448         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3449
3450         if (!crtc->config.ips_enabled)
3451                 return;
3452
3453         /* We can only enable IPS after we enable a plane and wait for a vblank.
3454          * We guarantee that the plane is enabled by calling intel_enable_ips
3455          * only after intel_enable_plane. And intel_enable_plane already waits
3456          * for a vblank, so all we need to do here is to enable the IPS bit. */
3457         assert_plane_enabled(dev_priv, crtc->plane);
3458         if (IS_BROADWELL(crtc->base.dev)) {
3459                 mutex_lock(&dev_priv->rps.hw_lock);
3460                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3461                 mutex_unlock(&dev_priv->rps.hw_lock);
3462                 /* Quoting Art Runyan: "its not safe to expect any particular
3463                  * value in IPS_CTL bit 31 after enabling IPS through the
3464                  * mailbox." Moreover, the mailbox may return a bogus state,
3465                  * so we need to just enable it and continue on.
3466                  */
3467         } else {
3468                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3469                 /* The bit only becomes 1 in the next vblank, so this wait here
3470                  * is essentially intel_wait_for_vblank. If we don't have this
3471                  * and don't wait for vblanks until the end of crtc_enable, then
3472                  * the HW state readout code will complain that the expected
3473                  * IPS_CTL value is not the one we read. */
3474                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3475                         DRM_ERROR("Timed out waiting for IPS enable\n");
3476         }
3477 }
3478
3479 void hsw_disable_ips(struct intel_crtc *crtc)
3480 {
3481         struct drm_device *dev = crtc->base.dev;
3482         struct drm_i915_private *dev_priv = dev->dev_private;
3483
3484         if (!crtc->config.ips_enabled)
3485                 return;
3486
3487         assert_plane_enabled(dev_priv, crtc->plane);
3488         if (IS_BROADWELL(crtc->base.dev)) {
3489                 mutex_lock(&dev_priv->rps.hw_lock);
3490                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3491                 mutex_unlock(&dev_priv->rps.hw_lock);
3492         } else {
3493                 I915_WRITE(IPS_CTL, 0);
3494                 POSTING_READ(IPS_CTL);
3495         }
3496
3497         /* We need to wait for a vblank before we can disable the plane. */
3498         intel_wait_for_vblank(dev, crtc->pipe);
3499 }
3500
3501 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3502 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         enum pipe pipe = intel_crtc->pipe;
3508         int palreg = PALETTE(pipe);
3509         int i;
3510         bool reenable_ips = false;
3511
3512         /* The clocks have to be on to load the palette. */
3513         if (!crtc->enabled || !intel_crtc->active)
3514                 return;
3515
3516         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3517                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3518                         assert_dsi_pll_enabled(dev_priv);
3519                 else
3520                         assert_pll_enabled(dev_priv, pipe);
3521         }
3522
3523         /* use legacy palette for Ironlake */
3524         if (HAS_PCH_SPLIT(dev))
3525                 palreg = LGC_PALETTE(pipe);
3526
3527         /* Workaround : Do not read or write the pipe palette/gamma data while
3528          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3529          */
3530         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3531             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3532              GAMMA_MODE_MODE_SPLIT)) {
3533                 hsw_disable_ips(intel_crtc);
3534                 reenable_ips = true;
3535         }
3536
3537         for (i = 0; i < 256; i++) {
3538                 I915_WRITE(palreg + 4 * i,
3539                            (intel_crtc->lut_r[i] << 16) |
3540                            (intel_crtc->lut_g[i] << 8) |
3541                            intel_crtc->lut_b[i]);
3542         }
3543
3544         if (reenable_ips)
3545                 hsw_enable_ips(intel_crtc);
3546 }
3547
3548 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         struct intel_encoder *encoder;
3554         int pipe = intel_crtc->pipe;
3555         int plane = intel_crtc->plane;
3556
3557         WARN_ON(!crtc->enabled);
3558
3559         if (intel_crtc->active)
3560                 return;
3561
3562         intel_crtc->active = true;
3563
3564         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3565         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3566
3567         for_each_encoder_on_crtc(dev, crtc, encoder)
3568                 if (encoder->pre_enable)
3569                         encoder->pre_enable(encoder);
3570
3571         if (intel_crtc->config.has_pch_encoder) {
3572                 /* Note: FDI PLL enabling _must_ be done before we enable the
3573                  * cpu pipes, hence this is separate from all the other fdi/pch
3574                  * enabling. */
3575                 ironlake_fdi_pll_enable(intel_crtc);
3576         } else {
3577                 assert_fdi_tx_disabled(dev_priv, pipe);
3578                 assert_fdi_rx_disabled(dev_priv, pipe);
3579         }
3580
3581         ironlake_pfit_enable(intel_crtc);
3582
3583         /*
3584          * On ILK+ LUT must be loaded before the pipe is running but with
3585          * clocks enabled
3586          */
3587         intel_crtc_load_lut(crtc);
3588
3589         intel_update_watermarks(crtc);
3590         intel_enable_pipe(dev_priv, pipe,
3591                           intel_crtc->config.has_pch_encoder, false);
3592         intel_enable_primary_plane(dev_priv, plane, pipe);
3593         intel_enable_planes(crtc);
3594         intel_crtc_update_cursor(crtc, true);
3595
3596         if (intel_crtc->config.has_pch_encoder)
3597                 ironlake_pch_enable(crtc);
3598
3599         mutex_lock(&dev->struct_mutex);
3600         intel_update_fbc(dev);
3601         mutex_unlock(&dev->struct_mutex);
3602
3603         for_each_encoder_on_crtc(dev, crtc, encoder)
3604                 encoder->enable(encoder);
3605
3606         if (HAS_PCH_CPT(dev))
3607                 cpt_verify_modeset(dev, intel_crtc->pipe);
3608
3609         /*
3610          * There seems to be a race in PCH platform hw (at least on some
3611          * outputs) where an enabled pipe still completes any pageflip right
3612          * away (as if the pipe is off) instead of waiting for vblank. As soon
3613          * as the first vblank happend, everything works as expected. Hence just
3614          * wait for one vblank before returning to avoid strange things
3615          * happening.
3616          */
3617         intel_wait_for_vblank(dev, intel_crtc->pipe);
3618 }
3619
3620 /* IPS only exists on ULT machines and is tied to pipe A. */
3621 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3622 {
3623         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3624 }
3625
3626 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3627 {
3628         struct drm_device *dev = crtc->dev;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631         int pipe = intel_crtc->pipe;
3632         int plane = intel_crtc->plane;
3633
3634         intel_enable_primary_plane(dev_priv, plane, pipe);
3635         intel_enable_planes(crtc);
3636         intel_crtc_update_cursor(crtc, true);
3637
3638         hsw_enable_ips(intel_crtc);
3639
3640         mutex_lock(&dev->struct_mutex);
3641         intel_update_fbc(dev);
3642         mutex_unlock(&dev->struct_mutex);
3643 }
3644
3645 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3646 {
3647         struct drm_device *dev = crtc->dev;
3648         struct drm_i915_private *dev_priv = dev->dev_private;
3649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650         int pipe = intel_crtc->pipe;
3651         int plane = intel_crtc->plane;
3652
3653         intel_crtc_wait_for_pending_flips(crtc);
3654         drm_vblank_off(dev, pipe);
3655
3656         /* FBC must be disabled before disabling the plane on HSW. */
3657         if (dev_priv->fbc.plane == plane)
3658                 intel_disable_fbc(dev);
3659
3660         hsw_disable_ips(intel_crtc);
3661
3662         intel_crtc_update_cursor(crtc, false);
3663         intel_disable_planes(crtc);
3664         intel_disable_primary_plane(dev_priv, plane, pipe);
3665 }
3666
3667 /*
3668  * This implements the workaround described in the "notes" section of the mode
3669  * set sequence documentation. When going from no pipes or single pipe to
3670  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3671  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3672  */
3673 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3674 {
3675         struct drm_device *dev = crtc->base.dev;
3676         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3677
3678         /* We want to get the other_active_crtc only if there's only 1 other
3679          * active crtc. */
3680         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3681                 if (!crtc_it->active || crtc_it == crtc)
3682                         continue;
3683
3684                 if (other_active_crtc)
3685                         return;
3686
3687                 other_active_crtc = crtc_it;
3688         }
3689         if (!other_active_crtc)
3690                 return;
3691
3692         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3693         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3694 }
3695
3696 static void haswell_crtc_enable(struct drm_crtc *crtc)
3697 {
3698         struct drm_device *dev = crtc->dev;
3699         struct drm_i915_private *dev_priv = dev->dev_private;
3700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3701         struct intel_encoder *encoder;
3702         int pipe = intel_crtc->pipe;
3703
3704         WARN_ON(!crtc->enabled);
3705
3706         if (intel_crtc->active)
3707                 return;
3708
3709         intel_crtc->active = true;
3710
3711         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3712         if (intel_crtc->config.has_pch_encoder)
3713                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3714
3715         if (intel_crtc->config.has_pch_encoder)
3716                 dev_priv->display.fdi_link_train(crtc);
3717
3718         for_each_encoder_on_crtc(dev, crtc, encoder)
3719                 if (encoder->pre_enable)
3720                         encoder->pre_enable(encoder);
3721
3722         intel_ddi_enable_pipe_clock(intel_crtc);
3723
3724         ironlake_pfit_enable(intel_crtc);
3725
3726         /*
3727          * On ILK+ LUT must be loaded before the pipe is running but with
3728          * clocks enabled
3729          */
3730         intel_crtc_load_lut(crtc);
3731
3732         intel_ddi_set_pipe_settings(crtc);
3733         intel_ddi_enable_transcoder_func(crtc);
3734
3735         intel_update_watermarks(crtc);
3736         intel_enable_pipe(dev_priv, pipe,
3737                           intel_crtc->config.has_pch_encoder, false);
3738
3739         if (intel_crtc->config.has_pch_encoder)
3740                 lpt_pch_enable(crtc);
3741
3742         for_each_encoder_on_crtc(dev, crtc, encoder) {
3743                 encoder->enable(encoder);
3744                 intel_opregion_notify_encoder(encoder, true);
3745         }
3746
3747         /* If we change the relative order between pipe/planes enabling, we need
3748          * to change the workaround. */
3749         haswell_mode_set_planes_workaround(intel_crtc);
3750         haswell_crtc_enable_planes(crtc);
3751
3752         /*
3753          * There seems to be a race in PCH platform hw (at least on some
3754          * outputs) where an enabled pipe still completes any pageflip right
3755          * away (as if the pipe is off) instead of waiting for vblank. As soon
3756          * as the first vblank happend, everything works as expected. Hence just
3757          * wait for one vblank before returning to avoid strange things
3758          * happening.
3759          */
3760         intel_wait_for_vblank(dev, intel_crtc->pipe);
3761 }
3762
3763 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3764 {
3765         struct drm_device *dev = crtc->base.dev;
3766         struct drm_i915_private *dev_priv = dev->dev_private;
3767         int pipe = crtc->pipe;
3768
3769         /* To avoid upsetting the power well on haswell only disable the pfit if
3770          * it's in use. The hw state code will make sure we get this right. */
3771         if (crtc->config.pch_pfit.enabled) {
3772                 I915_WRITE(PF_CTL(pipe), 0);
3773                 I915_WRITE(PF_WIN_POS(pipe), 0);
3774                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3775         }
3776 }
3777
3778 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3779 {
3780         struct drm_device *dev = crtc->dev;
3781         struct drm_i915_private *dev_priv = dev->dev_private;
3782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3783         struct intel_encoder *encoder;
3784         int pipe = intel_crtc->pipe;
3785         int plane = intel_crtc->plane;
3786         u32 reg, temp;
3787
3788
3789         if (!intel_crtc->active)
3790                 return;
3791
3792         for_each_encoder_on_crtc(dev, crtc, encoder)
3793                 encoder->disable(encoder);
3794
3795         intel_crtc_wait_for_pending_flips(crtc);
3796         drm_vblank_off(dev, pipe);
3797
3798         if (dev_priv->fbc.plane == plane)
3799                 intel_disable_fbc(dev);
3800
3801         intel_crtc_update_cursor(crtc, false);
3802         intel_disable_planes(crtc);
3803         intel_disable_primary_plane(dev_priv, plane, pipe);
3804
3805         if (intel_crtc->config.has_pch_encoder)
3806                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3807
3808         intel_disable_pipe(dev_priv, pipe);
3809
3810         ironlake_pfit_disable(intel_crtc);
3811
3812         for_each_encoder_on_crtc(dev, crtc, encoder)
3813                 if (encoder->post_disable)
3814                         encoder->post_disable(encoder);
3815
3816         if (intel_crtc->config.has_pch_encoder) {
3817                 ironlake_fdi_disable(crtc);
3818
3819                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3820
3821                 if (HAS_PCH_CPT(dev)) {
3822                         /* disable TRANS_DP_CTL */
3823                         reg = TRANS_DP_CTL(pipe);
3824                         temp = I915_READ(reg);
3825                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3826                                   TRANS_DP_PORT_SEL_MASK);
3827                         temp |= TRANS_DP_PORT_SEL_NONE;
3828                         I915_WRITE(reg, temp);
3829
3830                         /* disable DPLL_SEL */
3831                         temp = I915_READ(PCH_DPLL_SEL);
3832                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3833                         I915_WRITE(PCH_DPLL_SEL, temp);
3834                 }
3835
3836                 /* disable PCH DPLL */
3837                 intel_disable_shared_dpll(intel_crtc);
3838
3839                 ironlake_fdi_pll_disable(intel_crtc);
3840         }
3841
3842         intel_crtc->active = false;
3843         intel_update_watermarks(crtc);
3844
3845         mutex_lock(&dev->struct_mutex);
3846         intel_update_fbc(dev);
3847         mutex_unlock(&dev->struct_mutex);
3848 }
3849
3850 static void haswell_crtc_disable(struct drm_crtc *crtc)
3851 {
3852         struct drm_device *dev = crtc->dev;
3853         struct drm_i915_private *dev_priv = dev->dev_private;
3854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3855         struct intel_encoder *encoder;
3856         int pipe = intel_crtc->pipe;
3857         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3858
3859         if (!intel_crtc->active)
3860                 return;
3861
3862         haswell_crtc_disable_planes(crtc);
3863
3864         for_each_encoder_on_crtc(dev, crtc, encoder) {
3865                 intel_opregion_notify_encoder(encoder, false);
3866                 encoder->disable(encoder);
3867         }
3868
3869         if (intel_crtc->config.has_pch_encoder)
3870                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3871         intel_disable_pipe(dev_priv, pipe);
3872
3873         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3874
3875         ironlake_pfit_disable(intel_crtc);
3876
3877         intel_ddi_disable_pipe_clock(intel_crtc);
3878
3879         for_each_encoder_on_crtc(dev, crtc, encoder)
3880                 if (encoder->post_disable)
3881                         encoder->post_disable(encoder);
3882
3883         if (intel_crtc->config.has_pch_encoder) {
3884                 lpt_disable_pch_transcoder(dev_priv);
3885                 intel_ddi_fdi_disable(crtc);
3886         }
3887
3888         intel_crtc->active = false;
3889         intel_update_watermarks(crtc);
3890
3891         mutex_lock(&dev->struct_mutex);
3892         intel_update_fbc(dev);
3893         mutex_unlock(&dev->struct_mutex);
3894 }
3895
3896 static void ironlake_crtc_off(struct drm_crtc *crtc)
3897 {
3898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3899         intel_put_shared_dpll(intel_crtc);
3900 }
3901
3902 static void haswell_crtc_off(struct drm_crtc *crtc)
3903 {
3904         intel_ddi_put_crtc_pll(crtc);
3905 }
3906
3907 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3908 {
3909         if (!enable && intel_crtc->overlay) {
3910                 struct drm_device *dev = intel_crtc->base.dev;
3911                 struct drm_i915_private *dev_priv = dev->dev_private;
3912
3913                 mutex_lock(&dev->struct_mutex);
3914                 dev_priv->mm.interruptible = false;
3915                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3916                 dev_priv->mm.interruptible = true;
3917                 mutex_unlock(&dev->struct_mutex);
3918         }
3919
3920         /* Let userspace switch the overlay on again. In most cases userspace
3921          * has to recompute where to put it anyway.
3922          */
3923 }
3924
3925 /**
3926  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3927  * cursor plane briefly if not already running after enabling the display
3928  * plane.
3929  * This workaround avoids occasional blank screens when self refresh is
3930  * enabled.
3931  */
3932 static void
3933 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3934 {
3935         u32 cntl = I915_READ(CURCNTR(pipe));
3936
3937         if ((cntl & CURSOR_MODE) == 0) {
3938                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3939
3940                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3941                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3942                 intel_wait_for_vblank(dev_priv->dev, pipe);
3943                 I915_WRITE(CURCNTR(pipe), cntl);
3944                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3945                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3946         }
3947 }
3948
3949 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3950 {
3951         struct drm_device *dev = crtc->base.dev;
3952         struct drm_i915_private *dev_priv = dev->dev_private;
3953         struct intel_crtc_config *pipe_config = &crtc->config;
3954
3955         if (!crtc->config.gmch_pfit.control)
3956                 return;
3957
3958         /*
3959          * The panel fitter should only be adjusted whilst the pipe is disabled,
3960          * according to register description and PRM.
3961          */
3962         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3963         assert_pipe_disabled(dev_priv, crtc->pipe);
3964
3965         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3966         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3967
3968         /* Border color in case we don't scale up to the full screen. Black by
3969          * default, change to something else for debugging. */
3970         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3971 }
3972
3973 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3974 {
3975         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3976
3977         /* Obtain SKU information */
3978         mutex_lock(&dev_priv->dpio_lock);
3979         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3980                 CCK_FUSE_HPLL_FREQ_MASK;
3981         mutex_unlock(&dev_priv->dpio_lock);
3982
3983         return vco_freq[hpll_freq];
3984 }
3985
3986 /* Adjust CDclk dividers to allow high res or save power if possible */
3987 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3988 {
3989         struct drm_i915_private *dev_priv = dev->dev_private;
3990         u32 val, cmd;
3991
3992         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3993                 cmd = 2;
3994         else if (cdclk == 266)
3995                 cmd = 1;
3996         else
3997                 cmd = 0;
3998
3999         mutex_lock(&dev_priv->rps.hw_lock);
4000         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4001         val &= ~DSPFREQGUAR_MASK;
4002         val |= (cmd << DSPFREQGUAR_SHIFT);
4003         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4004         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4005                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4006                      50)) {
4007                 DRM_ERROR("timed out waiting for CDclk change\n");
4008         }
4009         mutex_unlock(&dev_priv->rps.hw_lock);
4010
4011         if (cdclk == 400) {
4012                 u32 divider, vco;
4013
4014                 vco = valleyview_get_vco(dev_priv);
4015                 divider = ((vco << 1) / cdclk) - 1;
4016
4017                 mutex_lock(&dev_priv->dpio_lock);
4018                 /* adjust cdclk divider */
4019                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4020                 val &= ~0xf;
4021                 val |= divider;
4022                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4023                 mutex_unlock(&dev_priv->dpio_lock);
4024         }
4025
4026         mutex_lock(&dev_priv->dpio_lock);
4027         /* adjust self-refresh exit latency value */
4028         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4029         val &= ~0x7f;
4030
4031         /*
4032          * For high bandwidth configs, we set a higher latency in the bunit
4033          * so that the core display fetch happens in time to avoid underruns.
4034          */
4035         if (cdclk == 400)
4036                 val |= 4500 / 250; /* 4.5 usec */
4037         else
4038                 val |= 3000 / 250; /* 3.0 usec */
4039         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4040         mutex_unlock(&dev_priv->dpio_lock);
4041
4042         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4043         intel_i2c_reset(dev);
4044 }
4045
4046 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4047 {
4048         int cur_cdclk, vco;
4049         int divider;
4050
4051         vco = valleyview_get_vco(dev_priv);
4052
4053         mutex_lock(&dev_priv->dpio_lock);
4054         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4055         mutex_unlock(&dev_priv->dpio_lock);
4056
4057         divider &= 0xf;
4058
4059         cur_cdclk = (vco << 1) / (divider + 1);
4060
4061         return cur_cdclk;
4062 }
4063
4064 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4065                                  int max_pixclk)
4066 {
4067         int cur_cdclk;
4068
4069         cur_cdclk = valleyview_cur_cdclk(dev_priv);
4070
4071         /*
4072          * Really only a few cases to deal with, as only 4 CDclks are supported:
4073          *   200MHz
4074          *   267MHz
4075          *   320MHz
4076          *   400MHz
4077          * So we check to see whether we're above 90% of the lower bin and
4078          * adjust if needed.
4079          */
4080         if (max_pixclk > 288000) {
4081                 return 400;
4082         } else if (max_pixclk > 240000) {
4083                 return 320;
4084         } else
4085                 return 266;
4086         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4087 }
4088
4089 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4090                                  unsigned modeset_pipes,
4091                                  struct intel_crtc_config *pipe_config)
4092 {
4093         struct drm_device *dev = dev_priv->dev;
4094         struct intel_crtc *intel_crtc;
4095         int max_pixclk = 0;
4096
4097         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4098                             base.head) {
4099                 if (modeset_pipes & (1 << intel_crtc->pipe))
4100                         max_pixclk = max(max_pixclk,
4101                                          pipe_config->adjusted_mode.crtc_clock);
4102                 else if (intel_crtc->base.enabled)
4103                         max_pixclk = max(max_pixclk,
4104                                          intel_crtc->config.adjusted_mode.crtc_clock);
4105         }
4106
4107         return max_pixclk;
4108 }
4109
4110 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4111                                             unsigned *prepare_pipes,
4112                                             unsigned modeset_pipes,
4113                                             struct intel_crtc_config *pipe_config)
4114 {
4115         struct drm_i915_private *dev_priv = dev->dev_private;
4116         struct intel_crtc *intel_crtc;
4117         int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4118                                                pipe_config);
4119         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4120
4121         if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4122                 return;
4123
4124         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4125                             base.head)
4126                 if (intel_crtc->base.enabled)
4127                         *prepare_pipes |= (1 << intel_crtc->pipe);
4128 }
4129
4130 static void valleyview_modeset_global_resources(struct drm_device *dev)
4131 {
4132         struct drm_i915_private *dev_priv = dev->dev_private;
4133         int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4134         int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4135         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4136
4137         if (req_cdclk != cur_cdclk)
4138                 valleyview_set_cdclk(dev, req_cdclk);
4139 }
4140
4141 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4142 {
4143         struct drm_device *dev = crtc->dev;
4144         struct drm_i915_private *dev_priv = dev->dev_private;
4145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4146         struct intel_encoder *encoder;
4147         int pipe = intel_crtc->pipe;
4148         int plane = intel_crtc->plane;
4149         bool is_dsi;
4150
4151         WARN_ON(!crtc->enabled);
4152
4153         if (intel_crtc->active)
4154                 return;
4155
4156         intel_crtc->active = true;
4157
4158         for_each_encoder_on_crtc(dev, crtc, encoder)
4159                 if (encoder->pre_pll_enable)
4160                         encoder->pre_pll_enable(encoder);
4161
4162         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4163
4164         if (!is_dsi)
4165                 vlv_enable_pll(intel_crtc);
4166
4167         for_each_encoder_on_crtc(dev, crtc, encoder)
4168                 if (encoder->pre_enable)
4169                         encoder->pre_enable(encoder);
4170
4171         i9xx_pfit_enable(intel_crtc);
4172
4173         intel_crtc_load_lut(crtc);
4174
4175         intel_update_watermarks(crtc);
4176         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4177         intel_enable_primary_plane(dev_priv, plane, pipe);
4178         intel_enable_planes(crtc);
4179         intel_crtc_update_cursor(crtc, true);
4180
4181         intel_update_fbc(dev);
4182
4183         for_each_encoder_on_crtc(dev, crtc, encoder)
4184                 encoder->enable(encoder);
4185 }
4186
4187 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4188 {
4189         struct drm_device *dev = crtc->dev;
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192         struct intel_encoder *encoder;
4193         int pipe = intel_crtc->pipe;
4194         int plane = intel_crtc->plane;
4195
4196         WARN_ON(!crtc->enabled);
4197
4198         if (intel_crtc->active)
4199                 return;
4200
4201         intel_crtc->active = true;
4202
4203         for_each_encoder_on_crtc(dev, crtc, encoder)
4204                 if (encoder->pre_enable)
4205                         encoder->pre_enable(encoder);
4206
4207         i9xx_enable_pll(intel_crtc);
4208
4209         i9xx_pfit_enable(intel_crtc);
4210
4211         intel_crtc_load_lut(crtc);
4212
4213         intel_update_watermarks(crtc);
4214         intel_enable_pipe(dev_priv, pipe, false, false);
4215         intel_enable_primary_plane(dev_priv, plane, pipe);
4216         intel_enable_planes(crtc);
4217         /* The fixup needs to happen before cursor is enabled */
4218         if (IS_G4X(dev))
4219                 g4x_fixup_plane(dev_priv, pipe);
4220         intel_crtc_update_cursor(crtc, true);
4221
4222         /* Give the overlay scaler a chance to enable if it's on this pipe */
4223         intel_crtc_dpms_overlay(intel_crtc, true);
4224
4225         intel_update_fbc(dev);
4226
4227         for_each_encoder_on_crtc(dev, crtc, encoder)
4228                 encoder->enable(encoder);
4229 }
4230
4231 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4232 {
4233         struct drm_device *dev = crtc->base.dev;
4234         struct drm_i915_private *dev_priv = dev->dev_private;
4235
4236         if (!crtc->config.gmch_pfit.control)
4237                 return;
4238
4239         assert_pipe_disabled(dev_priv, crtc->pipe);
4240
4241         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4242                          I915_READ(PFIT_CONTROL));
4243         I915_WRITE(PFIT_CONTROL, 0);
4244 }
4245
4246 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4247 {
4248         struct drm_device *dev = crtc->dev;
4249         struct drm_i915_private *dev_priv = dev->dev_private;
4250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251         struct intel_encoder *encoder;
4252         int pipe = intel_crtc->pipe;
4253         int plane = intel_crtc->plane;
4254
4255         if (!intel_crtc->active)
4256                 return;
4257
4258         for_each_encoder_on_crtc(dev, crtc, encoder)
4259                 encoder->disable(encoder);
4260
4261         /* Give the overlay scaler a chance to disable if it's on this pipe */
4262         intel_crtc_wait_for_pending_flips(crtc);
4263         drm_vblank_off(dev, pipe);
4264
4265         if (dev_priv->fbc.plane == plane)
4266                 intel_disable_fbc(dev);
4267
4268         intel_crtc_dpms_overlay(intel_crtc, false);
4269         intel_crtc_update_cursor(crtc, false);
4270         intel_disable_planes(crtc);
4271         intel_disable_primary_plane(dev_priv, plane, pipe);
4272
4273         intel_disable_pipe(dev_priv, pipe);
4274
4275         i9xx_pfit_disable(intel_crtc);
4276
4277         for_each_encoder_on_crtc(dev, crtc, encoder)
4278                 if (encoder->post_disable)
4279                         encoder->post_disable(encoder);
4280
4281         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4282                 vlv_disable_pll(dev_priv, pipe);
4283         else if (!IS_VALLEYVIEW(dev))
4284                 i9xx_disable_pll(dev_priv, pipe);
4285
4286         intel_crtc->active = false;
4287         intel_update_watermarks(crtc);
4288
4289         intel_update_fbc(dev);
4290 }
4291
4292 static void i9xx_crtc_off(struct drm_crtc *crtc)
4293 {
4294 }
4295
4296 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4297                                     bool enabled)
4298 {
4299         struct drm_device *dev = crtc->dev;
4300         struct drm_i915_master_private *master_priv;
4301         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4302         int pipe = intel_crtc->pipe;
4303
4304         if (!dev->primary->master)
4305                 return;
4306
4307         master_priv = dev->primary->master->driver_priv;
4308         if (!master_priv->sarea_priv)
4309                 return;
4310
4311         switch (pipe) {
4312         case 0:
4313                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4314                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4315                 break;
4316         case 1:
4317                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4318                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4319                 break;
4320         default:
4321                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4322                 break;
4323         }
4324 }
4325
4326 /**
4327  * Sets the power management mode of the pipe and plane.
4328  */
4329 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4330 {
4331         struct drm_device *dev = crtc->dev;
4332         struct drm_i915_private *dev_priv = dev->dev_private;
4333         struct intel_encoder *intel_encoder;
4334         bool enable = false;
4335
4336         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4337                 enable |= intel_encoder->connectors_active;
4338
4339         if (enable)
4340                 dev_priv->display.crtc_enable(crtc);
4341         else
4342                 dev_priv->display.crtc_disable(crtc);
4343
4344         intel_crtc_update_sarea(crtc, enable);
4345 }
4346
4347 static void intel_crtc_disable(struct drm_crtc *crtc)
4348 {
4349         struct drm_device *dev = crtc->dev;
4350         struct drm_connector *connector;
4351         struct drm_i915_private *dev_priv = dev->dev_private;
4352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4353
4354         /* crtc should still be enabled when we disable it. */
4355         WARN_ON(!crtc->enabled);
4356
4357         dev_priv->display.crtc_disable(crtc);
4358         intel_crtc->eld_vld = false;
4359         intel_crtc_update_sarea(crtc, false);
4360         dev_priv->display.off(crtc);
4361
4362         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4363         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4364         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4365
4366         if (crtc->fb) {
4367                 mutex_lock(&dev->struct_mutex);
4368                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4369                 mutex_unlock(&dev->struct_mutex);
4370                 crtc->fb = NULL;
4371         }
4372
4373         /* Update computed state. */
4374         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4375                 if (!connector->encoder || !connector->encoder->crtc)
4376                         continue;
4377
4378                 if (connector->encoder->crtc != crtc)
4379                         continue;
4380
4381                 connector->dpms = DRM_MODE_DPMS_OFF;
4382                 to_intel_encoder(connector->encoder)->connectors_active = false;
4383         }
4384 }
4385
4386 void intel_encoder_destroy(struct drm_encoder *encoder)
4387 {
4388         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4389
4390         drm_encoder_cleanup(encoder);
4391         kfree(intel_encoder);
4392 }
4393
4394 /* Simple dpms helper for encoders with just one connector, no cloning and only
4395  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4396  * state of the entire output pipe. */
4397 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4398 {
4399         if (mode == DRM_MODE_DPMS_ON) {
4400                 encoder->connectors_active = true;
4401
4402                 intel_crtc_update_dpms(encoder->base.crtc);
4403         } else {
4404                 encoder->connectors_active = false;
4405
4406                 intel_crtc_update_dpms(encoder->base.crtc);
4407         }
4408 }
4409
4410 /* Cross check the actual hw state with our own modeset state tracking (and it's
4411  * internal consistency). */
4412 static void intel_connector_check_state(struct intel_connector *connector)
4413 {
4414         if (connector->get_hw_state(connector)) {
4415                 struct intel_encoder *encoder = connector->encoder;
4416                 struct drm_crtc *crtc;
4417                 bool encoder_enabled;
4418                 enum pipe pipe;
4419
4420                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4421                               connector->base.base.id,
4422                               drm_get_connector_name(&connector->base));
4423
4424                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4425                      "wrong connector dpms state\n");
4426                 WARN(connector->base.encoder != &encoder->base,
4427                      "active connector not linked to encoder\n");
4428                 WARN(!encoder->connectors_active,
4429                      "encoder->connectors_active not set\n");
4430
4431                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4432                 WARN(!encoder_enabled, "encoder not enabled\n");
4433                 if (WARN_ON(!encoder->base.crtc))
4434                         return;
4435
4436                 crtc = encoder->base.crtc;
4437
4438                 WARN(!crtc->enabled, "crtc not enabled\n");
4439                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4440                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4441                      "encoder active on the wrong pipe\n");
4442         }
4443 }
4444
4445 /* Even simpler default implementation, if there's really no special case to
4446  * consider. */
4447 void intel_connector_dpms(struct drm_connector *connector, int mode)
4448 {
4449         /* All the simple cases only support two dpms states. */
4450         if (mode != DRM_MODE_DPMS_ON)
4451                 mode = DRM_MODE_DPMS_OFF;
4452
4453         if (mode == connector->dpms)
4454                 return;
4455
4456         connector->dpms = mode;
4457
4458         /* Only need to change hw state when actually enabled */
4459         if (connector->encoder)
4460                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4461
4462         intel_modeset_check_state(connector->dev);
4463 }
4464
4465 /* Simple connector->get_hw_state implementation for encoders that support only
4466  * one connector and no cloning and hence the encoder state determines the state
4467  * of the connector. */
4468 bool intel_connector_get_hw_state(struct intel_connector *connector)
4469 {
4470         enum pipe pipe = 0;
4471         struct intel_encoder *encoder = connector->encoder;
4472
4473         return encoder->get_hw_state(encoder, &pipe);
4474 }
4475
4476 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4477                                      struct intel_crtc_config *pipe_config)
4478 {
4479         struct drm_i915_private *dev_priv = dev->dev_private;
4480         struct intel_crtc *pipe_B_crtc =
4481                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4482
4483         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4484                       pipe_name(pipe), pipe_config->fdi_lanes);
4485         if (pipe_config->fdi_lanes > 4) {
4486                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4487                               pipe_name(pipe), pipe_config->fdi_lanes);
4488                 return false;
4489         }
4490
4491         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4492                 if (pipe_config->fdi_lanes > 2) {
4493                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4494                                       pipe_config->fdi_lanes);
4495                         return false;
4496                 } else {
4497                         return true;
4498                 }
4499         }
4500
4501         if (INTEL_INFO(dev)->num_pipes == 2)
4502                 return true;
4503
4504         /* Ivybridge 3 pipe is really complicated */
4505         switch (pipe) {
4506         case PIPE_A:
4507                 return true;
4508         case PIPE_B:
4509                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4510                     pipe_config->fdi_lanes > 2) {
4511                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4512                                       pipe_name(pipe), pipe_config->fdi_lanes);
4513                         return false;
4514                 }
4515                 return true;
4516         case PIPE_C:
4517                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4518                     pipe_B_crtc->config.fdi_lanes <= 2) {
4519                         if (pipe_config->fdi_lanes > 2) {
4520                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4521                                               pipe_name(pipe), pipe_config->fdi_lanes);
4522                                 return false;
4523                         }
4524                 } else {
4525                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4526                         return false;
4527                 }
4528                 return true;
4529         default:
4530                 BUG();
4531         }
4532 }
4533
4534 #define RETRY 1
4535 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4536                                        struct intel_crtc_config *pipe_config)
4537 {
4538         struct drm_device *dev = intel_crtc->base.dev;
4539         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4540         int lane, link_bw, fdi_dotclock;
4541         bool setup_ok, needs_recompute = false;
4542
4543 retry:
4544         /* FDI is a binary signal running at ~2.7GHz, encoding
4545          * each output octet as 10 bits. The actual frequency
4546          * is stored as a divider into a 100MHz clock, and the
4547          * mode pixel clock is stored in units of 1KHz.
4548          * Hence the bw of each lane in terms of the mode signal
4549          * is:
4550          */
4551         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4552
4553         fdi_dotclock = adjusted_mode->crtc_clock;
4554
4555         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4556                                            pipe_config->pipe_bpp);
4557
4558         pipe_config->fdi_lanes = lane;
4559
4560         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4561                                link_bw, &pipe_config->fdi_m_n);
4562
4563         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4564                                             intel_crtc->pipe, pipe_config);
4565         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4566                 pipe_config->pipe_bpp -= 2*3;
4567                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4568                               pipe_config->pipe_bpp);
4569                 needs_recompute = true;
4570                 pipe_config->bw_constrained = true;
4571
4572                 goto retry;
4573         }
4574
4575         if (needs_recompute)
4576                 return RETRY;
4577
4578         return setup_ok ? 0 : -EINVAL;
4579 }
4580
4581 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4582                                    struct intel_crtc_config *pipe_config)
4583 {
4584         pipe_config->ips_enabled = i915_enable_ips &&
4585                                    hsw_crtc_supports_ips(crtc) &&
4586                                    pipe_config->pipe_bpp <= 24;
4587 }
4588
4589 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4590                                      struct intel_crtc_config *pipe_config)
4591 {
4592         struct drm_device *dev = crtc->base.dev;
4593         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4594
4595         /* FIXME should check pixel clock limits on all platforms */
4596         if (INTEL_INFO(dev)->gen < 4) {
4597                 struct drm_i915_private *dev_priv = dev->dev_private;
4598                 int clock_limit =
4599                         dev_priv->display.get_display_clock_speed(dev);
4600
4601                 /*
4602                  * Enable pixel doubling when the dot clock
4603                  * is > 90% of the (display) core speed.
4604                  *
4605                  * GDG double wide on either pipe,
4606                  * otherwise pipe A only.
4607                  */
4608                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4609                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4610                         clock_limit *= 2;
4611                         pipe_config->double_wide = true;
4612                 }
4613
4614                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4615                         return -EINVAL;
4616         }
4617
4618         /*
4619          * Pipe horizontal size must be even in:
4620          * - DVO ganged mode
4621          * - LVDS dual channel mode
4622          * - Double wide pipe
4623          */
4624         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4625              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4626                 pipe_config->pipe_src_w &= ~1;
4627
4628         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4629          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4630          */
4631         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4632                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4633                 return -EINVAL;
4634
4635         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4636                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4637         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4638                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4639                  * for lvds. */
4640                 pipe_config->pipe_bpp = 8*3;
4641         }
4642
4643         if (HAS_IPS(dev))
4644                 hsw_compute_ips_config(crtc, pipe_config);
4645
4646         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4647          * clock survives for now. */
4648         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4649                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4650
4651         if (pipe_config->has_pch_encoder)
4652                 return ironlake_fdi_compute_config(crtc, pipe_config);
4653
4654         return 0;
4655 }
4656
4657 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4658 {
4659         return 400000; /* FIXME */
4660 }
4661
4662 static int i945_get_display_clock_speed(struct drm_device *dev)
4663 {
4664         return 400000;
4665 }
4666
4667 static int i915_get_display_clock_speed(struct drm_device *dev)
4668 {
4669         return 333000;
4670 }
4671
4672 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4673 {
4674         return 200000;
4675 }
4676
4677 static int pnv_get_display_clock_speed(struct drm_device *dev)
4678 {
4679         u16 gcfgc = 0;
4680
4681         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4682
4683         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4684         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4685                 return 267000;
4686         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4687                 return 333000;
4688         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4689                 return 444000;
4690         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4691                 return 200000;
4692         default:
4693                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4694         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4695                 return 133000;
4696         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4697                 return 167000;
4698         }
4699 }
4700
4701 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4702 {
4703         u16 gcfgc = 0;
4704
4705         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4706
4707         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4708                 return 133000;
4709         else {
4710                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4711                 case GC_DISPLAY_CLOCK_333_MHZ:
4712                         return 333000;
4713                 default:
4714                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4715                         return 190000;
4716                 }
4717         }
4718 }
4719
4720 static int i865_get_display_clock_speed(struct drm_device *dev)
4721 {
4722         return 266000;
4723 }
4724
4725 static int i855_get_display_clock_speed(struct drm_device *dev)
4726 {
4727         u16 hpllcc = 0;
4728         /* Assume that the hardware is in the high speed state.  This
4729          * should be the default.
4730          */
4731         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4732         case GC_CLOCK_133_200:
4733         case GC_CLOCK_100_200:
4734                 return 200000;
4735         case GC_CLOCK_166_250:
4736                 return 250000;
4737         case GC_CLOCK_100_133:
4738                 return 133000;
4739         }
4740
4741         /* Shouldn't happen */
4742         return 0;
4743 }
4744
4745 static int i830_get_display_clock_speed(struct drm_device *dev)
4746 {
4747         return 133000;
4748 }
4749
4750 static void
4751 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4752 {
4753         while (*num > DATA_LINK_M_N_MASK ||
4754                *den > DATA_LINK_M_N_MASK) {
4755                 *num >>= 1;
4756                 *den >>= 1;
4757         }
4758 }
4759
4760 static void compute_m_n(unsigned int m, unsigned int n,
4761                         uint32_t *ret_m, uint32_t *ret_n)
4762 {
4763         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4764         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4765         intel_reduce_m_n_ratio(ret_m, ret_n);
4766 }
4767
4768 void
4769 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4770                        int pixel_clock, int link_clock,
4771                        struct intel_link_m_n *m_n)
4772 {
4773         m_n->tu = 64;
4774
4775         compute_m_n(bits_per_pixel * pixel_clock,
4776                     link_clock * nlanes * 8,
4777                     &m_n->gmch_m, &m_n->gmch_n);
4778
4779         compute_m_n(pixel_clock, link_clock,
4780                     &m_n->link_m, &m_n->link_n);
4781 }
4782
4783 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4784 {
4785         if (i915_panel_use_ssc >= 0)
4786                 return i915_panel_use_ssc != 0;
4787         return dev_priv->vbt.lvds_use_ssc
4788                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4789 }
4790
4791 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4792 {
4793         struct drm_device *dev = crtc->dev;
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         int refclk;
4796
4797         if (IS_VALLEYVIEW(dev)) {
4798                 refclk = 100000;
4799         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4800             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4801                 refclk = dev_priv->vbt.lvds_ssc_freq;
4802                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4803         } else if (!IS_GEN2(dev)) {
4804                 refclk = 96000;
4805         } else {
4806                 refclk = 48000;
4807         }
4808
4809         return refclk;
4810 }
4811
4812 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4813 {
4814         return (1 << dpll->n) << 16 | dpll->m2;
4815 }
4816
4817 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4818 {
4819         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4820 }
4821
4822 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4823                                      intel_clock_t *reduced_clock)
4824 {
4825         struct drm_device *dev = crtc->base.dev;
4826         struct drm_i915_private *dev_priv = dev->dev_private;
4827         int pipe = crtc->pipe;
4828         u32 fp, fp2 = 0;
4829
4830         if (IS_PINEVIEW(dev)) {
4831                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4832                 if (reduced_clock)
4833                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4834         } else {
4835                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4836                 if (reduced_clock)
4837                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4838         }
4839
4840         I915_WRITE(FP0(pipe), fp);
4841         crtc->config.dpll_hw_state.fp0 = fp;
4842
4843         crtc->lowfreq_avail = false;
4844         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4845             reduced_clock && i915_powersave) {
4846                 I915_WRITE(FP1(pipe), fp2);
4847                 crtc->config.dpll_hw_state.fp1 = fp2;
4848                 crtc->lowfreq_avail = true;
4849         } else {
4850                 I915_WRITE(FP1(pipe), fp);
4851                 crtc->config.dpll_hw_state.fp1 = fp;
4852         }
4853 }
4854
4855 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4856                 pipe)
4857 {
4858         u32 reg_val;
4859
4860         /*
4861          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4862          * and set it to a reasonable value instead.
4863          */
4864         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4865         reg_val &= 0xffffff00;
4866         reg_val |= 0x00000030;
4867         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4868
4869         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4870         reg_val &= 0x8cffffff;
4871         reg_val = 0x8c000000;
4872         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4873
4874         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4875         reg_val &= 0xffffff00;
4876         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4877
4878         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4879         reg_val &= 0x00ffffff;
4880         reg_val |= 0xb0000000;
4881         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4882 }
4883
4884 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4885                                          struct intel_link_m_n *m_n)
4886 {
4887         struct drm_device *dev = crtc->base.dev;
4888         struct drm_i915_private *dev_priv = dev->dev_private;
4889         int pipe = crtc->pipe;
4890
4891         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4892         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4893         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4894         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4895 }
4896
4897 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4898                                          struct intel_link_m_n *m_n)
4899 {
4900         struct drm_device *dev = crtc->base.dev;
4901         struct drm_i915_private *dev_priv = dev->dev_private;
4902         int pipe = crtc->pipe;
4903         enum transcoder transcoder = crtc->config.cpu_transcoder;
4904
4905         if (INTEL_INFO(dev)->gen >= 5) {
4906                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4907                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4908                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4909                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4910         } else {
4911                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4912                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4913                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4914                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4915         }
4916 }
4917
4918 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4919 {
4920         if (crtc->config.has_pch_encoder)
4921                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4922         else
4923                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4924 }
4925
4926 static void vlv_update_pll(struct intel_crtc *crtc)
4927 {
4928         struct drm_device *dev = crtc->base.dev;
4929         struct drm_i915_private *dev_priv = dev->dev_private;
4930         int pipe = crtc->pipe;
4931         u32 dpll, mdiv;
4932         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4933         u32 coreclk, reg_val, dpll_md;
4934
4935         mutex_lock(&dev_priv->dpio_lock);
4936
4937         bestn = crtc->config.dpll.n;
4938         bestm1 = crtc->config.dpll.m1;
4939         bestm2 = crtc->config.dpll.m2;
4940         bestp1 = crtc->config.dpll.p1;
4941         bestp2 = crtc->config.dpll.p2;
4942
4943         /* See eDP HDMI DPIO driver vbios notes doc */
4944
4945         /* PLL B needs special handling */
4946         if (pipe)
4947                 vlv_pllb_recal_opamp(dev_priv, pipe);
4948
4949         /* Set up Tx target for periodic Rcomp update */
4950         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4951
4952         /* Disable target IRef on PLL */
4953         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4954         reg_val &= 0x00ffffff;
4955         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4956
4957         /* Disable fast lock */
4958         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4959
4960         /* Set idtafcrecal before PLL is enabled */
4961         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4962         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4963         mdiv |= ((bestn << DPIO_N_SHIFT));
4964         mdiv |= (1 << DPIO_K_SHIFT);
4965
4966         /*
4967          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4968          * but we don't support that).
4969          * Note: don't use the DAC post divider as it seems unstable.
4970          */
4971         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4972         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4973
4974         mdiv |= DPIO_ENABLE_CALIBRATION;
4975         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4976
4977         /* Set HBR and RBR LPF coefficients */
4978         if (crtc->config.port_clock == 162000 ||
4979             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4980             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4981                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4982                                  0x009f0003);
4983         else
4984                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4985                                  0x00d0000f);
4986
4987         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4988             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4989                 /* Use SSC source */
4990                 if (!pipe)
4991                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4992                                          0x0df40000);
4993                 else
4994                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4995                                          0x0df70000);
4996         } else { /* HDMI or VGA */
4997                 /* Use bend source */
4998                 if (!pipe)
4999                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5000                                          0x0df70000);
5001                 else
5002                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5003                                          0x0df40000);
5004         }
5005
5006         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5007         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5008         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5009             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5010                 coreclk |= 0x01000000;
5011         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5012
5013         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5014
5015         /*
5016          * Enable DPIO clock input. We should never disable the reference
5017          * clock for pipe B, since VGA hotplug / manual detection depends
5018          * on it.
5019          */
5020         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5021                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5022         /* We should never disable this, set it here for state tracking */
5023         if (pipe == PIPE_B)
5024                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5025         dpll |= DPLL_VCO_ENABLE;
5026         crtc->config.dpll_hw_state.dpll = dpll;
5027
5028         dpll_md = (crtc->config.pixel_multiplier - 1)
5029                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5030         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5031
5032         if (crtc->config.has_dp_encoder)
5033                 intel_dp_set_m_n(crtc);
5034
5035         mutex_unlock(&dev_priv->dpio_lock);
5036 }
5037
5038 static void i9xx_update_pll(struct intel_crtc *crtc,
5039                             intel_clock_t *reduced_clock,
5040                             int num_connectors)
5041 {
5042         struct drm_device *dev = crtc->base.dev;
5043         struct drm_i915_private *dev_priv = dev->dev_private;
5044         u32 dpll;
5045         bool is_sdvo;
5046         struct dpll *clock = &crtc->config.dpll;
5047
5048         i9xx_update_pll_dividers(crtc, reduced_clock);
5049
5050         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5051                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5052
5053         dpll = DPLL_VGA_MODE_DIS;
5054
5055         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5056                 dpll |= DPLLB_MODE_LVDS;
5057         else
5058                 dpll |= DPLLB_MODE_DAC_SERIAL;
5059
5060         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5061                 dpll |= (crtc->config.pixel_multiplier - 1)
5062                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5063         }
5064
5065         if (is_sdvo)
5066                 dpll |= DPLL_SDVO_HIGH_SPEED;
5067
5068         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5069                 dpll |= DPLL_SDVO_HIGH_SPEED;
5070
5071         /* compute bitmask from p1 value */
5072         if (IS_PINEVIEW(dev))
5073                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5074         else {
5075                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5076                 if (IS_G4X(dev) && reduced_clock)
5077                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5078         }
5079         switch (clock->p2) {
5080         case 5:
5081                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5082                 break;
5083         case 7:
5084                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5085                 break;
5086         case 10:
5087                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5088                 break;
5089         case 14:
5090                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5091                 break;
5092         }
5093         if (INTEL_INFO(dev)->gen >= 4)
5094                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5095
5096         if (crtc->config.sdvo_tv_clock)
5097                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5098         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5099                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5100                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5101         else
5102                 dpll |= PLL_REF_INPUT_DREFCLK;
5103
5104         dpll |= DPLL_VCO_ENABLE;
5105         crtc->config.dpll_hw_state.dpll = dpll;
5106
5107         if (INTEL_INFO(dev)->gen >= 4) {
5108                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5109                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5110                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5111         }
5112
5113         if (crtc->config.has_dp_encoder)
5114                 intel_dp_set_m_n(crtc);
5115 }
5116
5117 static void i8xx_update_pll(struct intel_crtc *crtc,
5118                             intel_clock_t *reduced_clock,
5119                             int num_connectors)
5120 {
5121         struct drm_device *dev = crtc->base.dev;
5122         struct drm_i915_private *dev_priv = dev->dev_private;
5123         u32 dpll;
5124         struct dpll *clock = &crtc->config.dpll;
5125
5126         i9xx_update_pll_dividers(crtc, reduced_clock);
5127
5128         dpll = DPLL_VGA_MODE_DIS;
5129
5130         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5131                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5132         } else {
5133                 if (clock->p1 == 2)
5134                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5135                 else
5136                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5137                 if (clock->p2 == 4)
5138                         dpll |= PLL_P2_DIVIDE_BY_4;
5139         }
5140
5141         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5142                 dpll |= DPLL_DVO_2X_MODE;
5143
5144         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5145                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5146                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5147         else
5148                 dpll |= PLL_REF_INPUT_DREFCLK;
5149
5150         dpll |= DPLL_VCO_ENABLE;
5151         crtc->config.dpll_hw_state.dpll = dpll;
5152 }
5153
5154 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5155 {
5156         struct drm_device *dev = intel_crtc->base.dev;
5157         struct drm_i915_private *dev_priv = dev->dev_private;
5158         enum pipe pipe = intel_crtc->pipe;
5159         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5160         struct drm_display_mode *adjusted_mode =
5161                 &intel_crtc->config.adjusted_mode;
5162         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5163
5164         /* We need to be careful not to changed the adjusted mode, for otherwise
5165          * the hw state checker will get angry at the mismatch. */
5166         crtc_vtotal = adjusted_mode->crtc_vtotal;
5167         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5168
5169         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5170                 /* the chip adds 2 halflines automatically */
5171                 crtc_vtotal -= 1;
5172                 crtc_vblank_end -= 1;
5173                 vsyncshift = adjusted_mode->crtc_hsync_start
5174                              - adjusted_mode->crtc_htotal / 2;
5175         } else {
5176                 vsyncshift = 0;
5177         }
5178
5179         if (INTEL_INFO(dev)->gen > 3)
5180                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5181
5182         I915_WRITE(HTOTAL(cpu_transcoder),
5183                    (adjusted_mode->crtc_hdisplay - 1) |
5184                    ((adjusted_mode->crtc_htotal - 1) << 16));
5185         I915_WRITE(HBLANK(cpu_transcoder),
5186                    (adjusted_mode->crtc_hblank_start - 1) |
5187                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5188         I915_WRITE(HSYNC(cpu_transcoder),
5189                    (adjusted_mode->crtc_hsync_start - 1) |
5190                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5191
5192         I915_WRITE(VTOTAL(cpu_transcoder),
5193                    (adjusted_mode->crtc_vdisplay - 1) |
5194                    ((crtc_vtotal - 1) << 16));
5195         I915_WRITE(VBLANK(cpu_transcoder),
5196                    (adjusted_mode->crtc_vblank_start - 1) |
5197                    ((crtc_vblank_end - 1) << 16));
5198         I915_WRITE(VSYNC(cpu_transcoder),
5199                    (adjusted_mode->crtc_vsync_start - 1) |
5200                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5201
5202         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5203          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5204          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5205          * bits. */
5206         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5207             (pipe == PIPE_B || pipe == PIPE_C))
5208                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5209
5210         /* pipesrc controls the size that is scaled from, which should
5211          * always be the user's requested size.
5212          */
5213         I915_WRITE(PIPESRC(pipe),
5214                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5215                    (intel_crtc->config.pipe_src_h - 1));
5216 }
5217
5218 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5219                                    struct intel_crtc_config *pipe_config)
5220 {
5221         struct drm_device *dev = crtc->base.dev;
5222         struct drm_i915_private *dev_priv = dev->dev_private;
5223         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5224         uint32_t tmp;
5225
5226         tmp = I915_READ(HTOTAL(cpu_transcoder));
5227         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5228         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5229         tmp = I915_READ(HBLANK(cpu_transcoder));
5230         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5231         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5232         tmp = I915_READ(HSYNC(cpu_transcoder));
5233         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5234         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5235
5236         tmp = I915_READ(VTOTAL(cpu_transcoder));
5237         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5238         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5239         tmp = I915_READ(VBLANK(cpu_transcoder));
5240         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5241         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5242         tmp = I915_READ(VSYNC(cpu_transcoder));
5243         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5244         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5245
5246         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5247                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5248                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5249                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5250         }
5251
5252         tmp = I915_READ(PIPESRC(crtc->pipe));
5253         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5254         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5255
5256         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5257         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5258 }
5259
5260 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5261                                              struct intel_crtc_config *pipe_config)
5262 {
5263         struct drm_crtc *crtc = &intel_crtc->base;
5264
5265         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5266         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5267         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5268         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5269
5270         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5271         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5272         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5273         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5274
5275         crtc->mode.flags = pipe_config->adjusted_mode.flags;
5276
5277         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5278         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5279 }
5280
5281 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5282 {
5283         struct drm_device *dev = intel_crtc->base.dev;
5284         struct drm_i915_private *dev_priv = dev->dev_private;
5285         uint32_t pipeconf;
5286
5287         pipeconf = 0;
5288
5289         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5290             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5291                 pipeconf |= PIPECONF_ENABLE;
5292
5293         if (intel_crtc->config.double_wide)
5294                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5295
5296         /* only g4x and later have fancy bpc/dither controls */
5297         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5298                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5299                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5300                         pipeconf |= PIPECONF_DITHER_EN |
5301                                     PIPECONF_DITHER_TYPE_SP;
5302
5303                 switch (intel_crtc->config.pipe_bpp) {
5304                 case 18:
5305                         pipeconf |= PIPECONF_6BPC;
5306                         break;
5307                 case 24:
5308                         pipeconf |= PIPECONF_8BPC;
5309                         break;
5310                 case 30:
5311                         pipeconf |= PIPECONF_10BPC;
5312                         break;
5313                 default:
5314                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5315                         BUG();
5316                 }
5317         }
5318
5319         if (HAS_PIPE_CXSR(dev)) {
5320                 if (intel_crtc->lowfreq_avail) {
5321                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5322                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5323                 } else {
5324                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5325                 }
5326         }
5327
5328         if (!IS_GEN2(dev) &&
5329             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5330                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5331         else
5332                 pipeconf |= PIPECONF_PROGRESSIVE;
5333
5334         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5335                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5336
5337         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5338         POSTING_READ(PIPECONF(intel_crtc->pipe));
5339 }
5340
5341 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5342                               int x, int y,
5343                               struct drm_framebuffer *fb)
5344 {
5345         struct drm_device *dev = crtc->dev;
5346         struct drm_i915_private *dev_priv = dev->dev_private;
5347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348         int pipe = intel_crtc->pipe;
5349         int plane = intel_crtc->plane;
5350         int refclk, num_connectors = 0;
5351         intel_clock_t clock, reduced_clock;
5352         u32 dspcntr;
5353         bool ok, has_reduced_clock = false;
5354         bool is_lvds = false, is_dsi = false;
5355         struct intel_encoder *encoder;
5356         const intel_limit_t *limit;
5357         int ret;
5358
5359         for_each_encoder_on_crtc(dev, crtc, encoder) {
5360                 switch (encoder->type) {
5361                 case INTEL_OUTPUT_LVDS:
5362                         is_lvds = true;
5363                         break;
5364                 case INTEL_OUTPUT_DSI:
5365                         is_dsi = true;
5366                         break;
5367                 }
5368
5369                 num_connectors++;
5370         }
5371
5372         if (is_dsi)
5373                 goto skip_dpll;
5374
5375         if (!intel_crtc->config.clock_set) {
5376                 refclk = i9xx_get_refclk(crtc, num_connectors);
5377
5378                 /*
5379                  * Returns a set of divisors for the desired target clock with
5380                  * the given refclk, or FALSE.  The returned values represent
5381                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5382                  * 2) / p1 / p2.
5383                  */
5384                 limit = intel_limit(crtc, refclk);
5385                 ok = dev_priv->display.find_dpll(limit, crtc,
5386                                                  intel_crtc->config.port_clock,
5387                                                  refclk, NULL, &clock);
5388                 if (!ok) {
5389                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5390                         return -EINVAL;
5391                 }
5392
5393                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5394                         /*
5395                          * Ensure we match the reduced clock's P to the target
5396                          * clock.  If the clocks don't match, we can't switch
5397                          * the display clock by using the FP0/FP1. In such case
5398                          * we will disable the LVDS downclock feature.
5399                          */
5400                         has_reduced_clock =
5401                                 dev_priv->display.find_dpll(limit, crtc,
5402                                                             dev_priv->lvds_downclock,
5403                                                             refclk, &clock,
5404                                                             &reduced_clock);
5405                 }
5406                 /* Compat-code for transition, will disappear. */
5407                 intel_crtc->config.dpll.n = clock.n;
5408                 intel_crtc->config.dpll.m1 = clock.m1;
5409                 intel_crtc->config.dpll.m2 = clock.m2;
5410                 intel_crtc->config.dpll.p1 = clock.p1;
5411                 intel_crtc->config.dpll.p2 = clock.p2;
5412         }
5413
5414         if (IS_GEN2(dev)) {
5415                 i8xx_update_pll(intel_crtc,
5416                                 has_reduced_clock ? &reduced_clock : NULL,
5417                                 num_connectors);
5418         } else if (IS_VALLEYVIEW(dev)) {
5419                 vlv_update_pll(intel_crtc);
5420         } else {
5421                 i9xx_update_pll(intel_crtc,
5422                                 has_reduced_clock ? &reduced_clock : NULL,
5423                                 num_connectors);
5424         }
5425
5426 skip_dpll:
5427         /* Set up the display plane register */
5428         dspcntr = DISPPLANE_GAMMA_ENABLE;
5429
5430         if (!IS_VALLEYVIEW(dev)) {
5431                 if (pipe == 0)
5432                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5433                 else
5434                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5435         }
5436
5437         intel_set_pipe_timings(intel_crtc);
5438
5439         /* pipesrc and dspsize control the size that is scaled from,
5440          * which should always be the user's requested size.
5441          */
5442         I915_WRITE(DSPSIZE(plane),
5443                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5444                    (intel_crtc->config.pipe_src_w - 1));
5445         I915_WRITE(DSPPOS(plane), 0);
5446
5447         i9xx_set_pipeconf(intel_crtc);
5448
5449         I915_WRITE(DSPCNTR(plane), dspcntr);
5450         POSTING_READ(DSPCNTR(plane));
5451
5452         ret = intel_pipe_set_base(crtc, x, y, fb);
5453
5454         return ret;
5455 }
5456
5457 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5458                                  struct intel_crtc_config *pipe_config)
5459 {
5460         struct drm_device *dev = crtc->base.dev;
5461         struct drm_i915_private *dev_priv = dev->dev_private;
5462         uint32_t tmp;
5463
5464         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5465                 return;
5466
5467         tmp = I915_READ(PFIT_CONTROL);
5468         if (!(tmp & PFIT_ENABLE))
5469                 return;
5470
5471         /* Check whether the pfit is attached to our pipe. */
5472         if (INTEL_INFO(dev)->gen < 4) {
5473                 if (crtc->pipe != PIPE_B)
5474                         return;
5475         } else {
5476                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5477                         return;
5478         }
5479
5480         pipe_config->gmch_pfit.control = tmp;
5481         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5482         if (INTEL_INFO(dev)->gen < 5)
5483                 pipe_config->gmch_pfit.lvds_border_bits =
5484                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5485 }
5486
5487 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5488                                struct intel_crtc_config *pipe_config)
5489 {
5490         struct drm_device *dev = crtc->base.dev;
5491         struct drm_i915_private *dev_priv = dev->dev_private;
5492         int pipe = pipe_config->cpu_transcoder;
5493         intel_clock_t clock;
5494         u32 mdiv;
5495         int refclk = 100000;
5496
5497         mutex_lock(&dev_priv->dpio_lock);
5498         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5499         mutex_unlock(&dev_priv->dpio_lock);
5500
5501         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5502         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5503         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5504         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5505         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5506
5507         vlv_clock(refclk, &clock);
5508
5509         /* clock.dot is the fast clock */
5510         pipe_config->port_clock = clock.dot / 5;
5511 }
5512
5513 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5514                                  struct intel_crtc_config *pipe_config)
5515 {
5516         struct drm_device *dev = crtc->base.dev;
5517         struct drm_i915_private *dev_priv = dev->dev_private;
5518         uint32_t tmp;
5519
5520         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5521         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5522
5523         tmp = I915_READ(PIPECONF(crtc->pipe));
5524         if (!(tmp & PIPECONF_ENABLE))
5525                 return false;
5526
5527         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5528                 switch (tmp & PIPECONF_BPC_MASK) {
5529                 case PIPECONF_6BPC:
5530                         pipe_config->pipe_bpp = 18;
5531                         break;
5532                 case PIPECONF_8BPC:
5533                         pipe_config->pipe_bpp = 24;
5534                         break;
5535                 case PIPECONF_10BPC:
5536                         pipe_config->pipe_bpp = 30;
5537                         break;
5538                 default:
5539                         break;
5540                 }
5541         }
5542
5543         if (INTEL_INFO(dev)->gen < 4)
5544                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5545
5546         intel_get_pipe_timings(crtc, pipe_config);
5547
5548         i9xx_get_pfit_config(crtc, pipe_config);
5549
5550         if (INTEL_INFO(dev)->gen >= 4) {
5551                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5552                 pipe_config->pixel_multiplier =
5553                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5554                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5555                 pipe_config->dpll_hw_state.dpll_md = tmp;
5556         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5557                 tmp = I915_READ(DPLL(crtc->pipe));
5558                 pipe_config->pixel_multiplier =
5559                         ((tmp & SDVO_MULTIPLIER_MASK)
5560                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5561         } else {
5562                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5563                  * port and will be fixed up in the encoder->get_config
5564                  * function. */
5565                 pipe_config->pixel_multiplier = 1;
5566         }
5567         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5568         if (!IS_VALLEYVIEW(dev)) {
5569                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5570                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5571         } else {
5572                 /* Mask out read-only status bits. */
5573                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5574                                                      DPLL_PORTC_READY_MASK |
5575                                                      DPLL_PORTB_READY_MASK);
5576         }
5577
5578         if (IS_VALLEYVIEW(dev))
5579                 vlv_crtc_clock_get(crtc, pipe_config);
5580         else
5581                 i9xx_crtc_clock_get(crtc, pipe_config);
5582
5583         return true;
5584 }
5585
5586 static void ironlake_init_pch_refclk(struct drm_device *dev)
5587 {
5588         struct drm_i915_private *dev_priv = dev->dev_private;
5589         struct drm_mode_config *mode_config = &dev->mode_config;
5590         struct intel_encoder *encoder;
5591         u32 val, final;
5592         bool has_lvds = false;
5593         bool has_cpu_edp = false;
5594         bool has_panel = false;
5595         bool has_ck505 = false;
5596         bool can_ssc = false;
5597
5598         /* We need to take the global config into account */
5599         list_for_each_entry(encoder, &mode_config->encoder_list,
5600                             base.head) {
5601                 switch (encoder->type) {
5602                 case INTEL_OUTPUT_LVDS:
5603                         has_panel = true;
5604                         has_lvds = true;
5605                         break;
5606                 case INTEL_OUTPUT_EDP:
5607                         has_panel = true;
5608                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5609                                 has_cpu_edp = true;
5610                         break;
5611                 }
5612         }
5613
5614         if (HAS_PCH_IBX(dev)) {
5615                 has_ck505 = dev_priv->vbt.display_clock_mode;
5616                 can_ssc = has_ck505;
5617         } else {
5618                 has_ck505 = false;
5619                 can_ssc = true;
5620         }
5621
5622         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5623                       has_panel, has_lvds, has_ck505);
5624
5625         /* Ironlake: try to setup display ref clock before DPLL
5626          * enabling. This is only under driver's control after
5627          * PCH B stepping, previous chipset stepping should be
5628          * ignoring this setting.
5629          */
5630         val = I915_READ(PCH_DREF_CONTROL);
5631
5632         /* As we must carefully and slowly disable/enable each source in turn,
5633          * compute the final state we want first and check if we need to
5634          * make any changes at all.
5635          */
5636         final = val;
5637         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5638         if (has_ck505)
5639                 final |= DREF_NONSPREAD_CK505_ENABLE;
5640         else
5641                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5642
5643         final &= ~DREF_SSC_SOURCE_MASK;
5644         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5645         final &= ~DREF_SSC1_ENABLE;
5646
5647         if (has_panel) {
5648                 final |= DREF_SSC_SOURCE_ENABLE;
5649
5650                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5651                         final |= DREF_SSC1_ENABLE;
5652
5653                 if (has_cpu_edp) {
5654                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5655                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5656                         else
5657                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5658                 } else
5659                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5660         } else {
5661                 final |= DREF_SSC_SOURCE_DISABLE;
5662                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5663         }
5664
5665         if (final == val)
5666                 return;
5667
5668         /* Always enable nonspread source */
5669         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5670
5671         if (has_ck505)
5672                 val |= DREF_NONSPREAD_CK505_ENABLE;
5673         else
5674                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5675
5676         if (has_panel) {
5677                 val &= ~DREF_SSC_SOURCE_MASK;
5678                 val |= DREF_SSC_SOURCE_ENABLE;
5679
5680                 /* SSC must be turned on before enabling the CPU output  */
5681                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5682                         DRM_DEBUG_KMS("Using SSC on panel\n");
5683                         val |= DREF_SSC1_ENABLE;
5684                 } else
5685                         val &= ~DREF_SSC1_ENABLE;
5686
5687                 /* Get SSC going before enabling the outputs */
5688                 I915_WRITE(PCH_DREF_CONTROL, val);
5689                 POSTING_READ(PCH_DREF_CONTROL);
5690                 udelay(200);
5691
5692                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5693
5694                 /* Enable CPU source on CPU attached eDP */
5695                 if (has_cpu_edp) {
5696                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5697                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5698                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5699                         }
5700                         else
5701                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5702                 } else
5703                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5704
5705                 I915_WRITE(PCH_DREF_CONTROL, val);
5706                 POSTING_READ(PCH_DREF_CONTROL);
5707                 udelay(200);
5708         } else {
5709                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5710
5711                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5712
5713                 /* Turn off CPU output */
5714                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5715
5716                 I915_WRITE(PCH_DREF_CONTROL, val);
5717                 POSTING_READ(PCH_DREF_CONTROL);
5718                 udelay(200);
5719
5720                 /* Turn off the SSC source */
5721                 val &= ~DREF_SSC_SOURCE_MASK;
5722                 val |= DREF_SSC_SOURCE_DISABLE;
5723
5724                 /* Turn off SSC1 */
5725                 val &= ~DREF_SSC1_ENABLE;
5726
5727                 I915_WRITE(PCH_DREF_CONTROL, val);
5728                 POSTING_READ(PCH_DREF_CONTROL);
5729                 udelay(200);
5730         }
5731
5732         BUG_ON(val != final);
5733 }
5734
5735 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5736 {
5737         uint32_t tmp;
5738
5739         tmp = I915_READ(SOUTH_CHICKEN2);
5740         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5741         I915_WRITE(SOUTH_CHICKEN2, tmp);
5742
5743         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5744                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5745                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5746
5747         tmp = I915_READ(SOUTH_CHICKEN2);
5748         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5749         I915_WRITE(SOUTH_CHICKEN2, tmp);
5750
5751         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5752                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5753                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5754 }
5755
5756 /* WaMPhyProgramming:hsw */
5757 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5758 {
5759         uint32_t tmp;
5760
5761         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5762         tmp &= ~(0xFF << 24);
5763         tmp |= (0x12 << 24);
5764         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5765
5766         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5767         tmp |= (1 << 11);
5768         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5769
5770         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5771         tmp |= (1 << 11);
5772         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5773
5774         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5775         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5776         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5777
5778         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5779         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5780         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5781
5782         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5783         tmp &= ~(7 << 13);
5784         tmp |= (5 << 13);
5785         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5786
5787         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5788         tmp &= ~(7 << 13);
5789         tmp |= (5 << 13);
5790         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5791
5792         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5793         tmp &= ~0xFF;
5794         tmp |= 0x1C;
5795         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5796
5797         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5798         tmp &= ~0xFF;
5799         tmp |= 0x1C;
5800         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5801
5802         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5803         tmp &= ~(0xFF << 16);
5804         tmp |= (0x1C << 16);
5805         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5806
5807         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5808         tmp &= ~(0xFF << 16);
5809         tmp |= (0x1C << 16);
5810         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5811
5812         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5813         tmp |= (1 << 27);
5814         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5815
5816         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5817         tmp |= (1 << 27);
5818         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5819
5820         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5821         tmp &= ~(0xF << 28);
5822         tmp |= (4 << 28);
5823         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5824
5825         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5826         tmp &= ~(0xF << 28);
5827         tmp |= (4 << 28);
5828         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5829 }
5830
5831 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5832  * Programming" based on the parameters passed:
5833  * - Sequence to enable CLKOUT_DP
5834  * - Sequence to enable CLKOUT_DP without spread
5835  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5836  */
5837 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5838                                  bool with_fdi)
5839 {
5840         struct drm_i915_private *dev_priv = dev->dev_private;
5841         uint32_t reg, tmp;
5842
5843         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5844                 with_spread = true;
5845         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5846                  with_fdi, "LP PCH doesn't have FDI\n"))
5847                 with_fdi = false;
5848
5849         mutex_lock(&dev_priv->dpio_lock);
5850
5851         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5852         tmp &= ~SBI_SSCCTL_DISABLE;
5853         tmp |= SBI_SSCCTL_PATHALT;
5854         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5855
5856         udelay(24);
5857
5858         if (with_spread) {
5859                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5860                 tmp &= ~SBI_SSCCTL_PATHALT;
5861                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5862
5863                 if (with_fdi) {
5864                         lpt_reset_fdi_mphy(dev_priv);
5865                         lpt_program_fdi_mphy(dev_priv);
5866                 }
5867         }
5868
5869         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5870                SBI_GEN0 : SBI_DBUFF0;
5871         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5872         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5873         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5874
5875         mutex_unlock(&dev_priv->dpio_lock);
5876 }
5877
5878 /* Sequence to disable CLKOUT_DP */
5879 static void lpt_disable_clkout_dp(struct drm_device *dev)
5880 {
5881         struct drm_i915_private *dev_priv = dev->dev_private;
5882         uint32_t reg, tmp;
5883
5884         mutex_lock(&dev_priv->dpio_lock);
5885
5886         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5887                SBI_GEN0 : SBI_DBUFF0;
5888         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5889         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5890         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5891
5892         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5893         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5894                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5895                         tmp |= SBI_SSCCTL_PATHALT;
5896                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5897                         udelay(32);
5898                 }
5899                 tmp |= SBI_SSCCTL_DISABLE;
5900                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5901         }
5902
5903         mutex_unlock(&dev_priv->dpio_lock);
5904 }
5905
5906 static void lpt_init_pch_refclk(struct drm_device *dev)
5907 {
5908         struct drm_mode_config *mode_config = &dev->mode_config;
5909         struct intel_encoder *encoder;
5910         bool has_vga = false;
5911
5912         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5913                 switch (encoder->type) {
5914                 case INTEL_OUTPUT_ANALOG:
5915                         has_vga = true;
5916                         break;
5917                 }
5918         }
5919
5920         if (has_vga)
5921                 lpt_enable_clkout_dp(dev, true, true);
5922         else
5923                 lpt_disable_clkout_dp(dev);
5924 }
5925
5926 /*
5927  * Initialize reference clocks when the driver loads
5928  */
5929 void intel_init_pch_refclk(struct drm_device *dev)
5930 {
5931         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5932                 ironlake_init_pch_refclk(dev);
5933         else if (HAS_PCH_LPT(dev))
5934                 lpt_init_pch_refclk(dev);
5935 }
5936
5937 static int ironlake_get_refclk(struct drm_crtc *crtc)
5938 {
5939         struct drm_device *dev = crtc->dev;
5940         struct drm_i915_private *dev_priv = dev->dev_private;
5941         struct intel_encoder *encoder;
5942         int num_connectors = 0;
5943         bool is_lvds = false;
5944
5945         for_each_encoder_on_crtc(dev, crtc, encoder) {
5946                 switch (encoder->type) {
5947                 case INTEL_OUTPUT_LVDS:
5948                         is_lvds = true;
5949                         break;
5950                 }
5951                 num_connectors++;
5952         }
5953
5954         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5955                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5956                               dev_priv->vbt.lvds_ssc_freq);
5957                 return dev_priv->vbt.lvds_ssc_freq;
5958         }
5959
5960         return 120000;
5961 }
5962
5963 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5964 {
5965         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5967         int pipe = intel_crtc->pipe;
5968         uint32_t val;
5969
5970         val = 0;
5971
5972         switch (intel_crtc->config.pipe_bpp) {
5973         case 18:
5974                 val |= PIPECONF_6BPC;
5975                 break;
5976         case 24:
5977                 val |= PIPECONF_8BPC;
5978                 break;
5979         case 30:
5980                 val |= PIPECONF_10BPC;
5981                 break;
5982         case 36:
5983                 val |= PIPECONF_12BPC;
5984                 break;
5985         default:
5986                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5987                 BUG();
5988         }
5989
5990         if (intel_crtc->config.dither)
5991                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5992
5993         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5994                 val |= PIPECONF_INTERLACED_ILK;
5995         else
5996                 val |= PIPECONF_PROGRESSIVE;
5997
5998         if (intel_crtc->config.limited_color_range)
5999                 val |= PIPECONF_COLOR_RANGE_SELECT;
6000
6001         I915_WRITE(PIPECONF(pipe), val);
6002         POSTING_READ(PIPECONF(pipe));
6003 }
6004
6005 /*
6006  * Set up the pipe CSC unit.
6007  *
6008  * Currently only full range RGB to limited range RGB conversion
6009  * is supported, but eventually this should handle various
6010  * RGB<->YCbCr scenarios as well.
6011  */
6012 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6013 {
6014         struct drm_device *dev = crtc->dev;
6015         struct drm_i915_private *dev_priv = dev->dev_private;
6016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6017         int pipe = intel_crtc->pipe;
6018         uint16_t coeff = 0x7800; /* 1.0 */
6019
6020         /*
6021          * TODO: Check what kind of values actually come out of the pipe
6022          * with these coeff/postoff values and adjust to get the best
6023          * accuracy. Perhaps we even need to take the bpc value into
6024          * consideration.
6025          */
6026
6027         if (intel_crtc->config.limited_color_range)
6028                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6029
6030         /*
6031          * GY/GU and RY/RU should be the other way around according
6032          * to BSpec, but reality doesn't agree. Just set them up in
6033          * a way that results in the correct picture.
6034          */
6035         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6036         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6037
6038         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6039         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6040
6041         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6042         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6043
6044         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6045         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6046         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6047
6048         if (INTEL_INFO(dev)->gen > 6) {
6049                 uint16_t postoff = 0;
6050
6051                 if (intel_crtc->config.limited_color_range)
6052                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6053
6054                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6055                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6056                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6057
6058                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6059         } else {
6060                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6061
6062                 if (intel_crtc->config.limited_color_range)
6063                         mode |= CSC_BLACK_SCREEN_OFFSET;
6064
6065                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6066         }
6067 }
6068
6069 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6070 {
6071         struct drm_device *dev = crtc->dev;
6072         struct drm_i915_private *dev_priv = dev->dev_private;
6073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6074         enum pipe pipe = intel_crtc->pipe;
6075         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6076         uint32_t val;
6077
6078         val = 0;
6079
6080         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6081                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6082
6083         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6084                 val |= PIPECONF_INTERLACED_ILK;
6085         else
6086                 val |= PIPECONF_PROGRESSIVE;
6087
6088         I915_WRITE(PIPECONF(cpu_transcoder), val);
6089         POSTING_READ(PIPECONF(cpu_transcoder));
6090
6091         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6092         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6093
6094         if (IS_BROADWELL(dev)) {
6095                 val = 0;
6096
6097                 switch (intel_crtc->config.pipe_bpp) {
6098                 case 18:
6099                         val |= PIPEMISC_DITHER_6_BPC;
6100                         break;
6101                 case 24:
6102                         val |= PIPEMISC_DITHER_8_BPC;
6103                         break;
6104                 case 30:
6105                         val |= PIPEMISC_DITHER_10_BPC;
6106                         break;
6107                 case 36:
6108                         val |= PIPEMISC_DITHER_12_BPC;
6109                         break;
6110                 default:
6111                         /* Case prevented by pipe_config_set_bpp. */
6112                         BUG();
6113                 }
6114
6115                 if (intel_crtc->config.dither)
6116                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6117
6118                 I915_WRITE(PIPEMISC(pipe), val);
6119         }
6120 }
6121
6122 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6123                                     intel_clock_t *clock,
6124                                     bool *has_reduced_clock,
6125                                     intel_clock_t *reduced_clock)
6126 {
6127         struct drm_device *dev = crtc->dev;
6128         struct drm_i915_private *dev_priv = dev->dev_private;
6129         struct intel_encoder *intel_encoder;
6130         int refclk;
6131         const intel_limit_t *limit;
6132         bool ret, is_lvds = false;
6133
6134         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6135                 switch (intel_encoder->type) {
6136                 case INTEL_OUTPUT_LVDS:
6137                         is_lvds = true;
6138                         break;
6139                 }
6140         }
6141
6142         refclk = ironlake_get_refclk(crtc);
6143
6144         /*
6145          * Returns a set of divisors for the desired target clock with the given
6146          * refclk, or FALSE.  The returned values represent the clock equation:
6147          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6148          */
6149         limit = intel_limit(crtc, refclk);
6150         ret = dev_priv->display.find_dpll(limit, crtc,
6151                                           to_intel_crtc(crtc)->config.port_clock,
6152                                           refclk, NULL, clock);
6153         if (!ret)
6154                 return false;
6155
6156         if (is_lvds && dev_priv->lvds_downclock_avail) {
6157                 /*
6158                  * Ensure we match the reduced clock's P to the target clock.
6159                  * If the clocks don't match, we can't switch the display clock
6160                  * by using the FP0/FP1. In such case we will disable the LVDS
6161                  * downclock feature.
6162                 */
6163                 *has_reduced_clock =
6164                         dev_priv->display.find_dpll(limit, crtc,
6165                                                     dev_priv->lvds_downclock,
6166                                                     refclk, clock,
6167                                                     reduced_clock);
6168         }
6169
6170         return true;
6171 }
6172
6173 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6174 {
6175         /*
6176          * Account for spread spectrum to avoid
6177          * oversubscribing the link. Max center spread
6178          * is 2.5%; use 5% for safety's sake.
6179          */
6180         u32 bps = target_clock * bpp * 21 / 20;
6181         return bps / (link_bw * 8) + 1;
6182 }
6183
6184 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6185 {
6186         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6187 }
6188
6189 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6190                                       u32 *fp,
6191                                       intel_clock_t *reduced_clock, u32 *fp2)
6192 {
6193         struct drm_crtc *crtc = &intel_crtc->base;
6194         struct drm_device *dev = crtc->dev;
6195         struct drm_i915_private *dev_priv = dev->dev_private;
6196         struct intel_encoder *intel_encoder;
6197         uint32_t dpll;
6198         int factor, num_connectors = 0;
6199         bool is_lvds = false, is_sdvo = false;
6200
6201         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6202                 switch (intel_encoder->type) {
6203                 case INTEL_OUTPUT_LVDS:
6204                         is_lvds = true;
6205                         break;
6206                 case INTEL_OUTPUT_SDVO:
6207                 case INTEL_OUTPUT_HDMI:
6208                         is_sdvo = true;
6209                         break;
6210                 }
6211
6212                 num_connectors++;
6213         }
6214
6215         /* Enable autotuning of the PLL clock (if permissible) */
6216         factor = 21;
6217         if (is_lvds) {
6218                 if ((intel_panel_use_ssc(dev_priv) &&
6219                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6220                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6221                         factor = 25;
6222         } else if (intel_crtc->config.sdvo_tv_clock)
6223                 factor = 20;
6224
6225         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6226                 *fp |= FP_CB_TUNE;
6227
6228         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6229                 *fp2 |= FP_CB_TUNE;
6230
6231         dpll = 0;
6232
6233         if (is_lvds)
6234                 dpll |= DPLLB_MODE_LVDS;
6235         else
6236                 dpll |= DPLLB_MODE_DAC_SERIAL;
6237
6238         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6239                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6240
6241         if (is_sdvo)
6242                 dpll |= DPLL_SDVO_HIGH_SPEED;
6243         if (intel_crtc->config.has_dp_encoder)
6244                 dpll |= DPLL_SDVO_HIGH_SPEED;
6245
6246         /* compute bitmask from p1 value */
6247         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6248         /* also FPA1 */
6249         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6250
6251         switch (intel_crtc->config.dpll.p2) {
6252         case 5:
6253                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6254                 break;
6255         case 7:
6256                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6257                 break;
6258         case 10:
6259                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6260                 break;
6261         case 14:
6262                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6263                 break;
6264         }
6265
6266         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6267                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6268         else
6269                 dpll |= PLL_REF_INPUT_DREFCLK;
6270
6271         return dpll | DPLL_VCO_ENABLE;
6272 }
6273
6274 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6275                                   int x, int y,
6276                                   struct drm_framebuffer *fb)
6277 {
6278         struct drm_device *dev = crtc->dev;
6279         struct drm_i915_private *dev_priv = dev->dev_private;
6280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6281         int pipe = intel_crtc->pipe;
6282         int plane = intel_crtc->plane;
6283         int num_connectors = 0;
6284         intel_clock_t clock, reduced_clock;
6285         u32 dpll = 0, fp = 0, fp2 = 0;
6286         bool ok, has_reduced_clock = false;
6287         bool is_lvds = false;
6288         struct intel_encoder *encoder;
6289         struct intel_shared_dpll *pll;
6290         int ret;
6291
6292         for_each_encoder_on_crtc(dev, crtc, encoder) {
6293                 switch (encoder->type) {
6294                 case INTEL_OUTPUT_LVDS:
6295                         is_lvds = true;
6296                         break;
6297                 }
6298
6299                 num_connectors++;
6300         }
6301
6302         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6303              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6304
6305         ok = ironlake_compute_clocks(crtc, &clock,
6306                                      &has_reduced_clock, &reduced_clock);
6307         if (!ok && !intel_crtc->config.clock_set) {
6308                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6309                 return -EINVAL;
6310         }
6311         /* Compat-code for transition, will disappear. */
6312         if (!intel_crtc->config.clock_set) {
6313                 intel_crtc->config.dpll.n = clock.n;
6314                 intel_crtc->config.dpll.m1 = clock.m1;
6315                 intel_crtc->config.dpll.m2 = clock.m2;
6316                 intel_crtc->config.dpll.p1 = clock.p1;
6317                 intel_crtc->config.dpll.p2 = clock.p2;
6318         }
6319
6320         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6321         if (intel_crtc->config.has_pch_encoder) {
6322                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6323                 if (has_reduced_clock)
6324                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6325
6326                 dpll = ironlake_compute_dpll(intel_crtc,
6327                                              &fp, &reduced_clock,
6328                                              has_reduced_clock ? &fp2 : NULL);
6329
6330                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6331                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6332                 if (has_reduced_clock)
6333                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6334                 else
6335                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6336
6337                 pll = intel_get_shared_dpll(intel_crtc);
6338                 if (pll == NULL) {
6339                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6340                                          pipe_name(pipe));
6341                         return -EINVAL;
6342                 }
6343         } else
6344                 intel_put_shared_dpll(intel_crtc);
6345
6346         if (intel_crtc->config.has_dp_encoder)
6347                 intel_dp_set_m_n(intel_crtc);
6348
6349         if (is_lvds && has_reduced_clock && i915_powersave)
6350                 intel_crtc->lowfreq_avail = true;
6351         else
6352                 intel_crtc->lowfreq_avail = false;
6353
6354         intel_set_pipe_timings(intel_crtc);
6355
6356         if (intel_crtc->config.has_pch_encoder) {
6357                 intel_cpu_transcoder_set_m_n(intel_crtc,
6358                                              &intel_crtc->config.fdi_m_n);
6359         }
6360
6361         ironlake_set_pipeconf(crtc);
6362
6363         /* Set up the display plane register */
6364         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6365         POSTING_READ(DSPCNTR(plane));
6366
6367         ret = intel_pipe_set_base(crtc, x, y, fb);
6368
6369         return ret;
6370 }
6371
6372 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6373                                          struct intel_link_m_n *m_n)
6374 {
6375         struct drm_device *dev = crtc->base.dev;
6376         struct drm_i915_private *dev_priv = dev->dev_private;
6377         enum pipe pipe = crtc->pipe;
6378
6379         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6380         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6381         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6382                 & ~TU_SIZE_MASK;
6383         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6384         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6385                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6386 }
6387
6388 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6389                                          enum transcoder transcoder,
6390                                          struct intel_link_m_n *m_n)
6391 {
6392         struct drm_device *dev = crtc->base.dev;
6393         struct drm_i915_private *dev_priv = dev->dev_private;
6394         enum pipe pipe = crtc->pipe;
6395
6396         if (INTEL_INFO(dev)->gen >= 5) {
6397                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6398                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6399                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6400                         & ~TU_SIZE_MASK;
6401                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6402                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6403                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6404         } else {
6405                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6406                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6407                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6408                         & ~TU_SIZE_MASK;
6409                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6410                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6411                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6412         }
6413 }
6414
6415 void intel_dp_get_m_n(struct intel_crtc *crtc,
6416                       struct intel_crtc_config *pipe_config)
6417 {
6418         if (crtc->config.has_pch_encoder)
6419                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6420         else
6421                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6422                                              &pipe_config->dp_m_n);
6423 }
6424
6425 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6426                                         struct intel_crtc_config *pipe_config)
6427 {
6428         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6429                                      &pipe_config->fdi_m_n);
6430 }
6431
6432 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6433                                      struct intel_crtc_config *pipe_config)
6434 {
6435         struct drm_device *dev = crtc->base.dev;
6436         struct drm_i915_private *dev_priv = dev->dev_private;
6437         uint32_t tmp;
6438
6439         tmp = I915_READ(PF_CTL(crtc->pipe));
6440
6441         if (tmp & PF_ENABLE) {
6442                 pipe_config->pch_pfit.enabled = true;
6443                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6444                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6445
6446                 /* We currently do not free assignements of panel fitters on
6447                  * ivb/hsw (since we don't use the higher upscaling modes which
6448                  * differentiates them) so just WARN about this case for now. */
6449                 if (IS_GEN7(dev)) {
6450                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6451                                 PF_PIPE_SEL_IVB(crtc->pipe));
6452                 }
6453         }
6454 }
6455
6456 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6457                                      struct intel_crtc_config *pipe_config)
6458 {
6459         struct drm_device *dev = crtc->base.dev;
6460         struct drm_i915_private *dev_priv = dev->dev_private;
6461         uint32_t tmp;
6462
6463         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6464         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6465
6466         tmp = I915_READ(PIPECONF(crtc->pipe));
6467         if (!(tmp & PIPECONF_ENABLE))
6468                 return false;
6469
6470         switch (tmp & PIPECONF_BPC_MASK) {
6471         case PIPECONF_6BPC:
6472                 pipe_config->pipe_bpp = 18;
6473                 break;
6474         case PIPECONF_8BPC:
6475                 pipe_config->pipe_bpp = 24;
6476                 break;
6477         case PIPECONF_10BPC:
6478                 pipe_config->pipe_bpp = 30;
6479                 break;
6480         case PIPECONF_12BPC:
6481                 pipe_config->pipe_bpp = 36;
6482                 break;
6483         default:
6484                 break;
6485         }
6486
6487         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6488                 struct intel_shared_dpll *pll;
6489
6490                 pipe_config->has_pch_encoder = true;
6491
6492                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6493                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6494                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6495
6496                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6497
6498                 if (HAS_PCH_IBX(dev_priv->dev)) {
6499                         pipe_config->shared_dpll =
6500                                 (enum intel_dpll_id) crtc->pipe;
6501                 } else {
6502                         tmp = I915_READ(PCH_DPLL_SEL);
6503                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6504                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6505                         else
6506                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6507                 }
6508
6509                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6510
6511                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6512                                            &pipe_config->dpll_hw_state));
6513
6514                 tmp = pipe_config->dpll_hw_state.dpll;
6515                 pipe_config->pixel_multiplier =
6516                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6517                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6518
6519                 ironlake_pch_clock_get(crtc, pipe_config);
6520         } else {
6521                 pipe_config->pixel_multiplier = 1;
6522         }
6523
6524         intel_get_pipe_timings(crtc, pipe_config);
6525
6526         ironlake_get_pfit_config(crtc, pipe_config);
6527
6528         return true;
6529 }
6530
6531 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6532 {
6533         struct drm_device *dev = dev_priv->dev;
6534         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6535         struct intel_crtc *crtc;
6536         unsigned long irqflags;
6537         uint32_t val;
6538
6539         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6540                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6541                      pipe_name(crtc->pipe));
6542
6543         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6544         WARN(plls->spll_refcount, "SPLL enabled\n");
6545         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6546         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6547         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6548         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6549              "CPU PWM1 enabled\n");
6550         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6551              "CPU PWM2 enabled\n");
6552         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6553              "PCH PWM1 enabled\n");
6554         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6555              "Utility pin enabled\n");
6556         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6557
6558         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6559         val = I915_READ(DEIMR);
6560         WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6561              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6562         val = I915_READ(SDEIMR);
6563         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6564              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6565         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6566 }
6567
6568 /*
6569  * This function implements pieces of two sequences from BSpec:
6570  * - Sequence for display software to disable LCPLL
6571  * - Sequence for display software to allow package C8+
6572  * The steps implemented here are just the steps that actually touch the LCPLL
6573  * register. Callers should take care of disabling all the display engine
6574  * functions, doing the mode unset, fixing interrupts, etc.
6575  */
6576 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6577                               bool switch_to_fclk, bool allow_power_down)
6578 {
6579         uint32_t val;
6580
6581         assert_can_disable_lcpll(dev_priv);
6582
6583         val = I915_READ(LCPLL_CTL);
6584
6585         if (switch_to_fclk) {
6586                 val |= LCPLL_CD_SOURCE_FCLK;
6587                 I915_WRITE(LCPLL_CTL, val);
6588
6589                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6590                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6591                         DRM_ERROR("Switching to FCLK failed\n");
6592
6593                 val = I915_READ(LCPLL_CTL);
6594         }
6595
6596         val |= LCPLL_PLL_DISABLE;
6597         I915_WRITE(LCPLL_CTL, val);
6598         POSTING_READ(LCPLL_CTL);
6599
6600         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6601                 DRM_ERROR("LCPLL still locked\n");
6602
6603         val = I915_READ(D_COMP);
6604         val |= D_COMP_COMP_DISABLE;
6605         mutex_lock(&dev_priv->rps.hw_lock);
6606         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6607                 DRM_ERROR("Failed to disable D_COMP\n");
6608         mutex_unlock(&dev_priv->rps.hw_lock);
6609         POSTING_READ(D_COMP);
6610         ndelay(100);
6611
6612         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6613                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6614
6615         if (allow_power_down) {
6616                 val = I915_READ(LCPLL_CTL);
6617                 val |= LCPLL_POWER_DOWN_ALLOW;
6618                 I915_WRITE(LCPLL_CTL, val);
6619                 POSTING_READ(LCPLL_CTL);
6620         }
6621 }
6622
6623 /*
6624  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6625  * source.
6626  */
6627 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6628 {
6629         uint32_t val;
6630
6631         val = I915_READ(LCPLL_CTL);
6632
6633         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6634                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6635                 return;
6636
6637         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6638          * we'll hang the machine! */
6639         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6640
6641         if (val & LCPLL_POWER_DOWN_ALLOW) {
6642                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6643                 I915_WRITE(LCPLL_CTL, val);
6644                 POSTING_READ(LCPLL_CTL);
6645         }
6646
6647         val = I915_READ(D_COMP);
6648         val |= D_COMP_COMP_FORCE;
6649         val &= ~D_COMP_COMP_DISABLE;
6650         mutex_lock(&dev_priv->rps.hw_lock);
6651         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6652                 DRM_ERROR("Failed to enable D_COMP\n");
6653         mutex_unlock(&dev_priv->rps.hw_lock);
6654         POSTING_READ(D_COMP);
6655
6656         val = I915_READ(LCPLL_CTL);
6657         val &= ~LCPLL_PLL_DISABLE;
6658         I915_WRITE(LCPLL_CTL, val);
6659
6660         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6661                 DRM_ERROR("LCPLL not locked yet\n");
6662
6663         if (val & LCPLL_CD_SOURCE_FCLK) {
6664                 val = I915_READ(LCPLL_CTL);
6665                 val &= ~LCPLL_CD_SOURCE_FCLK;
6666                 I915_WRITE(LCPLL_CTL, val);
6667
6668                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6669                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6670                         DRM_ERROR("Switching back to LCPLL failed\n");
6671         }
6672
6673         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6674 }
6675
6676 void hsw_enable_pc8_work(struct work_struct *__work)
6677 {
6678         struct drm_i915_private *dev_priv =
6679                 container_of(to_delayed_work(__work), struct drm_i915_private,
6680                              pc8.enable_work);
6681         struct drm_device *dev = dev_priv->dev;
6682         uint32_t val;
6683
6684         WARN_ON(!HAS_PC8(dev));
6685
6686         if (dev_priv->pc8.enabled)
6687                 return;
6688
6689         DRM_DEBUG_KMS("Enabling package C8+\n");
6690
6691         dev_priv->pc8.enabled = true;
6692
6693         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6694                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6695                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6696                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6697         }
6698
6699         lpt_disable_clkout_dp(dev);
6700         hsw_pc8_disable_interrupts(dev);
6701         hsw_disable_lcpll(dev_priv, true, true);
6702
6703         intel_runtime_pm_put(dev_priv);
6704 }
6705
6706 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6707 {
6708         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6709         WARN(dev_priv->pc8.disable_count < 1,
6710              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6711
6712         dev_priv->pc8.disable_count--;
6713         if (dev_priv->pc8.disable_count != 0)
6714                 return;
6715
6716         schedule_delayed_work(&dev_priv->pc8.enable_work,
6717                               msecs_to_jiffies(i915_pc8_timeout));
6718 }
6719
6720 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6721 {
6722         struct drm_device *dev = dev_priv->dev;
6723         uint32_t val;
6724
6725         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6726         WARN(dev_priv->pc8.disable_count < 0,
6727              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6728
6729         dev_priv->pc8.disable_count++;
6730         if (dev_priv->pc8.disable_count != 1)
6731                 return;
6732
6733         WARN_ON(!HAS_PC8(dev));
6734
6735         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6736         if (!dev_priv->pc8.enabled)
6737                 return;
6738
6739         DRM_DEBUG_KMS("Disabling package C8+\n");
6740
6741         intel_runtime_pm_get(dev_priv);
6742
6743         hsw_restore_lcpll(dev_priv);
6744         hsw_pc8_restore_interrupts(dev);
6745         lpt_init_pch_refclk(dev);
6746
6747         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6748                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6749                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6750                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6751         }
6752
6753         intel_prepare_ddi(dev);
6754         i915_gem_init_swizzling(dev);
6755         mutex_lock(&dev_priv->rps.hw_lock);
6756         gen6_update_ring_freq(dev);
6757         mutex_unlock(&dev_priv->rps.hw_lock);
6758         dev_priv->pc8.enabled = false;
6759 }
6760
6761 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6762 {
6763         if (!HAS_PC8(dev_priv->dev))
6764                 return;
6765
6766         mutex_lock(&dev_priv->pc8.lock);
6767         __hsw_enable_package_c8(dev_priv);
6768         mutex_unlock(&dev_priv->pc8.lock);
6769 }
6770
6771 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6772 {
6773         if (!HAS_PC8(dev_priv->dev))
6774                 return;
6775
6776         mutex_lock(&dev_priv->pc8.lock);
6777         __hsw_disable_package_c8(dev_priv);
6778         mutex_unlock(&dev_priv->pc8.lock);
6779 }
6780
6781 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6782 {
6783         struct drm_device *dev = dev_priv->dev;
6784         struct intel_crtc *crtc;
6785         uint32_t val;
6786
6787         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6788                 if (crtc->base.enabled)
6789                         return false;
6790
6791         /* This case is still possible since we have the i915.disable_power_well
6792          * parameter and also the KVMr or something else might be requesting the
6793          * power well. */
6794         val = I915_READ(HSW_PWR_WELL_DRIVER);
6795         if (val != 0) {
6796                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6797                 return false;
6798         }
6799
6800         return true;
6801 }
6802
6803 /* Since we're called from modeset_global_resources there's no way to
6804  * symmetrically increase and decrease the refcount, so we use
6805  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6806  * or not.
6807  */
6808 static void hsw_update_package_c8(struct drm_device *dev)
6809 {
6810         struct drm_i915_private *dev_priv = dev->dev_private;
6811         bool allow;
6812
6813         if (!HAS_PC8(dev_priv->dev))
6814                 return;
6815
6816         if (!i915_enable_pc8)
6817                 return;
6818
6819         mutex_lock(&dev_priv->pc8.lock);
6820
6821         allow = hsw_can_enable_package_c8(dev_priv);
6822
6823         if (allow == dev_priv->pc8.requirements_met)
6824                 goto done;
6825
6826         dev_priv->pc8.requirements_met = allow;
6827
6828         if (allow)
6829                 __hsw_enable_package_c8(dev_priv);
6830         else
6831                 __hsw_disable_package_c8(dev_priv);
6832
6833 done:
6834         mutex_unlock(&dev_priv->pc8.lock);
6835 }
6836
6837 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6838 {
6839         if (!HAS_PC8(dev_priv->dev))
6840                 return;
6841
6842         mutex_lock(&dev_priv->pc8.lock);
6843         if (!dev_priv->pc8.gpu_idle) {
6844                 dev_priv->pc8.gpu_idle = true;
6845                 __hsw_enable_package_c8(dev_priv);
6846         }
6847         mutex_unlock(&dev_priv->pc8.lock);
6848 }
6849
6850 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6851 {
6852         if (!HAS_PC8(dev_priv->dev))
6853                 return;
6854
6855         mutex_lock(&dev_priv->pc8.lock);
6856         if (dev_priv->pc8.gpu_idle) {
6857                 dev_priv->pc8.gpu_idle = false;
6858                 __hsw_disable_package_c8(dev_priv);
6859         }
6860         mutex_unlock(&dev_priv->pc8.lock);
6861 }
6862
6863 #define for_each_power_domain(domain, mask)                             \
6864         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6865                 if ((1 << (domain)) & (mask))
6866
6867 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6868                                             enum pipe pipe, bool pfit_enabled)
6869 {
6870         unsigned long mask;
6871         enum transcoder transcoder;
6872
6873         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6874
6875         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6876         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6877         if (pfit_enabled)
6878                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6879
6880         return mask;
6881 }
6882
6883 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6884 {
6885         struct drm_i915_private *dev_priv = dev->dev_private;
6886
6887         if (dev_priv->power_domains.init_power_on == enable)
6888                 return;
6889
6890         if (enable)
6891                 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6892         else
6893                 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6894
6895         dev_priv->power_domains.init_power_on = enable;
6896 }
6897
6898 static void modeset_update_power_wells(struct drm_device *dev)
6899 {
6900         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6901         struct intel_crtc *crtc;
6902
6903         /*
6904          * First get all needed power domains, then put all unneeded, to avoid
6905          * any unnecessary toggling of the power wells.
6906          */
6907         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6908                 enum intel_display_power_domain domain;
6909
6910                 if (!crtc->base.enabled)
6911                         continue;
6912
6913                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6914                                                 crtc->pipe,
6915                                                 crtc->config.pch_pfit.enabled);
6916
6917                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6918                         intel_display_power_get(dev, domain);
6919         }
6920
6921         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6922                 enum intel_display_power_domain domain;
6923
6924                 for_each_power_domain(domain, crtc->enabled_power_domains)
6925                         intel_display_power_put(dev, domain);
6926
6927                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6928         }
6929
6930         intel_display_set_init_power(dev, false);
6931 }
6932
6933 static void haswell_modeset_global_resources(struct drm_device *dev)
6934 {
6935         modeset_update_power_wells(dev);
6936         hsw_update_package_c8(dev);
6937 }
6938
6939 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6940                                  int x, int y,
6941                                  struct drm_framebuffer *fb)
6942 {
6943         struct drm_device *dev = crtc->dev;
6944         struct drm_i915_private *dev_priv = dev->dev_private;
6945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6946         int plane = intel_crtc->plane;
6947         int ret;
6948
6949         if (!intel_ddi_pll_select(intel_crtc))
6950                 return -EINVAL;
6951         intel_ddi_pll_enable(intel_crtc);
6952
6953         if (intel_crtc->config.has_dp_encoder)
6954                 intel_dp_set_m_n(intel_crtc);
6955
6956         intel_crtc->lowfreq_avail = false;
6957
6958         intel_set_pipe_timings(intel_crtc);
6959
6960         if (intel_crtc->config.has_pch_encoder) {
6961                 intel_cpu_transcoder_set_m_n(intel_crtc,
6962                                              &intel_crtc->config.fdi_m_n);
6963         }
6964
6965         haswell_set_pipeconf(crtc);
6966
6967         intel_set_pipe_csc(crtc);
6968
6969         /* Set up the display plane register */
6970         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6971         POSTING_READ(DSPCNTR(plane));
6972
6973         ret = intel_pipe_set_base(crtc, x, y, fb);
6974
6975         return ret;
6976 }
6977
6978 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6979                                     struct intel_crtc_config *pipe_config)
6980 {
6981         struct drm_device *dev = crtc->base.dev;
6982         struct drm_i915_private *dev_priv = dev->dev_private;
6983         enum intel_display_power_domain pfit_domain;
6984         uint32_t tmp;
6985
6986         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6987         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6988
6989         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6990         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6991                 enum pipe trans_edp_pipe;
6992                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6993                 default:
6994                         WARN(1, "unknown pipe linked to edp transcoder\n");
6995                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6996                 case TRANS_DDI_EDP_INPUT_A_ON:
6997                         trans_edp_pipe = PIPE_A;
6998                         break;
6999                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7000                         trans_edp_pipe = PIPE_B;
7001                         break;
7002                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7003                         trans_edp_pipe = PIPE_C;
7004                         break;
7005                 }
7006
7007                 if (trans_edp_pipe == crtc->pipe)
7008                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7009         }
7010
7011         if (!intel_display_power_enabled(dev,
7012                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7013                 return false;
7014
7015         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7016         if (!(tmp & PIPECONF_ENABLE))
7017                 return false;
7018
7019         /*
7020          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7021          * DDI E. So just check whether this pipe is wired to DDI E and whether
7022          * the PCH transcoder is on.
7023          */
7024         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7025         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7026             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7027                 pipe_config->has_pch_encoder = true;
7028
7029                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7030                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7031                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7032
7033                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7034         }
7035
7036         intel_get_pipe_timings(crtc, pipe_config);
7037
7038         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7039         if (intel_display_power_enabled(dev, pfit_domain))
7040                 ironlake_get_pfit_config(crtc, pipe_config);
7041
7042         if (IS_HASWELL(dev))
7043                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7044                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7045
7046         pipe_config->pixel_multiplier = 1;
7047
7048         return true;
7049 }
7050
7051 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7052                                int x, int y,
7053                                struct drm_framebuffer *fb)
7054 {
7055         struct drm_device *dev = crtc->dev;
7056         struct drm_i915_private *dev_priv = dev->dev_private;
7057         struct intel_encoder *encoder;
7058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7059         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7060         int pipe = intel_crtc->pipe;
7061         int ret;
7062
7063         drm_vblank_pre_modeset(dev, pipe);
7064
7065         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7066
7067         drm_vblank_post_modeset(dev, pipe);
7068
7069         if (ret != 0)
7070                 return ret;
7071
7072         for_each_encoder_on_crtc(dev, crtc, encoder) {
7073                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7074                         encoder->base.base.id,
7075                         drm_get_encoder_name(&encoder->base),
7076                         mode->base.id, mode->name);
7077                 encoder->mode_set(encoder);
7078         }
7079
7080         return 0;
7081 }
7082
7083 static struct {
7084         int clock;
7085         u32 config;
7086 } hdmi_audio_clock[] = {
7087         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7088         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7089         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7090         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7091         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7092         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7093         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7094         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7095         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7096         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7097 };
7098
7099 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7100 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7101 {
7102         int i;
7103
7104         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7105                 if (mode->clock == hdmi_audio_clock[i].clock)
7106                         break;
7107         }
7108
7109         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7110                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7111                 i = 1;
7112         }
7113
7114         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7115                       hdmi_audio_clock[i].clock,
7116                       hdmi_audio_clock[i].config);
7117
7118         return hdmi_audio_clock[i].config;
7119 }
7120
7121 static bool intel_eld_uptodate(struct drm_connector *connector,
7122                                int reg_eldv, uint32_t bits_eldv,
7123                                int reg_elda, uint32_t bits_elda,
7124                                int reg_edid)
7125 {
7126         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7127         uint8_t *eld = connector->eld;
7128         uint32_t i;
7129
7130         i = I915_READ(reg_eldv);
7131         i &= bits_eldv;
7132
7133         if (!eld[0])
7134                 return !i;
7135
7136         if (!i)
7137                 return false;
7138
7139         i = I915_READ(reg_elda);
7140         i &= ~bits_elda;
7141         I915_WRITE(reg_elda, i);
7142
7143         for (i = 0; i < eld[2]; i++)
7144                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7145                         return false;
7146
7147         return true;
7148 }
7149
7150 static void g4x_write_eld(struct drm_connector *connector,
7151                           struct drm_crtc *crtc,
7152                           struct drm_display_mode *mode)
7153 {
7154         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7155         uint8_t *eld = connector->eld;
7156         uint32_t eldv;
7157         uint32_t len;
7158         uint32_t i;
7159
7160         i = I915_READ(G4X_AUD_VID_DID);
7161
7162         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7163                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7164         else
7165                 eldv = G4X_ELDV_DEVCTG;
7166
7167         if (intel_eld_uptodate(connector,
7168                                G4X_AUD_CNTL_ST, eldv,
7169                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7170                                G4X_HDMIW_HDMIEDID))
7171                 return;
7172
7173         i = I915_READ(G4X_AUD_CNTL_ST);
7174         i &= ~(eldv | G4X_ELD_ADDR);
7175         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7176         I915_WRITE(G4X_AUD_CNTL_ST, i);
7177
7178         if (!eld[0])
7179                 return;
7180
7181         len = min_t(uint8_t, eld[2], len);
7182         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7183         for (i = 0; i < len; i++)
7184                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7185
7186         i = I915_READ(G4X_AUD_CNTL_ST);
7187         i |= eldv;
7188         I915_WRITE(G4X_AUD_CNTL_ST, i);
7189 }
7190
7191 static void haswell_write_eld(struct drm_connector *connector,
7192                               struct drm_crtc *crtc,
7193                               struct drm_display_mode *mode)
7194 {
7195         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7196         uint8_t *eld = connector->eld;
7197         struct drm_device *dev = crtc->dev;
7198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7199         uint32_t eldv;
7200         uint32_t i;
7201         int len;
7202         int pipe = to_intel_crtc(crtc)->pipe;
7203         int tmp;
7204
7205         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7206         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7207         int aud_config = HSW_AUD_CFG(pipe);
7208         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7209
7210
7211         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7212
7213         /* Audio output enable */
7214         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7215         tmp = I915_READ(aud_cntrl_st2);
7216         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7217         I915_WRITE(aud_cntrl_st2, tmp);
7218
7219         /* Wait for 1 vertical blank */
7220         intel_wait_for_vblank(dev, pipe);
7221
7222         /* Set ELD valid state */
7223         tmp = I915_READ(aud_cntrl_st2);
7224         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7225         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7226         I915_WRITE(aud_cntrl_st2, tmp);
7227         tmp = I915_READ(aud_cntrl_st2);
7228         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7229
7230         /* Enable HDMI mode */
7231         tmp = I915_READ(aud_config);
7232         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7233         /* clear N_programing_enable and N_value_index */
7234         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7235         I915_WRITE(aud_config, tmp);
7236
7237         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7238
7239         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7240         intel_crtc->eld_vld = true;
7241
7242         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7243                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7244                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7245                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7246         } else {
7247                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7248         }
7249
7250         if (intel_eld_uptodate(connector,
7251                                aud_cntrl_st2, eldv,
7252                                aud_cntl_st, IBX_ELD_ADDRESS,
7253                                hdmiw_hdmiedid))
7254                 return;
7255
7256         i = I915_READ(aud_cntrl_st2);
7257         i &= ~eldv;
7258         I915_WRITE(aud_cntrl_st2, i);
7259
7260         if (!eld[0])
7261                 return;
7262
7263         i = I915_READ(aud_cntl_st);
7264         i &= ~IBX_ELD_ADDRESS;
7265         I915_WRITE(aud_cntl_st, i);
7266         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7267         DRM_DEBUG_DRIVER("port num:%d\n", i);
7268
7269         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7270         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7271         for (i = 0; i < len; i++)
7272                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7273
7274         i = I915_READ(aud_cntrl_st2);
7275         i |= eldv;
7276         I915_WRITE(aud_cntrl_st2, i);
7277
7278 }
7279
7280 static void ironlake_write_eld(struct drm_connector *connector,
7281                                struct drm_crtc *crtc,
7282                                struct drm_display_mode *mode)
7283 {
7284         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7285         uint8_t *eld = connector->eld;
7286         uint32_t eldv;
7287         uint32_t i;
7288         int len;
7289         int hdmiw_hdmiedid;
7290         int aud_config;
7291         int aud_cntl_st;
7292         int aud_cntrl_st2;
7293         int pipe = to_intel_crtc(crtc)->pipe;
7294
7295         if (HAS_PCH_IBX(connector->dev)) {
7296                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7297                 aud_config = IBX_AUD_CFG(pipe);
7298                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7299                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7300         } else if (IS_VALLEYVIEW(connector->dev)) {
7301                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7302                 aud_config = VLV_AUD_CFG(pipe);
7303                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7304                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7305         } else {
7306                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7307                 aud_config = CPT_AUD_CFG(pipe);
7308                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7309                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7310         }
7311
7312         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7313
7314         if (IS_VALLEYVIEW(connector->dev))  {
7315                 struct intel_encoder *intel_encoder;
7316                 struct intel_digital_port *intel_dig_port;
7317
7318                 intel_encoder = intel_attached_encoder(connector);
7319                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7320                 i = intel_dig_port->port;
7321         } else {
7322                 i = I915_READ(aud_cntl_st);
7323                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7324                 /* DIP_Port_Select, 0x1 = PortB */
7325         }
7326
7327         if (!i) {
7328                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7329                 /* operate blindly on all ports */
7330                 eldv = IBX_ELD_VALIDB;
7331                 eldv |= IBX_ELD_VALIDB << 4;
7332                 eldv |= IBX_ELD_VALIDB << 8;
7333         } else {
7334                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7335                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7336         }
7337
7338         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7339                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7340                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7341                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7342         } else {
7343                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7344         }
7345
7346         if (intel_eld_uptodate(connector,
7347                                aud_cntrl_st2, eldv,
7348                                aud_cntl_st, IBX_ELD_ADDRESS,
7349                                hdmiw_hdmiedid))
7350                 return;
7351
7352         i = I915_READ(aud_cntrl_st2);
7353         i &= ~eldv;
7354         I915_WRITE(aud_cntrl_st2, i);
7355
7356         if (!eld[0])
7357                 return;
7358
7359         i = I915_READ(aud_cntl_st);
7360         i &= ~IBX_ELD_ADDRESS;
7361         I915_WRITE(aud_cntl_st, i);
7362
7363         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7364         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7365         for (i = 0; i < len; i++)
7366                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7367
7368         i = I915_READ(aud_cntrl_st2);
7369         i |= eldv;
7370         I915_WRITE(aud_cntrl_st2, i);
7371 }
7372
7373 void intel_write_eld(struct drm_encoder *encoder,
7374                      struct drm_display_mode *mode)
7375 {
7376         struct drm_crtc *crtc = encoder->crtc;
7377         struct drm_connector *connector;
7378         struct drm_device *dev = encoder->dev;
7379         struct drm_i915_private *dev_priv = dev->dev_private;
7380
7381         connector = drm_select_eld(encoder, mode);
7382         if (!connector)
7383                 return;
7384
7385         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7386                          connector->base.id,
7387                          drm_get_connector_name(connector),
7388                          connector->encoder->base.id,
7389                          drm_get_encoder_name(connector->encoder));
7390
7391         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7392
7393         if (dev_priv->display.write_eld)
7394                 dev_priv->display.write_eld(connector, crtc, mode);
7395 }
7396
7397 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7398 {
7399         struct drm_device *dev = crtc->dev;
7400         struct drm_i915_private *dev_priv = dev->dev_private;
7401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7402         bool visible = base != 0;
7403         u32 cntl;
7404
7405         if (intel_crtc->cursor_visible == visible)
7406                 return;
7407
7408         cntl = I915_READ(_CURACNTR);
7409         if (visible) {
7410                 /* On these chipsets we can only modify the base whilst
7411                  * the cursor is disabled.
7412                  */
7413                 I915_WRITE(_CURABASE, base);
7414
7415                 cntl &= ~(CURSOR_FORMAT_MASK);
7416                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7417                 cntl |= CURSOR_ENABLE |
7418                         CURSOR_GAMMA_ENABLE |
7419                         CURSOR_FORMAT_ARGB;
7420         } else
7421                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7422         I915_WRITE(_CURACNTR, cntl);
7423
7424         intel_crtc->cursor_visible = visible;
7425 }
7426
7427 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7428 {
7429         struct drm_device *dev = crtc->dev;
7430         struct drm_i915_private *dev_priv = dev->dev_private;
7431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7432         int pipe = intel_crtc->pipe;
7433         bool visible = base != 0;
7434
7435         if (intel_crtc->cursor_visible != visible) {
7436                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7437                 if (base) {
7438                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7439                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7440                         cntl |= pipe << 28; /* Connect to correct pipe */
7441                 } else {
7442                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7443                         cntl |= CURSOR_MODE_DISABLE;
7444                 }
7445                 I915_WRITE(CURCNTR(pipe), cntl);
7446
7447                 intel_crtc->cursor_visible = visible;
7448         }
7449         /* and commit changes on next vblank */
7450         POSTING_READ(CURCNTR(pipe));
7451         I915_WRITE(CURBASE(pipe), base);
7452         POSTING_READ(CURBASE(pipe));
7453 }
7454
7455 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7456 {
7457         struct drm_device *dev = crtc->dev;
7458         struct drm_i915_private *dev_priv = dev->dev_private;
7459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7460         int pipe = intel_crtc->pipe;
7461         bool visible = base != 0;
7462
7463         if (intel_crtc->cursor_visible != visible) {
7464                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7465                 if (base) {
7466                         cntl &= ~CURSOR_MODE;
7467                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7468                 } else {
7469                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7470                         cntl |= CURSOR_MODE_DISABLE;
7471                 }
7472                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7473                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7474                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7475                 }
7476                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7477
7478                 intel_crtc->cursor_visible = visible;
7479         }
7480         /* and commit changes on next vblank */
7481         POSTING_READ(CURCNTR_IVB(pipe));
7482         I915_WRITE(CURBASE_IVB(pipe), base);
7483         POSTING_READ(CURBASE_IVB(pipe));
7484 }
7485
7486 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7487 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7488                                      bool on)
7489 {
7490         struct drm_device *dev = crtc->dev;
7491         struct drm_i915_private *dev_priv = dev->dev_private;
7492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7493         int pipe = intel_crtc->pipe;
7494         int x = intel_crtc->cursor_x;
7495         int y = intel_crtc->cursor_y;
7496         u32 base = 0, pos = 0;
7497         bool visible;
7498
7499         if (on)
7500                 base = intel_crtc->cursor_addr;
7501
7502         if (x >= intel_crtc->config.pipe_src_w)
7503                 base = 0;
7504
7505         if (y >= intel_crtc->config.pipe_src_h)
7506                 base = 0;
7507
7508         if (x < 0) {
7509                 if (x + intel_crtc->cursor_width <= 0)
7510                         base = 0;
7511
7512                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7513                 x = -x;
7514         }
7515         pos |= x << CURSOR_X_SHIFT;
7516
7517         if (y < 0) {
7518                 if (y + intel_crtc->cursor_height <= 0)
7519                         base = 0;
7520
7521                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7522                 y = -y;
7523         }
7524         pos |= y << CURSOR_Y_SHIFT;
7525
7526         visible = base != 0;
7527         if (!visible && !intel_crtc->cursor_visible)
7528                 return;
7529
7530         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7531                 I915_WRITE(CURPOS_IVB(pipe), pos);
7532                 ivb_update_cursor(crtc, base);
7533         } else {
7534                 I915_WRITE(CURPOS(pipe), pos);
7535                 if (IS_845G(dev) || IS_I865G(dev))
7536                         i845_update_cursor(crtc, base);
7537                 else
7538                         i9xx_update_cursor(crtc, base);
7539         }
7540 }
7541
7542 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7543                                  struct drm_file *file,
7544                                  uint32_t handle,
7545                                  uint32_t width, uint32_t height)
7546 {
7547         struct drm_device *dev = crtc->dev;
7548         struct drm_i915_private *dev_priv = dev->dev_private;
7549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7550         struct drm_i915_gem_object *obj;
7551         uint32_t addr;
7552         int ret;
7553
7554         /* if we want to turn off the cursor ignore width and height */
7555         if (!handle) {
7556                 DRM_DEBUG_KMS("cursor off\n");
7557                 addr = 0;
7558                 obj = NULL;
7559                 mutex_lock(&dev->struct_mutex);
7560                 goto finish;
7561         }
7562
7563         /* Currently we only support 64x64 cursors */
7564         if (width != 64 || height != 64) {
7565                 DRM_ERROR("we currently only support 64x64 cursors\n");
7566                 return -EINVAL;
7567         }
7568
7569         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7570         if (&obj->base == NULL)
7571                 return -ENOENT;
7572
7573         if (obj->base.size < width * height * 4) {
7574                 DRM_ERROR("buffer is to small\n");
7575                 ret = -ENOMEM;
7576                 goto fail;
7577         }
7578
7579         /* we only need to pin inside GTT if cursor is non-phy */
7580         mutex_lock(&dev->struct_mutex);
7581         if (!dev_priv->info->cursor_needs_physical) {
7582                 unsigned alignment;
7583
7584                 if (obj->tiling_mode) {
7585                         DRM_ERROR("cursor cannot be tiled\n");
7586                         ret = -EINVAL;
7587                         goto fail_locked;
7588                 }
7589
7590                 /* Note that the w/a also requires 2 PTE of padding following
7591                  * the bo. We currently fill all unused PTE with the shadow
7592                  * page and so we should always have valid PTE following the
7593                  * cursor preventing the VT-d warning.
7594                  */
7595                 alignment = 0;
7596                 if (need_vtd_wa(dev))
7597                         alignment = 64*1024;
7598
7599                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7600                 if (ret) {
7601                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7602                         goto fail_locked;
7603                 }
7604
7605                 ret = i915_gem_object_put_fence(obj);
7606                 if (ret) {
7607                         DRM_ERROR("failed to release fence for cursor");
7608                         goto fail_unpin;
7609                 }
7610
7611                 addr = i915_gem_obj_ggtt_offset(obj);
7612         } else {
7613                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7614                 ret = i915_gem_attach_phys_object(dev, obj,
7615                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7616                                                   align);
7617                 if (ret) {
7618                         DRM_ERROR("failed to attach phys object\n");
7619                         goto fail_locked;
7620                 }
7621                 addr = obj->phys_obj->handle->busaddr;
7622         }
7623
7624         if (IS_GEN2(dev))
7625                 I915_WRITE(CURSIZE, (height << 12) | width);
7626
7627  finish:
7628         if (intel_crtc->cursor_bo) {
7629                 if (dev_priv->info->cursor_needs_physical) {
7630                         if (intel_crtc->cursor_bo != obj)
7631                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7632                 } else
7633                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7634                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7635         }
7636
7637         mutex_unlock(&dev->struct_mutex);
7638
7639         intel_crtc->cursor_addr = addr;
7640         intel_crtc->cursor_bo = obj;
7641         intel_crtc->cursor_width = width;
7642         intel_crtc->cursor_height = height;
7643
7644         if (intel_crtc->active)
7645                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7646
7647         return 0;
7648 fail_unpin:
7649         i915_gem_object_unpin_from_display_plane(obj);
7650 fail_locked:
7651         mutex_unlock(&dev->struct_mutex);
7652 fail:
7653         drm_gem_object_unreference_unlocked(&obj->base);
7654         return ret;
7655 }
7656
7657 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7658 {
7659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7660
7661         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7662         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7663
7664         if (intel_crtc->active)
7665                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7666
7667         return 0;
7668 }
7669
7670 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7671                                  u16 *blue, uint32_t start, uint32_t size)
7672 {
7673         int end = (start + size > 256) ? 256 : start + size, i;
7674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7675
7676         for (i = start; i < end; i++) {
7677                 intel_crtc->lut_r[i] = red[i] >> 8;
7678                 intel_crtc->lut_g[i] = green[i] >> 8;
7679                 intel_crtc->lut_b[i] = blue[i] >> 8;
7680         }
7681
7682         intel_crtc_load_lut(crtc);
7683 }
7684
7685 /* VESA 640x480x72Hz mode to set on the pipe */
7686 static struct drm_display_mode load_detect_mode = {
7687         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7688                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7689 };
7690
7691 static struct drm_framebuffer *
7692 intel_framebuffer_create(struct drm_device *dev,
7693                          struct drm_mode_fb_cmd2 *mode_cmd,
7694                          struct drm_i915_gem_object *obj)
7695 {
7696         struct intel_framebuffer *intel_fb;
7697         int ret;
7698
7699         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7700         if (!intel_fb) {
7701                 drm_gem_object_unreference_unlocked(&obj->base);
7702                 return ERR_PTR(-ENOMEM);
7703         }
7704
7705         ret = i915_mutex_lock_interruptible(dev);
7706         if (ret)
7707                 goto err;
7708
7709         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7710         mutex_unlock(&dev->struct_mutex);
7711         if (ret)
7712                 goto err;
7713
7714         return &intel_fb->base;
7715 err:
7716         drm_gem_object_unreference_unlocked(&obj->base);
7717         kfree(intel_fb);
7718
7719         return ERR_PTR(ret);
7720 }
7721
7722 static u32
7723 intel_framebuffer_pitch_for_width(int width, int bpp)
7724 {
7725         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7726         return ALIGN(pitch, 64);
7727 }
7728
7729 static u32
7730 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7731 {
7732         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7733         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7734 }
7735
7736 static struct drm_framebuffer *
7737 intel_framebuffer_create_for_mode(struct drm_device *dev,
7738                                   struct drm_display_mode *mode,
7739                                   int depth, int bpp)
7740 {
7741         struct drm_i915_gem_object *obj;
7742         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7743
7744         obj = i915_gem_alloc_object(dev,
7745                                     intel_framebuffer_size_for_mode(mode, bpp));
7746         if (obj == NULL)
7747                 return ERR_PTR(-ENOMEM);
7748
7749         mode_cmd.width = mode->hdisplay;
7750         mode_cmd.height = mode->vdisplay;
7751         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7752                                                                 bpp);
7753         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7754
7755         return intel_framebuffer_create(dev, &mode_cmd, obj);
7756 }
7757
7758 static struct drm_framebuffer *
7759 mode_fits_in_fbdev(struct drm_device *dev,
7760                    struct drm_display_mode *mode)
7761 {
7762 #ifdef CONFIG_DRM_I915_FBDEV
7763         struct drm_i915_private *dev_priv = dev->dev_private;
7764         struct drm_i915_gem_object *obj;
7765         struct drm_framebuffer *fb;
7766
7767         if (dev_priv->fbdev == NULL)
7768                 return NULL;
7769
7770         obj = dev_priv->fbdev->ifb.obj;
7771         if (obj == NULL)
7772                 return NULL;
7773
7774         fb = &dev_priv->fbdev->ifb.base;
7775         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7776                                                                fb->bits_per_pixel))
7777                 return NULL;
7778
7779         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7780                 return NULL;
7781
7782         return fb;
7783 #else
7784         return NULL;
7785 #endif
7786 }
7787
7788 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7789                                 struct drm_display_mode *mode,
7790                                 struct intel_load_detect_pipe *old)
7791 {
7792         struct intel_crtc *intel_crtc;
7793         struct intel_encoder *intel_encoder =
7794                 intel_attached_encoder(connector);
7795         struct drm_crtc *possible_crtc;
7796         struct drm_encoder *encoder = &intel_encoder->base;
7797         struct drm_crtc *crtc = NULL;
7798         struct drm_device *dev = encoder->dev;
7799         struct drm_framebuffer *fb;
7800         int i = -1;
7801
7802         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7803                       connector->base.id, drm_get_connector_name(connector),
7804                       encoder->base.id, drm_get_encoder_name(encoder));
7805
7806         /*
7807          * Algorithm gets a little messy:
7808          *
7809          *   - if the connector already has an assigned crtc, use it (but make
7810          *     sure it's on first)
7811          *
7812          *   - try to find the first unused crtc that can drive this connector,
7813          *     and use that if we find one
7814          */
7815
7816         /* See if we already have a CRTC for this connector */
7817         if (encoder->crtc) {
7818                 crtc = encoder->crtc;
7819
7820                 mutex_lock(&crtc->mutex);
7821
7822                 old->dpms_mode = connector->dpms;
7823                 old->load_detect_temp = false;
7824
7825                 /* Make sure the crtc and connector are running */
7826                 if (connector->dpms != DRM_MODE_DPMS_ON)
7827                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7828
7829                 return true;
7830         }
7831
7832         /* Find an unused one (if possible) */
7833         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7834                 i++;
7835                 if (!(encoder->possible_crtcs & (1 << i)))
7836                         continue;
7837                 if (!possible_crtc->enabled) {
7838                         crtc = possible_crtc;
7839                         break;
7840                 }
7841         }
7842
7843         /*
7844          * If we didn't find an unused CRTC, don't use any.
7845          */
7846         if (!crtc) {
7847                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7848                 return false;
7849         }
7850
7851         mutex_lock(&crtc->mutex);
7852         intel_encoder->new_crtc = to_intel_crtc(crtc);
7853         to_intel_connector(connector)->new_encoder = intel_encoder;
7854
7855         intel_crtc = to_intel_crtc(crtc);
7856         old->dpms_mode = connector->dpms;
7857         old->load_detect_temp = true;
7858         old->release_fb = NULL;
7859
7860         if (!mode)
7861                 mode = &load_detect_mode;
7862
7863         /* We need a framebuffer large enough to accommodate all accesses
7864          * that the plane may generate whilst we perform load detection.
7865          * We can not rely on the fbcon either being present (we get called
7866          * during its initialisation to detect all boot displays, or it may
7867          * not even exist) or that it is large enough to satisfy the
7868          * requested mode.
7869          */
7870         fb = mode_fits_in_fbdev(dev, mode);
7871         if (fb == NULL) {
7872                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7873                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7874                 old->release_fb = fb;
7875         } else
7876                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7877         if (IS_ERR(fb)) {
7878                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7879                 mutex_unlock(&crtc->mutex);
7880                 return false;
7881         }
7882
7883         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7884                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7885                 if (old->release_fb)
7886                         old->release_fb->funcs->destroy(old->release_fb);
7887                 mutex_unlock(&crtc->mutex);
7888                 return false;
7889         }
7890
7891         /* let the connector get through one full cycle before testing */
7892         intel_wait_for_vblank(dev, intel_crtc->pipe);
7893         return true;
7894 }
7895
7896 void intel_release_load_detect_pipe(struct drm_connector *connector,
7897                                     struct intel_load_detect_pipe *old)
7898 {
7899         struct intel_encoder *intel_encoder =
7900                 intel_attached_encoder(connector);
7901         struct drm_encoder *encoder = &intel_encoder->base;
7902         struct drm_crtc *crtc = encoder->crtc;
7903
7904         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7905                       connector->base.id, drm_get_connector_name(connector),
7906                       encoder->base.id, drm_get_encoder_name(encoder));
7907
7908         if (old->load_detect_temp) {
7909                 to_intel_connector(connector)->new_encoder = NULL;
7910                 intel_encoder->new_crtc = NULL;
7911                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7912
7913                 if (old->release_fb) {
7914                         drm_framebuffer_unregister_private(old->release_fb);
7915                         drm_framebuffer_unreference(old->release_fb);
7916                 }
7917
7918                 mutex_unlock(&crtc->mutex);
7919                 return;
7920         }
7921
7922         /* Switch crtc and encoder back off if necessary */
7923         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7924                 connector->funcs->dpms(connector, old->dpms_mode);
7925
7926         mutex_unlock(&crtc->mutex);
7927 }
7928
7929 static int i9xx_pll_refclk(struct drm_device *dev,
7930                            const struct intel_crtc_config *pipe_config)
7931 {
7932         struct drm_i915_private *dev_priv = dev->dev_private;
7933         u32 dpll = pipe_config->dpll_hw_state.dpll;
7934
7935         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7936                 return dev_priv->vbt.lvds_ssc_freq;
7937         else if (HAS_PCH_SPLIT(dev))
7938                 return 120000;
7939         else if (!IS_GEN2(dev))
7940                 return 96000;
7941         else
7942                 return 48000;
7943 }
7944
7945 /* Returns the clock of the currently programmed mode of the given pipe. */
7946 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7947                                 struct intel_crtc_config *pipe_config)
7948 {
7949         struct drm_device *dev = crtc->base.dev;
7950         struct drm_i915_private *dev_priv = dev->dev_private;
7951         int pipe = pipe_config->cpu_transcoder;
7952         u32 dpll = pipe_config->dpll_hw_state.dpll;
7953         u32 fp;
7954         intel_clock_t clock;
7955         int refclk = i9xx_pll_refclk(dev, pipe_config);
7956
7957         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7958                 fp = pipe_config->dpll_hw_state.fp0;
7959         else
7960                 fp = pipe_config->dpll_hw_state.fp1;
7961
7962         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7963         if (IS_PINEVIEW(dev)) {
7964                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7965                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7966         } else {
7967                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7968                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7969         }
7970
7971         if (!IS_GEN2(dev)) {
7972                 if (IS_PINEVIEW(dev))
7973                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7974                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7975                 else
7976                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7977                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7978
7979                 switch (dpll & DPLL_MODE_MASK) {
7980                 case DPLLB_MODE_DAC_SERIAL:
7981                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7982                                 5 : 10;
7983                         break;
7984                 case DPLLB_MODE_LVDS:
7985                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7986                                 7 : 14;
7987                         break;
7988                 default:
7989                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7990                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7991                         return;
7992                 }
7993
7994                 if (IS_PINEVIEW(dev))
7995                         pineview_clock(refclk, &clock);
7996                 else
7997                         i9xx_clock(refclk, &clock);
7998         } else {
7999                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8000                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8001
8002                 if (is_lvds) {
8003                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8004                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8005
8006                         if (lvds & LVDS_CLKB_POWER_UP)
8007                                 clock.p2 = 7;
8008                         else
8009                                 clock.p2 = 14;
8010                 } else {
8011                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8012                                 clock.p1 = 2;
8013                         else {
8014                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8015                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8016                         }
8017                         if (dpll & PLL_P2_DIVIDE_BY_4)
8018                                 clock.p2 = 4;
8019                         else
8020                                 clock.p2 = 2;
8021                 }
8022
8023                 i9xx_clock(refclk, &clock);
8024         }
8025
8026         /*
8027          * This value includes pixel_multiplier. We will use
8028          * port_clock to compute adjusted_mode.crtc_clock in the
8029          * encoder's get_config() function.
8030          */
8031         pipe_config->port_clock = clock.dot;
8032 }
8033
8034 int intel_dotclock_calculate(int link_freq,
8035                              const struct intel_link_m_n *m_n)
8036 {
8037         /*
8038          * The calculation for the data clock is:
8039          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8040          * But we want to avoid losing precison if possible, so:
8041          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8042          *
8043          * and the link clock is simpler:
8044          * link_clock = (m * link_clock) / n
8045          */
8046
8047         if (!m_n->link_n)
8048                 return 0;
8049
8050         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8051 }
8052
8053 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8054                                    struct intel_crtc_config *pipe_config)
8055 {
8056         struct drm_device *dev = crtc->base.dev;
8057
8058         /* read out port_clock from the DPLL */
8059         i9xx_crtc_clock_get(crtc, pipe_config);
8060
8061         /*
8062          * This value does not include pixel_multiplier.
8063          * We will check that port_clock and adjusted_mode.crtc_clock
8064          * agree once we know their relationship in the encoder's
8065          * get_config() function.
8066          */
8067         pipe_config->adjusted_mode.crtc_clock =
8068                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8069                                          &pipe_config->fdi_m_n);
8070 }
8071
8072 /** Returns the currently programmed mode of the given pipe. */
8073 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8074                                              struct drm_crtc *crtc)
8075 {
8076         struct drm_i915_private *dev_priv = dev->dev_private;
8077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8078         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8079         struct drm_display_mode *mode;
8080         struct intel_crtc_config pipe_config;
8081         int htot = I915_READ(HTOTAL(cpu_transcoder));
8082         int hsync = I915_READ(HSYNC(cpu_transcoder));
8083         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8084         int vsync = I915_READ(VSYNC(cpu_transcoder));
8085         enum pipe pipe = intel_crtc->pipe;
8086
8087         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8088         if (!mode)
8089                 return NULL;
8090
8091         /*
8092          * Construct a pipe_config sufficient for getting the clock info
8093          * back out of crtc_clock_get.
8094          *
8095          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8096          * to use a real value here instead.
8097          */
8098         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8099         pipe_config.pixel_multiplier = 1;
8100         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8101         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8102         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8103         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8104
8105         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8106         mode->hdisplay = (htot & 0xffff) + 1;
8107         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8108         mode->hsync_start = (hsync & 0xffff) + 1;
8109         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8110         mode->vdisplay = (vtot & 0xffff) + 1;
8111         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8112         mode->vsync_start = (vsync & 0xffff) + 1;
8113         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8114
8115         drm_mode_set_name(mode);
8116
8117         return mode;
8118 }
8119
8120 static void intel_increase_pllclock(struct drm_crtc *crtc)
8121 {
8122         struct drm_device *dev = crtc->dev;
8123         drm_i915_private_t *dev_priv = dev->dev_private;
8124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8125         int pipe = intel_crtc->pipe;
8126         int dpll_reg = DPLL(pipe);
8127         int dpll;
8128
8129         if (HAS_PCH_SPLIT(dev))
8130                 return;
8131
8132         if (!dev_priv->lvds_downclock_avail)
8133                 return;
8134
8135         dpll = I915_READ(dpll_reg);
8136         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8137                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8138
8139                 assert_panel_unlocked(dev_priv, pipe);
8140
8141                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8142                 I915_WRITE(dpll_reg, dpll);
8143                 intel_wait_for_vblank(dev, pipe);
8144
8145                 dpll = I915_READ(dpll_reg);
8146                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8147                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8148         }
8149 }
8150
8151 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8152 {
8153         struct drm_device *dev = crtc->dev;
8154         drm_i915_private_t *dev_priv = dev->dev_private;
8155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8156
8157         if (HAS_PCH_SPLIT(dev))
8158                 return;
8159
8160         if (!dev_priv->lvds_downclock_avail)
8161                 return;
8162
8163         /*
8164          * Since this is called by a timer, we should never get here in
8165          * the manual case.
8166          */
8167         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8168                 int pipe = intel_crtc->pipe;
8169                 int dpll_reg = DPLL(pipe);
8170                 int dpll;
8171
8172                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8173
8174                 assert_panel_unlocked(dev_priv, pipe);
8175
8176                 dpll = I915_READ(dpll_reg);
8177                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8178                 I915_WRITE(dpll_reg, dpll);
8179                 intel_wait_for_vblank(dev, pipe);
8180                 dpll = I915_READ(dpll_reg);
8181                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8182                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8183         }
8184
8185 }
8186
8187 void intel_mark_busy(struct drm_device *dev)
8188 {
8189         struct drm_i915_private *dev_priv = dev->dev_private;
8190
8191         hsw_package_c8_gpu_busy(dev_priv);
8192         i915_update_gfx_val(dev_priv);
8193 }
8194
8195 void intel_mark_idle(struct drm_device *dev)
8196 {
8197         struct drm_i915_private *dev_priv = dev->dev_private;
8198         struct drm_crtc *crtc;
8199
8200         hsw_package_c8_gpu_idle(dev_priv);
8201
8202         if (!i915_powersave)
8203                 return;
8204
8205         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8206                 if (!crtc->fb)
8207                         continue;
8208
8209                 intel_decrease_pllclock(crtc);
8210         }
8211
8212         if (dev_priv->info->gen >= 6)
8213                 gen6_rps_idle(dev->dev_private);
8214 }
8215
8216 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8217                         struct intel_ring_buffer *ring)
8218 {
8219         struct drm_device *dev = obj->base.dev;
8220         struct drm_crtc *crtc;
8221
8222         if (!i915_powersave)
8223                 return;
8224
8225         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8226                 if (!crtc->fb)
8227                         continue;
8228
8229                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8230                         continue;
8231
8232                 intel_increase_pllclock(crtc);
8233                 if (ring && intel_fbc_enabled(dev))
8234                         ring->fbc_dirty = true;
8235         }
8236 }
8237
8238 static void intel_crtc_destroy(struct drm_crtc *crtc)
8239 {
8240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8241         struct drm_device *dev = crtc->dev;
8242         struct intel_unpin_work *work;
8243         unsigned long flags;
8244
8245         spin_lock_irqsave(&dev->event_lock, flags);
8246         work = intel_crtc->unpin_work;
8247         intel_crtc->unpin_work = NULL;
8248         spin_unlock_irqrestore(&dev->event_lock, flags);
8249
8250         if (work) {
8251                 cancel_work_sync(&work->work);
8252                 kfree(work);
8253         }
8254
8255         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8256
8257         drm_crtc_cleanup(crtc);
8258
8259         kfree(intel_crtc);
8260 }
8261
8262 static void intel_unpin_work_fn(struct work_struct *__work)
8263 {
8264         struct intel_unpin_work *work =
8265                 container_of(__work, struct intel_unpin_work, work);
8266         struct drm_device *dev = work->crtc->dev;
8267
8268         mutex_lock(&dev->struct_mutex);
8269         intel_unpin_fb_obj(work->old_fb_obj);
8270         drm_gem_object_unreference(&work->pending_flip_obj->base);
8271         drm_gem_object_unreference(&work->old_fb_obj->base);
8272
8273         intel_update_fbc(dev);
8274         mutex_unlock(&dev->struct_mutex);
8275
8276         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8277         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8278
8279         kfree(work);
8280 }
8281
8282 static void do_intel_finish_page_flip(struct drm_device *dev,
8283                                       struct drm_crtc *crtc)
8284 {
8285         drm_i915_private_t *dev_priv = dev->dev_private;
8286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8287         struct intel_unpin_work *work;
8288         unsigned long flags;
8289
8290         /* Ignore early vblank irqs */
8291         if (intel_crtc == NULL)
8292                 return;
8293
8294         spin_lock_irqsave(&dev->event_lock, flags);
8295         work = intel_crtc->unpin_work;
8296
8297         /* Ensure we don't miss a work->pending update ... */
8298         smp_rmb();
8299
8300         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8301                 spin_unlock_irqrestore(&dev->event_lock, flags);
8302                 return;
8303         }
8304
8305         /* and that the unpin work is consistent wrt ->pending. */
8306         smp_rmb();
8307
8308         intel_crtc->unpin_work = NULL;
8309
8310         if (work->event)
8311                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8312
8313         drm_vblank_put(dev, intel_crtc->pipe);
8314
8315         spin_unlock_irqrestore(&dev->event_lock, flags);
8316
8317         wake_up_all(&dev_priv->pending_flip_queue);
8318
8319         queue_work(dev_priv->wq, &work->work);
8320
8321         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8322 }
8323
8324 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8325 {
8326         drm_i915_private_t *dev_priv = dev->dev_private;
8327         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8328
8329         do_intel_finish_page_flip(dev, crtc);
8330 }
8331
8332 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8333 {
8334         drm_i915_private_t *dev_priv = dev->dev_private;
8335         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8336
8337         do_intel_finish_page_flip(dev, crtc);
8338 }
8339
8340 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8341 {
8342         drm_i915_private_t *dev_priv = dev->dev_private;
8343         struct intel_crtc *intel_crtc =
8344                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8345         unsigned long flags;
8346
8347         /* NB: An MMIO update of the plane base pointer will also
8348          * generate a page-flip completion irq, i.e. every modeset
8349          * is also accompanied by a spurious intel_prepare_page_flip().
8350          */
8351         spin_lock_irqsave(&dev->event_lock, flags);
8352         if (intel_crtc->unpin_work)
8353                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8354         spin_unlock_irqrestore(&dev->event_lock, flags);
8355 }
8356
8357 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8358 {
8359         /* Ensure that the work item is consistent when activating it ... */
8360         smp_wmb();
8361         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8362         /* and that it is marked active as soon as the irq could fire. */
8363         smp_wmb();
8364 }
8365
8366 static int intel_gen2_queue_flip(struct drm_device *dev,
8367                                  struct drm_crtc *crtc,
8368                                  struct drm_framebuffer *fb,
8369                                  struct drm_i915_gem_object *obj,
8370                                  uint32_t flags)
8371 {
8372         struct drm_i915_private *dev_priv = dev->dev_private;
8373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8374         u32 flip_mask;
8375         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8376         int ret;
8377
8378         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8379         if (ret)
8380                 goto err;
8381
8382         ret = intel_ring_begin(ring, 6);
8383         if (ret)
8384                 goto err_unpin;
8385
8386         /* Can't queue multiple flips, so wait for the previous
8387          * one to finish before executing the next.
8388          */
8389         if (intel_crtc->plane)
8390                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8391         else
8392                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8393         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8394         intel_ring_emit(ring, MI_NOOP);
8395         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8396                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8397         intel_ring_emit(ring, fb->pitches[0]);
8398         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8399         intel_ring_emit(ring, 0); /* aux display base address, unused */
8400
8401         intel_mark_page_flip_active(intel_crtc);
8402         __intel_ring_advance(ring);
8403         return 0;
8404
8405 err_unpin:
8406         intel_unpin_fb_obj(obj);
8407 err:
8408         return ret;
8409 }
8410
8411 static int intel_gen3_queue_flip(struct drm_device *dev,
8412                                  struct drm_crtc *crtc,
8413                                  struct drm_framebuffer *fb,
8414                                  struct drm_i915_gem_object *obj,
8415                                  uint32_t flags)
8416 {
8417         struct drm_i915_private *dev_priv = dev->dev_private;
8418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8419         u32 flip_mask;
8420         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8421         int ret;
8422
8423         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8424         if (ret)
8425                 goto err;
8426
8427         ret = intel_ring_begin(ring, 6);
8428         if (ret)
8429                 goto err_unpin;
8430
8431         if (intel_crtc->plane)
8432                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8433         else
8434                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8435         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8436         intel_ring_emit(ring, MI_NOOP);
8437         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8438                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8439         intel_ring_emit(ring, fb->pitches[0]);
8440         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8441         intel_ring_emit(ring, MI_NOOP);
8442
8443         intel_mark_page_flip_active(intel_crtc);
8444         __intel_ring_advance(ring);
8445         return 0;
8446
8447 err_unpin:
8448         intel_unpin_fb_obj(obj);
8449 err:
8450         return ret;
8451 }
8452
8453 static int intel_gen4_queue_flip(struct drm_device *dev,
8454                                  struct drm_crtc *crtc,
8455                                  struct drm_framebuffer *fb,
8456                                  struct drm_i915_gem_object *obj,
8457                                  uint32_t flags)
8458 {
8459         struct drm_i915_private *dev_priv = dev->dev_private;
8460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8461         uint32_t pf, pipesrc;
8462         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8463         int ret;
8464
8465         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8466         if (ret)
8467                 goto err;
8468
8469         ret = intel_ring_begin(ring, 4);
8470         if (ret)
8471                 goto err_unpin;
8472
8473         /* i965+ uses the linear or tiled offsets from the
8474          * Display Registers (which do not change across a page-flip)
8475          * so we need only reprogram the base address.
8476          */
8477         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8478                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8479         intel_ring_emit(ring, fb->pitches[0]);
8480         intel_ring_emit(ring,
8481                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8482                         obj->tiling_mode);
8483
8484         /* XXX Enabling the panel-fitter across page-flip is so far
8485          * untested on non-native modes, so ignore it for now.
8486          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8487          */
8488         pf = 0;
8489         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8490         intel_ring_emit(ring, pf | pipesrc);
8491
8492         intel_mark_page_flip_active(intel_crtc);
8493         __intel_ring_advance(ring);
8494         return 0;
8495
8496 err_unpin:
8497         intel_unpin_fb_obj(obj);
8498 err:
8499         return ret;
8500 }
8501
8502 static int intel_gen6_queue_flip(struct drm_device *dev,
8503                                  struct drm_crtc *crtc,
8504                                  struct drm_framebuffer *fb,
8505                                  struct drm_i915_gem_object *obj,
8506                                  uint32_t flags)
8507 {
8508         struct drm_i915_private *dev_priv = dev->dev_private;
8509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8510         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8511         uint32_t pf, pipesrc;
8512         int ret;
8513
8514         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8515         if (ret)
8516                 goto err;
8517
8518         ret = intel_ring_begin(ring, 4);
8519         if (ret)
8520                 goto err_unpin;
8521
8522         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8523                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8524         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8525         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8526
8527         /* Contrary to the suggestions in the documentation,
8528          * "Enable Panel Fitter" does not seem to be required when page
8529          * flipping with a non-native mode, and worse causes a normal
8530          * modeset to fail.
8531          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8532          */
8533         pf = 0;
8534         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8535         intel_ring_emit(ring, pf | pipesrc);
8536
8537         intel_mark_page_flip_active(intel_crtc);
8538         __intel_ring_advance(ring);
8539         return 0;
8540
8541 err_unpin:
8542         intel_unpin_fb_obj(obj);
8543 err:
8544         return ret;
8545 }
8546
8547 static int intel_gen7_queue_flip(struct drm_device *dev,
8548                                  struct drm_crtc *crtc,
8549                                  struct drm_framebuffer *fb,
8550                                  struct drm_i915_gem_object *obj,
8551                                  uint32_t flags)
8552 {
8553         struct drm_i915_private *dev_priv = dev->dev_private;
8554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8555         struct intel_ring_buffer *ring;
8556         uint32_t plane_bit = 0;
8557         int len, ret;
8558
8559         ring = obj->ring;
8560         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8561                 ring = &dev_priv->ring[BCS];
8562
8563         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8564         if (ret)
8565                 goto err;
8566
8567         switch(intel_crtc->plane) {
8568         case PLANE_A:
8569                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8570                 break;
8571         case PLANE_B:
8572                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8573                 break;
8574         case PLANE_C:
8575                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8576                 break;
8577         default:
8578                 WARN_ONCE(1, "unknown plane in flip command\n");
8579                 ret = -ENODEV;
8580                 goto err_unpin;
8581         }
8582
8583         len = 4;
8584         if (ring->id == RCS)
8585                 len += 6;
8586
8587         /*
8588          * BSpec MI_DISPLAY_FLIP for IVB:
8589          * "The full packet must be contained within the same cache line."
8590          *
8591          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8592          * cacheline, if we ever start emitting more commands before
8593          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8594          * then do the cacheline alignment, and finally emit the
8595          * MI_DISPLAY_FLIP.
8596          */
8597         ret = intel_ring_cacheline_align(ring);
8598         if (ret)
8599                 goto err_unpin;
8600
8601         ret = intel_ring_begin(ring, len);
8602         if (ret)
8603                 goto err_unpin;
8604
8605         /* Unmask the flip-done completion message. Note that the bspec says that
8606          * we should do this for both the BCS and RCS, and that we must not unmask
8607          * more than one flip event at any time (or ensure that one flip message
8608          * can be sent by waiting for flip-done prior to queueing new flips).
8609          * Experimentation says that BCS works despite DERRMR masking all
8610          * flip-done completion events and that unmasking all planes at once
8611          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8612          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8613          */
8614         if (ring->id == RCS) {
8615                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8616                 intel_ring_emit(ring, DERRMR);
8617                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8618                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8619                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8620                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8621                                 MI_SRM_LRM_GLOBAL_GTT);
8622                 intel_ring_emit(ring, DERRMR);
8623                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8624         }
8625
8626         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8627         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8628         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8629         intel_ring_emit(ring, (MI_NOOP));
8630
8631         intel_mark_page_flip_active(intel_crtc);
8632         __intel_ring_advance(ring);
8633         return 0;
8634
8635 err_unpin:
8636         intel_unpin_fb_obj(obj);
8637 err:
8638         return ret;
8639 }
8640
8641 static int intel_default_queue_flip(struct drm_device *dev,
8642                                     struct drm_crtc *crtc,
8643                                     struct drm_framebuffer *fb,
8644                                     struct drm_i915_gem_object *obj,
8645                                     uint32_t flags)
8646 {
8647         return -ENODEV;
8648 }
8649
8650 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8651                                 struct drm_framebuffer *fb,
8652                                 struct drm_pending_vblank_event *event,
8653                                 uint32_t page_flip_flags)
8654 {
8655         struct drm_device *dev = crtc->dev;
8656         struct drm_i915_private *dev_priv = dev->dev_private;
8657         struct drm_framebuffer *old_fb = crtc->fb;
8658         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8660         struct intel_unpin_work *work;
8661         unsigned long flags;
8662         int ret;
8663
8664         /* Can't change pixel format via MI display flips. */
8665         if (fb->pixel_format != crtc->fb->pixel_format)
8666                 return -EINVAL;
8667
8668         /*
8669          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8670          * Note that pitch changes could also affect these register.
8671          */
8672         if (INTEL_INFO(dev)->gen > 3 &&
8673             (fb->offsets[0] != crtc->fb->offsets[0] ||
8674              fb->pitches[0] != crtc->fb->pitches[0]))
8675                 return -EINVAL;
8676
8677         work = kzalloc(sizeof(*work), GFP_KERNEL);
8678         if (work == NULL)
8679                 return -ENOMEM;
8680
8681         work->event = event;
8682         work->crtc = crtc;
8683         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8684         INIT_WORK(&work->work, intel_unpin_work_fn);
8685
8686         ret = drm_vblank_get(dev, intel_crtc->pipe);
8687         if (ret)
8688                 goto free_work;
8689
8690         /* We borrow the event spin lock for protecting unpin_work */
8691         spin_lock_irqsave(&dev->event_lock, flags);
8692         if (intel_crtc->unpin_work) {
8693                 spin_unlock_irqrestore(&dev->event_lock, flags);
8694                 kfree(work);
8695                 drm_vblank_put(dev, intel_crtc->pipe);
8696
8697                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8698                 return -EBUSY;
8699         }
8700         intel_crtc->unpin_work = work;
8701         spin_unlock_irqrestore(&dev->event_lock, flags);
8702
8703         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8704                 flush_workqueue(dev_priv->wq);
8705
8706         ret = i915_mutex_lock_interruptible(dev);
8707         if (ret)
8708                 goto cleanup;
8709
8710         /* Reference the objects for the scheduled work. */
8711         drm_gem_object_reference(&work->old_fb_obj->base);
8712         drm_gem_object_reference(&obj->base);
8713
8714         crtc->fb = fb;
8715
8716         work->pending_flip_obj = obj;
8717
8718         work->enable_stall_check = true;
8719
8720         atomic_inc(&intel_crtc->unpin_work_count);
8721         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8722
8723         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8724         if (ret)
8725                 goto cleanup_pending;
8726
8727         intel_disable_fbc(dev);
8728         intel_mark_fb_busy(obj, NULL);
8729         mutex_unlock(&dev->struct_mutex);
8730
8731         trace_i915_flip_request(intel_crtc->plane, obj);
8732
8733         return 0;
8734
8735 cleanup_pending:
8736         atomic_dec(&intel_crtc->unpin_work_count);
8737         crtc->fb = old_fb;
8738         drm_gem_object_unreference(&work->old_fb_obj->base);
8739         drm_gem_object_unreference(&obj->base);
8740         mutex_unlock(&dev->struct_mutex);
8741
8742 cleanup:
8743         spin_lock_irqsave(&dev->event_lock, flags);
8744         intel_crtc->unpin_work = NULL;
8745         spin_unlock_irqrestore(&dev->event_lock, flags);
8746
8747         drm_vblank_put(dev, intel_crtc->pipe);
8748 free_work:
8749         kfree(work);
8750
8751         return ret;
8752 }
8753
8754 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8755         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8756         .load_lut = intel_crtc_load_lut,
8757 };
8758
8759 /**
8760  * intel_modeset_update_staged_output_state
8761  *
8762  * Updates the staged output configuration state, e.g. after we've read out the
8763  * current hw state.
8764  */
8765 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8766 {
8767         struct intel_encoder *encoder;
8768         struct intel_connector *connector;
8769
8770         list_for_each_entry(connector, &dev->mode_config.connector_list,
8771                             base.head) {
8772                 connector->new_encoder =
8773                         to_intel_encoder(connector->base.encoder);
8774         }
8775
8776         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8777                             base.head) {
8778                 encoder->new_crtc =
8779                         to_intel_crtc(encoder->base.crtc);
8780         }
8781 }
8782
8783 /**
8784  * intel_modeset_commit_output_state
8785  *
8786  * This function copies the stage display pipe configuration to the real one.
8787  */
8788 static void intel_modeset_commit_output_state(struct drm_device *dev)
8789 {
8790         struct intel_encoder *encoder;
8791         struct intel_connector *connector;
8792
8793         list_for_each_entry(connector, &dev->mode_config.connector_list,
8794                             base.head) {
8795                 connector->base.encoder = &connector->new_encoder->base;
8796         }
8797
8798         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8799                             base.head) {
8800                 encoder->base.crtc = &encoder->new_crtc->base;
8801         }
8802 }
8803
8804 static void
8805 connected_sink_compute_bpp(struct intel_connector * connector,
8806                            struct intel_crtc_config *pipe_config)
8807 {
8808         int bpp = pipe_config->pipe_bpp;
8809
8810         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8811                 connector->base.base.id,
8812                 drm_get_connector_name(&connector->base));
8813
8814         /* Don't use an invalid EDID bpc value */
8815         if (connector->base.display_info.bpc &&
8816             connector->base.display_info.bpc * 3 < bpp) {
8817                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8818                               bpp, connector->base.display_info.bpc*3);
8819                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8820         }
8821
8822         /* Clamp bpp to 8 on screens without EDID 1.4 */
8823         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8824                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8825                               bpp);
8826                 pipe_config->pipe_bpp = 24;
8827         }
8828 }
8829
8830 static int
8831 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8832                           struct drm_framebuffer *fb,
8833                           struct intel_crtc_config *pipe_config)
8834 {
8835         struct drm_device *dev = crtc->base.dev;
8836         struct intel_connector *connector;
8837         int bpp;
8838
8839         switch (fb->pixel_format) {
8840         case DRM_FORMAT_C8:
8841                 bpp = 8*3; /* since we go through a colormap */
8842                 break;
8843         case DRM_FORMAT_XRGB1555:
8844         case DRM_FORMAT_ARGB1555:
8845                 /* checked in intel_framebuffer_init already */
8846                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8847                         return -EINVAL;
8848         case DRM_FORMAT_RGB565:
8849                 bpp = 6*3; /* min is 18bpp */
8850                 break;
8851         case DRM_FORMAT_XBGR8888:
8852         case DRM_FORMAT_ABGR8888:
8853                 /* checked in intel_framebuffer_init already */
8854                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8855                         return -EINVAL;
8856         case DRM_FORMAT_XRGB8888:
8857         case DRM_FORMAT_ARGB8888:
8858                 bpp = 8*3;
8859                 break;
8860         case DRM_FORMAT_XRGB2101010:
8861         case DRM_FORMAT_ARGB2101010:
8862         case DRM_FORMAT_XBGR2101010:
8863         case DRM_FORMAT_ABGR2101010:
8864                 /* checked in intel_framebuffer_init already */
8865                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8866                         return -EINVAL;
8867                 bpp = 10*3;
8868                 break;
8869         /* TODO: gen4+ supports 16 bpc floating point, too. */
8870         default:
8871                 DRM_DEBUG_KMS("unsupported depth\n");
8872                 return -EINVAL;
8873         }
8874
8875         pipe_config->pipe_bpp = bpp;
8876
8877         /* Clamp display bpp to EDID value */
8878         list_for_each_entry(connector, &dev->mode_config.connector_list,
8879                             base.head) {
8880                 if (!connector->new_encoder ||
8881                     connector->new_encoder->new_crtc != crtc)
8882                         continue;
8883
8884                 connected_sink_compute_bpp(connector, pipe_config);
8885         }
8886
8887         return bpp;
8888 }
8889
8890 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8891 {
8892         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8893                         "type: 0x%x flags: 0x%x\n",
8894                 mode->crtc_clock,
8895                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8896                 mode->crtc_hsync_end, mode->crtc_htotal,
8897                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8898                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8899 }
8900
8901 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8902                                    struct intel_crtc_config *pipe_config,
8903                                    const char *context)
8904 {
8905         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8906                       context, pipe_name(crtc->pipe));
8907
8908         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8909         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8910                       pipe_config->pipe_bpp, pipe_config->dither);
8911         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8912                       pipe_config->has_pch_encoder,
8913                       pipe_config->fdi_lanes,
8914                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8915                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8916                       pipe_config->fdi_m_n.tu);
8917         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8918                       pipe_config->has_dp_encoder,
8919                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8920                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8921                       pipe_config->dp_m_n.tu);
8922         DRM_DEBUG_KMS("requested mode:\n");
8923         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8924         DRM_DEBUG_KMS("adjusted mode:\n");
8925         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8926         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8927         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8928         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8929                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8930         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8931                       pipe_config->gmch_pfit.control,
8932                       pipe_config->gmch_pfit.pgm_ratios,
8933                       pipe_config->gmch_pfit.lvds_border_bits);
8934         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8935                       pipe_config->pch_pfit.pos,
8936                       pipe_config->pch_pfit.size,
8937                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8938         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8939         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8940 }
8941
8942 static bool check_encoder_cloning(struct drm_crtc *crtc)
8943 {
8944         int num_encoders = 0;
8945         bool uncloneable_encoders = false;
8946         struct intel_encoder *encoder;
8947
8948         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8949                             base.head) {
8950                 if (&encoder->new_crtc->base != crtc)
8951                         continue;
8952
8953                 num_encoders++;
8954                 if (!encoder->cloneable)
8955                         uncloneable_encoders = true;
8956         }
8957
8958         return !(num_encoders > 1 && uncloneable_encoders);
8959 }
8960
8961 static struct intel_crtc_config *
8962 intel_modeset_pipe_config(struct drm_crtc *crtc,
8963                           struct drm_framebuffer *fb,
8964                           struct drm_display_mode *mode)
8965 {
8966         struct drm_device *dev = crtc->dev;
8967         struct intel_encoder *encoder;
8968         struct intel_crtc_config *pipe_config;
8969         int plane_bpp, ret = -EINVAL;
8970         bool retry = true;
8971
8972         if (!check_encoder_cloning(crtc)) {
8973                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8974                 return ERR_PTR(-EINVAL);
8975         }
8976
8977         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8978         if (!pipe_config)
8979                 return ERR_PTR(-ENOMEM);
8980
8981         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8982         drm_mode_copy(&pipe_config->requested_mode, mode);
8983
8984         pipe_config->cpu_transcoder =
8985                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8986         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8987
8988         /*
8989          * Sanitize sync polarity flags based on requested ones. If neither
8990          * positive or negative polarity is requested, treat this as meaning
8991          * negative polarity.
8992          */
8993         if (!(pipe_config->adjusted_mode.flags &
8994               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8995                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8996
8997         if (!(pipe_config->adjusted_mode.flags &
8998               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8999                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9000
9001         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9002          * plane pixel format and any sink constraints into account. Returns the
9003          * source plane bpp so that dithering can be selected on mismatches
9004          * after encoders and crtc also have had their say. */
9005         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9006                                               fb, pipe_config);
9007         if (plane_bpp < 0)
9008                 goto fail;
9009
9010         /*
9011          * Determine the real pipe dimensions. Note that stereo modes can
9012          * increase the actual pipe size due to the frame doubling and
9013          * insertion of additional space for blanks between the frame. This
9014          * is stored in the crtc timings. We use the requested mode to do this
9015          * computation to clearly distinguish it from the adjusted mode, which
9016          * can be changed by the connectors in the below retry loop.
9017          */
9018         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9019         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9020         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9021
9022 encoder_retry:
9023         /* Ensure the port clock defaults are reset when retrying. */
9024         pipe_config->port_clock = 0;
9025         pipe_config->pixel_multiplier = 1;
9026
9027         /* Fill in default crtc timings, allow encoders to overwrite them. */
9028         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9029
9030         /* Pass our mode to the connectors and the CRTC to give them a chance to
9031          * adjust it according to limitations or connector properties, and also
9032          * a chance to reject the mode entirely.
9033          */
9034         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9035                             base.head) {
9036
9037                 if (&encoder->new_crtc->base != crtc)
9038                         continue;
9039
9040                 if (!(encoder->compute_config(encoder, pipe_config))) {
9041                         DRM_DEBUG_KMS("Encoder config failure\n");
9042                         goto fail;
9043                 }
9044         }
9045
9046         /* Set default port clock if not overwritten by the encoder. Needs to be
9047          * done afterwards in case the encoder adjusts the mode. */
9048         if (!pipe_config->port_clock)
9049                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9050                         * pipe_config->pixel_multiplier;
9051
9052         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9053         if (ret < 0) {
9054                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9055                 goto fail;
9056         }
9057
9058         if (ret == RETRY) {
9059                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9060                         ret = -EINVAL;
9061                         goto fail;
9062                 }
9063
9064                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9065                 retry = false;
9066                 goto encoder_retry;
9067         }
9068
9069         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9070         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9071                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9072
9073         return pipe_config;
9074 fail:
9075         kfree(pipe_config);
9076         return ERR_PTR(ret);
9077 }
9078
9079 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9080  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9081 static void
9082 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9083                              unsigned *prepare_pipes, unsigned *disable_pipes)
9084 {
9085         struct intel_crtc *intel_crtc;
9086         struct drm_device *dev = crtc->dev;
9087         struct intel_encoder *encoder;
9088         struct intel_connector *connector;
9089         struct drm_crtc *tmp_crtc;
9090
9091         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9092
9093         /* Check which crtcs have changed outputs connected to them, these need
9094          * to be part of the prepare_pipes mask. We don't (yet) support global
9095          * modeset across multiple crtcs, so modeset_pipes will only have one
9096          * bit set at most. */
9097         list_for_each_entry(connector, &dev->mode_config.connector_list,
9098                             base.head) {
9099                 if (connector->base.encoder == &connector->new_encoder->base)
9100                         continue;
9101
9102                 if (connector->base.encoder) {
9103                         tmp_crtc = connector->base.encoder->crtc;
9104
9105                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9106                 }
9107
9108                 if (connector->new_encoder)
9109                         *prepare_pipes |=
9110                                 1 << connector->new_encoder->new_crtc->pipe;
9111         }
9112
9113         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9114                             base.head) {
9115                 if (encoder->base.crtc == &encoder->new_crtc->base)
9116                         continue;
9117
9118                 if (encoder->base.crtc) {
9119                         tmp_crtc = encoder->base.crtc;
9120
9121                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9122                 }
9123
9124                 if (encoder->new_crtc)
9125                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9126         }
9127
9128         /* Check for any pipes that will be fully disabled ... */
9129         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9130                             base.head) {
9131                 bool used = false;
9132
9133                 /* Don't try to disable disabled crtcs. */
9134                 if (!intel_crtc->base.enabled)
9135                         continue;
9136
9137                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9138                                     base.head) {
9139                         if (encoder->new_crtc == intel_crtc)
9140                                 used = true;
9141                 }
9142
9143                 if (!used)
9144                         *disable_pipes |= 1 << intel_crtc->pipe;
9145         }
9146
9147
9148         /* set_mode is also used to update properties on life display pipes. */
9149         intel_crtc = to_intel_crtc(crtc);
9150         if (crtc->enabled)
9151                 *prepare_pipes |= 1 << intel_crtc->pipe;
9152
9153         /*
9154          * For simplicity do a full modeset on any pipe where the output routing
9155          * changed. We could be more clever, but that would require us to be
9156          * more careful with calling the relevant encoder->mode_set functions.
9157          */
9158         if (*prepare_pipes)
9159                 *modeset_pipes = *prepare_pipes;
9160
9161         /* ... and mask these out. */
9162         *modeset_pipes &= ~(*disable_pipes);
9163         *prepare_pipes &= ~(*disable_pipes);
9164
9165         /*
9166          * HACK: We don't (yet) fully support global modesets. intel_set_config
9167          * obies this rule, but the modeset restore mode of
9168          * intel_modeset_setup_hw_state does not.
9169          */
9170         *modeset_pipes &= 1 << intel_crtc->pipe;
9171         *prepare_pipes &= 1 << intel_crtc->pipe;
9172
9173         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9174                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9175 }
9176
9177 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9178 {
9179         struct drm_encoder *encoder;
9180         struct drm_device *dev = crtc->dev;
9181
9182         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9183                 if (encoder->crtc == crtc)
9184                         return true;
9185
9186         return false;
9187 }
9188
9189 static void
9190 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9191 {
9192         struct intel_encoder *intel_encoder;
9193         struct intel_crtc *intel_crtc;
9194         struct drm_connector *connector;
9195
9196         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9197                             base.head) {
9198                 if (!intel_encoder->base.crtc)
9199                         continue;
9200
9201                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9202
9203                 if (prepare_pipes & (1 << intel_crtc->pipe))
9204                         intel_encoder->connectors_active = false;
9205         }
9206
9207         intel_modeset_commit_output_state(dev);
9208
9209         /* Update computed state. */
9210         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9211                             base.head) {
9212                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9213         }
9214
9215         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9216                 if (!connector->encoder || !connector->encoder->crtc)
9217                         continue;
9218
9219                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9220
9221                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9222                         struct drm_property *dpms_property =
9223                                 dev->mode_config.dpms_property;
9224
9225                         connector->dpms = DRM_MODE_DPMS_ON;
9226                         drm_object_property_set_value(&connector->base,
9227                                                          dpms_property,
9228                                                          DRM_MODE_DPMS_ON);
9229
9230                         intel_encoder = to_intel_encoder(connector->encoder);
9231                         intel_encoder->connectors_active = true;
9232                 }
9233         }
9234
9235 }
9236
9237 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9238 {
9239         int diff;
9240
9241         if (clock1 == clock2)
9242                 return true;
9243
9244         if (!clock1 || !clock2)
9245                 return false;
9246
9247         diff = abs(clock1 - clock2);
9248
9249         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9250                 return true;
9251
9252         return false;
9253 }
9254
9255 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9256         list_for_each_entry((intel_crtc), \
9257                             &(dev)->mode_config.crtc_list, \
9258                             base.head) \
9259                 if (mask & (1 <<(intel_crtc)->pipe))
9260
9261 static bool
9262 intel_pipe_config_compare(struct drm_device *dev,
9263                           struct intel_crtc_config *current_config,
9264                           struct intel_crtc_config *pipe_config)
9265 {
9266 #define PIPE_CONF_CHECK_X(name) \
9267         if (current_config->name != pipe_config->name) { \
9268                 DRM_ERROR("mismatch in " #name " " \
9269                           "(expected 0x%08x, found 0x%08x)\n", \
9270                           current_config->name, \
9271                           pipe_config->name); \
9272                 return false; \
9273         }
9274
9275 #define PIPE_CONF_CHECK_I(name) \
9276         if (current_config->name != pipe_config->name) { \
9277                 DRM_ERROR("mismatch in " #name " " \
9278                           "(expected %i, found %i)\n", \
9279                           current_config->name, \
9280                           pipe_config->name); \
9281                 return false; \
9282         }
9283
9284 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9285         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9286                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9287                           "(expected %i, found %i)\n", \
9288                           current_config->name & (mask), \
9289                           pipe_config->name & (mask)); \
9290                 return false; \
9291         }
9292
9293 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9294         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9295                 DRM_ERROR("mismatch in " #name " " \
9296                           "(expected %i, found %i)\n", \
9297                           current_config->name, \
9298                           pipe_config->name); \
9299                 return false; \
9300         }
9301
9302 #define PIPE_CONF_QUIRK(quirk)  \
9303         ((current_config->quirks | pipe_config->quirks) & (quirk))
9304
9305         PIPE_CONF_CHECK_I(cpu_transcoder);
9306
9307         PIPE_CONF_CHECK_I(has_pch_encoder);
9308         PIPE_CONF_CHECK_I(fdi_lanes);
9309         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9310         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9311         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9312         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9313         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9314
9315         PIPE_CONF_CHECK_I(has_dp_encoder);
9316         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9317         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9318         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9319         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9320         PIPE_CONF_CHECK_I(dp_m_n.tu);
9321
9322         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9323         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9324         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9325         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9326         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9327         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9328
9329         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9330         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9331         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9332         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9333         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9334         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9335
9336         PIPE_CONF_CHECK_I(pixel_multiplier);
9337
9338         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9339                               DRM_MODE_FLAG_INTERLACE);
9340
9341         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9342                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9343                                       DRM_MODE_FLAG_PHSYNC);
9344                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9345                                       DRM_MODE_FLAG_NHSYNC);
9346                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9347                                       DRM_MODE_FLAG_PVSYNC);
9348                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9349                                       DRM_MODE_FLAG_NVSYNC);
9350         }
9351
9352         PIPE_CONF_CHECK_I(pipe_src_w);
9353         PIPE_CONF_CHECK_I(pipe_src_h);
9354
9355         /*
9356          * FIXME: BIOS likes to set up a cloned config with lvds+external
9357          * screen. Since we don't yet re-compute the pipe config when moving
9358          * just the lvds port away to another pipe the sw tracking won't match.
9359          *
9360          * Proper atomic modesets with recomputed global state will fix this.
9361          * Until then just don't check gmch state for inherited modes.
9362          */
9363         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9364                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9365                 /* pfit ratios are autocomputed by the hw on gen4+ */
9366                 if (INTEL_INFO(dev)->gen < 4)
9367                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9368                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9369         }
9370
9371         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9372         if (current_config->pch_pfit.enabled) {
9373                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9374                 PIPE_CONF_CHECK_I(pch_pfit.size);
9375         }
9376
9377         /* BDW+ don't expose a synchronous way to read the state */
9378         if (IS_HASWELL(dev))
9379                 PIPE_CONF_CHECK_I(ips_enabled);
9380
9381         PIPE_CONF_CHECK_I(double_wide);
9382
9383         PIPE_CONF_CHECK_I(shared_dpll);
9384         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9385         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9386         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9387         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9388
9389         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9390                 PIPE_CONF_CHECK_I(pipe_bpp);
9391
9392         if (!HAS_DDI(dev)) {
9393                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9394                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9395         }
9396
9397 #undef PIPE_CONF_CHECK_X
9398 #undef PIPE_CONF_CHECK_I
9399 #undef PIPE_CONF_CHECK_FLAGS
9400 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9401 #undef PIPE_CONF_QUIRK
9402
9403         return true;
9404 }
9405
9406 static void
9407 check_connector_state(struct drm_device *dev)
9408 {
9409         struct intel_connector *connector;
9410
9411         list_for_each_entry(connector, &dev->mode_config.connector_list,
9412                             base.head) {
9413                 /* This also checks the encoder/connector hw state with the
9414                  * ->get_hw_state callbacks. */
9415                 intel_connector_check_state(connector);
9416
9417                 WARN(&connector->new_encoder->base != connector->base.encoder,
9418                      "connector's staged encoder doesn't match current encoder\n");
9419         }
9420 }
9421
9422 static void
9423 check_encoder_state(struct drm_device *dev)
9424 {
9425         struct intel_encoder *encoder;
9426         struct intel_connector *connector;
9427
9428         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9429                             base.head) {
9430                 bool enabled = false;
9431                 bool active = false;
9432                 enum pipe pipe, tracked_pipe;
9433
9434                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9435                               encoder->base.base.id,
9436                               drm_get_encoder_name(&encoder->base));
9437
9438                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9439                      "encoder's stage crtc doesn't match current crtc\n");
9440                 WARN(encoder->connectors_active && !encoder->base.crtc,
9441                      "encoder's active_connectors set, but no crtc\n");
9442
9443                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9444                                     base.head) {
9445                         if (connector->base.encoder != &encoder->base)
9446                                 continue;
9447                         enabled = true;
9448                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9449                                 active = true;
9450                 }
9451                 WARN(!!encoder->base.crtc != enabled,
9452                      "encoder's enabled state mismatch "
9453                      "(expected %i, found %i)\n",
9454                      !!encoder->base.crtc, enabled);
9455                 WARN(active && !encoder->base.crtc,
9456                      "active encoder with no crtc\n");
9457
9458                 WARN(encoder->connectors_active != active,
9459                      "encoder's computed active state doesn't match tracked active state "
9460                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9461
9462                 active = encoder->get_hw_state(encoder, &pipe);
9463                 WARN(active != encoder->connectors_active,
9464                      "encoder's hw state doesn't match sw tracking "
9465                      "(expected %i, found %i)\n",
9466                      encoder->connectors_active, active);
9467
9468                 if (!encoder->base.crtc)
9469                         continue;
9470
9471                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9472                 WARN(active && pipe != tracked_pipe,
9473                      "active encoder's pipe doesn't match"
9474                      "(expected %i, found %i)\n",
9475                      tracked_pipe, pipe);
9476
9477         }
9478 }
9479
9480 static void
9481 check_crtc_state(struct drm_device *dev)
9482 {
9483         drm_i915_private_t *dev_priv = dev->dev_private;
9484         struct intel_crtc *crtc;
9485         struct intel_encoder *encoder;
9486         struct intel_crtc_config pipe_config;
9487
9488         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9489                             base.head) {
9490                 bool enabled = false;
9491                 bool active = false;
9492
9493                 memset(&pipe_config, 0, sizeof(pipe_config));
9494
9495                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9496                               crtc->base.base.id);
9497
9498                 WARN(crtc->active && !crtc->base.enabled,
9499                      "active crtc, but not enabled in sw tracking\n");
9500
9501                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9502                                     base.head) {
9503                         if (encoder->base.crtc != &crtc->base)
9504                                 continue;
9505                         enabled = true;
9506                         if (encoder->connectors_active)
9507                                 active = true;
9508                 }
9509
9510                 WARN(active != crtc->active,
9511                      "crtc's computed active state doesn't match tracked active state "
9512                      "(expected %i, found %i)\n", active, crtc->active);
9513                 WARN(enabled != crtc->base.enabled,
9514                      "crtc's computed enabled state doesn't match tracked enabled state "
9515                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9516
9517                 active = dev_priv->display.get_pipe_config(crtc,
9518                                                            &pipe_config);
9519
9520                 /* hw state is inconsistent with the pipe A quirk */
9521                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9522                         active = crtc->active;
9523
9524                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9525                                     base.head) {
9526                         enum pipe pipe;
9527                         if (encoder->base.crtc != &crtc->base)
9528                                 continue;
9529                         if (encoder->get_hw_state(encoder, &pipe))
9530                                 encoder->get_config(encoder, &pipe_config);
9531                 }
9532
9533                 WARN(crtc->active != active,
9534                      "crtc active state doesn't match with hw state "
9535                      "(expected %i, found %i)\n", crtc->active, active);
9536
9537                 if (active &&
9538                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9539                         WARN(1, "pipe state doesn't match!\n");
9540                         intel_dump_pipe_config(crtc, &pipe_config,
9541                                                "[hw state]");
9542                         intel_dump_pipe_config(crtc, &crtc->config,
9543                                                "[sw state]");
9544                 }
9545         }
9546 }
9547
9548 static void
9549 check_shared_dpll_state(struct drm_device *dev)
9550 {
9551         drm_i915_private_t *dev_priv = dev->dev_private;
9552         struct intel_crtc *crtc;
9553         struct intel_dpll_hw_state dpll_hw_state;
9554         int i;
9555
9556         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9557                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9558                 int enabled_crtcs = 0, active_crtcs = 0;
9559                 bool active;
9560
9561                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9562
9563                 DRM_DEBUG_KMS("%s\n", pll->name);
9564
9565                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9566
9567                 WARN(pll->active > pll->refcount,
9568                      "more active pll users than references: %i vs %i\n",
9569                      pll->active, pll->refcount);
9570                 WARN(pll->active && !pll->on,
9571                      "pll in active use but not on in sw tracking\n");
9572                 WARN(pll->on && !pll->active,
9573                      "pll in on but not on in use in sw tracking\n");
9574                 WARN(pll->on != active,
9575                      "pll on state mismatch (expected %i, found %i)\n",
9576                      pll->on, active);
9577
9578                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9579                                     base.head) {
9580                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9581                                 enabled_crtcs++;
9582                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9583                                 active_crtcs++;
9584                 }
9585                 WARN(pll->active != active_crtcs,
9586                      "pll active crtcs mismatch (expected %i, found %i)\n",
9587                      pll->active, active_crtcs);
9588                 WARN(pll->refcount != enabled_crtcs,
9589                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9590                      pll->refcount, enabled_crtcs);
9591
9592                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9593                                        sizeof(dpll_hw_state)),
9594                      "pll hw state mismatch\n");
9595         }
9596 }
9597
9598 void
9599 intel_modeset_check_state(struct drm_device *dev)
9600 {
9601         check_connector_state(dev);
9602         check_encoder_state(dev);
9603         check_crtc_state(dev);
9604         check_shared_dpll_state(dev);
9605 }
9606
9607 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9608                                      int dotclock)
9609 {
9610         /*
9611          * FDI already provided one idea for the dotclock.
9612          * Yell if the encoder disagrees.
9613          */
9614         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9615              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9616              pipe_config->adjusted_mode.crtc_clock, dotclock);
9617 }
9618
9619 static int __intel_set_mode(struct drm_crtc *crtc,
9620                             struct drm_display_mode *mode,
9621                             int x, int y, struct drm_framebuffer *fb)
9622 {
9623         struct drm_device *dev = crtc->dev;
9624         drm_i915_private_t *dev_priv = dev->dev_private;
9625         struct drm_display_mode *saved_mode;
9626         struct intel_crtc_config *pipe_config = NULL;
9627         struct intel_crtc *intel_crtc;
9628         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9629         int ret = 0;
9630
9631         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9632         if (!saved_mode)
9633                 return -ENOMEM;
9634
9635         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9636                                      &prepare_pipes, &disable_pipes);
9637
9638         *saved_mode = crtc->mode;
9639
9640         /* Hack: Because we don't (yet) support global modeset on multiple
9641          * crtcs, we don't keep track of the new mode for more than one crtc.
9642          * Hence simply check whether any bit is set in modeset_pipes in all the
9643          * pieces of code that are not yet converted to deal with mutliple crtcs
9644          * changing their mode at the same time. */
9645         if (modeset_pipes) {
9646                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9647                 if (IS_ERR(pipe_config)) {
9648                         ret = PTR_ERR(pipe_config);
9649                         pipe_config = NULL;
9650
9651                         goto out;
9652                 }
9653                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9654                                        "[modeset]");
9655         }
9656
9657         /*
9658          * See if the config requires any additional preparation, e.g.
9659          * to adjust global state with pipes off.  We need to do this
9660          * here so we can get the modeset_pipe updated config for the new
9661          * mode set on this crtc.  For other crtcs we need to use the
9662          * adjusted_mode bits in the crtc directly.
9663          */
9664         if (IS_VALLEYVIEW(dev)) {
9665                 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9666                                                 modeset_pipes, pipe_config);
9667
9668                 /* may have added more to prepare_pipes than we should */
9669                 prepare_pipes &= ~disable_pipes;
9670         }
9671
9672         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9673                 intel_crtc_disable(&intel_crtc->base);
9674
9675         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9676                 if (intel_crtc->base.enabled)
9677                         dev_priv->display.crtc_disable(&intel_crtc->base);
9678         }
9679
9680         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9681          * to set it here already despite that we pass it down the callchain.
9682          */
9683         if (modeset_pipes) {
9684                 crtc->mode = *mode;
9685                 /* mode_set/enable/disable functions rely on a correct pipe
9686                  * config. */
9687                 to_intel_crtc(crtc)->config = *pipe_config;
9688
9689                 /*
9690                  * Calculate and store various constants which
9691                  * are later needed by vblank and swap-completion
9692                  * timestamping. They are derived from true hwmode.
9693                  */
9694                 drm_calc_timestamping_constants(crtc,
9695                                                 &pipe_config->adjusted_mode);
9696         }
9697
9698         /* Only after disabling all output pipelines that will be changed can we
9699          * update the the output configuration. */
9700         intel_modeset_update_state(dev, prepare_pipes);
9701
9702         if (dev_priv->display.modeset_global_resources)
9703                 dev_priv->display.modeset_global_resources(dev);
9704
9705         /* Set up the DPLL and any encoders state that needs to adjust or depend
9706          * on the DPLL.
9707          */
9708         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9709                 ret = intel_crtc_mode_set(&intel_crtc->base,
9710                                           x, y, fb);
9711                 if (ret)
9712                         goto done;
9713         }
9714
9715         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9716         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9717                 dev_priv->display.crtc_enable(&intel_crtc->base);
9718
9719         /* FIXME: add subpixel order */
9720 done:
9721         if (ret && crtc->enabled)
9722                 crtc->mode = *saved_mode;
9723
9724 out:
9725         kfree(pipe_config);
9726         kfree(saved_mode);
9727         return ret;
9728 }
9729
9730 static int intel_set_mode(struct drm_crtc *crtc,
9731                           struct drm_display_mode *mode,
9732                           int x, int y, struct drm_framebuffer *fb)
9733 {
9734         int ret;
9735
9736         ret = __intel_set_mode(crtc, mode, x, y, fb);
9737
9738         if (ret == 0)
9739                 intel_modeset_check_state(crtc->dev);
9740
9741         return ret;
9742 }
9743
9744 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9745 {
9746         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9747 }
9748
9749 #undef for_each_intel_crtc_masked
9750
9751 static void intel_set_config_free(struct intel_set_config *config)
9752 {
9753         if (!config)
9754                 return;
9755
9756         kfree(config->save_connector_encoders);
9757         kfree(config->save_encoder_crtcs);
9758         kfree(config);
9759 }
9760
9761 static int intel_set_config_save_state(struct drm_device *dev,
9762                                        struct intel_set_config *config)
9763 {
9764         struct drm_encoder *encoder;
9765         struct drm_connector *connector;
9766         int count;
9767
9768         config->save_encoder_crtcs =
9769                 kcalloc(dev->mode_config.num_encoder,
9770                         sizeof(struct drm_crtc *), GFP_KERNEL);
9771         if (!config->save_encoder_crtcs)
9772                 return -ENOMEM;
9773
9774         config->save_connector_encoders =
9775                 kcalloc(dev->mode_config.num_connector,
9776                         sizeof(struct drm_encoder *), GFP_KERNEL);
9777         if (!config->save_connector_encoders)
9778                 return -ENOMEM;
9779
9780         /* Copy data. Note that driver private data is not affected.
9781          * Should anything bad happen only the expected state is
9782          * restored, not the drivers personal bookkeeping.
9783          */
9784         count = 0;
9785         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9786                 config->save_encoder_crtcs[count++] = encoder->crtc;
9787         }
9788
9789         count = 0;
9790         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9791                 config->save_connector_encoders[count++] = connector->encoder;
9792         }
9793
9794         return 0;
9795 }
9796
9797 static void intel_set_config_restore_state(struct drm_device *dev,
9798                                            struct intel_set_config *config)
9799 {
9800         struct intel_encoder *encoder;
9801         struct intel_connector *connector;
9802         int count;
9803
9804         count = 0;
9805         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9806                 encoder->new_crtc =
9807                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9808         }
9809
9810         count = 0;
9811         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9812                 connector->new_encoder =
9813                         to_intel_encoder(config->save_connector_encoders[count++]);
9814         }
9815 }
9816
9817 static bool
9818 is_crtc_connector_off(struct drm_mode_set *set)
9819 {
9820         int i;
9821
9822         if (set->num_connectors == 0)
9823                 return false;
9824
9825         if (WARN_ON(set->connectors == NULL))
9826                 return false;
9827
9828         for (i = 0; i < set->num_connectors; i++)
9829                 if (set->connectors[i]->encoder &&
9830                     set->connectors[i]->encoder->crtc == set->crtc &&
9831                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9832                         return true;
9833
9834         return false;
9835 }
9836
9837 static void
9838 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9839                                       struct intel_set_config *config)
9840 {
9841
9842         /* We should be able to check here if the fb has the same properties
9843          * and then just flip_or_move it */
9844         if (is_crtc_connector_off(set)) {
9845                 config->mode_changed = true;
9846         } else if (set->crtc->fb != set->fb) {
9847                 /* If we have no fb then treat it as a full mode set */
9848                 if (set->crtc->fb == NULL) {
9849                         struct intel_crtc *intel_crtc =
9850                                 to_intel_crtc(set->crtc);
9851
9852                         if (intel_crtc->active && i915_fastboot) {
9853                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9854                                 config->fb_changed = true;
9855                         } else {
9856                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9857                                 config->mode_changed = true;
9858                         }
9859                 } else if (set->fb == NULL) {
9860                         config->mode_changed = true;
9861                 } else if (set->fb->pixel_format !=
9862                            set->crtc->fb->pixel_format) {
9863                         config->mode_changed = true;
9864                 } else {
9865                         config->fb_changed = true;
9866                 }
9867         }
9868
9869         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9870                 config->fb_changed = true;
9871
9872         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9873                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9874                 drm_mode_debug_printmodeline(&set->crtc->mode);
9875                 drm_mode_debug_printmodeline(set->mode);
9876                 config->mode_changed = true;
9877         }
9878
9879         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9880                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9881 }
9882
9883 static int
9884 intel_modeset_stage_output_state(struct drm_device *dev,
9885                                  struct drm_mode_set *set,
9886                                  struct intel_set_config *config)
9887 {
9888         struct drm_crtc *new_crtc;
9889         struct intel_connector *connector;
9890         struct intel_encoder *encoder;
9891         int ro;
9892
9893         /* The upper layers ensure that we either disable a crtc or have a list
9894          * of connectors. For paranoia, double-check this. */
9895         WARN_ON(!set->fb && (set->num_connectors != 0));
9896         WARN_ON(set->fb && (set->num_connectors == 0));
9897
9898         list_for_each_entry(connector, &dev->mode_config.connector_list,
9899                             base.head) {
9900                 /* Otherwise traverse passed in connector list and get encoders
9901                  * for them. */
9902                 for (ro = 0; ro < set->num_connectors; ro++) {
9903                         if (set->connectors[ro] == &connector->base) {
9904                                 connector->new_encoder = connector->encoder;
9905                                 break;
9906                         }
9907                 }
9908
9909                 /* If we disable the crtc, disable all its connectors. Also, if
9910                  * the connector is on the changing crtc but not on the new
9911                  * connector list, disable it. */
9912                 if ((!set->fb || ro == set->num_connectors) &&
9913                     connector->base.encoder &&
9914                     connector->base.encoder->crtc == set->crtc) {
9915                         connector->new_encoder = NULL;
9916
9917                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9918                                 connector->base.base.id,
9919                                 drm_get_connector_name(&connector->base));
9920                 }
9921
9922
9923                 if (&connector->new_encoder->base != connector->base.encoder) {
9924                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9925                         config->mode_changed = true;
9926                 }
9927         }
9928         /* connector->new_encoder is now updated for all connectors. */
9929
9930         /* Update crtc of enabled connectors. */
9931         list_for_each_entry(connector, &dev->mode_config.connector_list,
9932                             base.head) {
9933                 if (!connector->new_encoder)
9934                         continue;
9935
9936                 new_crtc = connector->new_encoder->base.crtc;
9937
9938                 for (ro = 0; ro < set->num_connectors; ro++) {
9939                         if (set->connectors[ro] == &connector->base)
9940                                 new_crtc = set->crtc;
9941                 }
9942
9943                 /* Make sure the new CRTC will work with the encoder */
9944                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
9945                                          new_crtc)) {
9946                         return -EINVAL;
9947                 }
9948                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9949
9950                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9951                         connector->base.base.id,
9952                         drm_get_connector_name(&connector->base),
9953                         new_crtc->base.id);
9954         }
9955
9956         /* Check for any encoders that needs to be disabled. */
9957         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9958                             base.head) {
9959                 int num_connectors = 0;
9960                 list_for_each_entry(connector,
9961                                     &dev->mode_config.connector_list,
9962                                     base.head) {
9963                         if (connector->new_encoder == encoder) {
9964                                 WARN_ON(!connector->new_encoder->new_crtc);
9965                                 num_connectors++;
9966                         }
9967                 }
9968
9969                 if (num_connectors == 0)
9970                         encoder->new_crtc = NULL;
9971                 else if (num_connectors > 1)
9972                         return -EINVAL;
9973
9974                 /* Only now check for crtc changes so we don't miss encoders
9975                  * that will be disabled. */
9976                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9977                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9978                         config->mode_changed = true;
9979                 }
9980         }
9981         /* Now we've also updated encoder->new_crtc for all encoders. */
9982
9983         return 0;
9984 }
9985
9986 static int intel_crtc_set_config(struct drm_mode_set *set)
9987 {
9988         struct drm_device *dev;
9989         struct drm_mode_set save_set;
9990         struct intel_set_config *config;
9991         int ret;
9992
9993         BUG_ON(!set);
9994         BUG_ON(!set->crtc);
9995         BUG_ON(!set->crtc->helper_private);
9996
9997         /* Enforce sane interface api - has been abused by the fb helper. */
9998         BUG_ON(!set->mode && set->fb);
9999         BUG_ON(set->fb && set->num_connectors == 0);
10000
10001         if (set->fb) {
10002                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10003                                 set->crtc->base.id, set->fb->base.id,
10004                                 (int)set->num_connectors, set->x, set->y);
10005         } else {
10006                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10007         }
10008
10009         dev = set->crtc->dev;
10010
10011         ret = -ENOMEM;
10012         config = kzalloc(sizeof(*config), GFP_KERNEL);
10013         if (!config)
10014                 goto out_config;
10015
10016         ret = intel_set_config_save_state(dev, config);
10017         if (ret)
10018                 goto out_config;
10019
10020         save_set.crtc = set->crtc;
10021         save_set.mode = &set->crtc->mode;
10022         save_set.x = set->crtc->x;
10023         save_set.y = set->crtc->y;
10024         save_set.fb = set->crtc->fb;
10025
10026         /* Compute whether we need a full modeset, only an fb base update or no
10027          * change at all. In the future we might also check whether only the
10028          * mode changed, e.g. for LVDS where we only change the panel fitter in
10029          * such cases. */
10030         intel_set_config_compute_mode_changes(set, config);
10031
10032         ret = intel_modeset_stage_output_state(dev, set, config);
10033         if (ret)
10034                 goto fail;
10035
10036         if (config->mode_changed) {
10037                 ret = intel_set_mode(set->crtc, set->mode,
10038                                      set->x, set->y, set->fb);
10039         } else if (config->fb_changed) {
10040                 intel_crtc_wait_for_pending_flips(set->crtc);
10041
10042                 ret = intel_pipe_set_base(set->crtc,
10043                                           set->x, set->y, set->fb);
10044                 /*
10045                  * In the fastboot case this may be our only check of the
10046                  * state after boot.  It would be better to only do it on
10047                  * the first update, but we don't have a nice way of doing that
10048                  * (and really, set_config isn't used much for high freq page
10049                  * flipping, so increasing its cost here shouldn't be a big
10050                  * deal).
10051                  */
10052                 if (i915_fastboot && ret == 0)
10053                         intel_modeset_check_state(set->crtc->dev);
10054         }
10055
10056         if (ret) {
10057                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10058                               set->crtc->base.id, ret);
10059 fail:
10060                 intel_set_config_restore_state(dev, config);
10061
10062                 /* Try to restore the config */
10063                 if (config->mode_changed &&
10064                     intel_set_mode(save_set.crtc, save_set.mode,
10065                                    save_set.x, save_set.y, save_set.fb))
10066                         DRM_ERROR("failed to restore config after modeset failure\n");
10067         }
10068
10069 out_config:
10070         intel_set_config_free(config);
10071         return ret;
10072 }
10073
10074 static const struct drm_crtc_funcs intel_crtc_funcs = {
10075         .cursor_set = intel_crtc_cursor_set,
10076         .cursor_move = intel_crtc_cursor_move,
10077         .gamma_set = intel_crtc_gamma_set,
10078         .set_config = intel_crtc_set_config,
10079         .destroy = intel_crtc_destroy,
10080         .page_flip = intel_crtc_page_flip,
10081 };
10082
10083 static void intel_cpu_pll_init(struct drm_device *dev)
10084 {
10085         if (HAS_DDI(dev))
10086                 intel_ddi_pll_init(dev);
10087 }
10088
10089 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10090                                       struct intel_shared_dpll *pll,
10091                                       struct intel_dpll_hw_state *hw_state)
10092 {
10093         uint32_t val;
10094
10095         val = I915_READ(PCH_DPLL(pll->id));
10096         hw_state->dpll = val;
10097         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10098         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10099
10100         return val & DPLL_VCO_ENABLE;
10101 }
10102
10103 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10104                                   struct intel_shared_dpll *pll)
10105 {
10106         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10107         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10108 }
10109
10110 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10111                                 struct intel_shared_dpll *pll)
10112 {
10113         /* PCH refclock must be enabled first */
10114         ibx_assert_pch_refclk_enabled(dev_priv);
10115
10116         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10117
10118         /* Wait for the clocks to stabilize. */
10119         POSTING_READ(PCH_DPLL(pll->id));
10120         udelay(150);
10121
10122         /* The pixel multiplier can only be updated once the
10123          * DPLL is enabled and the clocks are stable.
10124          *
10125          * So write it again.
10126          */
10127         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10128         POSTING_READ(PCH_DPLL(pll->id));
10129         udelay(200);
10130 }
10131
10132 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10133                                  struct intel_shared_dpll *pll)
10134 {
10135         struct drm_device *dev = dev_priv->dev;
10136         struct intel_crtc *crtc;
10137
10138         /* Make sure no transcoder isn't still depending on us. */
10139         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10140                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10141                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10142         }
10143
10144         I915_WRITE(PCH_DPLL(pll->id), 0);
10145         POSTING_READ(PCH_DPLL(pll->id));
10146         udelay(200);
10147 }
10148
10149 static char *ibx_pch_dpll_names[] = {
10150         "PCH DPLL A",
10151         "PCH DPLL B",
10152 };
10153
10154 static void ibx_pch_dpll_init(struct drm_device *dev)
10155 {
10156         struct drm_i915_private *dev_priv = dev->dev_private;
10157         int i;
10158
10159         dev_priv->num_shared_dpll = 2;
10160
10161         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10162                 dev_priv->shared_dplls[i].id = i;
10163                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10164                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10165                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10166                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10167                 dev_priv->shared_dplls[i].get_hw_state =
10168                         ibx_pch_dpll_get_hw_state;
10169         }
10170 }
10171
10172 static void intel_shared_dpll_init(struct drm_device *dev)
10173 {
10174         struct drm_i915_private *dev_priv = dev->dev_private;
10175
10176         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10177                 ibx_pch_dpll_init(dev);
10178         else
10179                 dev_priv->num_shared_dpll = 0;
10180
10181         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10182 }
10183
10184 static void intel_crtc_init(struct drm_device *dev, int pipe)
10185 {
10186         drm_i915_private_t *dev_priv = dev->dev_private;
10187         struct intel_crtc *intel_crtc;
10188         int i;
10189
10190         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10191         if (intel_crtc == NULL)
10192                 return;
10193
10194         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10195
10196         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10197         for (i = 0; i < 256; i++) {
10198                 intel_crtc->lut_r[i] = i;
10199                 intel_crtc->lut_g[i] = i;
10200                 intel_crtc->lut_b[i] = i;
10201         }
10202
10203         /*
10204          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10205          * is hooked to plane B. Hence we want plane A feeding pipe B.
10206          */
10207         intel_crtc->pipe = pipe;
10208         intel_crtc->plane = pipe;
10209         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10210                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10211                 intel_crtc->plane = !pipe;
10212         }
10213
10214         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10215                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10216         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10217         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10218
10219         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10220 }
10221
10222 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10223 {
10224         struct drm_encoder *encoder = connector->base.encoder;
10225
10226         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10227
10228         if (!encoder)
10229                 return INVALID_PIPE;
10230
10231         return to_intel_crtc(encoder->crtc)->pipe;
10232 }
10233
10234 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10235                                 struct drm_file *file)
10236 {
10237         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10238         struct drm_mode_object *drmmode_obj;
10239         struct intel_crtc *crtc;
10240
10241         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10242                 return -ENODEV;
10243
10244         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10245                         DRM_MODE_OBJECT_CRTC);
10246
10247         if (!drmmode_obj) {
10248                 DRM_ERROR("no such CRTC id\n");
10249                 return -ENOENT;
10250         }
10251
10252         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10253         pipe_from_crtc_id->pipe = crtc->pipe;
10254
10255         return 0;
10256 }
10257
10258 static int intel_encoder_clones(struct intel_encoder *encoder)
10259 {
10260         struct drm_device *dev = encoder->base.dev;
10261         struct intel_encoder *source_encoder;
10262         int index_mask = 0;
10263         int entry = 0;
10264
10265         list_for_each_entry(source_encoder,
10266                             &dev->mode_config.encoder_list, base.head) {
10267
10268                 if (encoder == source_encoder)
10269                         index_mask |= (1 << entry);
10270
10271                 /* Intel hw has only one MUX where enocoders could be cloned. */
10272                 if (encoder->cloneable && source_encoder->cloneable)
10273                         index_mask |= (1 << entry);
10274
10275                 entry++;
10276         }
10277
10278         return index_mask;
10279 }
10280
10281 static bool has_edp_a(struct drm_device *dev)
10282 {
10283         struct drm_i915_private *dev_priv = dev->dev_private;
10284
10285         if (!IS_MOBILE(dev))
10286                 return false;
10287
10288         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10289                 return false;
10290
10291         if (IS_GEN5(dev) &&
10292             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10293                 return false;
10294
10295         return true;
10296 }
10297
10298 const char *intel_output_name(int output)
10299 {
10300         static const char *names[] = {
10301                 [INTEL_OUTPUT_UNUSED] = "Unused",
10302                 [INTEL_OUTPUT_ANALOG] = "Analog",
10303                 [INTEL_OUTPUT_DVO] = "DVO",
10304                 [INTEL_OUTPUT_SDVO] = "SDVO",
10305                 [INTEL_OUTPUT_LVDS] = "LVDS",
10306                 [INTEL_OUTPUT_TVOUT] = "TV",
10307                 [INTEL_OUTPUT_HDMI] = "HDMI",
10308                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10309                 [INTEL_OUTPUT_EDP] = "eDP",
10310                 [INTEL_OUTPUT_DSI] = "DSI",
10311                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10312         };
10313
10314         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10315                 return "Invalid";
10316
10317         return names[output];
10318 }
10319
10320 static void intel_setup_outputs(struct drm_device *dev)
10321 {
10322         struct drm_i915_private *dev_priv = dev->dev_private;
10323         struct intel_encoder *encoder;
10324         bool dpd_is_edp = false;
10325
10326         intel_lvds_init(dev);
10327
10328         if (!IS_ULT(dev))
10329                 intel_crt_init(dev);
10330
10331         if (HAS_DDI(dev)) {
10332                 int found;
10333
10334                 /* Haswell uses DDI functions to detect digital outputs */
10335                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10336                 /* DDI A only supports eDP */
10337                 if (found)
10338                         intel_ddi_init(dev, PORT_A);
10339
10340                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10341                  * register */
10342                 found = I915_READ(SFUSE_STRAP);
10343
10344                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10345                         intel_ddi_init(dev, PORT_B);
10346                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10347                         intel_ddi_init(dev, PORT_C);
10348                 if (found & SFUSE_STRAP_DDID_DETECTED)
10349                         intel_ddi_init(dev, PORT_D);
10350         } else if (HAS_PCH_SPLIT(dev)) {
10351                 int found;
10352                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10353
10354                 if (has_edp_a(dev))
10355                         intel_dp_init(dev, DP_A, PORT_A);
10356
10357                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10358                         /* PCH SDVOB multiplex with HDMIB */
10359                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10360                         if (!found)
10361                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10362                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10363                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10364                 }
10365
10366                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10367                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10368
10369                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10370                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10371
10372                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10373                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10374
10375                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10376                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10377         } else if (IS_VALLEYVIEW(dev)) {
10378                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10379                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10380                                         PORT_B);
10381                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10382                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10383                 }
10384
10385                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10386                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10387                                         PORT_C);
10388                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10389                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10390                 }
10391
10392                 intel_dsi_init(dev);
10393         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10394                 bool found = false;
10395
10396                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10397                         DRM_DEBUG_KMS("probing SDVOB\n");
10398                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10399                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10400                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10401                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10402                         }
10403
10404                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10405                                 intel_dp_init(dev, DP_B, PORT_B);
10406                 }
10407
10408                 /* Before G4X SDVOC doesn't have its own detect register */
10409
10410                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10411                         DRM_DEBUG_KMS("probing SDVOC\n");
10412                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10413                 }
10414
10415                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10416
10417                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10418                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10419                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10420                         }
10421                         if (SUPPORTS_INTEGRATED_DP(dev))
10422                                 intel_dp_init(dev, DP_C, PORT_C);
10423                 }
10424
10425                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10426                     (I915_READ(DP_D) & DP_DETECTED))
10427                         intel_dp_init(dev, DP_D, PORT_D);
10428         } else if (IS_GEN2(dev))
10429                 intel_dvo_init(dev);
10430
10431         if (SUPPORTS_TV(dev))
10432                 intel_tv_init(dev);
10433
10434         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10435                 encoder->base.possible_crtcs = encoder->crtc_mask;
10436                 encoder->base.possible_clones =
10437                         intel_encoder_clones(encoder);
10438         }
10439
10440         intel_init_pch_refclk(dev);
10441
10442         drm_helper_move_panel_connectors_to_head(dev);
10443 }
10444
10445 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10446 {
10447         drm_framebuffer_cleanup(&fb->base);
10448         WARN_ON(!fb->obj->framebuffer_references--);
10449         drm_gem_object_unreference_unlocked(&fb->obj->base);
10450 }
10451
10452 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10453 {
10454         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10455
10456         intel_framebuffer_fini(intel_fb);
10457         kfree(intel_fb);
10458 }
10459
10460 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10461                                                 struct drm_file *file,
10462                                                 unsigned int *handle)
10463 {
10464         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10465         struct drm_i915_gem_object *obj = intel_fb->obj;
10466
10467         return drm_gem_handle_create(file, &obj->base, handle);
10468 }
10469
10470 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10471         .destroy = intel_user_framebuffer_destroy,
10472         .create_handle = intel_user_framebuffer_create_handle,
10473 };
10474
10475 int intel_framebuffer_init(struct drm_device *dev,
10476                            struct intel_framebuffer *intel_fb,
10477                            struct drm_mode_fb_cmd2 *mode_cmd,
10478                            struct drm_i915_gem_object *obj)
10479 {
10480         int aligned_height, tile_height;
10481         int pitch_limit;
10482         int ret;
10483
10484         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10485
10486         if (obj->tiling_mode == I915_TILING_Y) {
10487                 DRM_DEBUG("hardware does not support tiling Y\n");
10488                 return -EINVAL;
10489         }
10490
10491         if (mode_cmd->pitches[0] & 63) {
10492                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10493                           mode_cmd->pitches[0]);
10494                 return -EINVAL;
10495         }
10496
10497         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10498                 pitch_limit = 32*1024;
10499         } else if (INTEL_INFO(dev)->gen >= 4) {
10500                 if (obj->tiling_mode)
10501                         pitch_limit = 16*1024;
10502                 else
10503                         pitch_limit = 32*1024;
10504         } else if (INTEL_INFO(dev)->gen >= 3) {
10505                 if (obj->tiling_mode)
10506                         pitch_limit = 8*1024;
10507                 else
10508                         pitch_limit = 16*1024;
10509         } else
10510                 /* XXX DSPC is limited to 4k tiled */
10511                 pitch_limit = 8*1024;
10512
10513         if (mode_cmd->pitches[0] > pitch_limit) {
10514                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10515                           obj->tiling_mode ? "tiled" : "linear",
10516                           mode_cmd->pitches[0], pitch_limit);
10517                 return -EINVAL;
10518         }
10519
10520         if (obj->tiling_mode != I915_TILING_NONE &&
10521             mode_cmd->pitches[0] != obj->stride) {
10522                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10523                           mode_cmd->pitches[0], obj->stride);
10524                 return -EINVAL;
10525         }
10526
10527         /* Reject formats not supported by any plane early. */
10528         switch (mode_cmd->pixel_format) {
10529         case DRM_FORMAT_C8:
10530         case DRM_FORMAT_RGB565:
10531         case DRM_FORMAT_XRGB8888:
10532         case DRM_FORMAT_ARGB8888:
10533                 break;
10534         case DRM_FORMAT_XRGB1555:
10535         case DRM_FORMAT_ARGB1555:
10536                 if (INTEL_INFO(dev)->gen > 3) {
10537                         DRM_DEBUG("unsupported pixel format: %s\n",
10538                                   drm_get_format_name(mode_cmd->pixel_format));
10539                         return -EINVAL;
10540                 }
10541                 break;
10542         case DRM_FORMAT_XBGR8888:
10543         case DRM_FORMAT_ABGR8888:
10544         case DRM_FORMAT_XRGB2101010:
10545         case DRM_FORMAT_ARGB2101010:
10546         case DRM_FORMAT_XBGR2101010:
10547         case DRM_FORMAT_ABGR2101010:
10548                 if (INTEL_INFO(dev)->gen < 4) {
10549                         DRM_DEBUG("unsupported pixel format: %s\n",
10550                                   drm_get_format_name(mode_cmd->pixel_format));
10551                         return -EINVAL;
10552                 }
10553                 break;
10554         case DRM_FORMAT_YUYV:
10555         case DRM_FORMAT_UYVY:
10556         case DRM_FORMAT_YVYU:
10557         case DRM_FORMAT_VYUY:
10558                 if (INTEL_INFO(dev)->gen < 5) {
10559                         DRM_DEBUG("unsupported pixel format: %s\n",
10560                                   drm_get_format_name(mode_cmd->pixel_format));
10561                         return -EINVAL;
10562                 }
10563                 break;
10564         default:
10565                 DRM_DEBUG("unsupported pixel format: %s\n",
10566                           drm_get_format_name(mode_cmd->pixel_format));
10567                 return -EINVAL;
10568         }
10569
10570         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10571         if (mode_cmd->offsets[0] != 0)
10572                 return -EINVAL;
10573
10574         tile_height = IS_GEN2(dev) ? 16 : 8;
10575         aligned_height = ALIGN(mode_cmd->height,
10576                                obj->tiling_mode ? tile_height : 1);
10577         /* FIXME drm helper for size checks (especially planar formats)? */
10578         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10579                 return -EINVAL;
10580
10581         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10582         intel_fb->obj = obj;
10583         intel_fb->obj->framebuffer_references++;
10584
10585         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10586         if (ret) {
10587                 DRM_ERROR("framebuffer init failed %d\n", ret);
10588                 return ret;
10589         }
10590
10591         return 0;
10592 }
10593
10594 static struct drm_framebuffer *
10595 intel_user_framebuffer_create(struct drm_device *dev,
10596                               struct drm_file *filp,
10597                               struct drm_mode_fb_cmd2 *mode_cmd)
10598 {
10599         struct drm_i915_gem_object *obj;
10600
10601         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10602                                                 mode_cmd->handles[0]));
10603         if (&obj->base == NULL)
10604                 return ERR_PTR(-ENOENT);
10605
10606         return intel_framebuffer_create(dev, mode_cmd, obj);
10607 }
10608
10609 #ifndef CONFIG_DRM_I915_FBDEV
10610 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10611 {
10612 }
10613 #endif
10614
10615 static const struct drm_mode_config_funcs intel_mode_funcs = {
10616         .fb_create = intel_user_framebuffer_create,
10617         .output_poll_changed = intel_fbdev_output_poll_changed,
10618 };
10619
10620 /* Set up chip specific display functions */
10621 static void intel_init_display(struct drm_device *dev)
10622 {
10623         struct drm_i915_private *dev_priv = dev->dev_private;
10624
10625         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10626                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10627         else if (IS_VALLEYVIEW(dev))
10628                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10629         else if (IS_PINEVIEW(dev))
10630                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10631         else
10632                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10633
10634         if (HAS_DDI(dev)) {
10635                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10636                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10637                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10638                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10639                 dev_priv->display.off = haswell_crtc_off;
10640                 dev_priv->display.update_plane = ironlake_update_plane;
10641         } else if (HAS_PCH_SPLIT(dev)) {
10642                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10643                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10644                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10645                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10646                 dev_priv->display.off = ironlake_crtc_off;
10647                 dev_priv->display.update_plane = ironlake_update_plane;
10648         } else if (IS_VALLEYVIEW(dev)) {
10649                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10650                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10651                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10652                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10653                 dev_priv->display.off = i9xx_crtc_off;
10654                 dev_priv->display.update_plane = i9xx_update_plane;
10655         } else {
10656                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10657                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10658                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10659                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10660                 dev_priv->display.off = i9xx_crtc_off;
10661                 dev_priv->display.update_plane = i9xx_update_plane;
10662         }
10663
10664         /* Returns the core display clock speed */
10665         if (IS_VALLEYVIEW(dev))
10666                 dev_priv->display.get_display_clock_speed =
10667                         valleyview_get_display_clock_speed;
10668         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10669                 dev_priv->display.get_display_clock_speed =
10670                         i945_get_display_clock_speed;
10671         else if (IS_I915G(dev))
10672                 dev_priv->display.get_display_clock_speed =
10673                         i915_get_display_clock_speed;
10674         else if (IS_I945GM(dev) || IS_845G(dev))
10675                 dev_priv->display.get_display_clock_speed =
10676                         i9xx_misc_get_display_clock_speed;
10677         else if (IS_PINEVIEW(dev))
10678                 dev_priv->display.get_display_clock_speed =
10679                         pnv_get_display_clock_speed;
10680         else if (IS_I915GM(dev))
10681                 dev_priv->display.get_display_clock_speed =
10682                         i915gm_get_display_clock_speed;
10683         else if (IS_I865G(dev))
10684                 dev_priv->display.get_display_clock_speed =
10685                         i865_get_display_clock_speed;
10686         else if (IS_I85X(dev))
10687                 dev_priv->display.get_display_clock_speed =
10688                         i855_get_display_clock_speed;
10689         else /* 852, 830 */
10690                 dev_priv->display.get_display_clock_speed =
10691                         i830_get_display_clock_speed;
10692
10693         if (HAS_PCH_SPLIT(dev)) {
10694                 if (IS_GEN5(dev)) {
10695                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10696                         dev_priv->display.write_eld = ironlake_write_eld;
10697                 } else if (IS_GEN6(dev)) {
10698                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10699                         dev_priv->display.write_eld = ironlake_write_eld;
10700                 } else if (IS_IVYBRIDGE(dev)) {
10701                         /* FIXME: detect B0+ stepping and use auto training */
10702                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10703                         dev_priv->display.write_eld = ironlake_write_eld;
10704                         dev_priv->display.modeset_global_resources =
10705                                 ivb_modeset_global_resources;
10706                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10707                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10708                         dev_priv->display.write_eld = haswell_write_eld;
10709                         dev_priv->display.modeset_global_resources =
10710                                 haswell_modeset_global_resources;
10711                 }
10712         } else if (IS_G4X(dev)) {
10713                 dev_priv->display.write_eld = g4x_write_eld;
10714         } else if (IS_VALLEYVIEW(dev)) {
10715                 dev_priv->display.modeset_global_resources =
10716                         valleyview_modeset_global_resources;
10717                 dev_priv->display.write_eld = ironlake_write_eld;
10718         }
10719
10720         /* Default just returns -ENODEV to indicate unsupported */
10721         dev_priv->display.queue_flip = intel_default_queue_flip;
10722
10723         switch (INTEL_INFO(dev)->gen) {
10724         case 2:
10725                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10726                 break;
10727
10728         case 3:
10729                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10730                 break;
10731
10732         case 4:
10733         case 5:
10734                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10735                 break;
10736
10737         case 6:
10738                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10739                 break;
10740         case 7:
10741         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10742                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10743                 break;
10744         }
10745
10746         intel_panel_init_backlight_funcs(dev);
10747 }
10748
10749 /*
10750  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10751  * resume, or other times.  This quirk makes sure that's the case for
10752  * affected systems.
10753  */
10754 static void quirk_pipea_force(struct drm_device *dev)
10755 {
10756         struct drm_i915_private *dev_priv = dev->dev_private;
10757
10758         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10759         DRM_INFO("applying pipe a force quirk\n");
10760 }
10761
10762 /*
10763  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10764  */
10765 static void quirk_ssc_force_disable(struct drm_device *dev)
10766 {
10767         struct drm_i915_private *dev_priv = dev->dev_private;
10768         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10769         DRM_INFO("applying lvds SSC disable quirk\n");
10770 }
10771
10772 /*
10773  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10774  * brightness value
10775  */
10776 static void quirk_invert_brightness(struct drm_device *dev)
10777 {
10778         struct drm_i915_private *dev_priv = dev->dev_private;
10779         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10780         DRM_INFO("applying inverted panel brightness quirk\n");
10781 }
10782
10783 /*
10784  * Some machines (Dell XPS13) suffer broken backlight controls if
10785  * BLM_PCH_PWM_ENABLE is set.
10786  */
10787 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10788 {
10789         struct drm_i915_private *dev_priv = dev->dev_private;
10790         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10791         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10792 }
10793
10794 struct intel_quirk {
10795         int device;
10796         int subsystem_vendor;
10797         int subsystem_device;
10798         void (*hook)(struct drm_device *dev);
10799 };
10800
10801 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10802 struct intel_dmi_quirk {
10803         void (*hook)(struct drm_device *dev);
10804         const struct dmi_system_id (*dmi_id_list)[];
10805 };
10806
10807 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10808 {
10809         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10810         return 1;
10811 }
10812
10813 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10814         {
10815                 .dmi_id_list = &(const struct dmi_system_id[]) {
10816                         {
10817                                 .callback = intel_dmi_reverse_brightness,
10818                                 .ident = "NCR Corporation",
10819                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10820                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10821                                 },
10822                         },
10823                         { }  /* terminating entry */
10824                 },
10825                 .hook = quirk_invert_brightness,
10826         },
10827 };
10828
10829 static struct intel_quirk intel_quirks[] = {
10830         /* HP Mini needs pipe A force quirk (LP: #322104) */
10831         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10832
10833         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10834         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10835
10836         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10837         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10838
10839         /* 830 needs to leave pipe A & dpll A up */
10840         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10841
10842         /* Lenovo U160 cannot use SSC on LVDS */
10843         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10844
10845         /* Sony Vaio Y cannot use SSC on LVDS */
10846         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10847
10848         /* Acer Aspire 5734Z must invert backlight brightness */
10849         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10850
10851         /* Acer/eMachines G725 */
10852         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10853
10854         /* Acer/eMachines e725 */
10855         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10856
10857         /* Acer/Packard Bell NCL20 */
10858         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10859
10860         /* Acer Aspire 4736Z */
10861         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10862
10863         /* Acer Aspire 5336 */
10864         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
10865
10866         /* Dell XPS13 HD Sandy Bridge */
10867         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10868         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10869         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10870 };
10871
10872 static void intel_init_quirks(struct drm_device *dev)
10873 {
10874         struct pci_dev *d = dev->pdev;
10875         int i;
10876
10877         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10878                 struct intel_quirk *q = &intel_quirks[i];
10879
10880                 if (d->device == q->device &&
10881                     (d->subsystem_vendor == q->subsystem_vendor ||
10882                      q->subsystem_vendor == PCI_ANY_ID) &&
10883                     (d->subsystem_device == q->subsystem_device ||
10884                      q->subsystem_device == PCI_ANY_ID))
10885                         q->hook(dev);
10886         }
10887         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10888                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10889                         intel_dmi_quirks[i].hook(dev);
10890         }
10891 }
10892
10893 /* Disable the VGA plane that we never use */
10894 static void i915_disable_vga(struct drm_device *dev)
10895 {
10896         struct drm_i915_private *dev_priv = dev->dev_private;
10897         u8 sr1;
10898         u32 vga_reg = i915_vgacntrl_reg(dev);
10899
10900         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10901         outb(SR01, VGA_SR_INDEX);
10902         sr1 = inb(VGA_SR_DATA);
10903         outb(sr1 | 1<<5, VGA_SR_DATA);
10904         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10905         udelay(300);
10906
10907         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10908         POSTING_READ(vga_reg);
10909 }
10910
10911 void intel_modeset_init_hw(struct drm_device *dev)
10912 {
10913         intel_prepare_ddi(dev);
10914
10915         intel_init_clock_gating(dev);
10916
10917         intel_reset_dpio(dev);
10918
10919         mutex_lock(&dev->struct_mutex);
10920         intel_enable_gt_powersave(dev);
10921         mutex_unlock(&dev->struct_mutex);
10922 }
10923
10924 void intel_modeset_suspend_hw(struct drm_device *dev)
10925 {
10926         intel_suspend_hw(dev);
10927 }
10928
10929 void intel_modeset_init(struct drm_device *dev)
10930 {
10931         struct drm_i915_private *dev_priv = dev->dev_private;
10932         int i, j, ret;
10933
10934         drm_mode_config_init(dev);
10935
10936         dev->mode_config.min_width = 0;
10937         dev->mode_config.min_height = 0;
10938
10939         dev->mode_config.preferred_depth = 24;
10940         dev->mode_config.prefer_shadow = 1;
10941
10942         dev->mode_config.funcs = &intel_mode_funcs;
10943
10944         intel_init_quirks(dev);
10945
10946         intel_init_pm(dev);
10947
10948         if (INTEL_INFO(dev)->num_pipes == 0)
10949                 return;
10950
10951         intel_init_display(dev);
10952
10953         if (IS_GEN2(dev)) {
10954                 dev->mode_config.max_width = 2048;
10955                 dev->mode_config.max_height = 2048;
10956         } else if (IS_GEN3(dev)) {
10957                 dev->mode_config.max_width = 4096;
10958                 dev->mode_config.max_height = 4096;
10959         } else {
10960                 dev->mode_config.max_width = 8192;
10961                 dev->mode_config.max_height = 8192;
10962         }
10963         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10964
10965         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10966                       INTEL_INFO(dev)->num_pipes,
10967                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10968
10969         for_each_pipe(i) {
10970                 intel_crtc_init(dev, i);
10971                 for (j = 0; j < dev_priv->num_plane; j++) {
10972                         ret = intel_plane_init(dev, i, j);
10973                         if (ret)
10974                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10975                                               pipe_name(i), sprite_name(i, j), ret);
10976                 }
10977         }
10978
10979         intel_init_dpio(dev);
10980         intel_reset_dpio(dev);
10981
10982         intel_cpu_pll_init(dev);
10983         intel_shared_dpll_init(dev);
10984
10985         /* Just disable it once at startup */
10986         i915_disable_vga(dev);
10987         intel_setup_outputs(dev);
10988
10989         /* Just in case the BIOS is doing something questionable. */
10990         intel_disable_fbc(dev);
10991 }
10992
10993 static void intel_enable_pipe_a(struct drm_device *dev)
10994 {
10995         struct intel_connector *connector;
10996         struct drm_connector *crt = NULL;
10997         struct intel_load_detect_pipe load_detect_temp;
10998
10999         /* We can't just switch on the pipe A, we need to set things up with a
11000          * proper mode and output configuration. As a gross hack, enable pipe A
11001          * by enabling the load detect pipe once. */
11002         list_for_each_entry(connector,
11003                             &dev->mode_config.connector_list,
11004                             base.head) {
11005                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11006                         crt = &connector->base;
11007                         break;
11008                 }
11009         }
11010
11011         if (!crt)
11012                 return;
11013
11014         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11015                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11016
11017
11018 }
11019
11020 static bool
11021 intel_check_plane_mapping(struct intel_crtc *crtc)
11022 {
11023         struct drm_device *dev = crtc->base.dev;
11024         struct drm_i915_private *dev_priv = dev->dev_private;
11025         u32 reg, val;
11026
11027         if (INTEL_INFO(dev)->num_pipes == 1)
11028                 return true;
11029
11030         reg = DSPCNTR(!crtc->plane);
11031         val = I915_READ(reg);
11032
11033         if ((val & DISPLAY_PLANE_ENABLE) &&
11034             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11035                 return false;
11036
11037         return true;
11038 }
11039
11040 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11041 {
11042         struct drm_device *dev = crtc->base.dev;
11043         struct drm_i915_private *dev_priv = dev->dev_private;
11044         u32 reg;
11045
11046         /* Clear any frame start delays used for debugging left by the BIOS */
11047         reg = PIPECONF(crtc->config.cpu_transcoder);
11048         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11049
11050         /* We need to sanitize the plane -> pipe mapping first because this will
11051          * disable the crtc (and hence change the state) if it is wrong. Note
11052          * that gen4+ has a fixed plane -> pipe mapping.  */
11053         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11054                 struct intel_connector *connector;
11055                 bool plane;
11056
11057                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11058                               crtc->base.base.id);
11059
11060                 /* Pipe has the wrong plane attached and the plane is active.
11061                  * Temporarily change the plane mapping and disable everything
11062                  * ...  */
11063                 plane = crtc->plane;
11064                 crtc->plane = !plane;
11065                 dev_priv->display.crtc_disable(&crtc->base);
11066                 crtc->plane = plane;
11067
11068                 /* ... and break all links. */
11069                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11070                                     base.head) {
11071                         if (connector->encoder->base.crtc != &crtc->base)
11072                                 continue;
11073
11074                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11075                         connector->base.encoder = NULL;
11076                 }
11077                 /* multiple connectors may have the same encoder:
11078                  *  handle them and break crtc link separately */
11079                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11080                                     base.head)
11081                         if (connector->encoder->base.crtc == &crtc->base) {
11082                                 connector->encoder->base.crtc = NULL;
11083                                 connector->encoder->connectors_active = false;
11084                         }
11085
11086                 WARN_ON(crtc->active);
11087                 crtc->base.enabled = false;
11088         }
11089
11090         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11091             crtc->pipe == PIPE_A && !crtc->active) {
11092                 /* BIOS forgot to enable pipe A, this mostly happens after
11093                  * resume. Force-enable the pipe to fix this, the update_dpms
11094                  * call below we restore the pipe to the right state, but leave
11095                  * the required bits on. */
11096                 intel_enable_pipe_a(dev);
11097         }
11098
11099         /* Adjust the state of the output pipe according to whether we
11100          * have active connectors/encoders. */
11101         intel_crtc_update_dpms(&crtc->base);
11102
11103         if (crtc->active != crtc->base.enabled) {
11104                 struct intel_encoder *encoder;
11105
11106                 /* This can happen either due to bugs in the get_hw_state
11107                  * functions or because the pipe is force-enabled due to the
11108                  * pipe A quirk. */
11109                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11110                               crtc->base.base.id,
11111                               crtc->base.enabled ? "enabled" : "disabled",
11112                               crtc->active ? "enabled" : "disabled");
11113
11114                 crtc->base.enabled = crtc->active;
11115
11116                 /* Because we only establish the connector -> encoder ->
11117                  * crtc links if something is active, this means the
11118                  * crtc is now deactivated. Break the links. connector
11119                  * -> encoder links are only establish when things are
11120                  *  actually up, hence no need to break them. */
11121                 WARN_ON(crtc->active);
11122
11123                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11124                         WARN_ON(encoder->connectors_active);
11125                         encoder->base.crtc = NULL;
11126                 }
11127         }
11128 }
11129
11130 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11131 {
11132         struct intel_connector *connector;
11133         struct drm_device *dev = encoder->base.dev;
11134
11135         /* We need to check both for a crtc link (meaning that the
11136          * encoder is active and trying to read from a pipe) and the
11137          * pipe itself being active. */
11138         bool has_active_crtc = encoder->base.crtc &&
11139                 to_intel_crtc(encoder->base.crtc)->active;
11140
11141         if (encoder->connectors_active && !has_active_crtc) {
11142                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11143                               encoder->base.base.id,
11144                               drm_get_encoder_name(&encoder->base));
11145
11146                 /* Connector is active, but has no active pipe. This is
11147                  * fallout from our resume register restoring. Disable
11148                  * the encoder manually again. */
11149                 if (encoder->base.crtc) {
11150                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11151                                       encoder->base.base.id,
11152                                       drm_get_encoder_name(&encoder->base));
11153                         encoder->disable(encoder);
11154                 }
11155                 encoder->base.crtc = NULL;
11156                 encoder->connectors_active = false;
11157
11158                 /* Inconsistent output/port/pipe state happens presumably due to
11159                  * a bug in one of the get_hw_state functions. Or someplace else
11160                  * in our code, like the register restore mess on resume. Clamp
11161                  * things to off as a safer default. */
11162                 list_for_each_entry(connector,
11163                                     &dev->mode_config.connector_list,
11164                                     base.head) {
11165                         if (connector->encoder != encoder)
11166                                 continue;
11167                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11168                         connector->base.encoder = NULL;
11169                 }
11170         }
11171         /* Enabled encoders without active connectors will be fixed in
11172          * the crtc fixup. */
11173 }
11174
11175 void i915_redisable_vga(struct drm_device *dev)
11176 {
11177         struct drm_i915_private *dev_priv = dev->dev_private;
11178         u32 vga_reg = i915_vgacntrl_reg(dev);
11179
11180         /* This function can be called both from intel_modeset_setup_hw_state or
11181          * at a very early point in our resume sequence, where the power well
11182          * structures are not yet restored. Since this function is at a very
11183          * paranoid "someone might have enabled VGA while we were not looking"
11184          * level, just check if the power well is enabled instead of trying to
11185          * follow the "don't touch the power well if we don't need it" policy
11186          * the rest of the driver uses. */
11187         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11188             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11189                 return;
11190
11191         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11192                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11193                 i915_disable_vga(dev);
11194         }
11195 }
11196
11197 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11198 {
11199         struct drm_i915_private *dev_priv = dev->dev_private;
11200         enum pipe pipe;
11201         struct intel_crtc *crtc;
11202         struct intel_encoder *encoder;
11203         struct intel_connector *connector;
11204         int i;
11205
11206         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11207                             base.head) {
11208                 memset(&crtc->config, 0, sizeof(crtc->config));
11209
11210                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11211
11212                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11213                                                                  &crtc->config);
11214
11215                 crtc->base.enabled = crtc->active;
11216                 crtc->primary_enabled = crtc->active;
11217
11218                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11219                               crtc->base.base.id,
11220                               crtc->active ? "enabled" : "disabled");
11221         }
11222
11223         /* FIXME: Smash this into the new shared dpll infrastructure. */
11224         if (HAS_DDI(dev))
11225                 intel_ddi_setup_hw_pll_state(dev);
11226
11227         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11228                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11229
11230                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11231                 pll->active = 0;
11232                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11233                                     base.head) {
11234                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11235                                 pll->active++;
11236                 }
11237                 pll->refcount = pll->active;
11238
11239                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11240                               pll->name, pll->refcount, pll->on);
11241         }
11242
11243         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11244                             base.head) {
11245                 pipe = 0;
11246
11247                 if (encoder->get_hw_state(encoder, &pipe)) {
11248                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11249                         encoder->base.crtc = &crtc->base;
11250                         encoder->get_config(encoder, &crtc->config);
11251                 } else {
11252                         encoder->base.crtc = NULL;
11253                 }
11254
11255                 encoder->connectors_active = false;
11256                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11257                               encoder->base.base.id,
11258                               drm_get_encoder_name(&encoder->base),
11259                               encoder->base.crtc ? "enabled" : "disabled",
11260                               pipe_name(pipe));
11261         }
11262
11263         list_for_each_entry(connector, &dev->mode_config.connector_list,
11264                             base.head) {
11265                 if (connector->get_hw_state(connector)) {
11266                         connector->base.dpms = DRM_MODE_DPMS_ON;
11267                         connector->encoder->connectors_active = true;
11268                         connector->base.encoder = &connector->encoder->base;
11269                 } else {
11270                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11271                         connector->base.encoder = NULL;
11272                 }
11273                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11274                               connector->base.base.id,
11275                               drm_get_connector_name(&connector->base),
11276                               connector->base.encoder ? "enabled" : "disabled");
11277         }
11278 }
11279
11280 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11281  * and i915 state tracking structures. */
11282 void intel_modeset_setup_hw_state(struct drm_device *dev,
11283                                   bool force_restore)
11284 {
11285         struct drm_i915_private *dev_priv = dev->dev_private;
11286         enum pipe pipe;
11287         struct intel_crtc *crtc;
11288         struct intel_encoder *encoder;
11289         int i;
11290
11291         intel_modeset_readout_hw_state(dev);
11292
11293         /*
11294          * Now that we have the config, copy it to each CRTC struct
11295          * Note that this could go away if we move to using crtc_config
11296          * checking everywhere.
11297          */
11298         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11299                             base.head) {
11300                 if (crtc->active && i915_fastboot) {
11301                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11302
11303                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11304                                       crtc->base.base.id);
11305                         drm_mode_debug_printmodeline(&crtc->base.mode);
11306                 }
11307         }
11308
11309         /* HW state is read out, now we need to sanitize this mess. */
11310         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11311                             base.head) {
11312                 intel_sanitize_encoder(encoder);
11313         }
11314
11315         for_each_pipe(pipe) {
11316                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11317                 intel_sanitize_crtc(crtc);
11318                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11319         }
11320
11321         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11322                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11323
11324                 if (!pll->on || pll->active)
11325                         continue;
11326
11327                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11328
11329                 pll->disable(dev_priv, pll);
11330                 pll->on = false;
11331         }
11332
11333         if (HAS_PCH_SPLIT(dev))
11334                 ilk_wm_get_hw_state(dev);
11335
11336         if (force_restore) {
11337                 i915_redisable_vga(dev);
11338
11339                 /*
11340                  * We need to use raw interfaces for restoring state to avoid
11341                  * checking (bogus) intermediate states.
11342                  */
11343                 for_each_pipe(pipe) {
11344                         struct drm_crtc *crtc =
11345                                 dev_priv->pipe_to_crtc_mapping[pipe];
11346
11347                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11348                                          crtc->fb);
11349                 }
11350         } else {
11351                 intel_modeset_update_staged_output_state(dev);
11352         }
11353
11354         intel_modeset_check_state(dev);
11355 }
11356
11357 void intel_modeset_gem_init(struct drm_device *dev)
11358 {
11359         intel_modeset_init_hw(dev);
11360
11361         intel_setup_overlay(dev);
11362
11363         mutex_lock(&dev->mode_config.mutex);
11364         drm_mode_config_reset(dev);
11365         intel_modeset_setup_hw_state(dev, false);
11366         mutex_unlock(&dev->mode_config.mutex);
11367 }
11368
11369 void intel_connector_unregister(struct intel_connector *intel_connector)
11370 {
11371         struct drm_connector *connector = &intel_connector->base;
11372
11373         intel_panel_destroy_backlight(connector);
11374         drm_sysfs_connector_remove(connector);
11375 }
11376
11377 void intel_modeset_cleanup(struct drm_device *dev)
11378 {
11379         struct drm_i915_private *dev_priv = dev->dev_private;
11380         struct drm_crtc *crtc;
11381         struct drm_connector *connector;
11382
11383         /*
11384          * Interrupts and polling as the first thing to avoid creating havoc.
11385          * Too much stuff here (turning of rps, connectors, ...) would
11386          * experience fancy races otherwise.
11387          */
11388         drm_irq_uninstall(dev);
11389         cancel_work_sync(&dev_priv->hotplug_work);
11390         /*
11391          * Due to the hpd irq storm handling the hotplug work can re-arm the
11392          * poll handlers. Hence disable polling after hpd handling is shut down.
11393          */
11394         drm_kms_helper_poll_fini(dev);
11395
11396         mutex_lock(&dev->struct_mutex);
11397
11398         intel_unregister_dsm_handler();
11399
11400         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11401                 /* Skip inactive CRTCs */
11402                 if (!crtc->fb)
11403                         continue;
11404
11405                 intel_increase_pllclock(crtc);
11406         }
11407
11408         intel_disable_fbc(dev);
11409
11410         intel_disable_gt_powersave(dev);
11411
11412         ironlake_teardown_rc6(dev);
11413
11414         mutex_unlock(&dev->struct_mutex);
11415
11416         /* flush any delayed tasks or pending work */
11417         flush_scheduled_work();
11418
11419         /* destroy the backlight and sysfs files before encoders/connectors */
11420         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11421                 struct intel_connector *intel_connector;
11422
11423                 intel_connector = to_intel_connector(connector);
11424                 intel_connector->unregister(intel_connector);
11425         }
11426
11427         drm_mode_config_cleanup(dev);
11428
11429         intel_cleanup_overlay(dev);
11430 }
11431
11432 /*
11433  * Return which encoder is currently attached for connector.
11434  */
11435 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11436 {
11437         return &intel_attached_encoder(connector)->base;
11438 }
11439
11440 void intel_connector_attach_encoder(struct intel_connector *connector,
11441                                     struct intel_encoder *encoder)
11442 {
11443         connector->encoder = encoder;
11444         drm_mode_connector_attach_encoder(&connector->base,
11445                                           &encoder->base);
11446 }
11447
11448 /*
11449  * set vga decode state - true == enable VGA decode
11450  */
11451 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11452 {
11453         struct drm_i915_private *dev_priv = dev->dev_private;
11454         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11455         u16 gmch_ctrl;
11456
11457         pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
11458         if (state)
11459                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11460         else
11461                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11462         pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
11463         return 0;
11464 }
11465
11466 struct intel_display_error_state {
11467
11468         u32 power_well_driver;
11469
11470         int num_transcoders;
11471
11472         struct intel_cursor_error_state {
11473                 u32 control;
11474                 u32 position;
11475                 u32 base;
11476                 u32 size;
11477         } cursor[I915_MAX_PIPES];
11478
11479         struct intel_pipe_error_state {
11480                 bool power_domain_on;
11481                 u32 source;
11482         } pipe[I915_MAX_PIPES];
11483
11484         struct intel_plane_error_state {
11485                 u32 control;
11486                 u32 stride;
11487                 u32 size;
11488                 u32 pos;
11489                 u32 addr;
11490                 u32 surface;
11491                 u32 tile_offset;
11492         } plane[I915_MAX_PIPES];
11493
11494         struct intel_transcoder_error_state {
11495                 bool power_domain_on;
11496                 enum transcoder cpu_transcoder;
11497
11498                 u32 conf;
11499
11500                 u32 htotal;
11501                 u32 hblank;
11502                 u32 hsync;
11503                 u32 vtotal;
11504                 u32 vblank;
11505                 u32 vsync;
11506         } transcoder[4];
11507 };
11508
11509 struct intel_display_error_state *
11510 intel_display_capture_error_state(struct drm_device *dev)
11511 {
11512         drm_i915_private_t *dev_priv = dev->dev_private;
11513         struct intel_display_error_state *error;
11514         int transcoders[] = {
11515                 TRANSCODER_A,
11516                 TRANSCODER_B,
11517                 TRANSCODER_C,
11518                 TRANSCODER_EDP,
11519         };
11520         int i;
11521
11522         if (INTEL_INFO(dev)->num_pipes == 0)
11523                 return NULL;
11524
11525         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11526         if (error == NULL)
11527                 return NULL;
11528
11529         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11530                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11531
11532         for_each_pipe(i) {
11533                 error->pipe[i].power_domain_on =
11534                         intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11535                 if (!error->pipe[i].power_domain_on)
11536                         continue;
11537
11538                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11539                         error->cursor[i].control = I915_READ(CURCNTR(i));
11540                         error->cursor[i].position = I915_READ(CURPOS(i));
11541                         error->cursor[i].base = I915_READ(CURBASE(i));
11542                 } else {
11543                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11544                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11545                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11546                 }
11547
11548                 error->plane[i].control = I915_READ(DSPCNTR(i));
11549                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11550                 if (INTEL_INFO(dev)->gen <= 3) {
11551                         error->plane[i].size = I915_READ(DSPSIZE(i));
11552                         error->plane[i].pos = I915_READ(DSPPOS(i));
11553                 }
11554                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11555                         error->plane[i].addr = I915_READ(DSPADDR(i));
11556                 if (INTEL_INFO(dev)->gen >= 4) {
11557                         error->plane[i].surface = I915_READ(DSPSURF(i));
11558                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11559                 }
11560
11561                 error->pipe[i].source = I915_READ(PIPESRC(i));
11562         }
11563
11564         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11565         if (HAS_DDI(dev_priv->dev))
11566                 error->num_transcoders++; /* Account for eDP. */
11567
11568         for (i = 0; i < error->num_transcoders; i++) {
11569                 enum transcoder cpu_transcoder = transcoders[i];
11570
11571                 error->transcoder[i].power_domain_on =
11572                         intel_display_power_enabled_sw(dev,
11573                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
11574                 if (!error->transcoder[i].power_domain_on)
11575                         continue;
11576
11577                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11578
11579                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11580                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11581                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11582                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11583                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11584                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11585                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11586         }
11587
11588         return error;
11589 }
11590
11591 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11592
11593 void
11594 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11595                                 struct drm_device *dev,
11596                                 struct intel_display_error_state *error)
11597 {
11598         int i;
11599
11600         if (!error)
11601                 return;
11602
11603         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11604         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11605                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11606                            error->power_well_driver);
11607         for_each_pipe(i) {
11608                 err_printf(m, "Pipe [%d]:\n", i);
11609                 err_printf(m, "  Power: %s\n",
11610                            error->pipe[i].power_domain_on ? "on" : "off");
11611                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11612
11613                 err_printf(m, "Plane [%d]:\n", i);
11614                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11615                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11616                 if (INTEL_INFO(dev)->gen <= 3) {
11617                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11618                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11619                 }
11620                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11621                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11622                 if (INTEL_INFO(dev)->gen >= 4) {
11623                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11624                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11625                 }
11626
11627                 err_printf(m, "Cursor [%d]:\n", i);
11628                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11629                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11630                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11631         }
11632
11633         for (i = 0; i < error->num_transcoders; i++) {
11634                 err_printf(m, "CPU transcoder: %c\n",
11635                            transcoder_name(error->transcoder[i].cpu_transcoder));
11636                 err_printf(m, "  Power: %s\n",
11637                            error->transcoder[i].power_domain_on ? "on" : "off");
11638                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11639                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11640                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11641                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11642                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11643                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11644                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11645         }
11646 }