2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
44 static __must_check int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
63 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
64 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
66 static bool cpu_cache_is_coherent(struct drm_device *dev,
67 enum i915_cache_level level)
69 return HAS_LLC(dev) || level != I915_CACHE_NONE;
72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
74 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
77 return obj->pin_display;
80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
83 i915_gem_release_mmap(obj);
85 /* As we do not have an associated fence register, we will force
86 * a tiling change if we ever need to acquire one.
88 obj->fence_dirty = false;
89 obj->fence_reg = I915_FENCE_REG_NONE;
92 /* some bookkeeping */
93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
96 spin_lock(&dev_priv->mm.object_stat_lock);
97 dev_priv->mm.object_count++;
98 dev_priv->mm.object_memory += size;
99 spin_unlock(&dev_priv->mm.object_stat_lock);
102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
105 spin_lock(&dev_priv->mm.object_stat_lock);
106 dev_priv->mm.object_count--;
107 dev_priv->mm.object_memory -= size;
108 spin_unlock(&dev_priv->mm.object_stat_lock);
112 i915_gem_wait_for_error(struct i915_gpu_error *error)
116 #define EXIT_COND (!i915_reset_in_progress(error) || \
117 i915_terminally_wedged(error))
122 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
123 * userspace. If it takes that long something really bad is going on and
124 * we should simply try to bail out and fail as gracefully as possible.
126 ret = wait_event_interruptible_timeout(error->reset_queue,
130 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
132 } else if (ret < 0) {
140 int i915_mutex_lock_interruptible(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
145 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
149 ret = mutex_lock_interruptible(&dev->struct_mutex);
153 WARN_ON(i915_verify_lists(dev));
158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
160 return i915_gem_obj_bound_any(obj) && !obj->active;
164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_init *args = data;
170 if (drm_core_check_feature(dev, DRIVER_MODESET))
173 if (args->gtt_start >= args->gtt_end ||
174 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
177 /* GEM with user mode setting was never supported on ilk and later. */
178 if (INTEL_INFO(dev)->gen >= 5)
181 mutex_lock(&dev->struct_mutex);
182 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
184 dev_priv->gtt.mappable_end = args->gtt_end;
185 mutex_unlock(&dev->struct_mutex);
191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
192 struct drm_file *file)
194 struct drm_i915_private *dev_priv = dev->dev_private;
195 struct drm_i915_gem_get_aperture *args = data;
196 struct drm_i915_gem_object *obj;
200 mutex_lock(&dev->struct_mutex);
201 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
202 if (i915_gem_obj_is_pinned(obj))
203 pinned += i915_gem_obj_ggtt_size(obj);
204 mutex_unlock(&dev->struct_mutex);
206 args->aper_size = dev_priv->gtt.base.total;
207 args->aper_available_size = args->aper_size - pinned;
212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
214 drm_dma_handle_t *phys = obj->phys_handle;
219 if (obj->madv == I915_MADV_WILLNEED) {
220 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
221 char *vaddr = phys->vaddr;
224 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
225 struct page *page = shmem_read_mapping_page(mapping, i);
227 char *dst = kmap_atomic(page);
228 memcpy(dst, vaddr, PAGE_SIZE);
229 drm_clflush_virt_range(dst, PAGE_SIZE);
232 set_page_dirty(page);
233 mark_page_accessed(page);
234 page_cache_release(page);
238 i915_gem_chipset_flush(obj->base.dev);
242 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
244 drm_pci_free(obj->base.dev, phys);
245 obj->phys_handle = NULL;
249 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
252 drm_dma_handle_t *phys;
253 struct address_space *mapping;
257 if (obj->phys_handle) {
258 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
264 if (obj->madv != I915_MADV_WILLNEED)
267 if (obj->base.filp == NULL)
270 /* create a new object */
271 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
277 set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
279 mapping = file_inode(obj->base.filp)->i_mapping;
280 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
284 page = shmem_read_mapping_page(mapping, i);
287 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
289 drm_pci_free(obj->base.dev, phys);
290 return PTR_ERR(page);
293 src = kmap_atomic(page);
294 memcpy(vaddr, src, PAGE_SIZE);
297 mark_page_accessed(page);
298 page_cache_release(page);
303 obj->phys_handle = phys;
308 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
309 struct drm_i915_gem_pwrite *args,
310 struct drm_file *file_priv)
312 struct drm_device *dev = obj->base.dev;
313 void *vaddr = obj->phys_handle->vaddr + args->offset;
314 char __user *user_data = to_user_ptr(args->data_ptr);
316 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
317 unsigned long unwritten;
319 /* The physical object once assigned is fixed for the lifetime
320 * of the obj, so we can safely drop the lock and continue
323 mutex_unlock(&dev->struct_mutex);
324 unwritten = copy_from_user(vaddr, user_data, args->size);
325 mutex_lock(&dev->struct_mutex);
330 i915_gem_chipset_flush(dev);
334 void *i915_gem_object_alloc(struct drm_device *dev)
336 struct drm_i915_private *dev_priv = dev->dev_private;
337 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
340 void i915_gem_object_free(struct drm_i915_gem_object *obj)
342 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
343 kmem_cache_free(dev_priv->slab, obj);
347 i915_gem_create(struct drm_file *file,
348 struct drm_device *dev,
352 struct drm_i915_gem_object *obj;
356 size = roundup(size, PAGE_SIZE);
360 /* Allocate the new object */
361 obj = i915_gem_alloc_object(dev, size);
365 ret = drm_gem_handle_create(file, &obj->base, &handle);
366 /* drop reference from allocate - handle holds it now */
367 drm_gem_object_unreference_unlocked(&obj->base);
376 i915_gem_dumb_create(struct drm_file *file,
377 struct drm_device *dev,
378 struct drm_mode_create_dumb *args)
380 /* have to work out size/pitch and return them */
381 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
382 args->size = args->pitch * args->height;
383 return i915_gem_create(file, dev,
384 args->size, &args->handle);
388 * Creates a new mm object and returns a handle to it.
391 i915_gem_create_ioctl(struct drm_device *dev, void *data,
392 struct drm_file *file)
394 struct drm_i915_gem_create *args = data;
396 return i915_gem_create(file, dev,
397 args->size, &args->handle);
401 __copy_to_user_swizzled(char __user *cpu_vaddr,
402 const char *gpu_vaddr, int gpu_offset,
405 int ret, cpu_offset = 0;
408 int cacheline_end = ALIGN(gpu_offset + 1, 64);
409 int this_length = min(cacheline_end - gpu_offset, length);
410 int swizzled_gpu_offset = gpu_offset ^ 64;
412 ret = __copy_to_user(cpu_vaddr + cpu_offset,
413 gpu_vaddr + swizzled_gpu_offset,
418 cpu_offset += this_length;
419 gpu_offset += this_length;
420 length -= this_length;
427 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
428 const char __user *cpu_vaddr,
431 int ret, cpu_offset = 0;
434 int cacheline_end = ALIGN(gpu_offset + 1, 64);
435 int this_length = min(cacheline_end - gpu_offset, length);
436 int swizzled_gpu_offset = gpu_offset ^ 64;
438 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
439 cpu_vaddr + cpu_offset,
444 cpu_offset += this_length;
445 gpu_offset += this_length;
446 length -= this_length;
453 * Pins the specified object's pages and synchronizes the object with
454 * GPU accesses. Sets needs_clflush to non-zero if the caller should
455 * flush the object from the CPU cache.
457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
467 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
468 /* If we're not in the cpu read domain, set ourself into the gtt
469 * read domain and manually flush cachelines (if required). This
470 * optimizes for the case when the gpu will dirty the data
471 * anyway again before the next pread happens. */
472 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
474 ret = i915_gem_object_wait_rendering(obj, true);
478 i915_gem_object_retire(obj);
481 ret = i915_gem_object_get_pages(obj);
485 i915_gem_object_pin_pages(obj);
490 /* Per-page copy function for the shmem pread fastpath.
491 * Flushes invalid cachelines before reading the target if
492 * needs_clflush is set. */
494 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
495 char __user *user_data,
496 bool page_do_bit17_swizzling, bool needs_clflush)
501 if (unlikely(page_do_bit17_swizzling))
504 vaddr = kmap_atomic(page);
506 drm_clflush_virt_range(vaddr + shmem_page_offset,
508 ret = __copy_to_user_inatomic(user_data,
509 vaddr + shmem_page_offset,
511 kunmap_atomic(vaddr);
513 return ret ? -EFAULT : 0;
517 shmem_clflush_swizzled_range(char *addr, unsigned long length,
520 if (unlikely(swizzled)) {
521 unsigned long start = (unsigned long) addr;
522 unsigned long end = (unsigned long) addr + length;
524 /* For swizzling simply ensure that we always flush both
525 * channels. Lame, but simple and it works. Swizzled
526 * pwrite/pread is far from a hotpath - current userspace
527 * doesn't use it at all. */
528 start = round_down(start, 128);
529 end = round_up(end, 128);
531 drm_clflush_virt_range((void *)start, end - start);
533 drm_clflush_virt_range(addr, length);
538 /* Only difference to the fast-path function is that this can handle bit17
539 * and uses non-atomic copy and kmap functions. */
541 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
542 char __user *user_data,
543 bool page_do_bit17_swizzling, bool needs_clflush)
550 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
552 page_do_bit17_swizzling);
554 if (page_do_bit17_swizzling)
555 ret = __copy_to_user_swizzled(user_data,
556 vaddr, shmem_page_offset,
559 ret = __copy_to_user(user_data,
560 vaddr + shmem_page_offset,
564 return ret ? - EFAULT : 0;
568 i915_gem_shmem_pread(struct drm_device *dev,
569 struct drm_i915_gem_object *obj,
570 struct drm_i915_gem_pread *args,
571 struct drm_file *file)
573 char __user *user_data;
576 int shmem_page_offset, ret = 0;
577 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
579 int needs_clflush = 0;
580 struct sg_page_iter sg_iter;
582 user_data = to_user_ptr(args->data_ptr);
585 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
587 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
591 offset = args->offset;
593 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
594 offset >> PAGE_SHIFT) {
595 struct page *page = sg_page_iter_page(&sg_iter);
596 unsigned int page_length;
601 /* Operation in this page
603 * shmem_page_offset = offset within page in shmem file
604 * page_length = bytes to copy for this page
606 shmem_page_offset = offset_in_page(offset);
607 page_length = min_t(u64, remain, PAGE_SIZE - shmem_page_offset);
609 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
610 (page_to_phys(page) & (1 << 17)) != 0;
612 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
613 user_data, page_do_bit17_swizzling,
618 mutex_unlock(&dev->struct_mutex);
620 if (likely(!i915.prefault_disable) && !prefaulted) {
621 ret = fault_in_multipages_writeable(user_data, remain);
622 /* Userspace is tricking us, but we've already clobbered
623 * its pages with the prefault and promised to write the
624 * data up to the first fault. Hence ignore any errors
625 * and just continue. */
630 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
631 user_data, page_do_bit17_swizzling,
634 mutex_lock(&dev->struct_mutex);
640 remain -= page_length;
641 user_data += page_length;
642 offset += page_length;
646 i915_gem_object_unpin_pages(obj);
652 * Reads data from the object referenced by handle.
654 * On error, the contents of *data are undefined.
657 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
658 struct drm_file *file)
660 struct drm_i915_gem_pread *args = data;
661 struct drm_i915_gem_object *obj;
667 if (!access_ok(VERIFY_WRITE,
668 to_user_ptr(args->data_ptr),
672 ret = i915_mutex_lock_interruptible(dev);
676 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
677 if (&obj->base == NULL) {
682 /* Bounds check source. */
683 if (args->offset > obj->base.size ||
684 args->size > obj->base.size - args->offset) {
689 /* prime objects have no backing filp to GEM pread/pwrite
692 if (!obj->base.filp) {
697 trace_i915_gem_object_pread(obj, args->offset, args->size);
699 ret = i915_gem_shmem_pread(dev, obj, args, file);
702 drm_gem_object_unreference(&obj->base);
704 mutex_unlock(&dev->struct_mutex);
708 /* This is the fast write path which cannot handle
709 * page faults in the source data
713 fast_user_write(struct io_mapping *mapping,
714 loff_t page_base, int page_offset,
715 char __user *user_data,
718 void __iomem *vaddr_atomic;
720 unsigned long unwritten;
722 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
723 /* We can use the cpu mem copy function because this is X86. */
724 vaddr = (void __force*)vaddr_atomic + page_offset;
725 unwritten = __copy_from_user_inatomic_nocache(vaddr,
727 io_mapping_unmap_atomic(vaddr_atomic);
732 * This is the fast pwrite path, where we copy the data directly from the
733 * user into the GTT, uncached.
736 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
737 struct drm_i915_gem_object *obj,
738 struct drm_i915_gem_pwrite *args,
739 struct drm_file *file)
741 struct drm_i915_private *dev_priv = dev->dev_private;
743 loff_t offset, page_base;
744 char __user *user_data;
745 int page_offset, page_length, ret;
747 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
751 ret = i915_gem_object_set_to_gtt_domain(obj, true);
755 ret = i915_gem_object_put_fence(obj);
759 user_data = to_user_ptr(args->data_ptr);
762 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
765 /* Operation in this page
767 * page_base = page offset within aperture
768 * page_offset = offset within page
769 * page_length = bytes to copy for this page
771 page_base = offset & PAGE_MASK;
772 page_offset = offset_in_page(offset);
773 page_length = remain;
774 if ((page_offset + remain) > PAGE_SIZE)
775 page_length = PAGE_SIZE - page_offset;
777 /* If we get a fault while copying data, then (presumably) our
778 * source page isn't available. Return the error and we'll
779 * retry in the slow path.
781 if (fast_user_write(dev_priv->gtt.mappable, page_base,
782 page_offset, user_data, page_length)) {
787 remain -= page_length;
788 user_data += page_length;
789 offset += page_length;
793 i915_gem_object_ggtt_unpin(obj);
798 /* Per-page copy function for the shmem pwrite fastpath.
799 * Flushes invalid cachelines before writing to the target if
800 * needs_clflush_before is set and flushes out any written cachelines after
801 * writing if needs_clflush is set. */
803 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
804 char __user *user_data,
805 bool page_do_bit17_swizzling,
806 bool needs_clflush_before,
807 bool needs_clflush_after)
812 if (unlikely(page_do_bit17_swizzling))
815 vaddr = kmap_atomic(page);
816 if (needs_clflush_before)
817 drm_clflush_virt_range(vaddr + shmem_page_offset,
819 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
820 user_data, page_length);
821 if (needs_clflush_after)
822 drm_clflush_virt_range(vaddr + shmem_page_offset,
824 kunmap_atomic(vaddr);
826 return ret ? -EFAULT : 0;
829 /* Only difference to the fast-path function is that this can handle bit17
830 * and uses non-atomic copy and kmap functions. */
832 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
833 char __user *user_data,
834 bool page_do_bit17_swizzling,
835 bool needs_clflush_before,
836 bool needs_clflush_after)
842 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
843 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
845 page_do_bit17_swizzling);
846 if (page_do_bit17_swizzling)
847 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
851 ret = __copy_from_user(vaddr + shmem_page_offset,
854 if (needs_clflush_after)
855 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
857 page_do_bit17_swizzling);
860 return ret ? -EFAULT : 0;
864 i915_gem_shmem_pwrite(struct drm_device *dev,
865 struct drm_i915_gem_object *obj,
866 struct drm_i915_gem_pwrite *args,
867 struct drm_file *file)
871 char __user *user_data;
872 int shmem_page_offset, ret = 0;
873 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
874 int hit_slowpath = 0;
875 int needs_clflush_after = 0;
876 int needs_clflush_before = 0;
877 struct sg_page_iter sg_iter;
879 user_data = to_user_ptr(args->data_ptr);
882 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
884 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
885 /* If we're not in the cpu write domain, set ourself into the gtt
886 * write domain and manually flush cachelines (if required). This
887 * optimizes for the case when the gpu will use the data
888 * right away and we therefore have to clflush anyway. */
889 needs_clflush_after = cpu_write_needs_clflush(obj);
890 ret = i915_gem_object_wait_rendering(obj, false);
894 i915_gem_object_retire(obj);
896 /* Same trick applies to invalidate partially written cachelines read
898 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
899 needs_clflush_before =
900 !cpu_cache_is_coherent(dev, obj->cache_level);
902 ret = i915_gem_object_get_pages(obj);
906 i915_gem_object_pin_pages(obj);
908 offset = args->offset;
911 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
912 offset >> PAGE_SHIFT) {
913 struct page *page = sg_page_iter_page(&sg_iter);
914 int partial_cacheline_write;
915 unsigned int page_length;
920 /* Operation in this page
922 * shmem_page_offset = offset within page in shmem file
923 * page_length = bytes to copy for this page
925 shmem_page_offset = offset_in_page(offset);
926 page_length = min_t(u64, remain, PAGE_SIZE - shmem_page_offset);
928 /* If we don't overwrite a cacheline completely we need to be
929 * careful to have up-to-date data by first clflushing. Don't
930 * overcomplicate things and flush the entire patch. */
931 partial_cacheline_write = needs_clflush_before &&
932 ((shmem_page_offset | page_length)
933 & (boot_cpu_data.x86_clflush_size - 1));
935 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
936 (page_to_phys(page) & (1 << 17)) != 0;
938 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
939 user_data, page_do_bit17_swizzling,
940 partial_cacheline_write,
941 needs_clflush_after);
946 mutex_unlock(&dev->struct_mutex);
947 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
948 user_data, page_do_bit17_swizzling,
949 partial_cacheline_write,
950 needs_clflush_after);
952 mutex_lock(&dev->struct_mutex);
958 remain -= page_length;
959 user_data += page_length;
960 offset += page_length;
964 i915_gem_object_unpin_pages(obj);
968 * Fixup: Flush cpu caches in case we didn't flush the dirty
969 * cachelines in-line while writing and the object moved
970 * out of the cpu write domain while we've dropped the lock.
972 if (!needs_clflush_after &&
973 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
974 if (i915_gem_clflush_object(obj, obj->pin_display))
975 i915_gem_chipset_flush(dev);
979 if (needs_clflush_after)
980 i915_gem_chipset_flush(dev);
986 * Writes data to the object referenced by handle.
988 * On error, the contents of the buffer that were to be modified are undefined.
991 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *file)
994 struct drm_i915_gem_pwrite *args = data;
995 struct drm_i915_gem_object *obj;
1001 if (!access_ok(VERIFY_READ,
1002 to_user_ptr(args->data_ptr),
1006 if (likely(!i915.prefault_disable)) {
1007 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1013 ret = i915_mutex_lock_interruptible(dev);
1017 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1018 if (&obj->base == NULL) {
1023 /* Bounds check destination. */
1024 if (args->offset > obj->base.size ||
1025 args->size > obj->base.size - args->offset) {
1030 /* prime objects have no backing filp to GEM pread/pwrite
1033 if (!obj->base.filp) {
1038 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1041 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1042 * it would end up going through the fenced access, and we'll get
1043 * different detiling behavior between reading and writing.
1044 * pread/pwrite currently are reading and writing from the CPU
1045 * perspective, requiring manual detiling by the client.
1047 if (obj->phys_handle) {
1048 ret = i915_gem_phys_pwrite(obj, args, file);
1052 if (obj->tiling_mode == I915_TILING_NONE &&
1053 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1054 cpu_write_needs_clflush(obj)) {
1055 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1056 /* Note that the gtt paths might fail with non-page-backed user
1057 * pointers (e.g. gtt mappings when moving data between
1058 * textures). Fallback to the shmem path in that case. */
1061 if (ret == -EFAULT || ret == -ENOSPC)
1062 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1065 drm_gem_object_unreference(&obj->base);
1067 mutex_unlock(&dev->struct_mutex);
1072 i915_gem_check_wedge(struct i915_gpu_error *error,
1075 if (i915_reset_in_progress(error)) {
1076 /* Non-interruptible callers can't handle -EAGAIN, hence return
1077 * -EIO unconditionally for these. */
1081 /* Recovery complete, but the reset failed ... */
1082 if (i915_terminally_wedged(error))
1092 * Compare seqno against outstanding lazy request. Emit a request if they are
1096 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1100 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1103 if (seqno == ring->outstanding_lazy_seqno)
1104 ret = i915_add_request(ring, NULL);
1109 static void fake_irq(unsigned long data)
1111 wake_up_process((struct task_struct *)data);
1114 static bool missed_irq(struct drm_i915_private *dev_priv,
1115 struct intel_engine_cs *ring)
1117 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1120 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1122 if (file_priv == NULL)
1125 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1129 * __wait_seqno - wait until execution of seqno has finished
1130 * @ring: the ring expected to report seqno
1132 * @reset_counter: reset sequence associated with the given seqno
1133 * @interruptible: do an interruptible wait (normally yes)
1134 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1136 * Note: It is of utmost importance that the passed in seqno and reset_counter
1137 * values have been read by the caller in an smp safe manner. Where read-side
1138 * locks are involved, it is sufficient to read the reset_counter before
1139 * unlocking the lock that protects the seqno. For lockless tricks, the
1140 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1143 * Returns 0 if the seqno was found within the alloted time. Else returns the
1144 * errno with remaining time filled in timeout argument.
1146 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1147 unsigned reset_counter,
1149 struct timespec *timeout,
1150 struct drm_i915_file_private *file_priv)
1152 struct drm_device *dev = ring->dev;
1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 const bool irq_test_in_progress =
1155 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1156 struct timespec before, now;
1158 unsigned long timeout_expire;
1161 WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n");
1163 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1166 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1168 if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1169 gen6_rps_boost(dev_priv);
1171 mod_delayed_work(dev_priv->wq,
1172 &file_priv->mm.idle_work,
1173 msecs_to_jiffies(100));
1176 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1179 /* Record current time in case interrupted by signal, or wedged */
1180 trace_i915_gem_request_wait_begin(ring, seqno);
1181 getrawmonotonic(&before);
1183 struct timer_list timer;
1185 prepare_to_wait(&ring->irq_queue, &wait,
1186 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1188 /* We need to check whether any gpu reset happened in between
1189 * the caller grabbing the seqno and now ... */
1190 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1191 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1192 * is truely gone. */
1193 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1199 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1204 if (interruptible && signal_pending(current)) {
1209 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1214 timer.function = NULL;
1215 if (timeout || missed_irq(dev_priv, ring)) {
1216 unsigned long expire;
1218 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1219 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1220 mod_timer(&timer, expire);
1225 if (timer.function) {
1226 del_singleshot_timer_sync(&timer);
1227 destroy_timer_on_stack(&timer);
1230 getrawmonotonic(&now);
1231 trace_i915_gem_request_wait_end(ring, seqno);
1233 if (!irq_test_in_progress)
1234 ring->irq_put(ring);
1236 finish_wait(&ring->irq_queue, &wait);
1239 struct timespec sleep_time = timespec_sub(now, before);
1240 *timeout = timespec_sub(*timeout, sleep_time);
1241 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1242 set_normalized_timespec(timeout, 0, 0);
1249 * Waits for a sequence number to be signaled, and cleans up the
1250 * request and object lists appropriately for that event.
1253 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1255 struct drm_device *dev = ring->dev;
1256 struct drm_i915_private *dev_priv = dev->dev_private;
1257 bool interruptible = dev_priv->mm.interruptible;
1260 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1263 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1267 ret = i915_gem_check_olr(ring, seqno);
1271 return __wait_seqno(ring, seqno,
1272 atomic_read(&dev_priv->gpu_error.reset_counter),
1273 interruptible, NULL, NULL);
1277 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1278 struct intel_engine_cs *ring)
1283 /* Manually manage the write flush as we may have not yet
1284 * retired the buffer.
1286 * Note that the last_write_seqno is always the earlier of
1287 * the two (read/write) seqno, so if we haved successfully waited,
1288 * we know we have passed the last write.
1290 obj->last_write_seqno = 0;
1296 * Ensures that all rendering to the object has completed and the object is
1297 * safe to unbind from the GTT or access from the CPU.
1299 static __must_check int
1300 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1303 struct intel_engine_cs *ring = obj->ring;
1307 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1311 ret = i915_wait_seqno(ring, seqno);
1315 return i915_gem_object_wait_rendering__tail(obj, ring);
1318 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1319 * as the object state may change during this call.
1321 static __must_check int
1322 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1323 struct drm_i915_file_private *file_priv,
1326 struct drm_device *dev = obj->base.dev;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1328 struct intel_engine_cs *ring = obj->ring;
1329 unsigned reset_counter;
1333 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1334 BUG_ON(!dev_priv->mm.interruptible);
1336 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1340 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1344 ret = i915_gem_check_olr(ring, seqno);
1348 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1349 mutex_unlock(&dev->struct_mutex);
1350 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1351 mutex_lock(&dev->struct_mutex);
1355 return i915_gem_object_wait_rendering__tail(obj, ring);
1359 * Called when user space prepares to use an object with the CPU, either
1360 * through the mmap ioctl's mapping or a GTT mapping.
1363 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1364 struct drm_file *file)
1366 struct drm_i915_gem_set_domain *args = data;
1367 struct drm_i915_gem_object *obj;
1368 uint32_t read_domains = args->read_domains;
1369 uint32_t write_domain = args->write_domain;
1372 /* Only handle setting domains to types used by the CPU. */
1373 if (write_domain & I915_GEM_GPU_DOMAINS)
1376 if (read_domains & I915_GEM_GPU_DOMAINS)
1379 /* Having something in the write domain implies it's in the read
1380 * domain, and only that read domain. Enforce that in the request.
1382 if (write_domain != 0 && read_domains != write_domain)
1385 ret = i915_mutex_lock_interruptible(dev);
1389 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1390 if (&obj->base == NULL) {
1395 /* Try to flush the object off the GPU without holding the lock.
1396 * We will repeat the flush holding the lock in the normal manner
1397 * to catch cases where we are gazumped.
1399 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1405 if (read_domains & I915_GEM_DOMAIN_GTT) {
1406 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1408 /* Silently promote "you're not bound, there was nothing to do"
1409 * to success, since the client was just asking us to
1410 * make sure everything was done.
1415 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1419 drm_gem_object_unreference(&obj->base);
1421 mutex_unlock(&dev->struct_mutex);
1426 * Called when user space has done writes to this buffer
1429 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1430 struct drm_file *file)
1432 struct drm_i915_gem_sw_finish *args = data;
1433 struct drm_i915_gem_object *obj;
1436 ret = i915_mutex_lock_interruptible(dev);
1440 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1441 if (&obj->base == NULL) {
1446 /* Pinned buffers may be scanout, so flush the cache */
1447 if (obj->pin_display)
1448 i915_gem_object_flush_cpu_write_domain(obj, true);
1450 drm_gem_object_unreference(&obj->base);
1452 mutex_unlock(&dev->struct_mutex);
1457 * Maps the contents of an object, returning the address it is mapped
1460 * While the mapping holds a reference on the contents of the object, it doesn't
1461 * imply a ref on the object itself.
1464 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1465 struct drm_file *file)
1467 struct drm_i915_gem_mmap *args = data;
1468 struct drm_gem_object *obj;
1471 obj = drm_gem_object_lookup(dev, file, args->handle);
1475 /* prime objects have no backing filp to GEM mmap
1479 drm_gem_object_unreference_unlocked(obj);
1483 addr = vm_mmap(obj->filp, 0, args->size,
1484 PROT_READ | PROT_WRITE, MAP_SHARED,
1486 drm_gem_object_unreference_unlocked(obj);
1487 if (IS_ERR((void *)addr))
1490 args->addr_ptr = (uint64_t) addr;
1496 * i915_gem_fault - fault a page into the GTT
1497 * vma: VMA in question
1500 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1501 * from userspace. The fault handler takes care of binding the object to
1502 * the GTT (if needed), allocating and programming a fence register (again,
1503 * only if needed based on whether the old reg is still valid or the object
1504 * is tiled) and inserting a new PTE into the faulting process.
1506 * Note that the faulting process may involve evicting existing objects
1507 * from the GTT and/or fence registers to make room. So performance may
1508 * suffer if the GTT working set is large or there are few fence registers
1511 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1513 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1514 struct drm_device *dev = obj->base.dev;
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516 pgoff_t page_offset;
1519 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1521 intel_runtime_pm_get(dev_priv);
1523 /* We don't use vmf->pgoff since that has the fake offset */
1524 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1527 ret = i915_mutex_lock_interruptible(dev);
1531 trace_i915_gem_object_fault(obj, page_offset, true, write);
1533 /* Try to flush the object off the GPU first without holding the lock.
1534 * Upon reacquiring the lock, we will perform our sanity checks and then
1535 * repeat the flush holding the lock in the normal manner to catch cases
1536 * where we are gazumped.
1538 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1542 /* Access to snoopable pages through the GTT is incoherent. */
1543 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1548 /* Now bind it into the GTT if needed */
1549 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1553 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1557 ret = i915_gem_object_get_fence(obj);
1561 obj->fault_mappable = true;
1563 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1567 /* Finally, remap it using the new GTT offset */
1568 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1570 i915_gem_object_ggtt_unpin(obj);
1572 mutex_unlock(&dev->struct_mutex);
1577 * We eat errors when the gpu is terminally wedged to avoid
1578 * userspace unduly crashing (gl has no provisions for mmaps to
1579 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1580 * and so needs to be reported.
1582 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1583 ret = VM_FAULT_SIGBUS;
1588 * EAGAIN means the gpu is hung and we'll wait for the error
1589 * handler to reset everything when re-faulting in
1590 * i915_mutex_lock_interruptible.
1597 * EBUSY is ok: this just means that another thread
1598 * already did the job.
1600 ret = VM_FAULT_NOPAGE;
1607 ret = VM_FAULT_SIGBUS;
1610 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1611 ret = VM_FAULT_SIGBUS;
1615 intel_runtime_pm_put(dev_priv);
1620 * i915_gem_release_mmap - remove physical page mappings
1621 * @obj: obj in question
1623 * Preserve the reservation of the mmapping with the DRM core code, but
1624 * relinquish ownership of the pages back to the system.
1626 * It is vital that we remove the page mapping if we have mapped a tiled
1627 * object through the GTT and then lose the fence register due to
1628 * resource pressure. Similarly if the object has been moved out of the
1629 * aperture, than pages mapped into userspace must be revoked. Removing the
1630 * mapping will then trigger a page fault on the next user access, allowing
1631 * fixup by i915_gem_fault().
1634 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1636 if (!obj->fault_mappable)
1639 drm_vma_node_unmap(&obj->base.vma_node,
1640 obj->base.dev->anon_inode->i_mapping);
1641 obj->fault_mappable = false;
1645 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1647 struct drm_i915_gem_object *obj;
1649 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1650 i915_gem_release_mmap(obj);
1654 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1658 if (INTEL_INFO(dev)->gen >= 4 ||
1659 tiling_mode == I915_TILING_NONE)
1662 /* Previous chips need a power-of-two fence region when tiling */
1663 if (INTEL_INFO(dev)->gen == 3)
1664 gtt_size = 1024*1024;
1666 gtt_size = 512*1024;
1668 while (gtt_size < size)
1675 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1676 * @obj: object to check
1678 * Return the required GTT alignment for an object, taking into account
1679 * potential fence register mapping.
1682 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1683 int tiling_mode, bool fenced)
1686 * Minimum alignment is 4k (GTT page size), but might be greater
1687 * if a fence register is needed for the object.
1689 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1690 tiling_mode == I915_TILING_NONE)
1694 * Previous chips need to be aligned to the size of the smallest
1695 * fence register that can contain the object.
1697 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1700 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1702 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1705 if (drm_vma_node_has_offset(&obj->base.vma_node))
1708 dev_priv->mm.shrinker_no_lock_stealing = true;
1710 ret = drm_gem_create_mmap_offset(&obj->base);
1714 /* Badly fragmented mmap space? The only way we can recover
1715 * space is by destroying unwanted objects. We can't randomly release
1716 * mmap_offsets as userspace expects them to be persistent for the
1717 * lifetime of the objects. The closest we can is to release the
1718 * offsets on purgeable objects by truncating it and marking it purged,
1719 * which prevents userspace from ever using that object again.
1721 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1722 ret = drm_gem_create_mmap_offset(&obj->base);
1726 i915_gem_shrink_all(dev_priv);
1727 ret = drm_gem_create_mmap_offset(&obj->base);
1729 dev_priv->mm.shrinker_no_lock_stealing = false;
1734 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1736 drm_gem_free_mmap_offset(&obj->base);
1740 i915_gem_mmap_gtt(struct drm_file *file,
1741 struct drm_device *dev,
1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 struct drm_i915_gem_object *obj;
1749 ret = i915_mutex_lock_interruptible(dev);
1753 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1754 if (&obj->base == NULL) {
1759 if (obj->base.size > dev_priv->gtt.mappable_end) {
1764 if (obj->madv != I915_MADV_WILLNEED) {
1765 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1770 ret = i915_gem_object_create_mmap_offset(obj);
1774 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1777 drm_gem_object_unreference(&obj->base);
1779 mutex_unlock(&dev->struct_mutex);
1784 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1786 * @data: GTT mapping ioctl data
1787 * @file: GEM object info
1789 * Simply returns the fake offset to userspace so it can mmap it.
1790 * The mmap call will end up in drm_gem_mmap(), which will set things
1791 * up so we can get faults in the handler above.
1793 * The fault handler will take care of binding the object into the GTT
1794 * (since it may have been evicted to make room for something), allocating
1795 * a fence register, and mapping the appropriate aperture address into
1799 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1800 struct drm_file *file)
1802 struct drm_i915_gem_mmap_gtt *args = data;
1804 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1808 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1810 return obj->madv == I915_MADV_DONTNEED;
1813 /* Immediately discard the backing storage */
1815 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1817 i915_gem_object_free_mmap_offset(obj);
1819 if (obj->base.filp == NULL)
1822 /* Our goal here is to return as much of the memory as
1823 * is possible back to the system as we are called from OOM.
1824 * To do this we must instruct the shmfs to drop all of its
1825 * backing pages, *now*.
1827 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1828 obj->madv = __I915_MADV_PURGED;
1831 /* Try to discard unwanted pages */
1833 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1835 struct address_space *mapping;
1837 switch (obj->madv) {
1838 case I915_MADV_DONTNEED:
1839 i915_gem_object_truncate(obj);
1840 case __I915_MADV_PURGED:
1844 if (obj->base.filp == NULL)
1847 mapping = file_inode(obj->base.filp)->i_mapping,
1848 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1852 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1854 struct sg_page_iter sg_iter;
1857 BUG_ON(obj->madv == __I915_MADV_PURGED);
1859 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1861 /* In the event of a disaster, abandon all caches and
1862 * hope for the best.
1864 WARN_ON(ret != -EIO);
1865 i915_gem_clflush_object(obj, true);
1866 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1869 if (i915_gem_object_needs_bit17_swizzle(obj))
1870 i915_gem_object_save_bit_17_swizzle(obj);
1872 if (obj->madv == I915_MADV_DONTNEED)
1875 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1876 struct page *page = sg_page_iter_page(&sg_iter);
1879 set_page_dirty(page);
1881 if (obj->madv == I915_MADV_WILLNEED)
1882 mark_page_accessed(page);
1884 page_cache_release(page);
1888 sg_free_table(obj->pages);
1893 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1895 const struct drm_i915_gem_object_ops *ops = obj->ops;
1897 if (obj->pages == NULL)
1900 if (obj->pages_pin_count)
1903 BUG_ON(i915_gem_obj_bound_any(obj));
1905 /* ->put_pages might need to allocate memory for the bit17 swizzle
1906 * array, hence protect them from being reaped by removing them from gtt
1908 list_del(&obj->global_list);
1910 ops->put_pages(obj);
1913 i915_gem_object_invalidate(obj);
1918 static unsigned long
1919 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1920 bool purgeable_only)
1922 struct list_head still_in_list;
1923 struct drm_i915_gem_object *obj;
1924 unsigned long count = 0;
1927 * As we may completely rewrite the (un)bound list whilst unbinding
1928 * (due to retiring requests) we have to strictly process only
1929 * one element of the list at the time, and recheck the list
1930 * on every iteration.
1932 * In particular, we must hold a reference whilst removing the
1933 * object as we may end up waiting for and/or retiring the objects.
1934 * This might release the final reference (held by the active list)
1935 * and result in the object being freed from under us. This is
1936 * similar to the precautions the eviction code must take whilst
1939 * Also note that although these lists do not hold a reference to
1940 * the object we can safely grab one here: The final object
1941 * unreferencing and the bound_list are both protected by the
1942 * dev->struct_mutex and so we won't ever be able to observe an
1943 * object on the bound_list with a reference count equals 0.
1945 INIT_LIST_HEAD(&still_in_list);
1946 while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1947 obj = list_first_entry(&dev_priv->mm.unbound_list,
1948 typeof(*obj), global_list);
1949 list_move_tail(&obj->global_list, &still_in_list);
1951 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1954 drm_gem_object_reference(&obj->base);
1956 if (i915_gem_object_put_pages(obj) == 0)
1957 count += obj->base.size >> PAGE_SHIFT;
1959 drm_gem_object_unreference(&obj->base);
1961 list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1963 INIT_LIST_HEAD(&still_in_list);
1964 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1965 struct i915_vma *vma, *v;
1967 obj = list_first_entry(&dev_priv->mm.bound_list,
1968 typeof(*obj), global_list);
1969 list_move_tail(&obj->global_list, &still_in_list);
1971 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1974 drm_gem_object_reference(&obj->base);
1976 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1977 if (i915_vma_unbind(vma))
1980 if (i915_gem_object_put_pages(obj) == 0)
1981 count += obj->base.size >> PAGE_SHIFT;
1983 drm_gem_object_unreference(&obj->base);
1985 list_splice(&still_in_list, &dev_priv->mm.bound_list);
1990 static unsigned long
1991 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1993 return __i915_gem_shrink(dev_priv, target, true);
1996 static unsigned long
1997 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1999 i915_gem_evict_everything(dev_priv->dev);
2000 return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2004 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2006 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2008 struct address_space *mapping;
2009 struct sg_table *st;
2010 struct scatterlist *sg;
2011 struct sg_page_iter sg_iter;
2013 unsigned long last_pfn = 0; /* suppress gcc warning */
2016 /* Assert that the object is not currently in any GPU domain. As it
2017 * wasn't in the GTT, there shouldn't be any way it could have been in
2020 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2021 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2023 st = kmalloc(sizeof(*st), GFP_KERNEL);
2027 page_count = obj->base.size / PAGE_SIZE;
2028 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2033 /* Get the list of pages out of our struct file. They'll be pinned
2034 * at this point until we release them.
2036 * Fail silently without starting the shrinker
2038 mapping = file_inode(obj->base.filp)->i_mapping;
2039 gfp = mapping_gfp_mask(mapping);
2040 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2041 gfp &= ~(__GFP_IO | __GFP_WAIT);
2044 for (i = 0; i < page_count; i++) {
2045 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2047 i915_gem_purge(dev_priv, page_count);
2048 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2051 /* We've tried hard to allocate the memory by reaping
2052 * our own buffer, now let the real VM do its job and
2053 * go down in flames if truly OOM.
2055 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
2056 gfp |= __GFP_IO | __GFP_WAIT;
2058 i915_gem_shrink_all(dev_priv);
2059 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2063 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2064 gfp &= ~(__GFP_IO | __GFP_WAIT);
2066 #ifdef CONFIG_SWIOTLB
2067 if (swiotlb_nr_tbl()) {
2069 sg_set_page(sg, page, PAGE_SIZE, 0);
2074 if (!i || page_to_pfn(page) != last_pfn + 1) {
2078 sg_set_page(sg, page, PAGE_SIZE, 0);
2080 sg->length += PAGE_SIZE;
2082 last_pfn = page_to_pfn(page);
2084 /* Check that the i965g/gm workaround works. */
2085 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2087 #ifdef CONFIG_SWIOTLB
2088 if (!swiotlb_nr_tbl())
2093 if (i915_gem_object_needs_bit17_swizzle(obj))
2094 i915_gem_object_do_bit_17_swizzle(obj);
2100 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2101 page_cache_release(sg_page_iter_page(&sg_iter));
2105 /* shmemfs first checks if there is enough memory to allocate the page
2106 * and reports ENOSPC should there be insufficient, along with the usual
2107 * ENOMEM for a genuine allocation failure.
2109 * We use ENOSPC in our driver to mean that we have run out of aperture
2110 * space and so want to translate the error from shmemfs back to our
2111 * usual understanding of ENOMEM.
2113 if (PTR_ERR(page) == -ENOSPC)
2116 return PTR_ERR(page);
2119 /* Ensure that the associated pages are gathered from the backing storage
2120 * and pinned into our object. i915_gem_object_get_pages() may be called
2121 * multiple times before they are released by a single call to
2122 * i915_gem_object_put_pages() - once the pages are no longer referenced
2123 * either as a result of memory pressure (reaping pages under the shrinker)
2124 * or as the object is itself released.
2127 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2129 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2130 const struct drm_i915_gem_object_ops *ops = obj->ops;
2136 if (obj->madv != I915_MADV_WILLNEED) {
2137 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2141 BUG_ON(obj->pages_pin_count);
2143 ret = ops->get_pages(obj);
2147 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2152 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2153 struct intel_engine_cs *ring)
2155 struct drm_device *dev = obj->base.dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 u32 seqno = intel_ring_get_seqno(ring);
2159 BUG_ON(ring == NULL);
2160 if (obj->ring != ring && obj->last_write_seqno) {
2161 /* Keep the seqno relative to the current ring */
2162 obj->last_write_seqno = seqno;
2166 /* Add a reference if we're newly entering the active list. */
2168 drm_gem_object_reference(&obj->base);
2172 list_move_tail(&obj->ring_list, &ring->active_list);
2174 obj->last_read_seqno = seqno;
2176 if (obj->fenced_gpu_access) {
2177 obj->last_fenced_seqno = seqno;
2179 /* Bump MRU to take account of the delayed flush */
2180 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2181 struct drm_i915_fence_reg *reg;
2183 reg = &dev_priv->fence_regs[obj->fence_reg];
2184 list_move_tail(®->lru_list,
2185 &dev_priv->mm.fence_list);
2190 void i915_vma_move_to_active(struct i915_vma *vma,
2191 struct intel_engine_cs *ring)
2193 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2194 return i915_gem_object_move_to_active(vma->obj, ring);
2198 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2200 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2201 struct i915_address_space *vm;
2202 struct i915_vma *vma;
2204 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2205 BUG_ON(!obj->active);
2207 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2208 vma = i915_gem_obj_to_vma(obj, vm);
2209 if (vma && !list_empty(&vma->mm_list))
2210 list_move_tail(&vma->mm_list, &vm->inactive_list);
2213 list_del_init(&obj->ring_list);
2216 obj->last_read_seqno = 0;
2217 obj->last_write_seqno = 0;
2218 obj->base.write_domain = 0;
2220 obj->last_fenced_seqno = 0;
2221 obj->fenced_gpu_access = false;
2224 drm_gem_object_unreference(&obj->base);
2226 WARN_ON(i915_verify_lists(dev));
2230 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2232 struct intel_engine_cs *ring = obj->ring;
2237 if (i915_seqno_passed(ring->get_seqno(ring, true),
2238 obj->last_read_seqno))
2239 i915_gem_object_move_to_inactive(obj);
2243 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2246 struct intel_engine_cs *ring;
2249 /* Carefully retire all requests without writing to the rings */
2250 for_each_ring(ring, dev_priv, i) {
2251 ret = intel_ring_idle(ring);
2255 i915_gem_retire_requests(dev);
2257 /* Finally reset hw state */
2258 for_each_ring(ring, dev_priv, i) {
2259 intel_ring_init_seqno(ring, seqno);
2261 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2262 ring->semaphore.sync_seqno[j] = 0;
2268 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2276 /* HWS page needs to be set less than what we
2277 * will inject to ring
2279 ret = i915_gem_init_seqno(dev, seqno - 1);
2283 /* Carefully set the last_seqno value so that wrap
2284 * detection still works
2286 dev_priv->next_seqno = seqno;
2287 dev_priv->last_seqno = seqno - 1;
2288 if (dev_priv->last_seqno == 0)
2289 dev_priv->last_seqno--;
2295 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2297 struct drm_i915_private *dev_priv = dev->dev_private;
2299 /* reserve 0 for non-seqno */
2300 if (dev_priv->next_seqno == 0) {
2301 int ret = i915_gem_init_seqno(dev, 0);
2305 dev_priv->next_seqno = 1;
2308 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2312 int __i915_add_request(struct intel_engine_cs *ring,
2313 struct drm_file *file,
2314 struct drm_i915_gem_object *obj,
2317 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2318 struct drm_i915_gem_request *request;
2319 u32 request_ring_position, request_start;
2322 request_start = intel_ring_get_tail(ring);
2324 * Emit any outstanding flushes - execbuf can fail to emit the flush
2325 * after having emitted the batchbuffer command. Hence we need to fix
2326 * things up similar to emitting the lazy request. The difference here
2327 * is that the flush _must_ happen before the next request, no matter
2330 ret = intel_ring_flush_all_caches(ring);
2334 request = ring->preallocated_lazy_request;
2335 if (WARN_ON(request == NULL))
2338 /* Record the position of the start of the request so that
2339 * should we detect the updated seqno part-way through the
2340 * GPU processing the request, we never over-estimate the
2341 * position of the head.
2343 request_ring_position = intel_ring_get_tail(ring);
2345 ret = ring->add_request(ring);
2349 request->seqno = intel_ring_get_seqno(ring);
2350 request->ring = ring;
2351 request->head = request_start;
2352 request->tail = request_ring_position;
2354 /* Whilst this request exists, batch_obj will be on the
2355 * active_list, and so will hold the active reference. Only when this
2356 * request is retired will the the batch_obj be moved onto the
2357 * inactive_list and lose its active reference. Hence we do not need
2358 * to explicitly hold another reference here.
2360 request->batch_obj = obj;
2362 /* Hold a reference to the current context so that we can inspect
2363 * it later in case a hangcheck error event fires.
2365 request->ctx = ring->last_context;
2367 i915_gem_context_reference(request->ctx);
2369 request->emitted_jiffies = jiffies;
2370 list_add_tail(&request->list, &ring->request_list);
2371 request->file_priv = NULL;
2374 struct drm_i915_file_private *file_priv = file->driver_priv;
2376 spin_lock(&file_priv->mm.lock);
2377 request->file_priv = file_priv;
2378 list_add_tail(&request->client_list,
2379 &file_priv->mm.request_list);
2380 spin_unlock(&file_priv->mm.lock);
2383 trace_i915_gem_request_add(ring, request->seqno);
2384 ring->outstanding_lazy_seqno = 0;
2385 ring->preallocated_lazy_request = NULL;
2387 if (!dev_priv->ums.mm_suspended) {
2388 i915_queue_hangcheck(ring->dev);
2390 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2391 queue_delayed_work(dev_priv->wq,
2392 &dev_priv->mm.retire_work,
2393 round_jiffies_up_relative(HZ));
2394 intel_mark_busy(dev_priv->dev);
2398 *out_seqno = request->seqno;
2403 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2405 struct drm_i915_file_private *file_priv = request->file_priv;
2410 spin_lock(&file_priv->mm.lock);
2411 list_del(&request->client_list);
2412 request->file_priv = NULL;
2413 spin_unlock(&file_priv->mm.lock);
2416 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2417 const struct intel_context *ctx)
2419 unsigned long elapsed;
2421 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2423 if (ctx->hang_stats.banned)
2426 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2427 if (!i915_gem_context_is_default(ctx)) {
2428 DRM_DEBUG("context hanging too fast, banning!\n");
2430 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2431 if (i915_stop_ring_allow_warn(dev_priv))
2432 DRM_ERROR("gpu hanging too fast, banning!\n");
2440 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2441 struct intel_context *ctx,
2444 struct i915_ctx_hang_stats *hs;
2449 hs = &ctx->hang_stats;
2452 hs->banned = i915_context_is_banned(dev_priv, ctx);
2454 hs->guilty_ts = get_seconds();
2456 hs->batch_pending++;
2460 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2462 list_del(&request->list);
2463 i915_gem_request_remove_from_client(request);
2466 i915_gem_context_unreference(request->ctx);
2471 struct drm_i915_gem_request *
2472 i915_gem_find_active_request(struct intel_engine_cs *ring)
2474 struct drm_i915_gem_request *request;
2475 u32 completed_seqno;
2477 completed_seqno = ring->get_seqno(ring, false);
2479 list_for_each_entry(request, &ring->request_list, list) {
2480 if (i915_seqno_passed(completed_seqno, request->seqno))
2489 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2490 struct intel_engine_cs *ring)
2492 struct drm_i915_gem_request *request;
2495 request = i915_gem_find_active_request(ring);
2497 if (request == NULL)
2500 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2502 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2504 list_for_each_entry_continue(request, &ring->request_list, list)
2505 i915_set_reset_status(dev_priv, request->ctx, false);
2508 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2509 struct intel_engine_cs *ring)
2511 while (!list_empty(&ring->active_list)) {
2512 struct drm_i915_gem_object *obj;
2514 obj = list_first_entry(&ring->active_list,
2515 struct drm_i915_gem_object,
2518 i915_gem_object_move_to_inactive(obj);
2522 * We must free the requests after all the corresponding objects have
2523 * been moved off active lists. Which is the same order as the normal
2524 * retire_requests function does. This is important if object hold
2525 * implicit references on things like e.g. ppgtt address spaces through
2528 while (!list_empty(&ring->request_list)) {
2529 struct drm_i915_gem_request *request;
2531 request = list_first_entry(&ring->request_list,
2532 struct drm_i915_gem_request,
2535 i915_gem_free_request(request);
2538 /* These may not have been flush before the reset, do so now */
2539 kfree(ring->preallocated_lazy_request);
2540 ring->preallocated_lazy_request = NULL;
2541 ring->outstanding_lazy_seqno = 0;
2544 void i915_gem_restore_fences(struct drm_device *dev)
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2549 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2550 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2553 * Commit delayed tiling changes if we have an object still
2554 * attached to the fence, otherwise just clear the fence.
2557 i915_gem_object_update_fence(reg->obj, reg,
2558 reg->obj->tiling_mode);
2560 i915_gem_write_fence(dev, i, NULL);
2565 void i915_gem_reset(struct drm_device *dev)
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568 struct intel_engine_cs *ring;
2572 * Before we free the objects from the requests, we need to inspect
2573 * them for finding the guilty party. As the requests only borrow
2574 * their reference to the objects, the inspection must be done first.
2576 for_each_ring(ring, dev_priv, i)
2577 i915_gem_reset_ring_status(dev_priv, ring);
2579 for_each_ring(ring, dev_priv, i)
2580 i915_gem_reset_ring_cleanup(dev_priv, ring);
2582 i915_gem_context_reset(dev);
2584 i915_gem_restore_fences(dev);
2588 * This function clears the request list as sequence numbers are passed.
2591 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2595 if (list_empty(&ring->request_list))
2598 WARN_ON(i915_verify_lists(ring->dev));
2600 seqno = ring->get_seqno(ring, true);
2602 /* Move any buffers on the active list that are no longer referenced
2603 * by the ringbuffer to the flushing/inactive lists as appropriate,
2604 * before we free the context associated with the requests.
2606 while (!list_empty(&ring->active_list)) {
2607 struct drm_i915_gem_object *obj;
2609 obj = list_first_entry(&ring->active_list,
2610 struct drm_i915_gem_object,
2613 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2616 i915_gem_object_move_to_inactive(obj);
2620 while (!list_empty(&ring->request_list)) {
2621 struct drm_i915_gem_request *request;
2623 request = list_first_entry(&ring->request_list,
2624 struct drm_i915_gem_request,
2627 if (!i915_seqno_passed(seqno, request->seqno))
2630 trace_i915_gem_request_retire(ring, request->seqno);
2631 /* We know the GPU must have read the request to have
2632 * sent us the seqno + interrupt, so use the position
2633 * of tail of the request to update the last known position
2636 ring->buffer->last_retired_head = request->tail;
2638 i915_gem_free_request(request);
2641 if (unlikely(ring->trace_irq_seqno &&
2642 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2643 ring->irq_put(ring);
2644 ring->trace_irq_seqno = 0;
2647 WARN_ON(i915_verify_lists(ring->dev));
2651 i915_gem_retire_requests(struct drm_device *dev)
2653 struct drm_i915_private *dev_priv = dev->dev_private;
2654 struct intel_engine_cs *ring;
2658 for_each_ring(ring, dev_priv, i) {
2659 i915_gem_retire_requests_ring(ring);
2660 idle &= list_empty(&ring->request_list);
2664 mod_delayed_work(dev_priv->wq,
2665 &dev_priv->mm.idle_work,
2666 msecs_to_jiffies(100));
2672 i915_gem_retire_work_handler(struct work_struct *work)
2674 struct drm_i915_private *dev_priv =
2675 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2676 struct drm_device *dev = dev_priv->dev;
2679 /* Come back later if the device is busy... */
2681 if (mutex_trylock(&dev->struct_mutex)) {
2682 idle = i915_gem_retire_requests(dev);
2683 mutex_unlock(&dev->struct_mutex);
2686 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2687 round_jiffies_up_relative(HZ));
2691 i915_gem_idle_work_handler(struct work_struct *work)
2693 struct drm_i915_private *dev_priv =
2694 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2696 intel_mark_idle(dev_priv->dev);
2700 * Ensures that an object will eventually get non-busy by flushing any required
2701 * write domains, emitting any outstanding lazy request and retiring and
2702 * completed requests.
2705 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2710 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2714 i915_gem_retire_requests_ring(obj->ring);
2721 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2722 * @DRM_IOCTL_ARGS: standard ioctl arguments
2724 * Returns 0 if successful, else an error is returned with the remaining time in
2725 * the timeout parameter.
2726 * -ETIME: object is still busy after timeout
2727 * -ERESTARTSYS: signal interrupted the wait
2728 * -ENONENT: object doesn't exist
2729 * Also possible, but rare:
2730 * -EAGAIN: GPU wedged
2732 * -ENODEV: Internal IRQ fail
2733 * -E?: The add request failed
2735 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2736 * non-zero timeout parameter the wait ioctl will wait for the given number of
2737 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2738 * without holding struct_mutex the object may become re-busied before this
2739 * function completes. A similar but shorter * race condition exists in the busy
2743 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2745 struct drm_i915_private *dev_priv = dev->dev_private;
2746 struct drm_i915_gem_wait *args = data;
2747 struct drm_i915_gem_object *obj;
2748 struct intel_engine_cs *ring = NULL;
2749 struct timespec timeout_stack, *timeout = NULL;
2750 unsigned reset_counter;
2754 if (args->timeout_ns >= 0) {
2755 timeout_stack = ns_to_timespec(args->timeout_ns);
2756 timeout = &timeout_stack;
2759 ret = i915_mutex_lock_interruptible(dev);
2763 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2764 if (&obj->base == NULL) {
2765 mutex_unlock(&dev->struct_mutex);
2769 /* Need to make sure the object gets inactive eventually. */
2770 ret = i915_gem_object_flush_active(obj);
2775 seqno = obj->last_read_seqno;
2782 /* Do this after OLR check to make sure we make forward progress polling
2783 * on this IOCTL with a 0 timeout (like busy ioctl)
2785 if (!args->timeout_ns) {
2790 drm_gem_object_unreference(&obj->base);
2791 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2792 mutex_unlock(&dev->struct_mutex);
2794 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2796 args->timeout_ns = timespec_to_ns(timeout);
2800 drm_gem_object_unreference(&obj->base);
2801 mutex_unlock(&dev->struct_mutex);
2806 * i915_gem_object_sync - sync an object to a ring.
2808 * @obj: object which may be in use on another ring.
2809 * @to: ring we wish to use the object on. May be NULL.
2811 * This code is meant to abstract object synchronization with the GPU.
2812 * Calling with NULL implies synchronizing the object with the CPU
2813 * rather than a particular GPU ring.
2815 * Returns 0 if successful, else propagates up the lower layer error.
2818 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2819 struct intel_engine_cs *to)
2821 struct intel_engine_cs *from = obj->ring;
2825 if (from == NULL || to == from)
2828 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2829 return i915_gem_object_wait_rendering(obj, false);
2831 idx = intel_ring_sync_index(from, to);
2833 seqno = obj->last_read_seqno;
2834 if (seqno <= from->semaphore.sync_seqno[idx])
2837 ret = i915_gem_check_olr(obj->ring, seqno);
2841 trace_i915_gem_ring_sync_to(from, to, seqno);
2842 ret = to->semaphore.sync_to(to, from, seqno);
2844 /* We use last_read_seqno because sync_to()
2845 * might have just caused seqno wrap under
2848 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2853 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2855 u32 old_write_domain, old_read_domains;
2857 /* Force a pagefault for domain tracking on next user access */
2858 i915_gem_release_mmap(obj);
2860 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2863 /* Wait for any direct GTT access to complete */
2866 old_read_domains = obj->base.read_domains;
2867 old_write_domain = obj->base.write_domain;
2869 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2870 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2872 trace_i915_gem_object_change_domain(obj,
2877 int i915_vma_unbind(struct i915_vma *vma)
2879 struct drm_i915_gem_object *obj = vma->obj;
2880 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2883 if (list_empty(&vma->vma_link))
2886 if (!drm_mm_node_allocated(&vma->node)) {
2887 i915_gem_vma_destroy(vma);
2894 BUG_ON(obj->pages == NULL);
2896 ret = i915_gem_object_finish_gpu(obj);
2899 /* Continue on if we fail due to EIO, the GPU is hung so we
2900 * should be safe and we need to cleanup or else we might
2901 * cause memory corruption through use-after-free.
2904 if (i915_is_ggtt(vma->vm)) {
2905 i915_gem_object_finish_gtt(obj);
2907 /* release the fence reg _after_ flushing */
2908 ret = i915_gem_object_put_fence(obj);
2913 trace_i915_vma_unbind(vma);
2915 vma->unbind_vma(vma);
2917 i915_gem_gtt_finish_object(obj);
2919 list_del_init(&vma->mm_list);
2920 /* Avoid an unnecessary call to unbind on rebind. */
2921 if (i915_is_ggtt(vma->vm))
2922 obj->map_and_fenceable = true;
2924 drm_mm_remove_node(&vma->node);
2925 i915_gem_vma_destroy(vma);
2927 /* Since the unbound list is global, only move to that list if
2928 * no more VMAs exist. */
2929 if (list_empty(&obj->vma_list))
2930 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2932 /* And finally now the object is completely decoupled from this vma,
2933 * we can drop its hold on the backing storage and allow it to be
2934 * reaped by the shrinker.
2936 i915_gem_object_unpin_pages(obj);
2941 int i915_gpu_idle(struct drm_device *dev)
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 struct intel_engine_cs *ring;
2947 /* Flush everything onto the inactive list. */
2948 for_each_ring(ring, dev_priv, i) {
2949 ret = i915_switch_context(ring, ring->default_context);
2953 ret = intel_ring_idle(ring);
2961 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2962 struct drm_i915_gem_object *obj)
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2966 int fence_pitch_shift;
2968 if (INTEL_INFO(dev)->gen >= 6) {
2969 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2970 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2972 fence_reg = FENCE_REG_965_0;
2973 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2976 fence_reg += reg * 8;
2978 /* To w/a incoherency with non-atomic 64-bit register updates,
2979 * we split the 64-bit update into two 32-bit writes. In order
2980 * for a partial fence not to be evaluated between writes, we
2981 * precede the update with write to turn off the fence register,
2982 * and only enable the fence as the last step.
2984 * For extra levels of paranoia, we make sure each step lands
2985 * before applying the next step.
2987 I915_WRITE(fence_reg, 0);
2988 POSTING_READ(fence_reg);
2991 u32 size = i915_gem_obj_ggtt_size(obj);
2994 /* Adjust fence size to match tiled area */
2995 if (obj->tiling_mode != I915_TILING_NONE) {
2996 uint32_t row_size = obj->stride *
2997 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
2998 size = (size / row_size) * row_size;
3001 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3003 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3004 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3005 if (obj->tiling_mode == I915_TILING_Y)
3006 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3007 val |= I965_FENCE_REG_VALID;
3009 I915_WRITE(fence_reg + 4, val >> 32);
3010 POSTING_READ(fence_reg + 4);
3012 I915_WRITE(fence_reg + 0, val);
3013 POSTING_READ(fence_reg);
3015 I915_WRITE(fence_reg + 4, 0);
3016 POSTING_READ(fence_reg + 4);
3020 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3021 struct drm_i915_gem_object *obj)
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3027 u32 size = i915_gem_obj_ggtt_size(obj);
3031 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3032 (size & -size) != size ||
3033 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3034 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3035 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3037 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3042 /* Note: pitch better be a power of two tile widths */
3043 pitch_val = obj->stride / tile_width;
3044 pitch_val = ffs(pitch_val) - 1;
3046 val = i915_gem_obj_ggtt_offset(obj);
3047 if (obj->tiling_mode == I915_TILING_Y)
3048 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3049 val |= I915_FENCE_SIZE_BITS(size);
3050 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3051 val |= I830_FENCE_REG_VALID;
3056 reg = FENCE_REG_830_0 + reg * 4;
3058 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3060 I915_WRITE(reg, val);
3064 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3065 struct drm_i915_gem_object *obj)
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3071 u32 size = i915_gem_obj_ggtt_size(obj);
3074 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3075 (size & -size) != size ||
3076 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3077 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3078 i915_gem_obj_ggtt_offset(obj), size);
3080 pitch_val = obj->stride / 128;
3081 pitch_val = ffs(pitch_val) - 1;
3083 val = i915_gem_obj_ggtt_offset(obj);
3084 if (obj->tiling_mode == I915_TILING_Y)
3085 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3086 val |= I830_FENCE_SIZE_BITS(size);
3087 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3088 val |= I830_FENCE_REG_VALID;
3092 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3093 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3096 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3098 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3101 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3102 struct drm_i915_gem_object *obj)
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3106 /* Ensure that all CPU reads are completed before installing a fence
3107 * and all writes before removing the fence.
3109 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3112 WARN(obj && (!obj->stride || !obj->tiling_mode),
3113 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3114 obj->stride, obj->tiling_mode);
3116 switch (INTEL_INFO(dev)->gen) {
3121 case 4: i965_write_fence_reg(dev, reg, obj); break;
3122 case 3: i915_write_fence_reg(dev, reg, obj); break;
3123 case 2: i830_write_fence_reg(dev, reg, obj); break;
3127 /* And similarly be paranoid that no direct access to this region
3128 * is reordered to before the fence is installed.
3130 if (i915_gem_object_needs_mb(obj))
3134 static inline int fence_number(struct drm_i915_private *dev_priv,
3135 struct drm_i915_fence_reg *fence)
3137 return fence - dev_priv->fence_regs;
3140 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3141 struct drm_i915_fence_reg *fence,
3144 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3145 int reg = fence_number(dev_priv, fence);
3147 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3150 obj->fence_reg = reg;
3152 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3154 obj->fence_reg = I915_FENCE_REG_NONE;
3156 list_del_init(&fence->lru_list);
3158 obj->fence_dirty = false;
3162 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3164 if (obj->last_fenced_seqno) {
3165 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3169 obj->last_fenced_seqno = 0;
3172 obj->fenced_gpu_access = false;
3177 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3180 struct drm_i915_fence_reg *fence;
3183 ret = i915_gem_object_wait_fence(obj);
3187 if (obj->fence_reg == I915_FENCE_REG_NONE)
3190 fence = &dev_priv->fence_regs[obj->fence_reg];
3192 if (WARN_ON(fence->pin_count))
3195 i915_gem_object_fence_lost(obj);
3196 i915_gem_object_update_fence(obj, fence, false);
3201 static struct drm_i915_fence_reg *
3202 i915_find_fence_reg(struct drm_device *dev)
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct drm_i915_fence_reg *reg, *avail;
3208 /* First try to find a free reg */
3210 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3211 reg = &dev_priv->fence_regs[i];
3215 if (!reg->pin_count)
3222 /* None available, try to steal one or wait for a user to finish */
3223 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3231 /* Wait for completion of pending flips which consume fences */
3232 if (intel_has_pending_fb_unpin(dev))
3233 return ERR_PTR(-EAGAIN);
3235 return ERR_PTR(-EDEADLK);
3239 * i915_gem_object_get_fence - set up fencing for an object
3240 * @obj: object to map through a fence reg
3242 * When mapping objects through the GTT, userspace wants to be able to write
3243 * to them without having to worry about swizzling if the object is tiled.
3244 * This function walks the fence regs looking for a free one for @obj,
3245 * stealing one if it can't find any.
3247 * It then sets up the reg based on the object's properties: address, pitch
3248 * and tiling format.
3250 * For an untiled surface, this removes any existing fence.
3253 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3255 struct drm_device *dev = obj->base.dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 bool enable = obj->tiling_mode != I915_TILING_NONE;
3258 struct drm_i915_fence_reg *reg;
3261 /* Have we updated the tiling parameters upon the object and so
3262 * will need to serialise the write to the associated fence register?
3264 if (obj->fence_dirty) {
3265 ret = i915_gem_object_wait_fence(obj);
3270 /* Just update our place in the LRU if our fence is getting reused. */
3271 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3272 reg = &dev_priv->fence_regs[obj->fence_reg];
3273 if (!obj->fence_dirty) {
3274 list_move_tail(®->lru_list,
3275 &dev_priv->mm.fence_list);
3278 } else if (enable) {
3279 reg = i915_find_fence_reg(dev);
3281 return PTR_ERR(reg);
3284 struct drm_i915_gem_object *old = reg->obj;
3286 ret = i915_gem_object_wait_fence(old);
3290 i915_gem_object_fence_lost(old);
3295 i915_gem_object_update_fence(obj, reg, enable);
3300 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3301 struct drm_mm_node *gtt_space,
3302 unsigned long cache_level)
3304 struct drm_mm_node *other;
3306 /* On non-LLC machines we have to be careful when putting differing
3307 * types of snoopable memory together to avoid the prefetcher
3308 * crossing memory domains and dying.
3313 if (!drm_mm_node_allocated(gtt_space))
3316 if (list_empty(>t_space->node_list))
3319 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3320 if (other->allocated && !other->hole_follows && other->color != cache_level)
3323 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3324 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3330 static void i915_gem_verify_gtt(struct drm_device *dev)
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 struct drm_i915_gem_object *obj;
3337 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3338 if (obj->gtt_space == NULL) {
3339 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3344 if (obj->cache_level != obj->gtt_space->color) {
3345 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3346 i915_gem_obj_ggtt_offset(obj),
3347 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3349 obj->gtt_space->color);
3354 if (!i915_gem_valid_gtt_space(dev,
3356 obj->cache_level)) {
3357 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3358 i915_gem_obj_ggtt_offset(obj),
3359 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3371 * Finds free space in the GTT aperture and binds the object there.
3373 static struct i915_vma *
3374 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3375 struct i915_address_space *vm,
3379 struct drm_device *dev = obj->base.dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 u32 size, fence_size, fence_alignment, unfenced_alignment;
3382 unsigned long start =
3383 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3385 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3386 struct i915_vma *vma;
3389 fence_size = i915_gem_get_gtt_size(dev,
3392 fence_alignment = i915_gem_get_gtt_alignment(dev,
3394 obj->tiling_mode, true);
3395 unfenced_alignment =
3396 i915_gem_get_gtt_alignment(dev,
3398 obj->tiling_mode, false);
3401 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3403 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3404 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3405 return ERR_PTR(-EINVAL);
3408 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3410 /* If the object is bigger than the entire aperture, reject it early
3411 * before evicting everything in a vain attempt to find space.
3413 if (obj->base.size > end) {
3414 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3416 flags & PIN_MAPPABLE ? "mappable" : "total",
3418 return ERR_PTR(-E2BIG);
3421 ret = i915_gem_object_get_pages(obj);
3423 return ERR_PTR(ret);
3425 i915_gem_object_pin_pages(obj);
3427 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3432 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3436 DRM_MM_SEARCH_DEFAULT,
3437 DRM_MM_CREATE_DEFAULT);
3439 ret = i915_gem_evict_something(dev, vm, size, alignment,
3448 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3449 obj->cache_level))) {
3451 goto err_remove_node;
3454 ret = i915_gem_gtt_prepare_object(obj);
3456 goto err_remove_node;
3458 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3459 list_add_tail(&vma->mm_list, &vm->inactive_list);
3461 if (i915_is_ggtt(vm)) {
3462 bool mappable, fenceable;
3464 fenceable = (vma->node.size == fence_size &&
3465 (vma->node.start & (fence_alignment - 1)) == 0);
3467 mappable = (vma->node.start + obj->base.size <=
3468 dev_priv->gtt.mappable_end);
3470 obj->map_and_fenceable = mappable && fenceable;
3473 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3475 trace_i915_vma_bind(vma, flags);
3476 vma->bind_vma(vma, obj->cache_level,
3477 flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3479 i915_gem_verify_gtt(dev);
3483 drm_mm_remove_node(&vma->node);
3485 i915_gem_vma_destroy(vma);
3488 i915_gem_object_unpin_pages(obj);
3493 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3496 /* If we don't have a page list set up, then we're not pinned
3497 * to GPU, and we can ignore the cache flush because it'll happen
3498 * again at bind time.
3500 if (obj->pages == NULL)
3504 * Stolen memory is always coherent with the GPU as it is explicitly
3505 * marked as wc by the system, or the system is cache-coherent.
3510 /* If the GPU is snooping the contents of the CPU cache,
3511 * we do not need to manually clear the CPU cache lines. However,
3512 * the caches are only snooped when the render cache is
3513 * flushed/invalidated. As we always have to emit invalidations
3514 * and flushes when moving into and out of the RENDER domain, correct
3515 * snooping behaviour occurs naturally as the result of our domain
3518 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3521 trace_i915_gem_object_clflush(obj);
3522 drm_clflush_sg(obj->pages);
3527 /** Flushes the GTT write domain for the object if it's dirty. */
3529 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3531 uint32_t old_write_domain;
3533 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3536 /* No actual flushing is required for the GTT write domain. Writes
3537 * to it immediately go to main memory as far as we know, so there's
3538 * no chipset flush. It also doesn't land in render cache.
3540 * However, we do have to enforce the order so that all writes through
3541 * the GTT land before any writes to the device, such as updates to
3546 old_write_domain = obj->base.write_domain;
3547 obj->base.write_domain = 0;
3549 trace_i915_gem_object_change_domain(obj,
3550 obj->base.read_domains,
3554 /** Flushes the CPU write domain for the object if it's dirty. */
3556 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3559 uint32_t old_write_domain;
3561 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3564 if (i915_gem_clflush_object(obj, force))
3565 i915_gem_chipset_flush(obj->base.dev);
3567 old_write_domain = obj->base.write_domain;
3568 obj->base.write_domain = 0;
3570 trace_i915_gem_object_change_domain(obj,
3571 obj->base.read_domains,
3576 * Moves a single object to the GTT read, and possibly write domain.
3578 * This function returns when the move is complete, including waiting on
3582 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3584 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3585 uint32_t old_write_domain, old_read_domains;
3588 /* Not valid to be called on unbound objects. */
3589 if (!i915_gem_obj_bound_any(obj))
3592 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3595 ret = i915_gem_object_wait_rendering(obj, !write);
3599 i915_gem_object_retire(obj);
3600 i915_gem_object_flush_cpu_write_domain(obj, false);
3602 /* Serialise direct access to this object with the barriers for
3603 * coherent writes from the GPU, by effectively invalidating the
3604 * GTT domain upon first access.
3606 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3609 old_write_domain = obj->base.write_domain;
3610 old_read_domains = obj->base.read_domains;
3612 /* It should now be out of any other write domains, and we can update
3613 * the domain values for our changes.
3615 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3616 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3618 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3619 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3623 trace_i915_gem_object_change_domain(obj,
3627 /* And bump the LRU for this access */
3628 if (i915_gem_object_is_inactive(obj)) {
3629 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3631 list_move_tail(&vma->mm_list,
3632 &dev_priv->gtt.base.inactive_list);
3639 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3640 enum i915_cache_level cache_level)
3642 struct drm_device *dev = obj->base.dev;
3643 struct i915_vma *vma, *next;
3646 if (obj->cache_level == cache_level)
3649 if (i915_gem_obj_is_pinned(obj)) {
3650 DRM_DEBUG("can not change the cache level of pinned objects\n");
3654 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3655 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3656 ret = i915_vma_unbind(vma);
3662 if (i915_gem_obj_bound_any(obj)) {
3663 ret = i915_gem_object_finish_gpu(obj);
3667 i915_gem_object_finish_gtt(obj);
3669 /* Before SandyBridge, you could not use tiling or fence
3670 * registers with snooped memory, so relinquish any fences
3671 * currently pointing to our region in the aperture.
3673 if (INTEL_INFO(dev)->gen < 6) {
3674 ret = i915_gem_object_put_fence(obj);
3679 list_for_each_entry(vma, &obj->vma_list, vma_link)
3680 if (drm_mm_node_allocated(&vma->node))
3681 vma->bind_vma(vma, cache_level,
3682 obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3685 list_for_each_entry(vma, &obj->vma_list, vma_link)
3686 vma->node.color = cache_level;
3687 obj->cache_level = cache_level;
3689 if (cpu_write_needs_clflush(obj)) {
3690 u32 old_read_domains, old_write_domain;
3692 /* If we're coming from LLC cached, then we haven't
3693 * actually been tracking whether the data is in the
3694 * CPU cache or not, since we only allow one bit set
3695 * in obj->write_domain and have been skipping the clflushes.
3696 * Just set it to the CPU cache for now.
3698 i915_gem_object_retire(obj);
3699 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3701 old_read_domains = obj->base.read_domains;
3702 old_write_domain = obj->base.write_domain;
3704 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3705 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3707 trace_i915_gem_object_change_domain(obj,
3712 i915_gem_verify_gtt(dev);
3716 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3717 struct drm_file *file)
3719 struct drm_i915_gem_caching *args = data;
3720 struct drm_i915_gem_object *obj;
3723 ret = i915_mutex_lock_interruptible(dev);
3727 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3728 if (&obj->base == NULL) {
3733 switch (obj->cache_level) {
3734 case I915_CACHE_LLC:
3735 case I915_CACHE_L3_LLC:
3736 args->caching = I915_CACHING_CACHED;
3740 args->caching = I915_CACHING_DISPLAY;
3744 args->caching = I915_CACHING_NONE;
3748 drm_gem_object_unreference(&obj->base);
3750 mutex_unlock(&dev->struct_mutex);
3754 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3755 struct drm_file *file)
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 struct drm_i915_gem_caching *args = data;
3759 struct drm_i915_gem_object *obj;
3760 enum i915_cache_level level;
3763 switch (args->caching) {
3764 case I915_CACHING_NONE:
3765 level = I915_CACHE_NONE;
3767 case I915_CACHING_CACHED:
3768 level = I915_CACHE_LLC;
3770 case I915_CACHING_DISPLAY:
3771 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3777 intel_runtime_pm_get(dev_priv);
3779 ret = i915_mutex_lock_interruptible(dev);
3783 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3784 if (&obj->base == NULL) {
3789 ret = i915_gem_object_set_cache_level(obj, level);
3791 drm_gem_object_unreference(&obj->base);
3793 mutex_unlock(&dev->struct_mutex);
3795 intel_runtime_pm_put(dev_priv);
3800 static bool is_pin_display(struct drm_i915_gem_object *obj)
3802 struct i915_vma *vma;
3804 if (list_empty(&obj->vma_list))
3807 vma = i915_gem_obj_to_ggtt(obj);
3811 /* There are 3 sources that pin objects:
3812 * 1. The display engine (scanouts, sprites, cursors);
3813 * 2. Reservations for execbuffer;
3816 * We can ignore reservations as we hold the struct_mutex and
3817 * are only called outside of the reservation path. The user
3818 * can only increment pin_count once, and so if after
3819 * subtracting the potential reference by the user, any pin_count
3820 * remains, it must be due to another use by the display engine.
3822 return vma->pin_count - !!obj->user_pin_count;
3826 * Prepare buffer for display plane (scanout, cursors, etc).
3827 * Can be called from an uninterruptible phase (modesetting) and allows
3828 * any flushes to be pipelined (for pageflips).
3831 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3833 struct intel_engine_cs *pipelined)
3835 u32 old_read_domains, old_write_domain;
3836 bool was_pin_display;
3839 if (pipelined != obj->ring) {
3840 ret = i915_gem_object_sync(obj, pipelined);
3845 /* Mark the pin_display early so that we account for the
3846 * display coherency whilst setting up the cache domains.
3848 was_pin_display = obj->pin_display;
3849 obj->pin_display = true;
3851 /* The display engine is not coherent with the LLC cache on gen6. As
3852 * a result, we make sure that the pinning that is about to occur is
3853 * done with uncached PTEs. This is lowest common denominator for all
3856 * However for gen6+, we could do better by using the GFDT bit instead
3857 * of uncaching, which would allow us to flush all the LLC-cached data
3858 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3860 ret = i915_gem_object_set_cache_level(obj,
3861 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3863 goto err_unpin_display;
3865 /* As the user may map the buffer once pinned in the display plane
3866 * (e.g. libkms for the bootup splash), we have to ensure that we
3867 * always use map_and_fenceable for all scanout buffers.
3869 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3871 goto err_unpin_display;
3873 i915_gem_object_flush_cpu_write_domain(obj, true);
3875 old_write_domain = obj->base.write_domain;
3876 old_read_domains = obj->base.read_domains;
3878 /* It should now be out of any other write domains, and we can update
3879 * the domain values for our changes.
3881 obj->base.write_domain = 0;
3882 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3884 trace_i915_gem_object_change_domain(obj,
3891 WARN_ON(was_pin_display != is_pin_display(obj));
3892 obj->pin_display = was_pin_display;
3897 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3899 i915_gem_object_ggtt_unpin(obj);
3900 obj->pin_display = is_pin_display(obj);
3904 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3908 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3911 ret = i915_gem_object_wait_rendering(obj, false);
3915 /* Ensure that we invalidate the GPU's caches and TLBs. */
3916 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3921 * Moves a single object to the CPU read, and possibly write domain.
3923 * This function returns when the move is complete, including waiting on
3927 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3929 uint32_t old_write_domain, old_read_domains;
3932 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3935 ret = i915_gem_object_wait_rendering(obj, !write);
3939 i915_gem_object_retire(obj);
3940 i915_gem_object_flush_gtt_write_domain(obj);
3942 old_write_domain = obj->base.write_domain;
3943 old_read_domains = obj->base.read_domains;
3945 /* Flush the CPU cache if it's still invalid. */
3946 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3947 i915_gem_clflush_object(obj, false);
3949 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3952 /* It should now be out of any other write domains, and we can update
3953 * the domain values for our changes.
3955 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3957 /* If we're writing through the CPU, then the GPU read domains will
3958 * need to be invalidated at next use.
3961 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3962 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3965 trace_i915_gem_object_change_domain(obj,
3972 /* Throttle our rendering by waiting until the ring has completed our requests
3973 * emitted over 20 msec ago.
3975 * Note that if we were to use the current jiffies each time around the loop,
3976 * we wouldn't escape the function with any frames outstanding if the time to
3977 * render a frame was over 20ms.
3979 * This should get us reasonable parallelism between CPU and GPU but also
3980 * relatively low latency when blocking on a particular request to finish.
3983 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3986 struct drm_i915_file_private *file_priv = file->driver_priv;
3987 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3988 struct drm_i915_gem_request *request;
3989 struct intel_engine_cs *ring = NULL;
3990 unsigned reset_counter;
3994 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3998 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4002 spin_lock(&file_priv->mm.lock);
4003 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4004 if (time_after_eq(request->emitted_jiffies, recent_enough))
4007 ring = request->ring;
4008 seqno = request->seqno;
4010 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4011 spin_unlock(&file_priv->mm.lock);
4016 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4018 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4024 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4026 struct drm_i915_gem_object *obj = vma->obj;
4029 vma->node.start & (alignment - 1))
4032 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4035 if (flags & PIN_OFFSET_BIAS &&
4036 vma->node.start < (flags & PIN_OFFSET_MASK))
4043 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4044 struct i915_address_space *vm,
4048 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4049 struct i915_vma *vma;
4052 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4055 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4058 vma = i915_gem_obj_to_vma(obj, vm);
4060 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4063 if (i915_vma_misplaced(vma, alignment, flags)) {
4064 WARN(vma->pin_count,
4065 "bo is already pinned with incorrect alignment:"
4066 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4067 " obj->map_and_fenceable=%d\n",
4068 i915_gem_obj_offset(obj, vm), alignment,
4069 !!(flags & PIN_MAPPABLE),
4070 obj->map_and_fenceable);
4071 ret = i915_vma_unbind(vma);
4079 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4080 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4082 return PTR_ERR(vma);
4085 if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4086 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4089 if (flags & PIN_MAPPABLE)
4090 obj->pin_mappable |= true;
4096 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4098 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4101 BUG_ON(vma->pin_count == 0);
4102 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4104 if (--vma->pin_count == 0)
4105 obj->pin_mappable = false;
4109 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4111 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4112 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4113 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4115 WARN_ON(!ggtt_vma ||
4116 dev_priv->fence_regs[obj->fence_reg].pin_count >
4117 ggtt_vma->pin_count);
4118 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4125 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4127 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4129 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4130 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4135 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4136 struct drm_file *file)
4138 struct drm_i915_gem_pin *args = data;
4139 struct drm_i915_gem_object *obj;
4142 if (INTEL_INFO(dev)->gen >= 6)
4145 ret = i915_mutex_lock_interruptible(dev);
4149 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4150 if (&obj->base == NULL) {
4155 if (obj->madv != I915_MADV_WILLNEED) {
4156 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4161 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4162 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4168 if (obj->user_pin_count == ULONG_MAX) {
4173 if (obj->user_pin_count == 0) {
4174 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4179 obj->user_pin_count++;
4180 obj->pin_filp = file;
4182 args->offset = i915_gem_obj_ggtt_offset(obj);
4184 drm_gem_object_unreference(&obj->base);
4186 mutex_unlock(&dev->struct_mutex);
4191 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4192 struct drm_file *file)
4194 struct drm_i915_gem_pin *args = data;
4195 struct drm_i915_gem_object *obj;
4198 ret = i915_mutex_lock_interruptible(dev);
4202 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4203 if (&obj->base == NULL) {
4208 if (obj->pin_filp != file) {
4209 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4214 obj->user_pin_count--;
4215 if (obj->user_pin_count == 0) {
4216 obj->pin_filp = NULL;
4217 i915_gem_object_ggtt_unpin(obj);
4221 drm_gem_object_unreference(&obj->base);
4223 mutex_unlock(&dev->struct_mutex);
4228 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4229 struct drm_file *file)
4231 struct drm_i915_gem_busy *args = data;
4232 struct drm_i915_gem_object *obj;
4235 ret = i915_mutex_lock_interruptible(dev);
4239 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4240 if (&obj->base == NULL) {
4245 /* Count all active objects as busy, even if they are currently not used
4246 * by the gpu. Users of this interface expect objects to eventually
4247 * become non-busy without any further actions, therefore emit any
4248 * necessary flushes here.
4250 ret = i915_gem_object_flush_active(obj);
4252 args->busy = obj->active;
4254 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4255 args->busy |= intel_ring_flag(obj->ring) << 16;
4258 drm_gem_object_unreference(&obj->base);
4260 mutex_unlock(&dev->struct_mutex);
4265 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4266 struct drm_file *file_priv)
4268 return i915_gem_ring_throttle(dev, file_priv);
4272 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4273 struct drm_file *file_priv)
4275 struct drm_i915_gem_madvise *args = data;
4276 struct drm_i915_gem_object *obj;
4279 switch (args->madv) {
4280 case I915_MADV_DONTNEED:
4281 case I915_MADV_WILLNEED:
4287 ret = i915_mutex_lock_interruptible(dev);
4291 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4292 if (&obj->base == NULL) {
4297 if (i915_gem_obj_is_pinned(obj)) {
4302 if (obj->madv != __I915_MADV_PURGED)
4303 obj->madv = args->madv;
4305 /* if the object is no longer attached, discard its backing storage */
4306 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4307 i915_gem_object_truncate(obj);
4309 args->retained = obj->madv != __I915_MADV_PURGED;
4312 drm_gem_object_unreference(&obj->base);
4314 mutex_unlock(&dev->struct_mutex);
4318 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4319 const struct drm_i915_gem_object_ops *ops)
4321 INIT_LIST_HEAD(&obj->global_list);
4322 INIT_LIST_HEAD(&obj->ring_list);
4323 INIT_LIST_HEAD(&obj->obj_exec_link);
4324 INIT_LIST_HEAD(&obj->vma_list);
4328 obj->fence_reg = I915_FENCE_REG_NONE;
4329 obj->madv = I915_MADV_WILLNEED;
4330 /* Avoid an unnecessary call to unbind on the first bind. */
4331 obj->map_and_fenceable = true;
4333 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4336 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4337 .get_pages = i915_gem_object_get_pages_gtt,
4338 .put_pages = i915_gem_object_put_pages_gtt,
4341 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4344 struct drm_i915_gem_object *obj;
4345 struct address_space *mapping;
4348 obj = i915_gem_object_alloc(dev);
4352 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4353 i915_gem_object_free(obj);
4357 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4358 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4359 /* 965gm cannot relocate objects above 4GiB. */
4360 mask &= ~__GFP_HIGHMEM;
4361 mask |= __GFP_DMA32;
4364 mapping = file_inode(obj->base.filp)->i_mapping;
4365 mapping_set_gfp_mask(mapping, mask);
4367 i915_gem_object_init(obj, &i915_gem_object_ops);
4369 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4370 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4373 /* On some devices, we can have the GPU use the LLC (the CPU
4374 * cache) for about a 10% performance improvement
4375 * compared to uncached. Graphics requests other than
4376 * display scanout are coherent with the CPU in
4377 * accessing this cache. This means in this mode we
4378 * don't need to clflush on the CPU side, and on the
4379 * GPU side we only need to flush internal caches to
4380 * get data visible to the CPU.
4382 * However, we maintain the display planes as UC, and so
4383 * need to rebind when first used as such.
4385 obj->cache_level = I915_CACHE_LLC;
4387 obj->cache_level = I915_CACHE_NONE;
4389 trace_i915_gem_object_create(obj);
4394 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4396 /* If we are the last user of the backing storage (be it shmemfs
4397 * pages or stolen etc), we know that the pages are going to be
4398 * immediately released. In this case, we can then skip copying
4399 * back the contents from the GPU.
4402 if (obj->madv != I915_MADV_WILLNEED)
4405 if (obj->base.filp == NULL)
4408 /* At first glance, this looks racy, but then again so would be
4409 * userspace racing mmap against close. However, the first external
4410 * reference to the filp can only be obtained through the
4411 * i915_gem_mmap_ioctl() which safeguards us against the user
4412 * acquiring such a reference whilst we are in the middle of
4413 * freeing the object.
4415 return atomic_long_read(&obj->base.filp->f_count) == 1;
4418 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4420 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4421 struct drm_device *dev = obj->base.dev;
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4423 struct i915_vma *vma, *next;
4425 intel_runtime_pm_get(dev_priv);
4427 trace_i915_gem_object_destroy(obj);
4429 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4433 ret = i915_vma_unbind(vma);
4434 if (WARN_ON(ret == -ERESTARTSYS)) {
4435 bool was_interruptible;
4437 was_interruptible = dev_priv->mm.interruptible;
4438 dev_priv->mm.interruptible = false;
4440 WARN_ON(i915_vma_unbind(vma));
4442 dev_priv->mm.interruptible = was_interruptible;
4446 i915_gem_object_detach_phys(obj);
4448 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4449 * before progressing. */
4451 i915_gem_object_unpin_pages(obj);
4453 if (WARN_ON(obj->pages_pin_count))
4454 obj->pages_pin_count = 0;
4455 if (discard_backing_storage(obj))
4456 obj->madv = I915_MADV_DONTNEED;
4457 i915_gem_object_put_pages(obj);
4458 i915_gem_object_free_mmap_offset(obj);
4459 i915_gem_object_release_stolen(obj);
4463 if (obj->base.import_attach)
4464 drm_prime_gem_destroy(&obj->base, NULL);
4466 if (obj->ops->release)
4467 obj->ops->release(obj);
4469 drm_gem_object_release(&obj->base);
4470 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4473 i915_gem_object_free(obj);
4475 intel_runtime_pm_put(dev_priv);
4478 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4479 struct i915_address_space *vm)
4481 struct i915_vma *vma;
4482 list_for_each_entry(vma, &obj->vma_list, vma_link)
4489 void i915_gem_vma_destroy(struct i915_vma *vma)
4491 WARN_ON(vma->node.allocated);
4493 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4494 if (!list_empty(&vma->exec_list))
4497 list_del(&vma->vma_link);
4503 i915_gem_stop_ringbuffers(struct drm_device *dev)
4505 struct drm_i915_private *dev_priv = dev->dev_private;
4506 struct intel_engine_cs *ring;
4509 for_each_ring(ring, dev_priv, i)
4510 intel_stop_ring_buffer(ring);
4514 i915_gem_suspend(struct drm_device *dev)
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4519 mutex_lock(&dev->struct_mutex);
4520 if (dev_priv->ums.mm_suspended)
4523 ret = i915_gpu_idle(dev);
4527 i915_gem_retire_requests(dev);
4529 /* Under UMS, be paranoid and evict. */
4530 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4531 i915_gem_evict_everything(dev);
4533 i915_kernel_lost_context(dev);
4534 i915_gem_stop_ringbuffers(dev);
4536 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4537 * We need to replace this with a semaphore, or something.
4538 * And not confound ums.mm_suspended!
4540 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4542 mutex_unlock(&dev->struct_mutex);
4544 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4545 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4546 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4551 mutex_unlock(&dev->struct_mutex);
4555 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4557 struct drm_device *dev = ring->dev;
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4560 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4563 if (!HAS_L3_DPF(dev) || !remap_info)
4566 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4571 * Note: We do not worry about the concurrent register cacheline hang
4572 * here because no other code should access these registers other than
4573 * at initialization time.
4575 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4576 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4577 intel_ring_emit(ring, reg_base + i);
4578 intel_ring_emit(ring, remap_info[i/4]);
4581 intel_ring_advance(ring);
4586 void i915_gem_init_swizzling(struct drm_device *dev)
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4590 if (INTEL_INFO(dev)->gen < 5 ||
4591 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4594 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4595 DISP_TILE_SURFACE_SWIZZLING);
4600 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4602 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4603 else if (IS_GEN7(dev))
4604 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4605 else if (IS_GEN8(dev))
4606 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4612 intel_enable_blt(struct drm_device *dev)
4617 /* The blitter was dysfunctional on early prototypes */
4618 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4619 DRM_INFO("BLT not supported on this pre-production hardware;"
4620 " graphics performance will be degraded.\n");
4627 static int i915_gem_init_rings(struct drm_device *dev)
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4632 ret = intel_init_render_ring_buffer(dev);
4637 ret = intel_init_bsd_ring_buffer(dev);
4639 goto cleanup_render_ring;
4642 if (intel_enable_blt(dev)) {
4643 ret = intel_init_blt_ring_buffer(dev);
4645 goto cleanup_bsd_ring;
4648 if (HAS_VEBOX(dev)) {
4649 ret = intel_init_vebox_ring_buffer(dev);
4651 goto cleanup_blt_ring;
4654 if (HAS_BSD2(dev)) {
4655 ret = intel_init_bsd2_ring_buffer(dev);
4657 goto cleanup_vebox_ring;
4660 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4662 goto cleanup_bsd2_ring;
4667 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4669 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4671 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4673 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4674 cleanup_render_ring:
4675 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4681 i915_gem_init_hw(struct drm_device *dev)
4683 struct drm_i915_private *dev_priv = dev->dev_private;
4686 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4689 if (dev_priv->ellc_size)
4690 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4692 if (IS_HASWELL(dev))
4693 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4694 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4696 if (HAS_PCH_NOP(dev)) {
4697 if (IS_IVYBRIDGE(dev)) {
4698 u32 temp = I915_READ(GEN7_MSG_CTL);
4699 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4700 I915_WRITE(GEN7_MSG_CTL, temp);
4701 } else if (INTEL_INFO(dev)->gen >= 7) {
4702 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4703 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4704 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4708 i915_gem_init_swizzling(dev);
4710 ret = i915_gem_init_rings(dev);
4714 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4715 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4718 * XXX: Contexts should only be initialized once. Doing a switch to the
4719 * default context switch however is something we'd like to do after
4720 * reset or thaw (the latter may not actually be necessary for HW, but
4721 * goes with our code better). Context switching requires rings (for
4722 * the do_switch), but before enabling PPGTT. So don't move this.
4724 ret = i915_gem_context_enable(dev_priv);
4725 if (ret && ret != -EIO) {
4726 DRM_ERROR("Context enable failed %d\n", ret);
4727 i915_gem_cleanup_ringbuffer(dev);
4733 int i915_gem_init(struct drm_device *dev)
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4738 mutex_lock(&dev->struct_mutex);
4740 if (IS_VALLEYVIEW(dev)) {
4741 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4742 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4743 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4744 VLV_GTLC_ALLOWWAKEACK), 10))
4745 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4748 i915_gem_init_userptr(dev);
4749 i915_gem_init_global_gtt(dev);
4751 ret = i915_gem_context_init(dev);
4753 mutex_unlock(&dev->struct_mutex);
4757 ret = i915_gem_init_hw(dev);
4759 /* Allow ring initialisation to fail by marking the GPU as
4760 * wedged. But we only want to do this where the GPU is angry,
4761 * for all other failure, such as an allocation failure, bail.
4763 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4764 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4767 mutex_unlock(&dev->struct_mutex);
4769 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4770 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4771 dev_priv->dri1.allow_batchbuffer = 1;
4776 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4779 struct intel_engine_cs *ring;
4782 for_each_ring(ring, dev_priv, i)
4783 intel_cleanup_ring_buffer(ring);
4787 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4788 struct drm_file *file_priv)
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4793 if (drm_core_check_feature(dev, DRIVER_MODESET))
4796 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4797 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4798 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4801 mutex_lock(&dev->struct_mutex);
4802 dev_priv->ums.mm_suspended = 0;
4804 ret = i915_gem_init_hw(dev);
4806 mutex_unlock(&dev->struct_mutex);
4810 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4812 ret = drm_irq_install(dev, dev->pdev->irq);
4814 goto cleanup_ringbuffer;
4815 mutex_unlock(&dev->struct_mutex);
4820 i915_gem_cleanup_ringbuffer(dev);
4821 dev_priv->ums.mm_suspended = 1;
4822 mutex_unlock(&dev->struct_mutex);
4828 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4829 struct drm_file *file_priv)
4831 if (drm_core_check_feature(dev, DRIVER_MODESET))
4834 mutex_lock(&dev->struct_mutex);
4835 drm_irq_uninstall(dev);
4836 mutex_unlock(&dev->struct_mutex);
4838 return i915_gem_suspend(dev);
4842 i915_gem_lastclose(struct drm_device *dev)
4846 if (drm_core_check_feature(dev, DRIVER_MODESET))
4849 ret = i915_gem_suspend(dev);
4851 DRM_ERROR("failed to idle hardware: %d\n", ret);
4855 init_ring_lists(struct intel_engine_cs *ring)
4857 INIT_LIST_HEAD(&ring->active_list);
4858 INIT_LIST_HEAD(&ring->request_list);
4861 void i915_init_vm(struct drm_i915_private *dev_priv,
4862 struct i915_address_space *vm)
4864 if (!i915_is_ggtt(vm))
4865 drm_mm_init(&vm->mm, vm->start, vm->total);
4866 vm->dev = dev_priv->dev;
4867 INIT_LIST_HEAD(&vm->active_list);
4868 INIT_LIST_HEAD(&vm->inactive_list);
4869 INIT_LIST_HEAD(&vm->global_link);
4870 list_add_tail(&vm->global_link, &dev_priv->vm_list);
4874 i915_gem_load(struct drm_device *dev)
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4880 kmem_cache_create("i915_gem_object",
4881 sizeof(struct drm_i915_gem_object), 0,
4885 INIT_LIST_HEAD(&dev_priv->vm_list);
4886 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4888 INIT_LIST_HEAD(&dev_priv->context_list);
4889 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4890 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4891 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4892 for (i = 0; i < I915_NUM_RINGS; i++)
4893 init_ring_lists(&dev_priv->ring[i]);
4894 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4895 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4896 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4897 i915_gem_retire_work_handler);
4898 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4899 i915_gem_idle_work_handler);
4900 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4902 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4903 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4904 I915_WRITE(MI_ARB_STATE,
4905 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4908 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4910 /* Old X drivers will take 0-2 for front, back, depth buffers */
4911 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4912 dev_priv->fence_reg_start = 3;
4914 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4915 dev_priv->num_fence_regs = 32;
4916 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4917 dev_priv->num_fence_regs = 16;
4919 dev_priv->num_fence_regs = 8;
4921 /* Initialize fence registers to zero */
4922 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4923 i915_gem_restore_fences(dev);
4925 i915_gem_detect_bit_6_swizzle(dev);
4926 init_waitqueue_head(&dev_priv->pending_flip_queue);
4928 dev_priv->mm.interruptible = true;
4930 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4931 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4932 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4933 register_shrinker(&dev_priv->mm.shrinker);
4935 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4936 register_oom_notifier(&dev_priv->mm.oom_notifier);
4939 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4941 struct drm_i915_file_private *file_priv = file->driver_priv;
4943 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4945 /* Clean up our request list when the client is going away, so that
4946 * later retire_requests won't dereference our soon-to-be-gone
4949 spin_lock(&file_priv->mm.lock);
4950 while (!list_empty(&file_priv->mm.request_list)) {
4951 struct drm_i915_gem_request *request;
4953 request = list_first_entry(&file_priv->mm.request_list,
4954 struct drm_i915_gem_request,
4956 list_del(&request->client_list);
4957 request->file_priv = NULL;
4959 spin_unlock(&file_priv->mm.lock);
4963 i915_gem_file_idle_work_handler(struct work_struct *work)
4965 struct drm_i915_file_private *file_priv =
4966 container_of(work, typeof(*file_priv), mm.idle_work.work);
4968 atomic_set(&file_priv->rps_wait_boost, false);
4971 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4973 struct drm_i915_file_private *file_priv;
4976 DRM_DEBUG_DRIVER("\n");
4978 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4982 file->driver_priv = file_priv;
4983 file_priv->dev_priv = dev->dev_private;
4984 file_priv->file = file;
4986 spin_lock_init(&file_priv->mm.lock);
4987 INIT_LIST_HEAD(&file_priv->mm.request_list);
4988 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4989 i915_gem_file_idle_work_handler);
4991 ret = i915_gem_context_open(dev, file);
4998 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5000 if (!mutex_is_locked(mutex))
5003 #if defined(CONFIG_SMP) && !defined(CONFIG_DEBUG_MUTEXES)
5004 return mutex->owner == task;
5006 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5011 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5013 if (!mutex_trylock(&dev->struct_mutex)) {
5014 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5017 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5027 static int num_vma_bound(struct drm_i915_gem_object *obj)
5029 struct i915_vma *vma;
5032 list_for_each_entry(vma, &obj->vma_list, vma_link)
5033 if (drm_mm_node_allocated(&vma->node))
5039 static unsigned long
5040 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5042 struct drm_i915_private *dev_priv =
5043 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5044 struct drm_device *dev = dev_priv->dev;
5045 struct drm_i915_gem_object *obj;
5046 unsigned long count;
5049 if (!i915_gem_shrinker_lock(dev, &unlock))
5053 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5054 if (obj->pages_pin_count == 0)
5055 count += obj->base.size >> PAGE_SHIFT;
5057 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5058 if (!i915_gem_obj_is_pinned(obj) &&
5059 obj->pages_pin_count == num_vma_bound(obj))
5060 count += obj->base.size >> PAGE_SHIFT;
5064 mutex_unlock(&dev->struct_mutex);
5069 /* All the new VM stuff */
5070 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5071 struct i915_address_space *vm)
5073 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5074 struct i915_vma *vma;
5076 if (!dev_priv->mm.aliasing_ppgtt ||
5077 vm == &dev_priv->mm.aliasing_ppgtt->base)
5078 vm = &dev_priv->gtt.base;
5080 BUG_ON(list_empty(&o->vma_list));
5081 list_for_each_entry(vma, &o->vma_list, vma_link) {
5083 return vma->node.start;
5089 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5090 struct i915_address_space *vm)
5092 struct i915_vma *vma;
5094 list_for_each_entry(vma, &o->vma_list, vma_link)
5095 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5101 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5103 struct i915_vma *vma;
5105 list_for_each_entry(vma, &o->vma_list, vma_link)
5106 if (drm_mm_node_allocated(&vma->node))
5112 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5113 struct i915_address_space *vm)
5115 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5116 struct i915_vma *vma;
5118 if (!dev_priv->mm.aliasing_ppgtt ||
5119 vm == &dev_priv->mm.aliasing_ppgtt->base)
5120 vm = &dev_priv->gtt.base;
5122 BUG_ON(list_empty(&o->vma_list));
5124 list_for_each_entry(vma, &o->vma_list, vma_link)
5126 return vma->node.size;
5131 static unsigned long
5132 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5134 struct drm_i915_private *dev_priv =
5135 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5136 struct drm_device *dev = dev_priv->dev;
5137 unsigned long freed;
5140 if (!i915_gem_shrinker_lock(dev, &unlock))
5143 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5144 if (freed < sc->nr_to_scan)
5145 freed += __i915_gem_shrink(dev_priv,
5146 sc->nr_to_scan - freed,
5149 mutex_unlock(&dev->struct_mutex);
5155 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5157 struct drm_i915_private *dev_priv =
5158 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5159 struct drm_device *dev = dev_priv->dev;
5160 struct drm_i915_gem_object *obj;
5161 unsigned long timeout = msecs_to_jiffies(5000) + 1;
5162 unsigned long pinned, bound, unbound, freed;
5163 bool was_interruptible;
5166 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout)
5167 schedule_timeout_killable(1);
5169 pr_err("Unable to purge GPU memory due lock contention.\n");
5173 was_interruptible = dev_priv->mm.interruptible;
5174 dev_priv->mm.interruptible = false;
5176 freed = i915_gem_shrink_all(dev_priv);
5178 dev_priv->mm.interruptible = was_interruptible;
5180 /* Because we may be allocating inside our own driver, we cannot
5181 * assert that there are no objects with pinned pages that are not
5182 * being pointed to by hardware.
5184 unbound = bound = pinned = 0;
5185 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5186 if (!obj->base.filp) /* not backed by a freeable object */
5189 if (obj->pages_pin_count)
5190 pinned += obj->base.size;
5192 unbound += obj->base.size;
5194 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5195 if (!obj->base.filp)
5198 if (obj->pages_pin_count)
5199 pinned += obj->base.size;
5201 bound += obj->base.size;
5205 mutex_unlock(&dev->struct_mutex);
5207 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5209 if (unbound || bound)
5210 pr_err("%lu and %lu bytes still available in the "
5211 "bound and unbound GPU page lists.\n",
5214 *(unsigned long *)ptr += freed;
5218 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5220 struct i915_vma *vma;
5222 /* This WARN has probably outlived its usefulness (callers already
5223 * WARN if they don't find the GGTT vma they expect). When removing,
5224 * remember to remove the pre-check in is_pin_display() as well */
5225 if (WARN_ON(list_empty(&obj->vma_list)))
5228 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5229 if (vma->vm != obj_to_ggtt(obj))