drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <linux/pm_runtime.h>
  40 #include <drm/drm_crtc_helper.h>
  41
  42 static struct drm_driver driver;
  43
  44 #define GEN_DEFAULT_PIPEOFFSETS \
  45         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  46                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  47         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  48                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  49         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
  50         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
  51         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  52
  53 #define GEN_CHV_PIPEOFFSETS \
  54         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  55                           CHV_PIPE_C_OFFSET }, \
  56         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  57                            CHV_TRANSCODER_C_OFFSET, }, \
  58         .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
  59                           CHV_DPLL_C_OFFSET }, \
  60         .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
  61                              CHV_DPLL_C_MD_OFFSET }, \
  62         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  63                              CHV_PALETTE_C_OFFSET }
  64
  65 #define CURSOR_OFFSETS \
  66         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  67
  68 #define IVB_CURSOR_OFFSETS \
  69         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  70
  71 static const struct intel_device_info intel_i830_info = {
  72         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  73         .has_overlay = 1, .overlay_needs_physical = 1,
  74         .ring_mask = RENDER_RING,
  75         GEN_DEFAULT_PIPEOFFSETS,
  76         CURSOR_OFFSETS,
  77 };
  78
  79 static const struct intel_device_info intel_845g_info = {
  80         .gen = 2, .num_pipes = 1,
  81         .has_overlay = 1, .overlay_needs_physical = 1,
  82         .ring_mask = RENDER_RING,
  83         GEN_DEFAULT_PIPEOFFSETS,
  84         CURSOR_OFFSETS,
  85 };
  86
  87 static const struct intel_device_info intel_i85x_info = {
  88         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  89         .cursor_needs_physical = 1,
  90         .has_overlay = 1, .overlay_needs_physical = 1,
  91         .has_fbc = 1,
  92         .ring_mask = RENDER_RING,
  93         GEN_DEFAULT_PIPEOFFSETS,
  94         CURSOR_OFFSETS,
  95 };
  96
  97 static const struct intel_device_info intel_i865g_info = {
  98         .gen = 2, .num_pipes = 1,
  99         .has_overlay = 1, .overlay_needs_physical = 1,
 100         .ring_mask = RENDER_RING,
 101         GEN_DEFAULT_PIPEOFFSETS,
 102         CURSOR_OFFSETS,
 103 };
 104
 105 static const struct intel_device_info intel_i915g_info = {
 106         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 107         .has_overlay = 1, .overlay_needs_physical = 1,
 108         .ring_mask = RENDER_RING,
 109         GEN_DEFAULT_PIPEOFFSETS,
 110         CURSOR_OFFSETS,
 111 };
 112 static const struct intel_device_info intel_i915gm_info = {
 113         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 114         .cursor_needs_physical = 1,
 115         .has_overlay = 1, .overlay_needs_physical = 1,
 116         .supports_tv = 1,
 117         .has_fbc = 1,
 118         .ring_mask = RENDER_RING,
 119         GEN_DEFAULT_PIPEOFFSETS,
 120         CURSOR_OFFSETS,
 121 };
 122 static const struct intel_device_info intel_i945g_info = {
 123         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 124         .has_overlay = 1, .overlay_needs_physical = 1,
 125         .ring_mask = RENDER_RING,
 126         GEN_DEFAULT_PIPEOFFSETS,
 127         CURSOR_OFFSETS,
 128 };
 129 static const struct intel_device_info intel_i945gm_info = {
 130         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 131         .has_hotplug = 1, .cursor_needs_physical = 1,
 132         .has_overlay = 1, .overlay_needs_physical = 1,
 133         .supports_tv = 1,
 134         .has_fbc = 1,
 135         .ring_mask = RENDER_RING,
 136         GEN_DEFAULT_PIPEOFFSETS,
 137         CURSOR_OFFSETS,
 138 };
 139
 140 static const struct intel_device_info intel_i965g_info = {
 141         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 142         .has_hotplug = 1,
 143         .has_overlay = 1,
 144         .ring_mask = RENDER_RING,
 145         GEN_DEFAULT_PIPEOFFSETS,
 146         CURSOR_OFFSETS,
 147 };
 148
 149 static const struct intel_device_info intel_i965gm_info = {
 150         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 151         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 152         .has_overlay = 1,
 153         .supports_tv = 1,
 154         .ring_mask = RENDER_RING,
 155         GEN_DEFAULT_PIPEOFFSETS,
 156         CURSOR_OFFSETS,
 157 };
 158
 159 static const struct intel_device_info intel_g33_info = {
 160         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 161         .need_gfx_hws = 1, .has_hotplug = 1,
 162         .has_overlay = 1,
 163         .ring_mask = RENDER_RING,
 164         GEN_DEFAULT_PIPEOFFSETS,
 165         CURSOR_OFFSETS,
 166 };
 167
 168 static const struct intel_device_info intel_g45_info = {
 169         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 170         .has_pipe_cxsr = 1, .has_hotplug = 1,
 171         .ring_mask = RENDER_RING | BSD_RING,
 172         GEN_DEFAULT_PIPEOFFSETS,
 173         CURSOR_OFFSETS,
 174 };
 175
 176 static const struct intel_device_info intel_gm45_info = {
 177         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 178         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 179         .has_pipe_cxsr = 1, .has_hotplug = 1,
 180         .supports_tv = 1,
 181         .ring_mask = RENDER_RING | BSD_RING,
 182         GEN_DEFAULT_PIPEOFFSETS,
 183         CURSOR_OFFSETS,
 184 };
 185
 186 static const struct intel_device_info intel_pineview_info = {
 187         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 188         .need_gfx_hws = 1, .has_hotplug = 1,
 189         .has_overlay = 1,
 190         GEN_DEFAULT_PIPEOFFSETS,
 191         CURSOR_OFFSETS,
 192 };
 193
 194 static const struct intel_device_info intel_ironlake_d_info = {
 195         .gen = 5, .num_pipes = 2,
 196         .need_gfx_hws = 1, .has_hotplug = 1,
 197         .ring_mask = RENDER_RING | BSD_RING,
 198         GEN_DEFAULT_PIPEOFFSETS,
 199         CURSOR_OFFSETS,
 200 };
 201
 202 static const struct intel_device_info intel_ironlake_m_info = {
 203         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 204         .need_gfx_hws = 1, .has_hotplug = 1,
 205         .has_fbc = 1,
 206         .ring_mask = RENDER_RING | BSD_RING,
 207         GEN_DEFAULT_PIPEOFFSETS,
 208         CURSOR_OFFSETS,
 209 };
 210
 211 static const struct intel_device_info intel_sandybridge_d_info = {
 212         .gen = 6, .num_pipes = 2,
 213         .need_gfx_hws = 1, .has_hotplug = 1,
 214         .has_fbc = 1,
 215         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 216         .has_llc = 1,
 217         GEN_DEFAULT_PIPEOFFSETS,
 218         CURSOR_OFFSETS,
 219 };
 220
 221 static const struct intel_device_info intel_sandybridge_m_info = {
 222         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_fbc = 1,
 225         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 226         .has_llc = 1,
 227         GEN_DEFAULT_PIPEOFFSETS,
 228         CURSOR_OFFSETS,
 229 };
 230
 231 #define GEN7_FEATURES  \
 232         .gen = 7, .num_pipes = 3, \
 233         .need_gfx_hws = 1, .has_hotplug = 1, \
 234         .has_fbc = 1, \
 235         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 236         .has_llc = 1
 237
 238 static const struct intel_device_info intel_ivybridge_d_info = {
 239         GEN7_FEATURES,
 240         .is_ivybridge = 1,
 241         GEN_DEFAULT_PIPEOFFSETS,
 242         IVB_CURSOR_OFFSETS,
 243 };
 244
 245 static const struct intel_device_info intel_ivybridge_m_info = {
 246         GEN7_FEATURES,
 247         .is_ivybridge = 1,
 248         .is_mobile = 1,
 249         GEN_DEFAULT_PIPEOFFSETS,
 250         IVB_CURSOR_OFFSETS,
 251 };
 252
 253 static const struct intel_device_info intel_ivybridge_q_info = {
 254         GEN7_FEATURES,
 255         .is_ivybridge = 1,
 256         .num_pipes = 0, /* legal, last one wins */
 257         GEN_DEFAULT_PIPEOFFSETS,
 258         IVB_CURSOR_OFFSETS,
 259 };
 260
 261 static const struct intel_device_info intel_valleyview_m_info = {
 262         GEN7_FEATURES,
 263         .is_mobile = 1,
 264         .num_pipes = 2,
 265         .is_valleyview = 1,
 266         .display_mmio_offset = VLV_DISPLAY_BASE,
 267         .has_fbc = 0, /* legal, last one wins */
 268         .has_llc = 0, /* legal, last one wins */
 269         GEN_DEFAULT_PIPEOFFSETS,
 270         CURSOR_OFFSETS,
 271 };
 272
 273 static const struct intel_device_info intel_valleyview_d_info = {
 274         GEN7_FEATURES,
 275         .num_pipes = 2,
 276         .is_valleyview = 1,
 277         .display_mmio_offset = VLV_DISPLAY_BASE,
 278         .has_fbc = 0, /* legal, last one wins */
 279         .has_llc = 0, /* legal, last one wins */
 280         GEN_DEFAULT_PIPEOFFSETS,
 281         CURSOR_OFFSETS,
 282 };
 283
 284 static const struct intel_device_info intel_haswell_d_info = {
 285         GEN7_FEATURES,
 286         .is_haswell = 1,
 287         .has_ddi = 1,
 288         .has_fpga_dbg = 1,
 289         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 290         GEN_DEFAULT_PIPEOFFSETS,
 291         IVB_CURSOR_OFFSETS,
 292 };
 293
 294 static const struct intel_device_info intel_haswell_m_info = {
 295         GEN7_FEATURES,
 296         .is_haswell = 1,
 297         .is_mobile = 1,
 298         .has_ddi = 1,
 299         .has_fpga_dbg = 1,
 300         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 301         GEN_DEFAULT_PIPEOFFSETS,
 302         IVB_CURSOR_OFFSETS,
 303 };
 304
 305 static const struct intel_device_info intel_broadwell_d_info = {
 306         .gen = 8, .num_pipes = 3,
 307         .need_gfx_hws = 1, .has_hotplug = 1,
 308         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 309         .has_llc = 1,
 310         .has_ddi = 1,
 311         .has_fbc = 1,
 312         GEN_DEFAULT_PIPEOFFSETS,
 313         IVB_CURSOR_OFFSETS,
 314 };
 315
 316 static const struct intel_device_info intel_broadwell_m_info = {
 317         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 318         .need_gfx_hws = 1, .has_hotplug = 1,
 319         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 320         .has_llc = 1,
 321         .has_ddi = 1,
 322         .has_fbc = 1,
 323         GEN_DEFAULT_PIPEOFFSETS,
 324         IVB_CURSOR_OFFSETS,
 325 };
 326
 327 static const struct intel_device_info intel_broadwell_gt3d_info = {
 328         .gen = 8, .num_pipes = 3,
 329         .need_gfx_hws = 1, .has_hotplug = 1,
 330         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 331         .has_llc = 1,
 332         .has_ddi = 1,
 333         .has_fbc = 1,
 334         GEN_DEFAULT_PIPEOFFSETS,
 335         IVB_CURSOR_OFFSETS,
 336 };
 337
 338 static const struct intel_device_info intel_broadwell_gt3m_info = {
 339         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 340         .need_gfx_hws = 1, .has_hotplug = 1,
 341         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 342         .has_llc = 1,
 343         .has_ddi = 1,
 344         .has_fbc = 1,
 345         GEN_DEFAULT_PIPEOFFSETS,
 346         IVB_CURSOR_OFFSETS,
 347 };
 348
 349 static const struct intel_device_info intel_cherryview_info = {
 350         .is_preliminary = 1,
 351         .gen = 8, .num_pipes = 3,
 352         .need_gfx_hws = 1, .has_hotplug = 1,
 353         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 354         .is_valleyview = 1,
 355         .display_mmio_offset = VLV_DISPLAY_BASE,
 356         GEN_CHV_PIPEOFFSETS,
 357         CURSOR_OFFSETS,
 358 };
 359
 360 /*
 361  * Make sure any device matches here are from most specific to most
 362  * general.  For example, since the Quanta match is based on the subsystem
 363  * and subvendor IDs, we need it to come before the more general IVB
 364  * PCI ID matches, otherwise we'll use the wrong info struct above.
 365  */
 366 #define INTEL_PCI_IDS \
 367         INTEL_I830_IDS(&intel_i830_info),       \
 368         INTEL_I845G_IDS(&intel_845g_info),      \
 369         INTEL_I85X_IDS(&intel_i85x_info),       \
 370         INTEL_I865G_IDS(&intel_i865g_info),     \
 371         INTEL_I915G_IDS(&intel_i915g_info),     \
 372         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 373         INTEL_I945G_IDS(&intel_i945g_info),     \
 374         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 375         INTEL_I965G_IDS(&intel_i965g_info),     \
 376         INTEL_G33_IDS(&intel_g33_info),         \
 377         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 378         INTEL_GM45_IDS(&intel_gm45_info),       \
 379         INTEL_G45_IDS(&intel_g45_info),         \
 380         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 381         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 382         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 383         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 384         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 385         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 386         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 387         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 388         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 389         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 390         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 391         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 392         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 393         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 394         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 395         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 396         INTEL_CHV_IDS(&intel_cherryview_info)
 397
 398 static const struct pci_device_id pciidlist[] = {               /* aka */
 399         INTEL_PCI_IDS,
 400         {0, 0, 0}
 401 };
 402
 403 #if defined(CONFIG_DRM_I915_KMS)
 404 MODULE_DEVICE_TABLE(pci, pciidlist);
 405 #endif
 406
 407 void intel_detect_pch(struct drm_device *dev)
 408 {
 409         struct drm_i915_private *dev_priv = dev->dev_private;
 410         struct pci_dev *pch = NULL;
 411
 412         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 413          * (which really amounts to a PCH but no South Display).
 414          */
 415         if (INTEL_INFO(dev)->num_pipes == 0) {
 416                 dev_priv->pch_type = PCH_NOP;
 417                 return;
 418         }
 419
 420         /*
 421          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 422          * make graphics device passthrough work easy for VMM, that only
 423          * need to expose ISA bridge to let driver know the real hardware
 424          * underneath. This is a requirement from virtualization team.
 425          *
 426          * In some virtualized environments (e.g. XEN), there is irrelevant
 427          * ISA bridge in the system. To work reliably, we should scan trhough
 428          * all the ISA bridge devices and check for the first match, instead
 429          * of only checking the first one.
 430          */
 431         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 432                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 433                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 434                         dev_priv->pch_id = id;
 435
 436                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 437                                 dev_priv->pch_type = PCH_IBX;
 438                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 439                                 WARN_ON(!IS_GEN5(dev));
 440                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 441                                 dev_priv->pch_type = PCH_CPT;
 442                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 443                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 444                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 445                                 /* PantherPoint is CPT compatible */
 446                                 dev_priv->pch_type = PCH_CPT;
 447                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 448                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 449                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 450                                 dev_priv->pch_type = PCH_LPT;
 451                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 452                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 453                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 454                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 455                                 dev_priv->pch_type = PCH_LPT;
 456                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 457                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 458                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 459                         } else
 460                                 continue;
 461
 462                         break;
 463                 }
 464         }
 465         if (!pch)
 466                 DRM_DEBUG_KMS("No PCH found.\n");
 467
 468         pci_dev_put(pch);
 469 }
 470
 471 bool i915_semaphore_is_enabled(struct drm_device *dev)
 472 {
 473         if (INTEL_INFO(dev)->gen < 6)
 474                 return false;
 475
 476         if (i915.semaphores >= 0)
 477                 return i915.semaphores;
 478
 479         /* Until we get further testing... */
 480         if (IS_GEN8(dev))
 481                 return false;
 482
 483 #ifdef CONFIG_INTEL_IOMMU
 484         /* Enable semaphores on SNB when IO remapping is off */
 485         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 486                 return false;
 487 #endif
 488
 489         return true;
 490 }
 491
 492 static int i915_drm_freeze(struct drm_device *dev)
 493 {
 494         struct drm_i915_private *dev_priv = dev->dev_private;
 495         struct drm_crtc *crtc;
 496
 497         intel_runtime_pm_get(dev_priv);
 498
 499         /* ignore lid events during suspend */
 500         mutex_lock(&dev_priv->modeset_restore_lock);
 501         dev_priv->modeset_restore = MODESET_SUSPENDED;
 502         mutex_unlock(&dev_priv->modeset_restore_lock);
 503
 504         /* We do a lot of poking in a lot of registers, make sure they work
 505          * properly. */
 506         intel_display_set_init_power(dev_priv, true);
 507
 508         drm_kms_helper_poll_disable(dev);
 509
 510         pci_save_state(dev->pdev);
 511
 512         /* If KMS is active, we do the leavevt stuff here */
 513         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 514                 int error;
 515
 516                 error = i915_gem_suspend(dev);
 517                 if (error) {
 518                         dev_err(&dev->pdev->dev,
 519                                 "GEM idle failed, resume might fail\n");
 520                         return error;
 521                 }
 522
 523                 drm_irq_uninstall(dev);
 524                 dev_priv->enable_hotplug_processing = false;
 525
 526                 intel_disable_gt_powersave(dev);
 527
 528                 /*
 529                  * Disable CRTCs directly since we want to preserve sw state
 530                  * for _thaw.
 531                  */
 532                 drm_modeset_lock_all(dev);
 533                 for_each_crtc(dev, crtc) {
 534                         dev_priv->display.crtc_disable(crtc);
 535                 }
 536                 drm_modeset_unlock_all(dev);
 537
 538                 intel_modeset_suspend_hw(dev);
 539         }
 540
 541         i915_gem_suspend_gtt_mappings(dev);
 542
 543         i915_save_state(dev);
 544
 545         intel_opregion_fini(dev);
 546         intel_uncore_fini(dev);
 547
 548         console_lock();
 549         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 550         console_unlock();
 551
 552         dev_priv->suspend_count++;
 553
 554         return 0;
 555 }
 556
 557 int i915_suspend(struct drm_device *dev, pm_message_t state)
 558 {
 559         int error;
 560
 561         if (!dev || !dev->dev_private) {
 562                 DRM_ERROR("dev: %p\n", dev);
 563                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 564                 return -ENODEV;
 565         }
 566
 567         if (state.event == PM_EVENT_PRETHAW)
 568                 return 0;
 569
 570
 571         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 572                 return 0;
 573
 574         error = i915_drm_freeze(dev);
 575         if (error)
 576                 return error;
 577
 578         if (state.event == PM_EVENT_SUSPEND) {
 579                 /* Shut down the device */
 580                 pci_disable_device(dev->pdev);
 581                 pci_set_power_state(dev->pdev, PCI_D3hot);
 582         }
 583
 584         return 0;
 585 }
 586
 587 void intel_console_resume(struct work_struct *work)
 588 {
 589         struct drm_i915_private *dev_priv =
 590                 container_of(work, struct drm_i915_private,
 591                              console_resume_work);
 592         struct drm_device *dev = dev_priv->dev;
 593
 594         console_lock();
 595         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 596         console_unlock();
 597 }
 598
 599 static int i915_drm_thaw_early(struct drm_device *dev)
 600 {
 601         struct drm_i915_private *dev_priv = dev->dev_private;
 602
 603         intel_uncore_early_sanitize(dev);
 604         intel_uncore_sanitize(dev);
 605         intel_power_domains_init_hw(dev_priv);
 606
 607         i915_rc6_ctx_wa_resume(dev_priv);
 608
 609         return 0;
 610 }
 611
 612 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 613 {
 614         struct drm_i915_private *dev_priv = dev->dev_private;
 615
 616         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 617             restore_gtt_mappings) {
 618                 mutex_lock(&dev->struct_mutex);
 619                 i915_gem_restore_gtt_mappings(dev);
 620                 mutex_unlock(&dev->struct_mutex);
 621         }
 622
 623         i915_restore_state(dev);
 624         intel_opregion_setup(dev);
 625
 626         /* KMS EnterVT equivalent */
 627         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 628                 intel_init_pch_refclk(dev);
 629                 drm_mode_config_reset(dev);
 630
 631                 mutex_lock(&dev->struct_mutex);
 632                 if (i915_gem_init_hw(dev)) {
 633                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 634                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 635                 }
 636                 mutex_unlock(&dev->struct_mutex);
 637
 638                 /* We need working interrupts for modeset enabling ... */
 639                 drm_irq_install(dev, dev->pdev->irq);
 640
 641                 intel_modeset_init_hw(dev);
 642
 643                 drm_modeset_lock_all(dev);
 644                 intel_modeset_setup_hw_state(dev, true);
 645                 drm_modeset_unlock_all(dev);
 646
 647                 /*
 648                  * ... but also need to make sure that hotplug processing
 649                  * doesn't cause havoc. Like in the driver load code we don't
 650                  * bother with the tiny race here where we might loose hotplug
 651                  * notifications.
 652                  * */
 653                 intel_hpd_init(dev);
 654                 dev_priv->enable_hotplug_processing = true;
 655                 /* Config may have changed between suspend and resume */
 656                 drm_helper_hpd_irq_event(dev);
 657         }
 658
 659         intel_opregion_init(dev);
 660
 661         /*
 662          * The console lock can be pretty contented on resume due
 663          * to all the printk activity.  Try to keep it out of the hot
 664          * path of resume if possible.
 665          */
 666         if (console_trylock()) {
 667                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 668                 console_unlock();
 669         } else {
 670                 schedule_work(&dev_priv->console_resume_work);
 671         }
 672
 673         mutex_lock(&dev_priv->modeset_restore_lock);
 674         dev_priv->modeset_restore = MODESET_DONE;
 675         mutex_unlock(&dev_priv->modeset_restore_lock);
 676
 677         intel_runtime_pm_put(dev_priv);
 678         return 0;
 679 }
 680
 681 static int i915_drm_thaw(struct drm_device *dev)
 682 {
 683         if (drm_core_check_feature(dev, DRIVER_MODESET))
 684                 i915_check_and_clear_faults(dev);
 685
 686         return __i915_drm_thaw(dev, true);
 687 }
 688
 689 static int i915_resume_early(struct drm_device *dev)
 690 {
 691         int ret;
 692
 693         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 694                 return 0;
 695
 696         /*
 697          * We have a resume ordering issue with the snd-hda driver also
 698          * requiring our device to be power up. Due to the lack of a
 699          * parent/child relationship we currently solve this with an early
 700          * resume hook.
 701          *
 702          * FIXME: This should be solved with a special hdmi sink device or
 703          * similar so that power domains can be employed.
 704          */
 705
 706         /*
 707          * Note that we need to set the power state explicitly, since we
 708          * powered off the device during freeze and the PCI core won't power
 709          * it back up for us during thaw. Powering off the device during
 710          * freeze is not a hard requirement though, and during the
 711          * suspend/resume phases the PCI core makes sure we get here with the
 712          * device powered on. So in case we change our freeze logic and keep
 713          * the device powered we can also remove the following set power state
 714          * call.
 715          */
 716         ret = pci_set_power_state(dev->pdev, PCI_D0);
 717         if (ret) {
 718                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
 719                 return ret;
 720         }
 721
 722         /*
 723          * Note that pci_enable_device() first enables any parent bridge
 724          * device and only then sets the power state for this device. The
 725          * bridge enabling is a nop though, since bridge devices are resumed
 726          * first. The order of enabling power and enabling the device is
 727          * imposed by the PCI core as described above, so here we preserve the
 728          * same order for the freeze/thaw phases.
 729          *
 730          * TODO: eventually we should remove pci_disable_device() /
 731          * pci_enable_enable_device() from suspend/resume. Due to how they
 732          * depend on the device enable refcount we can't anyway depend on them
 733          * disabling/enabling the device.
 734          */
 735         if (pci_enable_device(dev->pdev))
 736                 return -EIO;
 737
 738         pci_set_master(dev->pdev);
 739
 740         return i915_drm_thaw_early(dev);
 741 }
 742
 743 int i915_resume(struct drm_device *dev)
 744 {
 745         struct drm_i915_private *dev_priv = dev->dev_private;
 746         int ret;
 747
 748         /*
 749          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 750          * earlier) need to restore the GTT mappings since the BIOS might clear
 751          * all our scratch PTEs.
 752          */
 753         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 754         if (ret)
 755                 return ret;
 756
 757         drm_kms_helper_poll_enable(dev);
 758         return 0;
 759 }
 760
 761 static int i915_resume_legacy(struct drm_device *dev)
 762 {
 763         i915_resume_early(dev);
 764         i915_resume(dev);
 765
 766         return 0;
 767 }
 768
 769 /**
 770  * i915_reset - reset chip after a hang
 771  * @dev: drm device to reset
 772  *
 773  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 774  * reset or otherwise an error code.
 775  *
 776  * Procedure is fairly simple:
 777  *   - reset the chip using the reset reg
 778  *   - re-init context state
 779  *   - re-init hardware status page
 780  *   - re-init ring buffer
 781  *   - re-init interrupt state
 782  *   - re-init display
 783  */
 784 int i915_reset(struct drm_device *dev)
 785 {
 786         struct drm_i915_private *dev_priv = dev->dev_private;
 787         bool simulated;
 788         int ret;
 789
 790         if (!i915.reset)
 791                 return 0;
 792
 793         mutex_lock(&dev->struct_mutex);
 794
 795         i915_gem_reset(dev);
 796
 797         simulated = dev_priv->gpu_error.stop_rings != 0;
 798
 799         ret = intel_gpu_reset(dev);
 800
 801         /* Also reset the gpu hangman. */
 802         if (simulated) {
 803                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 804                 dev_priv->gpu_error.stop_rings = 0;
 805                 if (ret == -ENODEV) {
 806                         DRM_INFO("Reset not implemented, but ignoring "
 807                                  "error for simulated gpu hangs\n");
 808                         ret = 0;
 809                 }
 810         }
 811
 812         if (ret) {
 813                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 814                 mutex_unlock(&dev->struct_mutex);
 815                 return ret;
 816         }
 817
 818         /* Ok, now get things going again... */
 819
 820         /*
 821          * Everything depends on having the GTT running, so we need to start
 822          * there.  Fortunately we don't need to do this unless we reset the
 823          * chip at a PCI level.
 824          *
 825          * Next we need to restore the context, but we don't use those
 826          * yet either...
 827          *
 828          * Ring buffer needs to be re-initialized in the KMS case, or if X
 829          * was running at the time of the reset (i.e. we weren't VT
 830          * switched away).
 831          */
 832         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 833                         !dev_priv->ums.mm_suspended) {
 834                 dev_priv->ums.mm_suspended = 0;
 835
 836                 ret = i915_gem_init_hw(dev);
 837                 mutex_unlock(&dev->struct_mutex);
 838                 if (ret) {
 839                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 840                         return ret;
 841                 }
 842
 843                 /*
 844                  * FIXME: This races pretty badly against concurrent holders of
 845                  * ring interrupts. This is possible since we've started to drop
 846                  * dev->struct_mutex in select places when waiting for the gpu.
 847                  */
 848
 849                 /*
 850                  * rps/rc6 re-init is necessary to restore state lost after the
 851                  * reset and the re-install of gt irqs. Skip for ironlake per
 852                  * previous concerns that it doesn't respond well to some forms
 853                  * of re-init after reset.
 854                  */
 855                 if (INTEL_INFO(dev)->gen > 5)
 856                         intel_reset_gt_powersave(dev);
 857
 858                 intel_hpd_init(dev);
 859         } else {
 860                 mutex_unlock(&dev->struct_mutex);
 861         }
 862
 863         return 0;
 864 }
 865
 866 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 867 {
 868         struct intel_device_info *intel_info =
 869                 (struct intel_device_info *) ent->driver_data;
 870
 871         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 872                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 873                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 874                 return -ENODEV;
 875         }
 876
 877         /* Only bind to function 0 of the device. Early generations
 878          * used function 1 as a placeholder for multi-head. This causes
 879          * us confusion instead, especially on the systems where both
 880          * functions have the same PCI-ID!
 881          */
 882         if (PCI_FUNC(pdev->devfn))
 883                 return -ENODEV;
 884
 885         driver.driver_features &= ~(DRIVER_USE_AGP);
 886
 887         return drm_get_pci_dev(pdev, ent, &driver);
 888 }
 889
 890 static void
 891 i915_pci_remove(struct pci_dev *pdev)
 892 {
 893         struct drm_device *dev = pci_get_drvdata(pdev);
 894
 895         drm_put_dev(dev);
 896 }
 897
 898 static int i915_pm_suspend(struct device *dev)
 899 {
 900         struct pci_dev *pdev = to_pci_dev(dev);
 901         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 902
 903         if (!drm_dev || !drm_dev->dev_private) {
 904                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 905                 return -ENODEV;
 906         }
 907
 908         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 909                 return 0;
 910
 911         return i915_drm_freeze(drm_dev);
 912 }
 913
 914 static int i915_pm_suspend_late(struct device *dev)
 915 {
 916         struct pci_dev *pdev = to_pci_dev(dev);
 917         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 918
 919         /*
 920          * We have a suspedn ordering issue with the snd-hda driver also
 921          * requiring our device to be power up. Due to the lack of a
 922          * parent/child relationship we currently solve this with an late
 923          * suspend hook.
 924          *
 925          * FIXME: This should be solved with a special hdmi sink device or
 926          * similar so that power domains can be employed.
 927          */
 928         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 929                 return 0;
 930
 931         i915_rc6_ctx_wa_suspend(to_i915(drm_dev));
 932
 933         pci_disable_device(pdev);
 934         pci_set_power_state(pdev, PCI_D3hot);
 935
 936         return 0;
 937 }
 938
 939 static int i915_pm_resume_early(struct device *dev)
 940 {
 941         struct pci_dev *pdev = to_pci_dev(dev);
 942         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 943
 944         return i915_resume_early(drm_dev);
 945 }
 946
 947 static int i915_pm_resume(struct device *dev)
 948 {
 949         struct pci_dev *pdev = to_pci_dev(dev);
 950         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 951
 952         return i915_resume(drm_dev);
 953 }
 954
 955 static int i915_pm_freeze(struct device *dev)
 956 {
 957         struct pci_dev *pdev = to_pci_dev(dev);
 958         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 959
 960         if (!drm_dev || !drm_dev->dev_private) {
 961                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 962                 return -ENODEV;
 963         }
 964
 965         return i915_drm_freeze(drm_dev);
 966 }
 967
 968 static int i915_pm_thaw_early(struct device *dev)
 969 {
 970         struct pci_dev *pdev = to_pci_dev(dev);
 971         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 972
 973         return i915_drm_thaw_early(drm_dev);
 974 }
 975
 976 static int i915_pm_thaw(struct device *dev)
 977 {
 978         struct pci_dev *pdev = to_pci_dev(dev);
 979         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 980
 981         return i915_drm_thaw(drm_dev);
 982 }
 983
 984 static int i915_pm_poweroff(struct device *dev)
 985 {
 986         struct pci_dev *pdev = to_pci_dev(dev);
 987         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 988
 989         return i915_drm_freeze(drm_dev);
 990 }
 991
 992 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 993 {
 994         hsw_enable_pc8(dev_priv);
 995
 996         return 0;
 997 }
 998
 999 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
1000 {
1001         struct drm_device *dev = dev_priv->dev;
1002
1003         intel_init_pch_refclk(dev);
1004
1005         return 0;
1006 }
1007
1008 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
1009 {
1010         hsw_disable_pc8(dev_priv);
1011
1012         return 0;
1013 }
1014
1015 /*
1016  * Save all Gunit registers that may be lost after a D3 and a subsequent
1017  * S0i[R123] transition. The list of registers needing a save/restore is
1018  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1019  * registers in the following way:
1020  * - Driver: saved/restored by the driver
1021  * - Punit : saved/restored by the Punit firmware
1022  * - No, w/o marking: no need to save/restore, since the register is R/O or
1023  *                    used internally by the HW in a way that doesn't depend
1024  *                    keeping the content across a suspend/resume.
1025  * - Debug : used for debugging
1026  *
1027  * We save/restore all registers marked with 'Driver', with the following
1028  * exceptions:
1029  * - Registers out of use, including also registers marked with 'Debug'.
1030  *   These have no effect on the driver's operation, so we don't save/restore
1031  *   them to reduce the overhead.
1032  * - Registers that are fully setup by an initialization function called from
1033  *   the resume path. For example many clock gating and RPS/RC6 registers.
1034  * - Registers that provide the right functionality with their reset defaults.
1035  *
1036  * TODO: Except for registers that based on the above 3 criteria can be safely
1037  * ignored, we save/restore all others, practically treating the HW context as
1038  * a black-box for the driver. Further investigation is needed to reduce the
1039  * saved/restored registers even further, by following the same 3 criteria.
1040  */
1041 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1042 {
1043         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1044         int i;
1045
1046         /* GAM 0x4000-0x4770 */
1047         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1048         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1049         s->arb_mode             = I915_READ(ARB_MODE);
1050         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1051         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1052
1053         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1054                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1055
1056         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1057         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1058
1059         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1060         s->ecochk               = I915_READ(GAM_ECOCHK);
1061         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1062         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1063
1064         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1065
1066         /* MBC 0x9024-0x91D0, 0x8500 */
1067         s->g3dctl               = I915_READ(VLV_G3DCTL);
1068         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1069         s->mbctl                = I915_READ(GEN6_MBCTL);
1070
1071         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1072         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1073         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1074         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1075         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1076         s->rstctl               = I915_READ(GEN6_RSTCTL);
1077         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1078
1079         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1080         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1081         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1082         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1083         s->ecobus               = I915_READ(ECOBUS);
1084         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1085         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1086         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1087         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1088         s->rcedata              = I915_READ(VLV_RCEDATA);
1089         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1090
1091         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1092         s->gt_imr               = I915_READ(GTIMR);
1093         s->gt_ier               = I915_READ(GTIER);
1094         s->pm_imr               = I915_READ(GEN6_PMIMR);
1095         s->pm_ier               = I915_READ(GEN6_PMIER);
1096
1097         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1098                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1099
1100         /* GT SA CZ domain, 0x100000-0x138124 */
1101         s->tilectl              = I915_READ(TILECTL);
1102         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1103         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1104         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1105         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1106
1107         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1108         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1109         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1110         s->pcbr                 = I915_READ(VLV_PCBR);
1111         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1112
1113         /*
1114          * Not saving any of:
1115          * DFT,         0x9800-0x9EC0
1116          * SARB,        0xB000-0xB1FC
1117          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1118          * PCI CFG
1119          */
1120 }
1121
1122 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1123 {
1124         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1125         u32 val;
1126         int i;
1127
1128         /* GAM 0x4000-0x4770 */
1129         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1130         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1131         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1132         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1133         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1134
1135         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1136                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1137
1138         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1139         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1140
1141         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1142         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1143         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1144         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1145
1146         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1147
1148         /* MBC 0x9024-0x91D0, 0x8500 */
1149         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1150         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1151         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1152
1153         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1154         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1155         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1156         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1157         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1158         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1159         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1160
1161         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1162         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1163         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1164         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1165         I915_WRITE(ECOBUS,              s->ecobus);
1166         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1167         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1168         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1169         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1170         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1171         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1172
1173         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1174         I915_WRITE(GTIMR,               s->gt_imr);
1175         I915_WRITE(GTIER,               s->gt_ier);
1176         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1177         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1178
1179         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1180                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1181
1182         /* GT SA CZ domain, 0x100000-0x138124 */
1183         I915_WRITE(TILECTL,                     s->tilectl);
1184         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1185         /*
1186          * Preserve the GT allow wake and GFX force clock bit, they are not
1187          * be restored, as they are used to control the s0ix suspend/resume
1188          * sequence by the caller.
1189          */
1190         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1191         val &= VLV_GTLC_ALLOWWAKEREQ;
1192         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1193         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1194
1195         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1196         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1197         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1198         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1199
1200         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1201
1202         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1203         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1204         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1205         I915_WRITE(VLV_PCBR,                    s->pcbr);
1206         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1207 }
1208
1209 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1210 {
1211         u32 val;
1212         int err;
1213
1214 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1215
1216         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1217         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1218         if (force_on)
1219                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1220         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1221
1222         if (!force_on)
1223                 return 0;
1224
1225         err = wait_for(COND, 20);
1226         if (err)
1227                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1228                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1229
1230         return err;
1231 #undef COND
1232 }
1233
1234 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1235 {
1236         u32 val;
1237         int err = 0;
1238
1239         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1240         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1241         if (allow)
1242                 val |= VLV_GTLC_ALLOWWAKEREQ;
1243         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1244         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1245
1246 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1247               allow)
1248         err = wait_for(COND, 1);
1249         if (err)
1250                 DRM_ERROR("timeout disabling GT waking\n");
1251         return err;
1252 #undef COND
1253 }
1254
1255 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1256                                  bool wait_for_on)
1257 {
1258         u32 mask;
1259         u32 val;
1260         int err;
1261
1262         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1263         val = wait_for_on ? mask : 0;
1264 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1265         if (COND)
1266                 return 0;
1267
1268         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1269                         wait_for_on ? "on" : "off",
1270                         I915_READ(VLV_GTLC_PW_STATUS));
1271
1272         /*
1273          * RC6 transitioning can be delayed up to 2 msec (see
1274          * valleyview_enable_rps), use 3 msec for safety.
1275          */
1276         err = wait_for(COND, 3);
1277         if (err)
1278                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1279                           wait_for_on ? "on" : "off");
1280
1281         return err;
1282 #undef COND
1283 }
1284
1285 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1286 {
1287         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1288                 return;
1289
1290         DRM_ERROR("GT register access while GT waking disabled\n");
1291         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1292 }
1293
1294 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1295 {
1296         u32 mask;
1297         int err;
1298
1299         /*
1300          * Bspec defines the following GT well on flags as debug only, so
1301          * don't treat them as hard failures.
1302          */
1303         (void)vlv_wait_for_gt_wells(dev_priv, false);
1304
1305         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1306         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1307
1308         vlv_check_no_gt_access(dev_priv);
1309
1310         err = vlv_force_gfx_clock(dev_priv, true);
1311         if (err)
1312                 goto err1;
1313
1314         err = vlv_allow_gt_wake(dev_priv, false);
1315         if (err)
1316                 goto err2;
1317         vlv_save_gunit_s0ix_state(dev_priv);
1318
1319         err = vlv_force_gfx_clock(dev_priv, false);
1320         if (err)
1321                 goto err2;
1322
1323         return 0;
1324
1325 err2:
1326         /* For safety always re-enable waking and disable gfx clock forcing */
1327         vlv_allow_gt_wake(dev_priv, true);
1328 err1:
1329         vlv_force_gfx_clock(dev_priv, false);
1330
1331         return err;
1332 }
1333
1334 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1335 {
1336         struct drm_device *dev = dev_priv->dev;
1337         int err;
1338         int ret;
1339
1340         /*
1341          * If any of the steps fail just try to continue, that's the best we
1342          * can do at this point. Return the first error code (which will also
1343          * leave RPM permanently disabled).
1344          */
1345         ret = vlv_force_gfx_clock(dev_priv, true);
1346
1347         vlv_restore_gunit_s0ix_state(dev_priv);
1348
1349         err = vlv_allow_gt_wake(dev_priv, true);
1350         if (!ret)
1351                 ret = err;
1352
1353         err = vlv_force_gfx_clock(dev_priv, false);
1354         if (!ret)
1355                 ret = err;
1356
1357         vlv_check_no_gt_access(dev_priv);
1358
1359         intel_init_clock_gating(dev);
1360         i915_gem_restore_fences(dev);
1361
1362         return ret;
1363 }
1364
1365 static int intel_runtime_suspend(struct device *device)
1366 {
1367         struct pci_dev *pdev = to_pci_dev(device);
1368         struct drm_device *dev = pci_get_drvdata(pdev);
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370         int ret;
1371
1372         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1373                 return -ENODEV;
1374
1375         WARN_ON(!HAS_RUNTIME_PM(dev));
1376         assert_force_wake_inactive(dev_priv);
1377
1378         DRM_DEBUG_KMS("Suspending device\n");
1379
1380         /*
1381          * We could deadlock here in case another thread holding struct_mutex
1382          * calls RPM suspend concurrently, since the RPM suspend will wait
1383          * first for this RPM suspend to finish. In this case the concurrent
1384          * RPM resume will be followed by its RPM suspend counterpart. Still
1385          * for consistency return -EAGAIN, which will reschedule this suspend.
1386          */
1387         if (!mutex_trylock(&dev->struct_mutex)) {
1388                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1389                 /*
1390                  * Bump the expiration timestamp, otherwise the suspend won't
1391                  * be rescheduled.
1392                  */
1393                 pm_runtime_mark_last_busy(device);
1394
1395                 return -EAGAIN;
1396         }
1397         /*
1398          * We are safe here against re-faults, since the fault handler takes
1399          * an RPM reference.
1400          */
1401         i915_gem_release_all_mmaps(dev_priv);
1402         mutex_unlock(&dev->struct_mutex);
1403
1404         /*
1405          * rps.work can't be rearmed here, since we get here only after making
1406          * sure the GPU is idle and the RPS freq is set to the minimum. See
1407          * intel_mark_idle().
1408          */
1409         cancel_work_sync(&dev_priv->rps.work);
1410         intel_runtime_pm_disable_interrupts(dev);
1411
1412         if (IS_GEN6(dev)) {
1413                 ret = 0;
1414         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1415                 ret = hsw_runtime_suspend(dev_priv);
1416         } else if (IS_VALLEYVIEW(dev)) {
1417                 ret = vlv_runtime_suspend(dev_priv);
1418         } else {
1419                 ret = -ENODEV;
1420                 WARN_ON(1);
1421         }
1422
1423         if (ret) {
1424                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1425                 intel_runtime_pm_restore_interrupts(dev);
1426
1427                 return ret;
1428         }
1429
1430         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1431         dev_priv->pm.suspended = true;
1432
1433         /*
1434          * current versions of firmware which depend on this opregion
1435          * notification have repurposed the D1 definition to mean
1436          * "runtime suspended" vs. what you would normally expect (D3)
1437          * to distinguish it from notifications that might be sent
1438          * via the suspend path.
1439          */
1440         intel_opregion_notify_adapter(dev, PCI_D1);
1441
1442         DRM_DEBUG_KMS("Device suspended\n");
1443         return 0;
1444 }
1445
1446 static int intel_runtime_resume(struct device *device)
1447 {
1448         struct pci_dev *pdev = to_pci_dev(device);
1449         struct drm_device *dev = pci_get_drvdata(pdev);
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451         int ret;
1452
1453         WARN_ON(!HAS_RUNTIME_PM(dev));
1454
1455         DRM_DEBUG_KMS("Resuming device\n");
1456
1457         intel_opregion_notify_adapter(dev, PCI_D0);
1458         dev_priv->pm.suspended = false;
1459
1460         if (IS_GEN6(dev)) {
1461                 ret = snb_runtime_resume(dev_priv);
1462         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1463                 ret = hsw_runtime_resume(dev_priv);
1464         } else if (IS_VALLEYVIEW(dev)) {
1465                 ret = vlv_runtime_resume(dev_priv);
1466         } else {
1467                 WARN_ON(1);
1468                 ret = -ENODEV;
1469         }
1470
1471         /*
1472          * No point of rolling back things in case of an error, as the best
1473          * we can do is to hope that things will still work (and disable RPM).
1474          */
1475         i915_gem_init_swizzling(dev);
1476         gen6_update_ring_freq(dev);
1477
1478         intel_runtime_pm_restore_interrupts(dev);
1479         intel_reset_gt_powersave(dev);
1480
1481         if (ret)
1482                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1483         else
1484                 DRM_DEBUG_KMS("Device resumed\n");
1485
1486         return ret;
1487 }
1488
1489 static const struct dev_pm_ops i915_pm_ops = {
1490         .suspend = i915_pm_suspend,
1491         .suspend_late = i915_pm_suspend_late,
1492         .resume_early = i915_pm_resume_early,
1493         .resume = i915_pm_resume,
1494         .freeze = i915_pm_freeze,
1495         .thaw_early = i915_pm_thaw_early,
1496         .thaw = i915_pm_thaw,
1497         .poweroff = i915_pm_poweroff,
1498         .restore_early = i915_pm_resume_early,
1499         .restore = i915_pm_resume,
1500         .runtime_suspend = intel_runtime_suspend,
1501         .runtime_resume = intel_runtime_resume,
1502 };
1503
1504 static const struct vm_operations_struct i915_gem_vm_ops = {
1505         .fault = i915_gem_fault,
1506         .open = drm_gem_vm_open,
1507         .close = drm_gem_vm_close,
1508 };
1509
1510 static const struct file_operations i915_driver_fops = {
1511         .owner = THIS_MODULE,
1512         .open = drm_open,
1513         .release = drm_release,
1514         .unlocked_ioctl = drm_ioctl,
1515         .mmap = drm_gem_mmap,
1516         .poll = drm_poll,
1517         .read = drm_read,
1518 #ifdef CONFIG_COMPAT
1519         .compat_ioctl = i915_compat_ioctl,
1520 #endif
1521         .llseek = noop_llseek,
1522 };
1523
1524 static struct drm_driver driver = {
1525         /* Don't use MTRRs here; the Xserver or userspace app should
1526          * deal with them for Intel hardware.
1527          */
1528         .driver_features =
1529             DRIVER_USE_AGP |
1530             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1531             DRIVER_RENDER,
1532         .load = i915_driver_load,
1533         .unload = i915_driver_unload,
1534         .open = i915_driver_open,
1535         .lastclose = i915_driver_lastclose,
1536         .preclose = i915_driver_preclose,
1537         .postclose = i915_driver_postclose,
1538
1539         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1540         .suspend = i915_suspend,
1541         .resume = i915_resume_legacy,
1542
1543         .device_is_agp = i915_driver_device_is_agp,
1544         .master_create = i915_master_create,
1545         .master_destroy = i915_master_destroy,
1546 #if defined(CONFIG_DEBUG_FS)
1547         .debugfs_init = i915_debugfs_init,
1548         .debugfs_cleanup = i915_debugfs_cleanup,
1549 #endif
1550         .gem_free_object = i915_gem_free_object,
1551         .gem_vm_ops = &i915_gem_vm_ops,
1552
1553         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1554         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1555         .gem_prime_export = i915_gem_prime_export,
1556         .gem_prime_import = i915_gem_prime_import,
1557
1558         .dumb_create = i915_gem_dumb_create,
1559         .dumb_map_offset = i915_gem_mmap_gtt,
1560         .dumb_destroy = drm_gem_dumb_destroy,
1561         .ioctls = i915_ioctls,
1562         .fops = &i915_driver_fops,
1563         .name = DRIVER_NAME,
1564         .desc = DRIVER_DESC,
1565         .date = DRIVER_DATE,
1566         .major = DRIVER_MAJOR,
1567         .minor = DRIVER_MINOR,
1568         .patchlevel = DRIVER_PATCHLEVEL,
1569 };
1570
1571 static struct pci_driver i915_pci_driver = {
1572         .name = DRIVER_NAME,
1573         .id_table = pciidlist,
1574         .probe = i915_pci_probe,
1575         .remove = i915_pci_remove,
1576         .driver.pm = &i915_pm_ops,
1577 };
1578
1579 static int __init i915_init(void)
1580 {
1581         driver.num_ioctls = i915_max_ioctl;
1582
1583         /*
1584          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1585          * explicitly disabled with the module pararmeter.
1586          *
1587          * Otherwise, just follow the parameter (defaulting to off).
1588          *
1589          * Allow optional vga_text_mode_force boot option to override
1590          * the default behavior.
1591          */
1592 #if defined(CONFIG_DRM_I915_KMS)
1593         if (i915.modeset != 0)
1594                 driver.driver_features |= DRIVER_MODESET;
1595 #endif
1596         if (i915.modeset == 1)
1597                 driver.driver_features |= DRIVER_MODESET;
1598
1599 #ifdef CONFIG_VGA_CONSOLE
1600         if (vgacon_text_force() && i915.modeset == -1)
1601                 driver.driver_features &= ~DRIVER_MODESET;
1602 #endif
1603
1604         if (!(driver.driver_features & DRIVER_MODESET)) {
1605                 driver.get_vblank_timestamp = NULL;
1606 #ifndef CONFIG_DRM_I915_UMS
1607                 /* Silently fail loading to not upset userspace. */
1608                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1609                 return 0;
1610 #endif
1611         }
1612
1613         return drm_pci_init(&driver, &i915_pci_driver);
1614 }
1615
1616 static void __exit i915_exit(void)
1617 {
1618 #ifndef CONFIG_DRM_I915_UMS
1619         if (!(driver.driver_features & DRIVER_MODESET))
1620                 return; /* Never loaded a driver. */
1621 #endif
1622
1623         drm_pci_exit(&driver, &i915_pci_driver);
1624 }
1625
1626 module_init(i915_init);
1627 module_exit(i915_exit);
1628
1629 MODULE_AUTHOR(DRIVER_AUTHOR);
1630 MODULE_DESCRIPTION(DRIVER_DESC);
1631 MODULE_LICENSE("GPL and additional rights");