2 * SPDX-License-Identifier: MIT
4 * Copyright © 2016-2018 Intel Corporation
7 #include "gt/intel_gt_types.h"
11 #include "i915_active.h"
12 #include "i915_syncmap.h"
13 #include "gt/intel_timeline.h"
15 #define ptr_set_bit(ptr, bit) ((typeof(ptr))((unsigned long)(ptr) | BIT(bit)))
16 #define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit))
18 struct intel_timeline_hwsp {
20 struct intel_gt_timelines *gt_timelines;
21 struct list_head free_link;
26 struct intel_timeline_cacheline {
27 struct i915_active active;
28 struct intel_timeline_hwsp *hwsp;
30 #define CACHELINE_BITS 6
31 #define CACHELINE_FREE CACHELINE_BITS
34 static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
36 struct drm_i915_private *i915 = gt->i915;
37 struct drm_i915_gem_object *obj;
40 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
44 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
46 vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
48 i915_gem_object_put(obj);
53 static struct i915_vma *
54 hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
56 struct intel_gt_timelines *gt = &timeline->gt->timelines;
57 struct intel_timeline_hwsp *hwsp;
59 BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
61 spin_lock_irq(>->hwsp_lock);
63 /* hwsp_free_list only contains HWSP that have available cachelines */
64 hwsp = list_first_entry_or_null(>->hwsp_free_list,
65 typeof(*hwsp), free_link);
69 spin_unlock_irq(>->hwsp_lock);
71 hwsp = kmalloc(sizeof(*hwsp), GFP_KERNEL);
73 return ERR_PTR(-ENOMEM);
75 vma = __hwsp_alloc(timeline->gt);
82 hwsp->gt = timeline->gt;
84 hwsp->free_bitmap = ~0ull;
85 hwsp->gt_timelines = gt;
87 spin_lock_irq(>->hwsp_lock);
88 list_add(&hwsp->free_link, >->hwsp_free_list);
91 GEM_BUG_ON(!hwsp->free_bitmap);
92 *cacheline = __ffs64(hwsp->free_bitmap);
93 hwsp->free_bitmap &= ~BIT_ULL(*cacheline);
94 if (!hwsp->free_bitmap)
95 list_del(&hwsp->free_link);
97 spin_unlock_irq(>->hwsp_lock);
99 GEM_BUG_ON(hwsp->vma->private != hwsp);
103 static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
105 struct intel_gt_timelines *gt = hwsp->gt_timelines;
108 spin_lock_irqsave(>->hwsp_lock, flags);
110 /* As a cacheline becomes available, publish the HWSP on the freelist */
111 if (!hwsp->free_bitmap)
112 list_add_tail(&hwsp->free_link, >->hwsp_free_list);
114 GEM_BUG_ON(cacheline >= BITS_PER_TYPE(hwsp->free_bitmap));
115 hwsp->free_bitmap |= BIT_ULL(cacheline);
117 /* And if no one is left using it, give the page back to the system */
118 if (hwsp->free_bitmap == ~0ull) {
119 i915_vma_put(hwsp->vma);
120 list_del(&hwsp->free_link);
124 spin_unlock_irqrestore(>->hwsp_lock, flags);
127 static void __idle_cacheline_free(struct intel_timeline_cacheline *cl)
129 GEM_BUG_ON(!i915_active_is_idle(&cl->active));
131 i915_gem_object_unpin_map(cl->hwsp->vma->obj);
132 i915_vma_put(cl->hwsp->vma);
133 __idle_hwsp_free(cl->hwsp, ptr_unmask_bits(cl->vaddr, CACHELINE_BITS));
135 i915_active_fini(&cl->active);
139 static void __cacheline_retire(struct i915_active *active)
141 struct intel_timeline_cacheline *cl =
142 container_of(active, typeof(*cl), active);
144 i915_vma_unpin(cl->hwsp->vma);
145 if (ptr_test_bit(cl->vaddr, CACHELINE_FREE))
146 __idle_cacheline_free(cl);
149 static int __cacheline_active(struct i915_active *active)
151 struct intel_timeline_cacheline *cl =
152 container_of(active, typeof(*cl), active);
154 __i915_vma_pin(cl->hwsp->vma);
158 static struct intel_timeline_cacheline *
159 cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
161 struct intel_timeline_cacheline *cl;
164 GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS));
166 cl = kmalloc(sizeof(*cl), GFP_KERNEL);
168 return ERR_PTR(-ENOMEM);
170 vaddr = i915_gem_object_pin_map(hwsp->vma->obj, I915_MAP_WB);
173 return ERR_CAST(vaddr);
176 i915_vma_get(hwsp->vma);
178 cl->vaddr = page_pack_bits(vaddr, cacheline);
180 i915_active_init(hwsp->gt->i915, &cl->active,
181 __cacheline_active, __cacheline_retire);
186 static void cacheline_acquire(struct intel_timeline_cacheline *cl)
189 i915_active_acquire(&cl->active);
192 static void cacheline_release(struct intel_timeline_cacheline *cl)
195 i915_active_release(&cl->active);
198 static void cacheline_free(struct intel_timeline_cacheline *cl)
200 GEM_BUG_ON(ptr_test_bit(cl->vaddr, CACHELINE_FREE));
201 cl->vaddr = ptr_set_bit(cl->vaddr, CACHELINE_FREE);
203 if (i915_active_is_idle(&cl->active))
204 __idle_cacheline_free(cl);
207 int intel_timeline_init(struct intel_timeline *timeline,
209 struct i915_vma *hwsp)
213 kref_init(&timeline->kref);
214 atomic_set(&timeline->pin_count, 0);
218 timeline->has_initial_breadcrumb = !hwsp;
219 timeline->hwsp_cacheline = NULL;
222 struct intel_timeline_cacheline *cl;
223 unsigned int cacheline;
225 hwsp = hwsp_alloc(timeline, &cacheline);
227 return PTR_ERR(hwsp);
229 cl = cacheline_alloc(hwsp->private, cacheline);
231 __idle_hwsp_free(hwsp->private, cacheline);
235 timeline->hwsp_cacheline = cl;
236 timeline->hwsp_offset = cacheline * CACHELINE_BYTES;
238 vaddr = page_mask_bits(cl->vaddr);
240 timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;
242 vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
244 return PTR_ERR(vaddr);
247 timeline->hwsp_seqno =
248 memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES);
250 timeline->hwsp_ggtt = i915_vma_get(hwsp);
251 GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
253 timeline->fence_context = dma_fence_context_alloc(1);
255 mutex_init(&timeline->mutex);
257 INIT_ACTIVE_REQUEST(&timeline->last_request, &timeline->mutex);
258 INIT_LIST_HEAD(&timeline->requests);
260 i915_syncmap_init(&timeline->sync);
265 static void timelines_init(struct intel_gt *gt)
267 struct intel_gt_timelines *timelines = >->timelines;
269 spin_lock_init(&timelines->lock);
270 INIT_LIST_HEAD(&timelines->active_list);
272 spin_lock_init(&timelines->hwsp_lock);
273 INIT_LIST_HEAD(&timelines->hwsp_free_list);
276 void intel_timelines_init(struct drm_i915_private *i915)
278 timelines_init(&i915->gt);
281 void intel_timeline_fini(struct intel_timeline *timeline)
283 GEM_BUG_ON(atomic_read(&timeline->pin_count));
284 GEM_BUG_ON(!list_empty(&timeline->requests));
286 if (timeline->hwsp_cacheline)
287 cacheline_free(timeline->hwsp_cacheline);
289 i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
291 i915_vma_put(timeline->hwsp_ggtt);
294 struct intel_timeline *
295 intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
297 struct intel_timeline *timeline;
300 timeline = kzalloc(sizeof(*timeline), GFP_KERNEL);
302 return ERR_PTR(-ENOMEM);
304 err = intel_timeline_init(timeline, gt, global_hwsp);
313 int intel_timeline_pin(struct intel_timeline *tl)
317 if (atomic_add_unless(&tl->pin_count, 1, 0))
320 err = i915_vma_pin(tl->hwsp_ggtt, 0, 0, PIN_GLOBAL | PIN_HIGH);
325 i915_ggtt_offset(tl->hwsp_ggtt) +
326 offset_in_page(tl->hwsp_offset);
328 cacheline_acquire(tl->hwsp_cacheline);
329 if (atomic_fetch_inc(&tl->pin_count)) {
330 cacheline_release(tl->hwsp_cacheline);
331 __i915_vma_unpin(tl->hwsp_ggtt);
337 void intel_timeline_enter(struct intel_timeline *tl)
339 struct intel_gt_timelines *timelines = &tl->gt->timelines;
342 lockdep_assert_held(&tl->mutex);
344 GEM_BUG_ON(!atomic_read(&tl->pin_count));
345 if (tl->active_count++)
347 GEM_BUG_ON(!tl->active_count); /* overflow? */
349 spin_lock_irqsave(&timelines->lock, flags);
350 list_add(&tl->link, &timelines->active_list);
351 spin_unlock_irqrestore(&timelines->lock, flags);
354 void intel_timeline_exit(struct intel_timeline *tl)
356 struct intel_gt_timelines *timelines = &tl->gt->timelines;
359 lockdep_assert_held(&tl->mutex);
361 GEM_BUG_ON(!tl->active_count);
362 if (--tl->active_count)
365 spin_lock_irqsave(&timelines->lock, flags);
367 spin_unlock_irqrestore(&timelines->lock, flags);
370 * Since this timeline is idle, all bariers upon which we were waiting
371 * must also be complete and so we can discard the last used barriers
372 * without loss of information.
374 i915_syncmap_free(&tl->sync);
377 static u32 timeline_advance(struct intel_timeline *tl)
379 GEM_BUG_ON(!atomic_read(&tl->pin_count));
380 GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
382 return tl->seqno += 1 + tl->has_initial_breadcrumb;
385 static void timeline_rollback(struct intel_timeline *tl)
387 tl->seqno -= 1 + tl->has_initial_breadcrumb;
391 __intel_timeline_get_seqno(struct intel_timeline *tl,
392 struct i915_request *rq,
395 struct intel_timeline_cacheline *cl;
396 unsigned int cacheline;
397 struct i915_vma *vma;
402 * If there is an outstanding GPU reference to this cacheline,
403 * such as it being sampled by a HW semaphore on another timeline,
404 * we cannot wraparound our seqno value (the HW semaphore does
405 * a strict greater-than-or-equals compare, not i915_seqno_passed).
406 * So if the cacheline is still busy, we must detach ourselves
407 * from it and leave it inflight alongside its users.
409 * However, if nobody is watching and we can guarantee that nobody
410 * will, we could simply reuse the same cacheline.
412 * if (i915_active_request_is_signaled(&tl->last_request) &&
413 * i915_active_is_signaled(&tl->hwsp_cacheline->active))
416 * That seems unlikely for a busy timeline that needed to wrap in
417 * the first place, so just replace the cacheline.
420 vma = hwsp_alloc(tl, &cacheline);
426 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
428 __idle_hwsp_free(vma->private, cacheline);
432 cl = cacheline_alloc(vma->private, cacheline);
435 __idle_hwsp_free(vma->private, cacheline);
438 GEM_BUG_ON(cl->hwsp->vma != vma);
441 * Attach the old cacheline to the current request, so that we only
442 * free it after the current request is retired, which ensures that
443 * all writes into the cacheline from previous requests are complete.
445 err = i915_active_ref(&tl->hwsp_cacheline->active, tl, rq);
449 cacheline_release(tl->hwsp_cacheline); /* ownership now xfered to rq */
450 cacheline_free(tl->hwsp_cacheline);
452 i915_vma_unpin(tl->hwsp_ggtt); /* binding kept alive by old cacheline */
453 i915_vma_put(tl->hwsp_ggtt);
455 tl->hwsp_ggtt = i915_vma_get(vma);
457 vaddr = page_mask_bits(cl->vaddr);
458 tl->hwsp_offset = cacheline * CACHELINE_BYTES;
460 memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
462 tl->hwsp_offset += i915_ggtt_offset(vma);
464 cacheline_acquire(cl);
465 tl->hwsp_cacheline = cl;
467 *seqno = timeline_advance(tl);
468 GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqno));
476 timeline_rollback(tl);
480 int intel_timeline_get_seqno(struct intel_timeline *tl,
481 struct i915_request *rq,
484 *seqno = timeline_advance(tl);
486 /* Replace the HWSP on wraparound for HW semaphores */
487 if (unlikely(!*seqno && tl->hwsp_cacheline))
488 return __intel_timeline_get_seqno(tl, rq, seqno);
493 static int cacheline_ref(struct intel_timeline_cacheline *cl,
494 struct i915_request *rq)
496 return i915_active_ref(&cl->active, rq->timeline, rq);
499 int intel_timeline_read_hwsp(struct i915_request *from,
500 struct i915_request *to,
503 struct intel_timeline_cacheline *cl = from->hwsp_cacheline;
504 struct intel_timeline *tl = from->timeline;
507 GEM_BUG_ON(to->timeline == tl);
509 mutex_lock_nested(&tl->mutex, SINGLE_DEPTH_NESTING);
510 err = i915_request_completed(from);
512 err = cacheline_ref(cl, to);
514 if (likely(cl == tl->hwsp_cacheline)) {
515 *hwsp = tl->hwsp_offset;
516 } else { /* across a seqno wrap, recover the original offset */
517 *hwsp = i915_ggtt_offset(cl->hwsp->vma) +
518 ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) *
522 mutex_unlock(&tl->mutex);
527 void intel_timeline_unpin(struct intel_timeline *tl)
529 GEM_BUG_ON(!atomic_read(&tl->pin_count));
530 if (!atomic_dec_and_test(&tl->pin_count))
533 cacheline_release(tl->hwsp_cacheline);
535 __i915_vma_unpin(tl->hwsp_ggtt);
538 void __intel_timeline_free(struct kref *kref)
540 struct intel_timeline *timeline =
541 container_of(kref, typeof(*timeline), kref);
543 intel_timeline_fini(timeline);
547 static void timelines_fini(struct intel_gt *gt)
549 struct intel_gt_timelines *timelines = >->timelines;
551 GEM_BUG_ON(!list_empty(&timelines->active_list));
552 GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
555 void intel_timelines_fini(struct drm_i915_private *i915)
557 timelines_fini(&i915->gt);
560 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
561 #include "gt/selftests/mock_timeline.c"
562 #include "gt/selftest_timeline.c"