2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <drm/drm_scdc_helper.h>
31 #include "intel_audio.h"
32 #include "intel_combo_phy.h"
33 #include "intel_connector.h"
34 #include "intel_ddi.h"
35 #include "intel_display_types.h"
37 #include "intel_dp_link_training.h"
38 #include "intel_dpio_phy.h"
39 #include "intel_dsi.h"
40 #include "intel_fifo_underrun.h"
41 #include "intel_gmbus.h"
42 #include "intel_hdcp.h"
43 #include "intel_hdmi.h"
44 #include "intel_hotplug.h"
45 #include "intel_lspcon.h"
46 #include "intel_panel.h"
47 #include "intel_psr.h"
49 #include "intel_vdsc.h"
51 struct ddi_buf_trans {
52 u32 trans1; /* balance leg enable, de-emph level */
53 u32 trans2; /* vref sel, vswing */
54 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
57 static const u8 index_to_dp_signal_levels[] = {
58 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
59 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
60 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
61 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
62 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
63 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
64 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
65 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
66 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
67 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
70 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
71 * them for both DP and FDI transports, allowing those ports to
72 * automatically adapt to HDMI connections as well
74 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
75 { 0x00FFFFFF, 0x0006000E, 0x0 },
76 { 0x00D75FFF, 0x0005000A, 0x0 },
77 { 0x00C30FFF, 0x00040006, 0x0 },
78 { 0x80AAAFFF, 0x000B0000, 0x0 },
79 { 0x00FFFFFF, 0x0005000A, 0x0 },
80 { 0x00D75FFF, 0x000C0004, 0x0 },
81 { 0x80C30FFF, 0x000B0000, 0x0 },
82 { 0x00FFFFFF, 0x00040006, 0x0 },
83 { 0x80D75FFF, 0x000B0000, 0x0 },
86 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
87 { 0x00FFFFFF, 0x0007000E, 0x0 },
88 { 0x00D75FFF, 0x000F000A, 0x0 },
89 { 0x00C30FFF, 0x00060006, 0x0 },
90 { 0x00AAAFFF, 0x001E0000, 0x0 },
91 { 0x00FFFFFF, 0x000F000A, 0x0 },
92 { 0x00D75FFF, 0x00160004, 0x0 },
93 { 0x00C30FFF, 0x001E0000, 0x0 },
94 { 0x00FFFFFF, 0x00060006, 0x0 },
95 { 0x00D75FFF, 0x001E0000, 0x0 },
98 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
99 /* Idx NT mV d T mV d db */
100 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
101 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
102 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
103 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
104 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
105 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
106 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
107 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
108 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
109 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
110 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
111 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
114 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
115 { 0x00FFFFFF, 0x00000012, 0x0 },
116 { 0x00EBAFFF, 0x00020011, 0x0 },
117 { 0x00C71FFF, 0x0006000F, 0x0 },
118 { 0x00AAAFFF, 0x000E000A, 0x0 },
119 { 0x00FFFFFF, 0x00020011, 0x0 },
120 { 0x00DB6FFF, 0x0005000F, 0x0 },
121 { 0x00BEEFFF, 0x000A000C, 0x0 },
122 { 0x00FFFFFF, 0x0005000F, 0x0 },
123 { 0x00DB6FFF, 0x000A000C, 0x0 },
126 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
127 { 0x00FFFFFF, 0x0007000E, 0x0 },
128 { 0x00D75FFF, 0x000E000A, 0x0 },
129 { 0x00BEFFFF, 0x00140006, 0x0 },
130 { 0x80B2CFFF, 0x001B0002, 0x0 },
131 { 0x00FFFFFF, 0x000E000A, 0x0 },
132 { 0x00DB6FFF, 0x00160005, 0x0 },
133 { 0x80C71FFF, 0x001A0002, 0x0 },
134 { 0x00F7DFFF, 0x00180004, 0x0 },
135 { 0x80D75FFF, 0x001B0002, 0x0 },
138 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
139 { 0x00FFFFFF, 0x0001000E, 0x0 },
140 { 0x00D75FFF, 0x0004000A, 0x0 },
141 { 0x00C30FFF, 0x00070006, 0x0 },
142 { 0x00AAAFFF, 0x000C0000, 0x0 },
143 { 0x00FFFFFF, 0x0004000A, 0x0 },
144 { 0x00D75FFF, 0x00090004, 0x0 },
145 { 0x00C30FFF, 0x000C0000, 0x0 },
146 { 0x00FFFFFF, 0x00070006, 0x0 },
147 { 0x00D75FFF, 0x000C0000, 0x0 },
150 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
151 /* Idx NT mV d T mV df db */
152 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
153 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
154 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
155 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
156 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
157 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
158 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
159 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
160 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
161 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
164 /* Skylake H and S */
165 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
166 { 0x00002016, 0x000000A0, 0x0 },
167 { 0x00005012, 0x0000009B, 0x0 },
168 { 0x00007011, 0x00000088, 0x0 },
169 { 0x80009010, 0x000000C0, 0x1 },
170 { 0x00002016, 0x0000009B, 0x0 },
171 { 0x00005012, 0x00000088, 0x0 },
172 { 0x80007011, 0x000000C0, 0x1 },
173 { 0x00002016, 0x000000DF, 0x0 },
174 { 0x80005012, 0x000000C0, 0x1 },
178 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
179 { 0x0000201B, 0x000000A2, 0x0 },
180 { 0x00005012, 0x00000088, 0x0 },
181 { 0x80007011, 0x000000CD, 0x1 },
182 { 0x80009010, 0x000000C0, 0x1 },
183 { 0x0000201B, 0x0000009D, 0x0 },
184 { 0x80005012, 0x000000C0, 0x1 },
185 { 0x80007011, 0x000000C0, 0x1 },
186 { 0x00002016, 0x00000088, 0x0 },
187 { 0x80005012, 0x000000C0, 0x1 },
191 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
192 { 0x00000018, 0x000000A2, 0x0 },
193 { 0x00005012, 0x00000088, 0x0 },
194 { 0x80007011, 0x000000CD, 0x3 },
195 { 0x80009010, 0x000000C0, 0x3 },
196 { 0x00000018, 0x0000009D, 0x0 },
197 { 0x80005012, 0x000000C0, 0x3 },
198 { 0x80007011, 0x000000C0, 0x3 },
199 { 0x00000018, 0x00000088, 0x0 },
200 { 0x80005012, 0x000000C0, 0x3 },
203 /* Kabylake H and S */
204 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
205 { 0x00002016, 0x000000A0, 0x0 },
206 { 0x00005012, 0x0000009B, 0x0 },
207 { 0x00007011, 0x00000088, 0x0 },
208 { 0x80009010, 0x000000C0, 0x1 },
209 { 0x00002016, 0x0000009B, 0x0 },
210 { 0x00005012, 0x00000088, 0x0 },
211 { 0x80007011, 0x000000C0, 0x1 },
212 { 0x00002016, 0x00000097, 0x0 },
213 { 0x80005012, 0x000000C0, 0x1 },
217 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
218 { 0x0000201B, 0x000000A1, 0x0 },
219 { 0x00005012, 0x00000088, 0x0 },
220 { 0x80007011, 0x000000CD, 0x3 },
221 { 0x80009010, 0x000000C0, 0x3 },
222 { 0x0000201B, 0x0000009D, 0x0 },
223 { 0x80005012, 0x000000C0, 0x3 },
224 { 0x80007011, 0x000000C0, 0x3 },
225 { 0x00002016, 0x0000004F, 0x0 },
226 { 0x80005012, 0x000000C0, 0x3 },
230 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
231 { 0x00001017, 0x000000A1, 0x0 },
232 { 0x00005012, 0x00000088, 0x0 },
233 { 0x80007011, 0x000000CD, 0x3 },
234 { 0x8000800F, 0x000000C0, 0x3 },
235 { 0x00001017, 0x0000009D, 0x0 },
236 { 0x80005012, 0x000000C0, 0x3 },
237 { 0x80007011, 0x000000C0, 0x3 },
238 { 0x00001017, 0x0000004C, 0x0 },
239 { 0x80005012, 0x000000C0, 0x3 },
243 * Skylake/Kabylake H and S
244 * eDP 1.4 low vswing translation parameters
246 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
247 { 0x00000018, 0x000000A8, 0x0 },
248 { 0x00004013, 0x000000A9, 0x0 },
249 { 0x00007011, 0x000000A2, 0x0 },
250 { 0x00009010, 0x0000009C, 0x0 },
251 { 0x00000018, 0x000000A9, 0x0 },
252 { 0x00006013, 0x000000A2, 0x0 },
253 { 0x00007011, 0x000000A6, 0x0 },
254 { 0x00000018, 0x000000AB, 0x0 },
255 { 0x00007013, 0x0000009F, 0x0 },
256 { 0x00000018, 0x000000DF, 0x0 },
261 * eDP 1.4 low vswing translation parameters
263 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
264 { 0x00000018, 0x000000A8, 0x0 },
265 { 0x00004013, 0x000000A9, 0x0 },
266 { 0x00007011, 0x000000A2, 0x0 },
267 { 0x00009010, 0x0000009C, 0x0 },
268 { 0x00000018, 0x000000A9, 0x0 },
269 { 0x00006013, 0x000000A2, 0x0 },
270 { 0x00007011, 0x000000A6, 0x0 },
271 { 0x00002016, 0x000000AB, 0x0 },
272 { 0x00005013, 0x0000009F, 0x0 },
273 { 0x00000018, 0x000000DF, 0x0 },
278 * eDP 1.4 low vswing translation parameters
280 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
281 { 0x00000018, 0x000000A8, 0x0 },
282 { 0x00004013, 0x000000AB, 0x0 },
283 { 0x00007011, 0x000000A4, 0x0 },
284 { 0x00009010, 0x000000DF, 0x0 },
285 { 0x00000018, 0x000000AA, 0x0 },
286 { 0x00006013, 0x000000A4, 0x0 },
287 { 0x00007011, 0x0000009D, 0x0 },
288 { 0x00000018, 0x000000A0, 0x0 },
289 { 0x00006012, 0x000000DF, 0x0 },
290 { 0x00000018, 0x0000008A, 0x0 },
293 /* Skylake/Kabylake U, H and S */
294 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
295 { 0x00000018, 0x000000AC, 0x0 },
296 { 0x00005012, 0x0000009D, 0x0 },
297 { 0x00007011, 0x00000088, 0x0 },
298 { 0x00000018, 0x000000A1, 0x0 },
299 { 0x00000018, 0x00000098, 0x0 },
300 { 0x00004013, 0x00000088, 0x0 },
301 { 0x80006012, 0x000000CD, 0x1 },
302 { 0x00000018, 0x000000DF, 0x0 },
303 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
304 { 0x80003015, 0x000000C0, 0x1 },
305 { 0x80000018, 0x000000C0, 0x1 },
308 /* Skylake/Kabylake Y */
309 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
310 { 0x00000018, 0x000000A1, 0x0 },
311 { 0x00005012, 0x000000DF, 0x0 },
312 { 0x80007011, 0x000000CB, 0x3 },
313 { 0x00000018, 0x000000A4, 0x0 },
314 { 0x00000018, 0x0000009D, 0x0 },
315 { 0x00004013, 0x00000080, 0x0 },
316 { 0x80006013, 0x000000C0, 0x3 },
317 { 0x00000018, 0x0000008A, 0x0 },
318 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
319 { 0x80003015, 0x000000C0, 0x3 },
320 { 0x80000018, 0x000000C0, 0x3 },
323 struct bxt_ddi_buf_trans {
324 u8 margin; /* swing value */
325 u8 scale; /* scale value */
326 u8 enable; /* scale enable */
330 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
331 /* Idx NT mV diff db */
332 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
333 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
334 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
335 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
336 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
337 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
338 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
339 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
340 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
341 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
344 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
345 /* Idx NT mV diff db */
346 { 26, 0, 0, 128, }, /* 0: 200 0 */
347 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
348 { 48, 0, 0, 96, }, /* 2: 200 4 */
349 { 54, 0, 0, 69, }, /* 3: 200 6 */
350 { 32, 0, 0, 128, }, /* 4: 250 0 */
351 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
352 { 54, 0, 0, 85, }, /* 6: 250 4 */
353 { 43, 0, 0, 128, }, /* 7: 300 0 */
354 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
355 { 48, 0, 0, 128, }, /* 9: 300 0 */
358 /* BSpec has 2 recommended values - entries 0 and 8.
359 * Using the entry with higher vswing.
361 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
362 /* Idx NT mV diff db */
363 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
364 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
365 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
366 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
367 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
368 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
369 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
370 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
371 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
372 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
375 struct cnl_ddi_buf_trans {
379 u8 dw4_post_cursor_2;
380 u8 dw4_post_cursor_1;
383 /* Voltage Swing Programming for VccIO 0.85V for DP */
384 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
385 /* NT mV Trans mV db */
386 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
387 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
388 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
389 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
390 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
391 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
392 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
393 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
394 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
395 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
398 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
399 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
400 /* NT mV Trans mV db */
401 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
402 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
403 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
404 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
405 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
406 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
407 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
410 /* Voltage Swing Programming for VccIO 0.85V for eDP */
411 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
412 /* NT mV Trans mV db */
413 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
414 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
415 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
416 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
417 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
418 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
419 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
420 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
421 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 /* Voltage Swing Programming for VccIO 0.95V for DP */
425 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
426 /* NT mV Trans mV db */
427 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
428 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
429 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
430 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
431 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
432 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
433 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
434 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
435 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
436 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
439 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
440 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
441 /* NT mV Trans mV db */
442 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
443 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
444 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
445 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
446 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
447 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
448 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
449 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
450 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
451 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
452 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
455 /* Voltage Swing Programming for VccIO 0.95V for eDP */
456 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
457 /* NT mV Trans mV db */
458 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
459 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
460 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
461 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
462 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
463 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
464 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
465 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
466 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
467 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 /* Voltage Swing Programming for VccIO 1.05V for DP */
471 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
472 /* NT mV Trans mV db */
473 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
474 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
475 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
476 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
477 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
478 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
479 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
480 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
481 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
482 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
485 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
486 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
487 /* NT mV Trans mV db */
488 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
489 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
490 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
491 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
492 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
493 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
494 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
495 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
496 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
497 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
498 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
501 /* Voltage Swing Programming for VccIO 1.05V for eDP */
502 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
503 /* NT mV Trans mV db */
504 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
505 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
506 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
507 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
508 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
509 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
510 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
511 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
512 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
515 /* icl_combo_phy_ddi_translations */
516 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
517 /* NT mV Trans mV db */
518 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
519 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
520 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
521 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
522 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
523 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
524 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
525 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
526 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
527 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
530 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
531 /* NT mV Trans mV db */
532 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
533 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
534 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
535 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
536 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
537 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
538 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
539 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
540 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
541 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
544 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
545 /* NT mV Trans mV db */
546 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
547 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
548 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
549 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
550 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
551 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
552 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
553 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
554 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
555 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
558 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
559 /* NT mV Trans mV db */
560 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
561 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
562 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
563 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
564 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
565 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
566 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
569 struct icl_mg_phy_ddi_buf_trans {
570 u32 cri_txdeemph_override_5_0;
571 u32 cri_txdeemph_override_11_6;
572 u32 cri_txdeemph_override_17_12;
575 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
576 /* Voltage swing pre-emphasis */
577 { 0x0, 0x1B, 0x00 }, /* 0 0 */
578 { 0x0, 0x23, 0x08 }, /* 0 1 */
579 { 0x0, 0x2D, 0x12 }, /* 0 2 */
580 { 0x0, 0x00, 0x00 }, /* 0 3 */
581 { 0x0, 0x23, 0x00 }, /* 1 0 */
582 { 0x0, 0x2B, 0x09 }, /* 1 1 */
583 { 0x0, 0x2E, 0x11 }, /* 1 2 */
584 { 0x0, 0x2F, 0x00 }, /* 2 0 */
585 { 0x0, 0x33, 0x0C }, /* 2 1 */
586 { 0x0, 0x00, 0x00 }, /* 3 0 */
589 static const struct ddi_buf_trans *
590 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
592 if (dev_priv->vbt.edp.low_vswing) {
593 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
594 return bdw_ddi_translations_edp;
596 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
597 return bdw_ddi_translations_dp;
601 static const struct ddi_buf_trans *
602 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
604 if (IS_SKL_ULX(dev_priv)) {
605 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
606 return skl_y_ddi_translations_dp;
607 } else if (IS_SKL_ULT(dev_priv)) {
608 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
609 return skl_u_ddi_translations_dp;
611 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
612 return skl_ddi_translations_dp;
616 static const struct ddi_buf_trans *
617 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
619 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
620 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
621 return kbl_y_ddi_translations_dp;
622 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
623 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
624 return kbl_u_ddi_translations_dp;
626 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
627 return kbl_ddi_translations_dp;
631 static const struct ddi_buf_trans *
632 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
634 if (dev_priv->vbt.edp.low_vswing) {
635 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
636 IS_CFL_ULX(dev_priv)) {
637 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
638 return skl_y_ddi_translations_edp;
639 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
640 IS_CFL_ULT(dev_priv)) {
641 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
642 return skl_u_ddi_translations_edp;
644 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
645 return skl_ddi_translations_edp;
649 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
650 return kbl_get_buf_trans_dp(dev_priv, n_entries);
652 return skl_get_buf_trans_dp(dev_priv, n_entries);
655 static const struct ddi_buf_trans *
656 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
658 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
659 IS_CFL_ULX(dev_priv)) {
660 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
661 return skl_y_ddi_translations_hdmi;
663 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
664 return skl_ddi_translations_hdmi;
668 static int skl_buf_trans_num_entries(enum port port, int n_entries)
670 /* Only DDIA and DDIE can select the 10th register with DP */
671 if (port == PORT_A || port == PORT_E)
672 return min(n_entries, 10);
674 return min(n_entries, 9);
677 static const struct ddi_buf_trans *
678 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
679 enum port port, int *n_entries)
681 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
682 const struct ddi_buf_trans *ddi_translations =
683 kbl_get_buf_trans_dp(dev_priv, n_entries);
684 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
685 return ddi_translations;
686 } else if (IS_SKYLAKE(dev_priv)) {
687 const struct ddi_buf_trans *ddi_translations =
688 skl_get_buf_trans_dp(dev_priv, n_entries);
689 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
690 return ddi_translations;
691 } else if (IS_BROADWELL(dev_priv)) {
692 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
693 return bdw_ddi_translations_dp;
694 } else if (IS_HASWELL(dev_priv)) {
695 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
696 return hsw_ddi_translations_dp;
703 static const struct ddi_buf_trans *
704 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
705 enum port port, int *n_entries)
707 if (IS_GEN9_BC(dev_priv)) {
708 const struct ddi_buf_trans *ddi_translations =
709 skl_get_buf_trans_edp(dev_priv, n_entries);
710 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
711 return ddi_translations;
712 } else if (IS_BROADWELL(dev_priv)) {
713 return bdw_get_buf_trans_edp(dev_priv, n_entries);
714 } else if (IS_HASWELL(dev_priv)) {
715 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
716 return hsw_ddi_translations_dp;
723 static const struct ddi_buf_trans *
724 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
727 if (IS_BROADWELL(dev_priv)) {
728 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
729 return bdw_ddi_translations_fdi;
730 } else if (IS_HASWELL(dev_priv)) {
731 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
732 return hsw_ddi_translations_fdi;
739 static const struct ddi_buf_trans *
740 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
743 if (IS_GEN9_BC(dev_priv)) {
744 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
745 } else if (IS_BROADWELL(dev_priv)) {
746 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
747 return bdw_ddi_translations_hdmi;
748 } else if (IS_HASWELL(dev_priv)) {
749 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
750 return hsw_ddi_translations_hdmi;
757 static const struct bxt_ddi_buf_trans *
758 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
760 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
761 return bxt_ddi_translations_dp;
764 static const struct bxt_ddi_buf_trans *
765 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
767 if (dev_priv->vbt.edp.low_vswing) {
768 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
769 return bxt_ddi_translations_edp;
772 return bxt_get_buf_trans_dp(dev_priv, n_entries);
775 static const struct bxt_ddi_buf_trans *
776 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
778 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
779 return bxt_ddi_translations_hdmi;
782 static const struct cnl_ddi_buf_trans *
783 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
785 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
787 if (voltage == VOLTAGE_INFO_0_85V) {
788 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
789 return cnl_ddi_translations_hdmi_0_85V;
790 } else if (voltage == VOLTAGE_INFO_0_95V) {
791 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
792 return cnl_ddi_translations_hdmi_0_95V;
793 } else if (voltage == VOLTAGE_INFO_1_05V) {
794 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
795 return cnl_ddi_translations_hdmi_1_05V;
797 *n_entries = 1; /* shut up gcc */
798 MISSING_CASE(voltage);
803 static const struct cnl_ddi_buf_trans *
804 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
806 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
808 if (voltage == VOLTAGE_INFO_0_85V) {
809 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
810 return cnl_ddi_translations_dp_0_85V;
811 } else if (voltage == VOLTAGE_INFO_0_95V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
813 return cnl_ddi_translations_dp_0_95V;
814 } else if (voltage == VOLTAGE_INFO_1_05V) {
815 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
816 return cnl_ddi_translations_dp_1_05V;
818 *n_entries = 1; /* shut up gcc */
819 MISSING_CASE(voltage);
824 static const struct cnl_ddi_buf_trans *
825 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
827 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
829 if (dev_priv->vbt.edp.low_vswing) {
830 if (voltage == VOLTAGE_INFO_0_85V) {
831 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
832 return cnl_ddi_translations_edp_0_85V;
833 } else if (voltage == VOLTAGE_INFO_0_95V) {
834 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
835 return cnl_ddi_translations_edp_0_95V;
836 } else if (voltage == VOLTAGE_INFO_1_05V) {
837 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
838 return cnl_ddi_translations_edp_1_05V;
840 *n_entries = 1; /* shut up gcc */
841 MISSING_CASE(voltage);
845 return cnl_get_buf_trans_dp(dev_priv, n_entries);
849 static const struct cnl_ddi_buf_trans *
850 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
853 if (type == INTEL_OUTPUT_HDMI) {
854 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
855 return icl_combo_phy_ddi_translations_hdmi;
856 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
857 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
858 return icl_combo_phy_ddi_translations_edp_hbr3;
859 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
860 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
861 return icl_combo_phy_ddi_translations_edp_hbr2;
864 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
865 return icl_combo_phy_ddi_translations_dp_hbr2;
868 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
870 int n_entries, level, default_entry;
871 enum phy phy = intel_port_to_phy(dev_priv, port);
873 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
875 if (INTEL_GEN(dev_priv) >= 11) {
876 if (intel_phy_is_combo(dev_priv, phy))
877 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
880 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
881 default_entry = n_entries - 1;
882 } else if (IS_CANNONLAKE(dev_priv)) {
883 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
884 default_entry = n_entries - 1;
885 } else if (IS_GEN9_LP(dev_priv)) {
886 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
887 default_entry = n_entries - 1;
888 } else if (IS_GEN9_BC(dev_priv)) {
889 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
891 } else if (IS_BROADWELL(dev_priv)) {
892 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
894 } else if (IS_HASWELL(dev_priv)) {
895 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
898 WARN(1, "ddi translation table missing\n");
902 /* Choose a good default if VBT is badly populated */
903 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
904 level = default_entry;
906 if (WARN_ON_ONCE(n_entries == 0))
908 if (WARN_ON_ONCE(level >= n_entries))
909 level = n_entries - 1;
915 * Starting with Haswell, DDI port buffers must be programmed with correct
916 * values in advance. This function programs the correct values for
917 * DP/eDP/FDI use cases.
919 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
920 const struct intel_crtc_state *crtc_state)
922 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
925 enum port port = encoder->port;
926 const struct ddi_buf_trans *ddi_translations;
928 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
929 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
931 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
932 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
935 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
938 /* If we're boosting the current, set bit 31 of trans1 */
939 if (IS_GEN9_BC(dev_priv) &&
940 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
941 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
943 for (i = 0; i < n_entries; i++) {
944 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
945 ddi_translations[i].trans1 | iboost_bit);
946 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
947 ddi_translations[i].trans2);
952 * Starting with Haswell, DDI port buffers must be programmed with correct
953 * values in advance. This function programs the correct values for
954 * HDMI/DVI use cases.
956 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
959 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
962 enum port port = encoder->port;
963 const struct ddi_buf_trans *ddi_translations;
965 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
967 if (WARN_ON_ONCE(!ddi_translations))
969 if (WARN_ON_ONCE(level >= n_entries))
970 level = n_entries - 1;
972 /* If we're boosting the current, set bit 31 of trans1 */
973 if (IS_GEN9_BC(dev_priv) &&
974 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
975 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
977 /* Entry 9 is for HDMI: */
978 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
979 ddi_translations[level].trans1 | iboost_bit);
980 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
981 ddi_translations[level].trans2);
984 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
987 i915_reg_t reg = DDI_BUF_CTL(port);
990 for (i = 0; i < 16; i++) {
992 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
995 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
998 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1000 switch (pll->info->id) {
1001 case DPLL_ID_WRPLL1:
1002 return PORT_CLK_SEL_WRPLL1;
1003 case DPLL_ID_WRPLL2:
1004 return PORT_CLK_SEL_WRPLL2;
1006 return PORT_CLK_SEL_SPLL;
1007 case DPLL_ID_LCPLL_810:
1008 return PORT_CLK_SEL_LCPLL_810;
1009 case DPLL_ID_LCPLL_1350:
1010 return PORT_CLK_SEL_LCPLL_1350;
1011 case DPLL_ID_LCPLL_2700:
1012 return PORT_CLK_SEL_LCPLL_2700;
1014 MISSING_CASE(pll->info->id);
1015 return PORT_CLK_SEL_NONE;
1019 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1020 const struct intel_crtc_state *crtc_state)
1022 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1023 int clock = crtc_state->port_clock;
1024 const enum intel_dpll_id id = pll->info->id;
1029 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1030 * here, so do warn if this get passed in
1033 return DDI_CLK_SEL_NONE;
1034 case DPLL_ID_ICL_TBTPLL:
1037 return DDI_CLK_SEL_TBT_162;
1039 return DDI_CLK_SEL_TBT_270;
1041 return DDI_CLK_SEL_TBT_540;
1043 return DDI_CLK_SEL_TBT_810;
1045 MISSING_CASE(clock);
1046 return DDI_CLK_SEL_NONE;
1048 case DPLL_ID_ICL_MGPLL1:
1049 case DPLL_ID_ICL_MGPLL2:
1050 case DPLL_ID_ICL_MGPLL3:
1051 case DPLL_ID_ICL_MGPLL4:
1052 return DDI_CLK_SEL_MG;
1056 /* Starting with Haswell, different DDI ports can work in FDI mode for
1057 * connection to the PCH-located connectors. For this, it is necessary to train
1058 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1060 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1061 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1062 * DDI A (which is used for eDP)
1065 void hsw_fdi_link_train(struct intel_crtc *crtc,
1066 const struct intel_crtc_state *crtc_state)
1068 struct drm_device *dev = crtc->base.dev;
1069 struct drm_i915_private *dev_priv = to_i915(dev);
1070 struct intel_encoder *encoder;
1071 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1073 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1074 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1075 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1078 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1079 * mode set "sequence for CRT port" document:
1080 * - TP1 to TP2 time with the default value
1081 * - FDI delay to 90h
1083 * WaFDIAutoLinkSetTimingOverrride:hsw
1085 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1086 FDI_RX_PWRDN_LANE0_VAL(2) |
1087 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1089 /* Enable the PCH Receiver FDI PLL */
1090 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1092 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1093 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1094 POSTING_READ(FDI_RX_CTL(PIPE_A));
1097 /* Switch from Rawclk to PCDclk */
1098 rx_ctl_val |= FDI_PCDCLK;
1099 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1101 /* Configure Port Clock Select */
1102 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1103 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1104 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1106 /* Start the training iterating through available voltages and emphasis,
1107 * testing each value twice. */
1108 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1109 /* Configure DP_TP_CTL with auto-training */
1110 I915_WRITE(DP_TP_CTL(PORT_E),
1111 DP_TP_CTL_FDI_AUTOTRAIN |
1112 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1113 DP_TP_CTL_LINK_TRAIN_PAT1 |
1116 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1117 * DDI E does not support port reversal, the functionality is
1118 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1119 * port reversal bit */
1120 I915_WRITE(DDI_BUF_CTL(PORT_E),
1121 DDI_BUF_CTL_ENABLE |
1122 ((crtc_state->fdi_lanes - 1) << 1) |
1123 DDI_BUF_TRANS_SELECT(i / 2));
1124 POSTING_READ(DDI_BUF_CTL(PORT_E));
1128 /* Program PCH FDI Receiver TU */
1129 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1131 /* Enable PCH FDI Receiver with auto-training */
1132 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1133 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1134 POSTING_READ(FDI_RX_CTL(PIPE_A));
1136 /* Wait for FDI receiver lane calibration */
1139 /* Unset FDI_RX_MISC pwrdn lanes */
1140 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1141 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1142 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1143 POSTING_READ(FDI_RX_MISC(PIPE_A));
1145 /* Wait for FDI auto training time */
1148 temp = I915_READ(DP_TP_STATUS(PORT_E));
1149 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1150 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1155 * Leave things enabled even if we failed to train FDI.
1156 * Results in less fireworks from the state checker.
1158 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1159 DRM_ERROR("FDI link training failed!\n");
1163 rx_ctl_val &= ~FDI_RX_ENABLE;
1164 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1165 POSTING_READ(FDI_RX_CTL(PIPE_A));
1167 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1168 temp &= ~DDI_BUF_CTL_ENABLE;
1169 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1170 POSTING_READ(DDI_BUF_CTL(PORT_E));
1172 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1173 temp = I915_READ(DP_TP_CTL(PORT_E));
1174 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1175 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1176 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1177 POSTING_READ(DP_TP_CTL(PORT_E));
1179 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1181 /* Reset FDI_RX_MISC pwrdn lanes */
1182 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1185 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1186 POSTING_READ(FDI_RX_MISC(PIPE_A));
1189 /* Enable normal pixel sending for FDI */
1190 I915_WRITE(DP_TP_CTL(PORT_E),
1191 DP_TP_CTL_FDI_AUTOTRAIN |
1192 DP_TP_CTL_LINK_TRAIN_NORMAL |
1193 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1197 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1199 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1200 struct intel_digital_port *intel_dig_port =
1201 enc_to_dig_port(&encoder->base);
1203 intel_dp->DP = intel_dig_port->saved_port_bits |
1204 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1205 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1208 static struct intel_encoder *
1209 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1211 struct drm_device *dev = crtc->base.dev;
1212 struct intel_encoder *encoder, *ret = NULL;
1213 int num_encoders = 0;
1215 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1220 if (num_encoders != 1)
1221 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1222 pipe_name(crtc->pipe));
1224 BUG_ON(ret == NULL);
1228 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1235 wrpll = I915_READ(reg);
1236 switch (wrpll & WRPLL_REF_MASK) {
1237 case WRPLL_REF_SPECIAL_HSW:
1239 * muxed-SSC for BDW.
1240 * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1241 * for the non-SSC reference frequency.
1243 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1244 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1251 case WRPLL_REF_PCH_SSC:
1253 * We could calculate spread here, but our checking
1254 * code only cares about 5% accuracy, and spread is a max of
1259 case WRPLL_REF_LCPLL:
1263 MISSING_CASE(wrpll);
1267 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1268 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1269 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1271 /* Convert to KHz, p & r have a fixed point portion */
1272 return (refclk * n * 100) / (p * r);
1275 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1277 u32 p0, p1, p2, dco_freq;
1279 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1280 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1282 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1283 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1289 case DPLL_CFGCR2_PDIV_1:
1292 case DPLL_CFGCR2_PDIV_2:
1295 case DPLL_CFGCR2_PDIV_3:
1298 case DPLL_CFGCR2_PDIV_7:
1304 case DPLL_CFGCR2_KDIV_5:
1307 case DPLL_CFGCR2_KDIV_2:
1310 case DPLL_CFGCR2_KDIV_3:
1313 case DPLL_CFGCR2_KDIV_1:
1318 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1321 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1322 * 24 * 1000) / 0x8000;
1324 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1327 return dco_freq / (p0 * p1 * p2 * 5);
1330 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1331 struct intel_dpll_hw_state *pll_state)
1333 u32 p0, p1, p2, dco_freq, ref_clock;
1335 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1336 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1338 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1339 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1340 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1346 case DPLL_CFGCR1_PDIV_2:
1349 case DPLL_CFGCR1_PDIV_3:
1352 case DPLL_CFGCR1_PDIV_5:
1355 case DPLL_CFGCR1_PDIV_7:
1361 case DPLL_CFGCR1_KDIV_1:
1364 case DPLL_CFGCR1_KDIV_2:
1367 case DPLL_CFGCR1_KDIV_3:
1372 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1374 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1377 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1378 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1380 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1383 return dco_freq / (p0 * p1 * p2 * 5);
1386 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1389 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1392 case DDI_CLK_SEL_NONE:
1394 case DDI_CLK_SEL_TBT_162:
1396 case DDI_CLK_SEL_TBT_270:
1398 case DDI_CLK_SEL_TBT_540:
1400 case DDI_CLK_SEL_TBT_810:
1408 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1409 const struct intel_dpll_hw_state *pll_state)
1411 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1414 ref_clock = dev_priv->cdclk.hw.ref;
1416 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1417 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1418 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1419 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1420 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1422 switch (pll_state->mg_clktop2_hsclkctl &
1423 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1424 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1427 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1430 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1433 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1437 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1441 div2 = (pll_state->mg_clktop2_hsclkctl &
1442 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1443 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1445 /* div2 value of 0 is same as 1 means no div */
1450 * Adjust the original formula to delay the division by 2^22 in order to
1451 * minimize possible rounding errors.
1453 tmp = (u64)m1 * m2_int * ref_clock +
1454 (((u64)m1 * m2_frac * ref_clock) >> 22);
1455 tmp = div_u64(tmp, 5 * div1 * div2);
1460 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1464 if (pipe_config->has_pch_encoder)
1465 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1466 &pipe_config->fdi_m_n);
1467 else if (intel_crtc_has_dp_encoder(pipe_config))
1468 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1469 &pipe_config->dp_m_n);
1470 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1471 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1473 dotclock = pipe_config->port_clock;
1475 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1476 !intel_crtc_has_dp_encoder(pipe_config))
1479 if (pipe_config->pixel_multiplier)
1480 dotclock /= pipe_config->pixel_multiplier;
1482 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1485 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1486 struct intel_crtc_state *pipe_config)
1488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1489 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1490 enum port port = encoder->port;
1491 enum phy phy = intel_port_to_phy(dev_priv, port);
1494 if (intel_phy_is_combo(dev_priv, phy)) {
1495 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1497 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1498 pipe_config->shared_dpll);
1500 if (pll_id == DPLL_ID_ICL_TBTPLL)
1501 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1503 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1506 pipe_config->port_clock = link_clock;
1508 ddi_dotclock_get(pipe_config);
1511 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1512 struct intel_crtc_state *pipe_config)
1514 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1515 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1518 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1519 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1521 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1523 switch (link_clock) {
1524 case DPLL_CFGCR0_LINK_RATE_810:
1527 case DPLL_CFGCR0_LINK_RATE_1080:
1528 link_clock = 108000;
1530 case DPLL_CFGCR0_LINK_RATE_1350:
1531 link_clock = 135000;
1533 case DPLL_CFGCR0_LINK_RATE_1620:
1534 link_clock = 162000;
1536 case DPLL_CFGCR0_LINK_RATE_2160:
1537 link_clock = 216000;
1539 case DPLL_CFGCR0_LINK_RATE_2700:
1540 link_clock = 270000;
1542 case DPLL_CFGCR0_LINK_RATE_3240:
1543 link_clock = 324000;
1545 case DPLL_CFGCR0_LINK_RATE_4050:
1546 link_clock = 405000;
1549 WARN(1, "Unsupported link rate\n");
1555 pipe_config->port_clock = link_clock;
1557 ddi_dotclock_get(pipe_config);
1560 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1561 struct intel_crtc_state *pipe_config)
1563 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1567 * ctrl1 register is already shifted for each pll, just use 0 to get
1568 * the internal shift for each field
1570 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1571 link_clock = skl_calc_wrpll_link(pll_state);
1573 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1574 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1576 switch (link_clock) {
1577 case DPLL_CTRL1_LINK_RATE_810:
1580 case DPLL_CTRL1_LINK_RATE_1080:
1581 link_clock = 108000;
1583 case DPLL_CTRL1_LINK_RATE_1350:
1584 link_clock = 135000;
1586 case DPLL_CTRL1_LINK_RATE_1620:
1587 link_clock = 162000;
1589 case DPLL_CTRL1_LINK_RATE_2160:
1590 link_clock = 216000;
1592 case DPLL_CTRL1_LINK_RATE_2700:
1593 link_clock = 270000;
1596 WARN(1, "Unsupported link rate\n");
1602 pipe_config->port_clock = link_clock;
1604 ddi_dotclock_get(pipe_config);
1607 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1608 struct intel_crtc_state *pipe_config)
1610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1614 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1615 switch (val & PORT_CLK_SEL_MASK) {
1616 case PORT_CLK_SEL_LCPLL_810:
1619 case PORT_CLK_SEL_LCPLL_1350:
1620 link_clock = 135000;
1622 case PORT_CLK_SEL_LCPLL_2700:
1623 link_clock = 270000;
1625 case PORT_CLK_SEL_WRPLL1:
1626 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1628 case PORT_CLK_SEL_WRPLL2:
1629 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1631 case PORT_CLK_SEL_SPLL:
1632 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1633 if (pll == SPLL_FREQ_810MHz)
1635 else if (pll == SPLL_FREQ_1350MHz)
1636 link_clock = 135000;
1637 else if (pll == SPLL_FREQ_2700MHz)
1638 link_clock = 270000;
1640 WARN(1, "bad spll freq\n");
1645 WARN(1, "bad port clock sel\n");
1649 pipe_config->port_clock = link_clock * 2;
1651 ddi_dotclock_get(pipe_config);
1654 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1659 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1660 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1661 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1662 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1663 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1664 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1666 return chv_calc_dpll_params(100000, &clock);
1669 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1670 struct intel_crtc_state *pipe_config)
1672 pipe_config->port_clock =
1673 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1675 ddi_dotclock_get(pipe_config);
1678 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1679 struct intel_crtc_state *pipe_config)
1681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1683 if (INTEL_GEN(dev_priv) >= 11)
1684 icl_ddi_clock_get(encoder, pipe_config);
1685 else if (IS_CANNONLAKE(dev_priv))
1686 cnl_ddi_clock_get(encoder, pipe_config);
1687 else if (IS_GEN9_LP(dev_priv))
1688 bxt_ddi_clock_get(encoder, pipe_config);
1689 else if (IS_GEN9_BC(dev_priv))
1690 skl_ddi_clock_get(encoder, pipe_config);
1691 else if (INTEL_GEN(dev_priv) <= 8)
1692 hsw_ddi_clock_get(encoder, pipe_config);
1695 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1697 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1698 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1699 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1702 if (!intel_crtc_has_dp_encoder(crtc_state))
1705 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1707 temp = TRANS_MSA_SYNC_CLK;
1709 if (crtc_state->limited_color_range)
1710 temp |= TRANS_MSA_CEA_RANGE;
1712 switch (crtc_state->pipe_bpp) {
1714 temp |= TRANS_MSA_6_BPC;
1717 temp |= TRANS_MSA_8_BPC;
1720 temp |= TRANS_MSA_10_BPC;
1723 temp |= TRANS_MSA_12_BPC;
1726 MISSING_CASE(crtc_state->pipe_bpp);
1731 * As per DP 1.2 spec section 2.3.4.3 while sending
1732 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1733 * colorspace information. The output colorspace encoding is BT601.
1735 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1736 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1738 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1739 * of Color Encoding Format and Content Color Gamut] while sending
1740 * YCBCR 420 signals we should program MSA MISC1 fields which
1741 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1744 temp |= TRANS_MSA_USE_VSC_SDP;
1745 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1748 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1753 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1756 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1758 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1760 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1761 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1764 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1766 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1767 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1768 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1769 enum pipe pipe = crtc->pipe;
1770 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1771 enum port port = encoder->port;
1774 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1775 temp = TRANS_DDI_FUNC_ENABLE;
1776 if (INTEL_GEN(dev_priv) >= 12)
1777 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1779 temp |= TRANS_DDI_SELECT_PORT(port);
1781 switch (crtc_state->pipe_bpp) {
1783 temp |= TRANS_DDI_BPC_6;
1786 temp |= TRANS_DDI_BPC_8;
1789 temp |= TRANS_DDI_BPC_10;
1792 temp |= TRANS_DDI_BPC_12;
1798 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1799 temp |= TRANS_DDI_PVSYNC;
1800 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1801 temp |= TRANS_DDI_PHSYNC;
1803 if (cpu_transcoder == TRANSCODER_EDP) {
1806 /* On Haswell, can only use the always-on power well for
1807 * eDP when not using the panel fitter, and when not
1808 * using motion blur mitigation (which we don't
1810 if (crtc_state->pch_pfit.force_thru)
1811 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1813 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1816 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1819 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1827 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1828 if (crtc_state->has_hdmi_sink)
1829 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1831 temp |= TRANS_DDI_MODE_SELECT_DVI;
1833 if (crtc_state->hdmi_scrambling)
1834 temp |= TRANS_DDI_HDMI_SCRAMBLING;
1835 if (crtc_state->hdmi_high_tmds_clock_ratio)
1836 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1837 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1838 temp |= TRANS_DDI_MODE_SELECT_FDI;
1839 temp |= (crtc_state->fdi_lanes - 1) << 1;
1840 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1841 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1842 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1844 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1845 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1848 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1851 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1853 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1855 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1856 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1857 u32 val = I915_READ(reg);
1859 if (INTEL_GEN(dev_priv) >= 12) {
1860 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1861 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1863 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1864 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1866 I915_WRITE(reg, val);
1868 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1869 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1870 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1871 /* Quirk time at 100ms for reliable operation */
1876 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1879 struct drm_device *dev = intel_encoder->base.dev;
1880 struct drm_i915_private *dev_priv = to_i915(dev);
1881 intel_wakeref_t wakeref;
1886 wakeref = intel_display_power_get_if_enabled(dev_priv,
1887 intel_encoder->power_domain);
1888 if (WARN_ON(!wakeref))
1891 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1896 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1898 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1900 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1901 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1903 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1907 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1909 struct drm_device *dev = intel_connector->base.dev;
1910 struct drm_i915_private *dev_priv = to_i915(dev);
1911 struct intel_encoder *encoder = intel_connector->encoder;
1912 int type = intel_connector->base.connector_type;
1913 enum port port = encoder->port;
1914 enum transcoder cpu_transcoder;
1915 intel_wakeref_t wakeref;
1920 wakeref = intel_display_power_get_if_enabled(dev_priv,
1921 encoder->power_domain);
1925 if (!encoder->get_hw_state(encoder, &pipe)) {
1930 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1931 cpu_transcoder = TRANSCODER_EDP;
1933 cpu_transcoder = (enum transcoder) pipe;
1935 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1937 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1938 case TRANS_DDI_MODE_SELECT_HDMI:
1939 case TRANS_DDI_MODE_SELECT_DVI:
1940 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1943 case TRANS_DDI_MODE_SELECT_DP_SST:
1944 ret = type == DRM_MODE_CONNECTOR_eDP ||
1945 type == DRM_MODE_CONNECTOR_DisplayPort;
1948 case TRANS_DDI_MODE_SELECT_DP_MST:
1949 /* if the transcoder is in MST state then
1950 * connector isn't connected */
1954 case TRANS_DDI_MODE_SELECT_FDI:
1955 ret = type == DRM_MODE_CONNECTOR_VGA;
1964 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1969 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1970 u8 *pipe_mask, bool *is_dp_mst)
1972 struct drm_device *dev = encoder->base.dev;
1973 struct drm_i915_private *dev_priv = to_i915(dev);
1974 enum port port = encoder->port;
1975 intel_wakeref_t wakeref;
1983 wakeref = intel_display_power_get_if_enabled(dev_priv,
1984 encoder->power_domain);
1988 tmp = I915_READ(DDI_BUF_CTL(port));
1989 if (!(tmp & DDI_BUF_CTL_ENABLE))
1992 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1993 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1995 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1997 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1999 case TRANS_DDI_EDP_INPUT_A_ON:
2000 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2001 *pipe_mask = BIT(PIPE_A);
2003 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2004 *pipe_mask = BIT(PIPE_B);
2006 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2007 *pipe_mask = BIT(PIPE_C);
2015 for_each_pipe(dev_priv, p) {
2016 enum transcoder cpu_transcoder = (enum transcoder)p;
2017 unsigned int port_mask, ddi_select;
2018 intel_wakeref_t trans_wakeref;
2020 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2021 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2025 if (INTEL_GEN(dev_priv) >= 12) {
2026 port_mask = TGL_TRANS_DDI_PORT_MASK;
2027 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2029 port_mask = TRANS_DDI_PORT_MASK;
2030 ddi_select = TRANS_DDI_SELECT_PORT(port);
2033 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2034 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2037 if ((tmp & port_mask) != ddi_select)
2040 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2041 TRANS_DDI_MODE_SELECT_DP_MST)
2042 mst_pipe_mask |= BIT(p);
2044 *pipe_mask |= BIT(p);
2048 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2051 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2052 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2053 port_name(port), *pipe_mask);
2054 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2057 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2058 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2059 port_name(port), *pipe_mask, mst_pipe_mask);
2061 *is_dp_mst = mst_pipe_mask;
2064 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2065 tmp = I915_READ(BXT_PHY_CTL(port));
2066 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2067 BXT_PHY_LANE_POWERDOWN_ACK |
2068 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2069 DRM_ERROR("Port %c enabled but PHY powered down? "
2070 "(PHY_CTL %08x)\n", port_name(port), tmp);
2073 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2076 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2082 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2084 if (is_mst || !pipe_mask)
2087 *pipe = ffs(pipe_mask) - 1;
2092 static inline enum intel_display_power_domain
2093 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2095 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2096 * DC states enabled at the same time, while for driver initiated AUX
2097 * transfers we need the same AUX IOs to be powered but with DC states
2098 * disabled. Accordingly use the AUX power domain here which leaves DC
2100 * However, for non-A AUX ports the corresponding non-EDP transcoders
2101 * would have already enabled power well 2 and DC_OFF. This means we can
2102 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2103 * specific AUX_IO reference without powering up any extra wells.
2104 * Note that PSR is enabled only on Port A even though this function
2105 * returns the correct domain for other ports too.
2107 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2108 intel_aux_power_domain(dig_port);
2111 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2112 struct intel_crtc_state *crtc_state)
2114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2115 struct intel_digital_port *dig_port;
2116 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2119 * TODO: Add support for MST encoders. Atm, the following should never
2120 * happen since fake-MST encoders don't set their get_power_domains()
2123 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2126 dig_port = enc_to_dig_port(&encoder->base);
2128 if (!intel_phy_is_tc(dev_priv, phy) ||
2129 dig_port->tc_mode != TC_PORT_TBT_ALT)
2130 intel_display_power_get(dev_priv,
2131 dig_port->ddi_io_power_domain);
2134 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2137 if (intel_crtc_has_dp_encoder(crtc_state) ||
2138 intel_phy_is_tc(dev_priv, phy))
2139 intel_display_power_get(dev_priv,
2140 intel_ddi_main_link_aux_domain(dig_port));
2143 * VDSC power is needed when DSC is enabled
2145 if (crtc_state->dsc_params.compression_enable)
2146 intel_display_power_get(dev_priv,
2147 intel_dsc_power_domain(crtc_state));
2150 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2152 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2153 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2154 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2155 enum port port = encoder->port;
2156 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2158 if (cpu_transcoder != TRANSCODER_EDP) {
2159 if (INTEL_GEN(dev_priv) >= 12)
2160 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2161 TGL_TRANS_CLK_SEL_PORT(port));
2163 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2164 TRANS_CLK_SEL_PORT(port));
2168 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2170 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2171 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2173 if (cpu_transcoder != TRANSCODER_EDP) {
2174 if (INTEL_GEN(dev_priv) >= 12)
2175 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2176 TGL_TRANS_CLK_SEL_DISABLED);
2178 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2179 TRANS_CLK_SEL_DISABLED);
2183 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2184 enum port port, u8 iboost)
2188 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2189 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2191 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2193 tmp |= BALANCE_LEG_DISABLE(port);
2194 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2197 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2198 int level, enum intel_output_type type)
2200 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2202 enum port port = encoder->port;
2205 if (type == INTEL_OUTPUT_HDMI)
2206 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2208 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2211 const struct ddi_buf_trans *ddi_translations;
2214 if (type == INTEL_OUTPUT_HDMI)
2215 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2216 else if (type == INTEL_OUTPUT_EDP)
2217 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2219 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2221 if (WARN_ON_ONCE(!ddi_translations))
2223 if (WARN_ON_ONCE(level >= n_entries))
2224 level = n_entries - 1;
2226 iboost = ddi_translations[level].i_boost;
2229 /* Make sure that the requested I_boost is valid */
2230 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2231 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2235 _skl_ddi_set_iboost(dev_priv, port, iboost);
2237 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2238 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2241 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2242 int level, enum intel_output_type type)
2244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2245 const struct bxt_ddi_buf_trans *ddi_translations;
2246 enum port port = encoder->port;
2249 if (type == INTEL_OUTPUT_HDMI)
2250 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2251 else if (type == INTEL_OUTPUT_EDP)
2252 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2254 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2256 if (WARN_ON_ONCE(!ddi_translations))
2258 if (WARN_ON_ONCE(level >= n_entries))
2259 level = n_entries - 1;
2261 bxt_ddi_phy_set_signal_level(dev_priv, port,
2262 ddi_translations[level].margin,
2263 ddi_translations[level].scale,
2264 ddi_translations[level].enable,
2265 ddi_translations[level].deemphasis);
2268 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2271 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2272 enum port port = encoder->port;
2273 enum phy phy = intel_port_to_phy(dev_priv, port);
2276 if (INTEL_GEN(dev_priv) >= 11) {
2277 if (intel_phy_is_combo(dev_priv, phy))
2278 icl_get_combo_buf_trans(dev_priv, encoder->type,
2279 intel_dp->link_rate, &n_entries);
2281 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2282 } else if (IS_CANNONLAKE(dev_priv)) {
2283 if (encoder->type == INTEL_OUTPUT_EDP)
2284 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2286 cnl_get_buf_trans_dp(dev_priv, &n_entries);
2287 } else if (IS_GEN9_LP(dev_priv)) {
2288 if (encoder->type == INTEL_OUTPUT_EDP)
2289 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2291 bxt_get_buf_trans_dp(dev_priv, &n_entries);
2293 if (encoder->type == INTEL_OUTPUT_EDP)
2294 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2296 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2299 if (WARN_ON(n_entries < 1))
2301 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2302 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2304 return index_to_dp_signal_levels[n_entries - 1] &
2305 DP_TRAIN_VOLTAGE_SWING_MASK;
2309 * We assume that the full set of pre-emphasis values can be
2310 * used on all DDI platforms. Should that change we need to
2311 * rethink this code.
2313 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2315 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2317 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2319 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2321 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2324 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2328 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2329 int level, enum intel_output_type type)
2331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2332 const struct cnl_ddi_buf_trans *ddi_translations;
2333 enum port port = encoder->port;
2337 if (type == INTEL_OUTPUT_HDMI)
2338 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2339 else if (type == INTEL_OUTPUT_EDP)
2340 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2342 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2344 if (WARN_ON_ONCE(!ddi_translations))
2346 if (WARN_ON_ONCE(level >= n_entries))
2347 level = n_entries - 1;
2349 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2350 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2351 val &= ~SCALING_MODE_SEL_MASK;
2352 val |= SCALING_MODE_SEL(2);
2353 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2355 /* Program PORT_TX_DW2 */
2356 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2357 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2359 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2360 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2361 /* Rcomp scalar is fixed as 0x98 for every table entry */
2362 val |= RCOMP_SCALAR(0x98);
2363 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2365 /* Program PORT_TX_DW4 */
2366 /* We cannot write to GRP. It would overrite individual loadgen */
2367 for (ln = 0; ln < 4; ln++) {
2368 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2369 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2371 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2372 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2373 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2374 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2377 /* Program PORT_TX_DW5 */
2378 /* All DW5 values are fixed for every table entry */
2379 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2380 val &= ~RTERM_SELECT_MASK;
2381 val |= RTERM_SELECT(6);
2382 val |= TAP3_DISABLE;
2383 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2385 /* Program PORT_TX_DW7 */
2386 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2387 val &= ~N_SCALAR_MASK;
2388 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2389 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2392 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2393 int level, enum intel_output_type type)
2395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2396 enum port port = encoder->port;
2397 int width, rate, ln;
2400 if (type == INTEL_OUTPUT_HDMI) {
2402 rate = 0; /* Rate is always < than 6GHz for HDMI */
2404 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2406 width = intel_dp->lane_count;
2407 rate = intel_dp->link_rate;
2411 * 1. If port type is eDP or DP,
2412 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2415 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2416 if (type != INTEL_OUTPUT_HDMI)
2417 val |= COMMON_KEEPER_EN;
2419 val &= ~COMMON_KEEPER_EN;
2420 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2422 /* 2. Program loadgen select */
2424 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2425 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2426 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2427 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2429 for (ln = 0; ln <= 3; ln++) {
2430 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2431 val &= ~LOADGEN_SELECT;
2433 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2434 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2435 val |= LOADGEN_SELECT;
2437 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2440 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2441 val = I915_READ(CNL_PORT_CL1CM_DW5);
2442 val |= SUS_CLOCK_CONFIG;
2443 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2445 /* 4. Clear training enable to change swing values */
2446 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2447 val &= ~TX_TRAINING_EN;
2448 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2450 /* 5. Program swing and de-emphasis */
2451 cnl_ddi_vswing_program(encoder, level, type);
2453 /* 6. Set training enable to trigger update */
2454 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2455 val |= TX_TRAINING_EN;
2456 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2459 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2460 u32 level, enum phy phy, int type,
2463 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2467 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2469 if (!ddi_translations)
2472 if (level >= n_entries) {
2473 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2474 level = n_entries - 1;
2477 /* Set PORT_TX_DW5 */
2478 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2479 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2480 TAP2_DISABLE | TAP3_DISABLE);
2481 val |= SCALING_MODE_SEL(0x2);
2482 val |= RTERM_SELECT(0x6);
2483 val |= TAP3_DISABLE;
2484 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2486 /* Program PORT_TX_DW2 */
2487 val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2488 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2490 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2491 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2492 /* Program Rcomp scalar for every table entry */
2493 val |= RCOMP_SCALAR(0x98);
2494 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2496 /* Program PORT_TX_DW4 */
2497 /* We cannot write to GRP. It would overwrite individual loadgen. */
2498 for (ln = 0; ln <= 3; ln++) {
2499 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2500 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2502 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2503 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2504 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2505 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2508 /* Program PORT_TX_DW7 */
2509 val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2510 val &= ~N_SCALAR_MASK;
2511 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2512 I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2515 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2517 enum intel_output_type type)
2519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2520 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2526 if (type == INTEL_OUTPUT_HDMI) {
2528 /* Rate is always < than 6GHz for HDMI */
2530 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2532 width = intel_dp->lane_count;
2533 rate = intel_dp->link_rate;
2537 * 1. If port type is eDP or DP,
2538 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2541 val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2542 if (type == INTEL_OUTPUT_HDMI)
2543 val &= ~COMMON_KEEPER_EN;
2545 val |= COMMON_KEEPER_EN;
2546 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2548 /* 2. Program loadgen select */
2550 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2551 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2552 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2553 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2555 for (ln = 0; ln <= 3; ln++) {
2556 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2557 val &= ~LOADGEN_SELECT;
2559 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2560 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2561 val |= LOADGEN_SELECT;
2563 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2566 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2567 val = I915_READ(ICL_PORT_CL_DW5(phy));
2568 val |= SUS_CLOCK_CONFIG;
2569 I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2571 /* 4. Clear training enable to change swing values */
2572 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2573 val &= ~TX_TRAINING_EN;
2574 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2576 /* 5. Program swing and de-emphasis */
2577 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2579 /* 6. Set training enable to trigger update */
2580 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2581 val |= TX_TRAINING_EN;
2582 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2585 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2589 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2590 enum port port = encoder->port;
2591 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2595 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2596 ddi_translations = icl_mg_phy_ddi_translations;
2597 /* The table does not have values for level 3 and level 9. */
2598 if (level >= n_entries || level == 3 || level == 9) {
2599 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2600 level, n_entries - 2);
2601 level = n_entries - 2;
2604 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2605 for (ln = 0; ln < 2; ln++) {
2606 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2607 val &= ~CRI_USE_FS32;
2608 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2610 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2611 val &= ~CRI_USE_FS32;
2612 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2615 /* Program MG_TX_SWINGCTRL with values from vswing table */
2616 for (ln = 0; ln < 2; ln++) {
2617 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2618 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2619 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2620 ddi_translations[level].cri_txdeemph_override_17_12);
2621 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2623 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2624 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2625 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2626 ddi_translations[level].cri_txdeemph_override_17_12);
2627 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2630 /* Program MG_TX_DRVCTRL with values from vswing table */
2631 for (ln = 0; ln < 2; ln++) {
2632 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2633 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2634 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2635 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2636 ddi_translations[level].cri_txdeemph_override_5_0) |
2637 CRI_TXDEEMPH_OVERRIDE_11_6(
2638 ddi_translations[level].cri_txdeemph_override_11_6) |
2639 CRI_TXDEEMPH_OVERRIDE_EN;
2640 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2642 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2643 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2644 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2645 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2646 ddi_translations[level].cri_txdeemph_override_5_0) |
2647 CRI_TXDEEMPH_OVERRIDE_11_6(
2648 ddi_translations[level].cri_txdeemph_override_11_6) |
2649 CRI_TXDEEMPH_OVERRIDE_EN;
2650 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2652 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2656 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2657 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2658 * values from table for which TX1 and TX2 enabled.
2660 for (ln = 0; ln < 2; ln++) {
2661 val = I915_READ(MG_CLKHUB(ln, port));
2662 if (link_clock < 300000)
2663 val |= CFG_LOW_RATE_LKREN_EN;
2665 val &= ~CFG_LOW_RATE_LKREN_EN;
2666 I915_WRITE(MG_CLKHUB(ln, port), val);
2669 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2670 for (ln = 0; ln < 2; ln++) {
2671 val = I915_READ(MG_TX1_DCC(ln, port));
2672 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2673 if (link_clock <= 500000) {
2674 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2676 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2677 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2679 I915_WRITE(MG_TX1_DCC(ln, port), val);
2681 val = I915_READ(MG_TX2_DCC(ln, port));
2682 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2683 if (link_clock <= 500000) {
2684 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2686 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2687 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2689 I915_WRITE(MG_TX2_DCC(ln, port), val);
2692 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2693 for (ln = 0; ln < 2; ln++) {
2694 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2695 val |= CRI_CALCINIT;
2696 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2698 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2699 val |= CRI_CALCINIT;
2700 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2704 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2707 enum intel_output_type type)
2709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2710 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2712 if (intel_phy_is_combo(dev_priv, phy))
2713 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2715 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2718 static u32 translate_signal_level(int signal_levels)
2722 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2723 if (index_to_dp_signal_levels[i] == signal_levels)
2727 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2733 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2735 u8 train_set = intel_dp->train_set[0];
2736 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2737 DP_TRAIN_PRE_EMPHASIS_MASK);
2739 return translate_signal_level(signal_levels);
2742 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2744 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2745 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2746 struct intel_encoder *encoder = &dport->base;
2747 int level = intel_ddi_dp_level(intel_dp);
2749 if (INTEL_GEN(dev_priv) >= 11)
2750 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2751 level, encoder->type);
2752 else if (IS_CANNONLAKE(dev_priv))
2753 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2755 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2760 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2762 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2763 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2764 struct intel_encoder *encoder = &dport->base;
2765 int level = intel_ddi_dp_level(intel_dp);
2767 if (IS_GEN9_BC(dev_priv))
2768 skl_ddi_set_iboost(encoder, level, encoder->type);
2770 return DDI_BUF_TRANS_SELECT(level);
2774 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2777 if (intel_phy_is_combo(dev_priv, phy)) {
2778 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2779 } else if (intel_phy_is_tc(dev_priv, phy)) {
2780 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2783 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2789 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2790 const struct intel_crtc_state *crtc_state)
2792 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2793 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2794 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2797 mutex_lock(&dev_priv->dpll_lock);
2799 val = I915_READ(ICL_DPCLKA_CFGCR0);
2800 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2802 if (intel_phy_is_combo(dev_priv, phy)) {
2804 * Even though this register references DDIs, note that we
2805 * want to pass the PHY rather than the port (DDI). For
2806 * ICL, port=phy in all cases so it doesn't matter, but for
2807 * EHL the bspec notes the following:
2809 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2810 * Clock Select chooses the PLL for both DDIA and DDID and
2811 * drives port A in all cases."
2813 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2814 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2815 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2816 POSTING_READ(ICL_DPCLKA_CFGCR0);
2819 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2820 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2822 mutex_unlock(&dev_priv->dpll_lock);
2825 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2827 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2828 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2831 mutex_lock(&dev_priv->dpll_lock);
2833 val = I915_READ(ICL_DPCLKA_CFGCR0);
2834 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2835 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2837 mutex_unlock(&dev_priv->dpll_lock);
2840 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2842 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2846 bool ddi_clk_needed;
2849 * In case of DP MST, we sanitize the primary encoder only, not the
2852 if (encoder->type == INTEL_OUTPUT_DP_MST)
2855 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2859 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2861 * In the unlikely case that BIOS enables DP in MST mode, just
2862 * warn since our MST HW readout is incomplete.
2864 if (WARN_ON(is_mst))
2868 port_mask = BIT(encoder->port);
2869 ddi_clk_needed = encoder->base.crtc;
2871 if (encoder->type == INTEL_OUTPUT_DSI) {
2872 struct intel_encoder *other_encoder;
2874 port_mask = intel_dsi_encoder_ports(encoder);
2876 * Sanity check that we haven't incorrectly registered another
2877 * encoder using any of the ports of this DSI encoder.
2879 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2880 if (other_encoder == encoder)
2883 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2887 * For DSI we keep the ddi clocks gated
2888 * except during enable/disable sequence.
2890 ddi_clk_needed = false;
2893 val = I915_READ(ICL_DPCLKA_CFGCR0);
2894 for_each_port_masked(port, port_mask) {
2895 enum phy phy = intel_port_to_phy(dev_priv, port);
2897 bool ddi_clk_ungated = !(val &
2898 icl_dpclka_cfgcr0_clk_off(dev_priv,
2901 if (ddi_clk_needed == ddi_clk_ungated)
2905 * Punt on the case now where clock is gated, but it would
2906 * be needed by the port. Something else is really broken then.
2908 if (WARN_ON(ddi_clk_needed))
2911 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2913 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2914 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2918 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2919 const struct intel_crtc_state *crtc_state)
2921 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2922 enum port port = encoder->port;
2923 enum phy phy = intel_port_to_phy(dev_priv, port);
2925 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2930 mutex_lock(&dev_priv->dpll_lock);
2932 if (INTEL_GEN(dev_priv) >= 11) {
2933 if (!intel_phy_is_combo(dev_priv, phy))
2934 I915_WRITE(DDI_CLK_SEL(port),
2935 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2936 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
2938 * MG does not exist but the programming is required
2939 * to ungate DDIC and DDID
2941 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
2942 } else if (IS_CANNONLAKE(dev_priv)) {
2943 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2944 val = I915_READ(DPCLKA_CFGCR0);
2945 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2946 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2947 I915_WRITE(DPCLKA_CFGCR0, val);
2950 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2951 * This step and the step before must be done with separate
2954 val = I915_READ(DPCLKA_CFGCR0);
2955 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2956 I915_WRITE(DPCLKA_CFGCR0, val);
2957 } else if (IS_GEN9_BC(dev_priv)) {
2958 /* DDI -> PLL mapping */
2959 val = I915_READ(DPLL_CTRL2);
2961 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2962 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2963 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2964 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2966 I915_WRITE(DPLL_CTRL2, val);
2968 } else if (INTEL_GEN(dev_priv) < 9) {
2969 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2972 mutex_unlock(&dev_priv->dpll_lock);
2975 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2977 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2978 enum port port = encoder->port;
2979 enum phy phy = intel_port_to_phy(dev_priv, port);
2981 if (INTEL_GEN(dev_priv) >= 11) {
2982 if (!intel_phy_is_combo(dev_priv, phy) ||
2983 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
2984 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2985 } else if (IS_CANNONLAKE(dev_priv)) {
2986 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2987 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2988 } else if (IS_GEN9_BC(dev_priv)) {
2989 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2990 DPLL_CTRL2_DDI_CLK_OFF(port));
2991 } else if (INTEL_GEN(dev_priv) < 9) {
2992 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2996 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2998 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2999 enum port port = dig_port->base.port;
3000 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3004 if (tc_port == PORT_TC_NONE)
3007 for (ln = 0; ln < 2; ln++) {
3008 val = I915_READ(MG_DP_MODE(ln, port));
3009 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
3010 MG_DP_MODE_CFG_TRPWR_GATING |
3011 MG_DP_MODE_CFG_CLNPWR_GATING |
3012 MG_DP_MODE_CFG_DIGPWR_GATING |
3013 MG_DP_MODE_CFG_GAONPWR_GATING;
3014 I915_WRITE(MG_DP_MODE(ln, port), val);
3017 val = I915_READ(MG_MISC_SUS0(tc_port));
3018 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
3019 MG_MISC_SUS0_CFG_TR2PWR_GATING |
3020 MG_MISC_SUS0_CFG_CL2PWR_GATING |
3021 MG_MISC_SUS0_CFG_GAONPWR_GATING |
3022 MG_MISC_SUS0_CFG_TRPWR_GATING |
3023 MG_MISC_SUS0_CFG_CL1PWR_GATING |
3024 MG_MISC_SUS0_CFG_DGPWR_GATING;
3025 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3028 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
3030 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3031 enum port port = dig_port->base.port;
3032 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3036 if (tc_port == PORT_TC_NONE)
3039 for (ln = 0; ln < 2; ln++) {
3040 val = I915_READ(MG_DP_MODE(ln, port));
3041 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
3042 MG_DP_MODE_CFG_TRPWR_GATING |
3043 MG_DP_MODE_CFG_CLNPWR_GATING |
3044 MG_DP_MODE_CFG_DIGPWR_GATING |
3045 MG_DP_MODE_CFG_GAONPWR_GATING);
3046 I915_WRITE(MG_DP_MODE(ln, port), val);
3049 val = I915_READ(MG_MISC_SUS0(tc_port));
3050 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
3051 MG_MISC_SUS0_CFG_TR2PWR_GATING |
3052 MG_MISC_SUS0_CFG_CL2PWR_GATING |
3053 MG_MISC_SUS0_CFG_GAONPWR_GATING |
3054 MG_MISC_SUS0_CFG_TRPWR_GATING |
3055 MG_MISC_SUS0_CFG_CL1PWR_GATING |
3056 MG_MISC_SUS0_CFG_DGPWR_GATING);
3057 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3060 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
3062 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3063 enum port port = intel_dig_port->base.port;
3064 u32 ln0, ln1, lane_mask;
3066 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3069 ln0 = I915_READ(MG_DP_MODE(0, port));
3070 ln1 = I915_READ(MG_DP_MODE(1, port));
3072 switch (intel_dig_port->tc_mode) {
3073 case TC_PORT_DP_ALT:
3074 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3075 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3077 lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
3079 switch (lane_mask) {
3084 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3087 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3088 MG_DP_MODE_CFG_DP_X2_MODE;
3091 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3094 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3095 MG_DP_MODE_CFG_DP_X2_MODE;
3098 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3099 MG_DP_MODE_CFG_DP_X2_MODE;
3100 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3101 MG_DP_MODE_CFG_DP_X2_MODE;
3104 MISSING_CASE(lane_mask);
3108 case TC_PORT_LEGACY:
3109 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3110 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3114 MISSING_CASE(intel_dig_port->tc_mode);
3118 I915_WRITE(MG_DP_MODE(0, port), ln0);
3119 I915_WRITE(MG_DP_MODE(1, port), ln1);
3122 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3123 const struct intel_crtc_state *crtc_state)
3125 if (!crtc_state->fec_enable)
3128 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3129 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3132 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3133 const struct intel_crtc_state *crtc_state)
3135 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3136 enum port port = encoder->port;
3139 if (!crtc_state->fec_enable)
3142 val = I915_READ(DP_TP_CTL(port));
3143 val |= DP_TP_CTL_FEC_ENABLE;
3144 I915_WRITE(DP_TP_CTL(port), val);
3146 if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
3147 DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3148 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3151 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3152 const struct intel_crtc_state *crtc_state)
3154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3155 enum port port = encoder->port;
3158 if (!crtc_state->fec_enable)
3161 val = I915_READ(DP_TP_CTL(port));
3162 val &= ~DP_TP_CTL_FEC_ENABLE;
3163 I915_WRITE(DP_TP_CTL(port), val);
3164 POSTING_READ(DP_TP_CTL(port));
3167 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3168 const struct intel_crtc_state *crtc_state,
3169 const struct drm_connector_state *conn_state)
3171 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3173 enum port port = encoder->port;
3174 enum phy phy = intel_port_to_phy(dev_priv, port);
3175 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3176 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3177 int level = intel_ddi_dp_level(intel_dp);
3179 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3181 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3182 crtc_state->lane_count, is_mst);
3184 intel_edp_panel_on(intel_dp);
3186 intel_ddi_clk_select(encoder, crtc_state);
3188 if (!intel_phy_is_tc(dev_priv, phy) ||
3189 dig_port->tc_mode != TC_PORT_TBT_ALT)
3190 intel_display_power_get(dev_priv,
3191 dig_port->ddi_io_power_domain);
3193 icl_program_mg_dp_mode(dig_port);
3194 icl_disable_phy_clock_gating(dig_port);
3196 if (INTEL_GEN(dev_priv) >= 11)
3197 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3198 level, encoder->type);
3199 else if (IS_CANNONLAKE(dev_priv))
3200 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3201 else if (IS_GEN9_LP(dev_priv))
3202 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3204 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3206 if (intel_phy_is_combo(dev_priv, phy)) {
3207 bool lane_reversal =
3208 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3210 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3211 crtc_state->lane_count,
3215 intel_ddi_init_dp_buf_reg(encoder);
3217 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3218 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3220 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3221 intel_dp_start_link_train(intel_dp);
3222 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3223 intel_dp_stop_link_train(intel_dp);
3225 intel_ddi_enable_fec(encoder, crtc_state);
3227 icl_enable_phy_clock_gating(dig_port);
3230 intel_ddi_enable_pipe_clock(crtc_state);
3232 intel_dsc_enable(encoder, crtc_state);
3235 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3236 const struct intel_crtc_state *crtc_state,
3237 const struct drm_connector_state *conn_state)
3239 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3240 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3242 enum port port = encoder->port;
3243 int level = intel_ddi_hdmi_level(dev_priv, port);
3244 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3246 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3247 intel_ddi_clk_select(encoder, crtc_state);
3249 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3251 icl_program_mg_dp_mode(dig_port);
3252 icl_disable_phy_clock_gating(dig_port);
3254 if (INTEL_GEN(dev_priv) >= 11)
3255 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3256 level, INTEL_OUTPUT_HDMI);
3257 else if (IS_CANNONLAKE(dev_priv))
3258 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3259 else if (IS_GEN9_LP(dev_priv))
3260 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3262 intel_prepare_hdmi_ddi_buffers(encoder, level);
3264 icl_enable_phy_clock_gating(dig_port);
3266 if (IS_GEN9_BC(dev_priv))
3267 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3269 intel_ddi_enable_pipe_clock(crtc_state);
3271 intel_dig_port->set_infoframes(encoder,
3272 crtc_state->has_infoframe,
3273 crtc_state, conn_state);
3276 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3277 const struct intel_crtc_state *crtc_state,
3278 const struct drm_connector_state *conn_state)
3280 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3281 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3282 enum pipe pipe = crtc->pipe;
3285 * When called from DP MST code:
3286 * - conn_state will be NULL
3287 * - encoder will be the main encoder (ie. mst->primary)
3288 * - the main connector associated with this port
3289 * won't be active or linked to a crtc
3290 * - crtc_state will be the state of the first stream to
3291 * be activated on this port, and it may not be the same
3292 * stream that will be deactivated last, but each stream
3293 * should have a state that is identical when it comes to
3294 * the DP link parameteres
3297 WARN_ON(crtc_state->has_pch_encoder);
3299 if (INTEL_GEN(dev_priv) >= 11)
3300 icl_map_plls_to_ports(encoder, crtc_state);
3302 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3304 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3305 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3307 struct intel_lspcon *lspcon =
3308 enc_to_intel_lspcon(&encoder->base);
3310 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3311 if (lspcon->active) {
3312 struct intel_digital_port *dig_port =
3313 enc_to_dig_port(&encoder->base);
3315 dig_port->set_infoframes(encoder,
3316 crtc_state->has_infoframe,
3317 crtc_state, conn_state);
3322 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3323 const struct intel_crtc_state *crtc_state)
3325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3326 enum port port = encoder->port;
3330 val = I915_READ(DDI_BUF_CTL(port));
3331 if (val & DDI_BUF_CTL_ENABLE) {
3332 val &= ~DDI_BUF_CTL_ENABLE;
3333 I915_WRITE(DDI_BUF_CTL(port), val);
3337 val = I915_READ(DP_TP_CTL(port));
3338 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3339 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3340 I915_WRITE(DP_TP_CTL(port), val);
3342 /* Disable FEC in DP Sink */
3343 intel_ddi_disable_fec_state(encoder, crtc_state);
3346 intel_wait_ddi_buf_idle(dev_priv, port);
3349 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3350 const struct intel_crtc_state *old_crtc_state,
3351 const struct drm_connector_state *old_conn_state)
3353 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3354 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3355 struct intel_dp *intel_dp = &dig_port->dp;
3356 bool is_mst = intel_crtc_has_type(old_crtc_state,
3357 INTEL_OUTPUT_DP_MST);
3358 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3361 intel_ddi_disable_pipe_clock(old_crtc_state);
3363 * Power down sink before disabling the port, otherwise we end
3364 * up getting interrupts from the sink on detecting link loss.
3366 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3369 intel_disable_ddi_buf(encoder, old_crtc_state);
3371 intel_edp_panel_vdd_on(intel_dp);
3372 intel_edp_panel_off(intel_dp);
3374 if (!intel_phy_is_tc(dev_priv, phy) ||
3375 dig_port->tc_mode != TC_PORT_TBT_ALT)
3376 intel_display_power_put_unchecked(dev_priv,
3377 dig_port->ddi_io_power_domain);
3379 intel_ddi_clk_disable(encoder);
3382 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3383 const struct intel_crtc_state *old_crtc_state,
3384 const struct drm_connector_state *old_conn_state)
3386 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3387 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3388 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3390 dig_port->set_infoframes(encoder, false,
3391 old_crtc_state, old_conn_state);
3393 intel_ddi_disable_pipe_clock(old_crtc_state);
3395 intel_disable_ddi_buf(encoder, old_crtc_state);
3397 intel_display_power_put_unchecked(dev_priv,
3398 dig_port->ddi_io_power_domain);
3400 intel_ddi_clk_disable(encoder);
3402 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3405 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3406 const struct intel_crtc_state *old_crtc_state,
3407 const struct drm_connector_state *old_conn_state)
3409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3412 * When called from DP MST code:
3413 * - old_conn_state will be NULL
3414 * - encoder will be the main encoder (ie. mst->primary)
3415 * - the main connector associated with this port
3416 * won't be active or linked to a crtc
3417 * - old_crtc_state will be the state of the last stream to
3418 * be deactivated on this port, and it may not be the same
3419 * stream that was activated last, but each stream
3420 * should have a state that is identical when it comes to
3421 * the DP link parameteres
3424 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3425 intel_ddi_post_disable_hdmi(encoder,
3426 old_crtc_state, old_conn_state);
3428 intel_ddi_post_disable_dp(encoder,
3429 old_crtc_state, old_conn_state);
3431 if (INTEL_GEN(dev_priv) >= 11)
3432 icl_unmap_plls_to_ports(encoder);
3435 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3436 const struct intel_crtc_state *old_crtc_state,
3437 const struct drm_connector_state *old_conn_state)
3439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3443 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3444 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3445 * step 13 is the correct place for it. Step 18 is where it was
3446 * originally before the BUN.
3448 val = I915_READ(FDI_RX_CTL(PIPE_A));
3449 val &= ~FDI_RX_ENABLE;
3450 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3452 intel_disable_ddi_buf(encoder, old_crtc_state);
3453 intel_ddi_clk_disable(encoder);
3455 val = I915_READ(FDI_RX_MISC(PIPE_A));
3456 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3457 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3458 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3460 val = I915_READ(FDI_RX_CTL(PIPE_A));
3462 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3464 val = I915_READ(FDI_RX_CTL(PIPE_A));
3465 val &= ~FDI_RX_PLL_ENABLE;
3466 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3469 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3470 const struct intel_crtc_state *crtc_state,
3471 const struct drm_connector_state *conn_state)
3473 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3474 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3475 enum port port = encoder->port;
3477 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3478 intel_dp_stop_link_train(intel_dp);
3480 intel_edp_backlight_on(crtc_state, conn_state);
3481 intel_psr_enable(intel_dp, crtc_state);
3482 intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
3483 intel_edp_drrs_enable(intel_dp, crtc_state);
3485 if (crtc_state->has_audio)
3486 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3490 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3493 static const i915_reg_t regs[] = {
3494 [PORT_A] = CHICKEN_TRANS_EDP,
3495 [PORT_B] = CHICKEN_TRANS_A,
3496 [PORT_C] = CHICKEN_TRANS_B,
3497 [PORT_D] = CHICKEN_TRANS_C,
3498 [PORT_E] = CHICKEN_TRANS_A,
3501 WARN_ON(INTEL_GEN(dev_priv) < 9);
3503 if (WARN_ON(port < PORT_A || port > PORT_E))
3509 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3510 const struct intel_crtc_state *crtc_state,
3511 const struct drm_connector_state *conn_state)
3513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3514 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3515 struct drm_connector *connector = conn_state->connector;
3516 enum port port = encoder->port;
3518 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3519 crtc_state->hdmi_high_tmds_clock_ratio,
3520 crtc_state->hdmi_scrambling))
3521 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3522 connector->base.id, connector->name);
3524 /* Display WA #1143: skl,kbl,cfl */
3525 if (IS_GEN9_BC(dev_priv)) {
3527 * For some reason these chicken bits have been
3528 * stuffed into a transcoder register, event though
3529 * the bits affect a specific DDI port rather than
3530 * a specific transcoder.
3532 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3535 val = I915_READ(reg);
3538 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3539 DDIE_TRAINING_OVERRIDE_VALUE;
3541 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3542 DDI_TRAINING_OVERRIDE_VALUE;
3544 I915_WRITE(reg, val);
3550 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3551 DDIE_TRAINING_OVERRIDE_VALUE);
3553 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3554 DDI_TRAINING_OVERRIDE_VALUE);
3556 I915_WRITE(reg, val);
3559 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3560 * are ignored so nothing special needs to be done besides
3561 * enabling the port.
3563 I915_WRITE(DDI_BUF_CTL(port),
3564 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3566 if (crtc_state->has_audio)
3567 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3570 static void intel_enable_ddi(struct intel_encoder *encoder,
3571 const struct intel_crtc_state *crtc_state,
3572 const struct drm_connector_state *conn_state)
3574 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3575 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3577 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3579 /* Enable hdcp if it's desired */
3580 if (conn_state->content_protection ==
3581 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3582 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3583 (u8)conn_state->hdcp_content_type);
3586 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3587 const struct intel_crtc_state *old_crtc_state,
3588 const struct drm_connector_state *old_conn_state)
3590 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3592 intel_dp->link_trained = false;
3594 if (old_crtc_state->has_audio)
3595 intel_audio_codec_disable(encoder,
3596 old_crtc_state, old_conn_state);
3598 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3599 intel_psr_disable(intel_dp, old_crtc_state);
3600 intel_edp_backlight_off(old_conn_state);
3601 /* Disable the decompression in DP Sink */
3602 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3606 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3607 const struct intel_crtc_state *old_crtc_state,
3608 const struct drm_connector_state *old_conn_state)
3610 struct drm_connector *connector = old_conn_state->connector;
3612 if (old_crtc_state->has_audio)
3613 intel_audio_codec_disable(encoder,
3614 old_crtc_state, old_conn_state);
3616 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3618 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3619 connector->base.id, connector->name);
3622 static void intel_disable_ddi(struct intel_encoder *encoder,
3623 const struct intel_crtc_state *old_crtc_state,
3624 const struct drm_connector_state *old_conn_state)
3626 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3628 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3629 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3631 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3634 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3635 const struct intel_crtc_state *crtc_state,
3636 const struct drm_connector_state *conn_state)
3638 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3640 intel_ddi_set_pipe_settings(crtc_state);
3642 intel_psr_update(intel_dp, crtc_state);
3643 intel_edp_drrs_enable(intel_dp, crtc_state);
3645 intel_panel_update_backlight(encoder, crtc_state, conn_state);
3648 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3649 const struct intel_crtc_state *crtc_state,
3650 const struct drm_connector_state *conn_state)
3652 struct intel_connector *connector =
3653 to_intel_connector(conn_state->connector);
3654 struct intel_hdcp *hdcp = &connector->hdcp;
3655 bool content_protection_type_changed =
3656 (conn_state->hdcp_content_type != hdcp->content_type &&
3657 conn_state->content_protection !=
3658 DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
3660 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3661 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3664 * During the HDCP encryption session if Type change is requested,
3665 * disable the HDCP and reenable it with new TYPE value.
3667 if (conn_state->content_protection ==
3668 DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
3669 content_protection_type_changed)
3670 intel_hdcp_disable(connector);
3673 * Mark the hdcp state as DESIRED after the hdcp disable of type
3676 if (content_protection_type_changed) {
3677 mutex_lock(&hdcp->mutex);
3678 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3679 schedule_work(&hdcp->prop_work);
3680 mutex_unlock(&hdcp->mutex);
3683 if (conn_state->content_protection ==
3684 DRM_MODE_CONTENT_PROTECTION_DESIRED ||
3685 content_protection_type_changed)
3686 intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
3690 intel_ddi_update_prepare(struct intel_atomic_state *state,
3691 struct intel_encoder *encoder,
3692 struct intel_crtc *crtc)
3694 struct intel_crtc_state *crtc_state =
3695 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3696 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3698 WARN_ON(crtc && crtc->active);
3700 intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
3701 if (crtc_state && crtc_state->base.active)
3702 intel_update_active_dpll(state, crtc, encoder);
3706 intel_ddi_update_complete(struct intel_atomic_state *state,
3707 struct intel_encoder *encoder,
3708 struct intel_crtc *crtc)
3710 intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
3714 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3715 const struct intel_crtc_state *crtc_state,
3716 const struct drm_connector_state *conn_state)
3718 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3719 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3720 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3721 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3724 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3726 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3727 intel_display_power_get(dev_priv,
3728 intel_ddi_main_link_aux_domain(dig_port));
3730 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3732 * Program the lane count for static/dynamic connections on
3733 * Type-C ports. Skip this step for TBT.
3735 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3736 else if (IS_GEN9_LP(dev_priv))
3737 bxt_ddi_phy_set_lane_optim_mask(encoder,
3738 crtc_state->lane_lat_optim_mask);
3742 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3743 const struct intel_crtc_state *crtc_state,
3744 const struct drm_connector_state *conn_state)
3746 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3747 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3748 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3749 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3751 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3752 intel_display_power_put_unchecked(dev_priv,
3753 intel_ddi_main_link_aux_domain(dig_port));
3756 intel_tc_port_put_link(dig_port);
3759 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3761 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3762 struct drm_i915_private *dev_priv =
3763 to_i915(intel_dig_port->base.base.dev);
3764 enum port port = intel_dig_port->base.port;
3768 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3769 val = I915_READ(DDI_BUF_CTL(port));
3770 if (val & DDI_BUF_CTL_ENABLE) {
3771 val &= ~DDI_BUF_CTL_ENABLE;
3772 I915_WRITE(DDI_BUF_CTL(port), val);
3776 val = I915_READ(DP_TP_CTL(port));
3777 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3778 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3779 I915_WRITE(DP_TP_CTL(port), val);
3780 POSTING_READ(DP_TP_CTL(port));
3783 intel_wait_ddi_buf_idle(dev_priv, port);
3786 val = DP_TP_CTL_ENABLE |
3787 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3788 if (intel_dp->link_mst)
3789 val |= DP_TP_CTL_MODE_MST;
3791 val |= DP_TP_CTL_MODE_SST;
3792 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3793 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3795 I915_WRITE(DP_TP_CTL(port), val);
3796 POSTING_READ(DP_TP_CTL(port));
3798 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3799 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3800 POSTING_READ(DDI_BUF_CTL(port));
3805 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3806 enum transcoder cpu_transcoder)
3808 if (cpu_transcoder == TRANSCODER_EDP)
3811 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3814 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3815 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3818 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3819 struct intel_crtc_state *crtc_state)
3821 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3822 crtc_state->min_voltage_level = 1;
3823 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3824 crtc_state->min_voltage_level = 2;
3827 void intel_ddi_get_config(struct intel_encoder *encoder,
3828 struct intel_crtc_state *pipe_config)
3830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3831 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3832 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3833 u32 temp, flags = 0;
3835 /* XXX: DSI transcoder paranoia */
3836 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3839 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3840 if (temp & TRANS_DDI_PHSYNC)
3841 flags |= DRM_MODE_FLAG_PHSYNC;
3843 flags |= DRM_MODE_FLAG_NHSYNC;
3844 if (temp & TRANS_DDI_PVSYNC)
3845 flags |= DRM_MODE_FLAG_PVSYNC;
3847 flags |= DRM_MODE_FLAG_NVSYNC;
3849 pipe_config->base.adjusted_mode.flags |= flags;
3851 switch (temp & TRANS_DDI_BPC_MASK) {
3852 case TRANS_DDI_BPC_6:
3853 pipe_config->pipe_bpp = 18;
3855 case TRANS_DDI_BPC_8:
3856 pipe_config->pipe_bpp = 24;
3858 case TRANS_DDI_BPC_10:
3859 pipe_config->pipe_bpp = 30;
3861 case TRANS_DDI_BPC_12:
3862 pipe_config->pipe_bpp = 36;
3868 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3869 case TRANS_DDI_MODE_SELECT_HDMI:
3870 pipe_config->has_hdmi_sink = true;
3872 pipe_config->infoframes.enable |=
3873 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3875 if (pipe_config->infoframes.enable)
3876 pipe_config->has_infoframe = true;
3878 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3879 pipe_config->hdmi_scrambling = true;
3880 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3881 pipe_config->hdmi_high_tmds_clock_ratio = true;
3883 case TRANS_DDI_MODE_SELECT_DVI:
3884 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3885 pipe_config->lane_count = 4;
3887 case TRANS_DDI_MODE_SELECT_FDI:
3888 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3890 case TRANS_DDI_MODE_SELECT_DP_SST:
3891 if (encoder->type == INTEL_OUTPUT_EDP)
3892 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3894 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3895 pipe_config->lane_count =
3896 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3897 intel_dp_get_m_n(intel_crtc, pipe_config);
3899 case TRANS_DDI_MODE_SELECT_DP_MST:
3900 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3901 pipe_config->lane_count =
3902 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3903 intel_dp_get_m_n(intel_crtc, pipe_config);
3909 pipe_config->has_audio =
3910 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3912 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3913 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3915 * This is a big fat ugly hack.
3917 * Some machines in UEFI boot mode provide us a VBT that has 18
3918 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3919 * unknown we fail to light up. Yet the same BIOS boots up with
3920 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3921 * max, not what it tells us to use.
3923 * Note: This will still be broken if the eDP panel is not lit
3924 * up by the BIOS, and thus we can't get the mode at module
3927 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3928 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3929 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3932 intel_ddi_clock_get(encoder, pipe_config);
3934 if (IS_GEN9_LP(dev_priv))
3935 pipe_config->lane_lat_optim_mask =
3936 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3938 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3940 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3942 intel_read_infoframe(encoder, pipe_config,
3943 HDMI_INFOFRAME_TYPE_AVI,
3944 &pipe_config->infoframes.avi);
3945 intel_read_infoframe(encoder, pipe_config,
3946 HDMI_INFOFRAME_TYPE_SPD,
3947 &pipe_config->infoframes.spd);
3948 intel_read_infoframe(encoder, pipe_config,
3949 HDMI_INFOFRAME_TYPE_VENDOR,
3950 &pipe_config->infoframes.hdmi);
3951 intel_read_infoframe(encoder, pipe_config,
3952 HDMI_INFOFRAME_TYPE_DRM,
3953 &pipe_config->infoframes.drm);
3956 static enum intel_output_type
3957 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3958 struct intel_crtc_state *crtc_state,
3959 struct drm_connector_state *conn_state)
3961 switch (conn_state->connector->connector_type) {
3962 case DRM_MODE_CONNECTOR_HDMIA:
3963 return INTEL_OUTPUT_HDMI;
3964 case DRM_MODE_CONNECTOR_eDP:
3965 return INTEL_OUTPUT_EDP;
3966 case DRM_MODE_CONNECTOR_DisplayPort:
3967 return INTEL_OUTPUT_DP;
3969 MISSING_CASE(conn_state->connector->connector_type);
3970 return INTEL_OUTPUT_UNUSED;
3974 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3975 struct intel_crtc_state *pipe_config,
3976 struct drm_connector_state *conn_state)
3978 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3979 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3980 enum port port = encoder->port;
3983 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3984 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3986 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3987 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3989 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3993 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3994 pipe_config->cpu_transcoder == TRANSCODER_EDP)
3995 pipe_config->pch_pfit.force_thru =
3996 pipe_config->pch_pfit.enabled ||
3997 pipe_config->crc_enabled;
3999 if (IS_GEN9_LP(dev_priv))
4000 pipe_config->lane_lat_optim_mask =
4001 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4003 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4008 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4010 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4012 intel_dp_encoder_flush_work(encoder);
4014 drm_encoder_cleanup(encoder);
4018 static const struct drm_encoder_funcs intel_ddi_funcs = {
4019 .reset = intel_dp_encoder_reset,
4020 .destroy = intel_ddi_encoder_destroy,
4023 static struct intel_connector *
4024 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4026 struct intel_connector *connector;
4027 enum port port = intel_dig_port->base.port;
4029 connector = intel_connector_alloc();
4033 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4034 intel_dig_port->dp.prepare_link_retrain =
4035 intel_ddi_prepare_link_retrain;
4037 if (!intel_dp_init_connector(intel_dig_port, connector)) {
4045 static int modeset_pipe(struct drm_crtc *crtc,
4046 struct drm_modeset_acquire_ctx *ctx)
4048 struct drm_atomic_state *state;
4049 struct drm_crtc_state *crtc_state;
4052 state = drm_atomic_state_alloc(crtc->dev);
4056 state->acquire_ctx = ctx;
4058 crtc_state = drm_atomic_get_crtc_state(state, crtc);
4059 if (IS_ERR(crtc_state)) {
4060 ret = PTR_ERR(crtc_state);
4064 crtc_state->connectors_changed = true;
4066 ret = drm_atomic_commit(state);
4068 drm_atomic_state_put(state);
4073 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4074 struct drm_modeset_acquire_ctx *ctx)
4076 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4077 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4078 struct intel_connector *connector = hdmi->attached_connector;
4079 struct i2c_adapter *adapter =
4080 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4081 struct drm_connector_state *conn_state;
4082 struct intel_crtc_state *crtc_state;
4083 struct intel_crtc *crtc;
4087 if (!connector || connector->base.status != connector_status_connected)
4090 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4095 conn_state = connector->base.state;
4097 crtc = to_intel_crtc(conn_state->crtc);
4101 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4105 crtc_state = to_intel_crtc_state(crtc->base.state);
4107 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4109 if (!crtc_state->base.active)
4112 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4113 !crtc_state->hdmi_scrambling)
4116 if (conn_state->commit &&
4117 !try_wait_for_completion(&conn_state->commit->hw_done))
4120 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4122 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4126 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4127 crtc_state->hdmi_high_tmds_clock_ratio &&
4128 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4129 crtc_state->hdmi_scrambling)
4133 * HDMI 2.0 says that one should not send scrambled data
4134 * prior to configuring the sink scrambling, and that
4135 * TMDS clock/data transmission should be suspended when
4136 * changing the TMDS clock rate in the sink. So let's
4137 * just do a full modeset here, even though some sinks
4138 * would be perfectly happy if were to just reconfigure
4139 * the SCDC settings on the fly.
4141 return modeset_pipe(&crtc->base, ctx);
4144 static enum intel_hotplug_state
4145 intel_ddi_hotplug(struct intel_encoder *encoder,
4146 struct intel_connector *connector,
4149 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4150 struct drm_modeset_acquire_ctx ctx;
4151 enum intel_hotplug_state state;
4154 state = intel_encoder_hotplug(encoder, connector, irq_received);
4156 drm_modeset_acquire_init(&ctx, 0);
4159 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4160 ret = intel_hdmi_reset_link(encoder, &ctx);
4162 ret = intel_dp_retrain_link(encoder, &ctx);
4164 if (ret == -EDEADLK) {
4165 drm_modeset_backoff(&ctx);
4172 drm_modeset_drop_locks(&ctx);
4173 drm_modeset_acquire_fini(&ctx);
4174 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4177 * Unpowered type-c dongles can take some time to boot and be
4178 * responsible, so here giving some time to those dongles to power up
4179 * and then retrying the probe.
4181 * On many platforms the HDMI live state signal is known to be
4182 * unreliable, so we can't use it to detect if a sink is connected or
4183 * not. Instead we detect if it's connected based on whether we can
4184 * read the EDID or not. That in turn has a problem during disconnect,
4185 * since the HPD interrupt may be raised before the DDC lines get
4186 * disconnected (due to how the required length of DDC vs. HPD
4187 * connector pins are specified) and so we'll still be able to get a
4188 * valid EDID. To solve this schedule another detection cycle if this
4189 * time around we didn't detect any change in the sink's connection
4192 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4193 !dig_port->dp.is_mst)
4194 state = INTEL_HOTPLUG_RETRY;
4199 static struct intel_connector *
4200 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4202 struct intel_connector *connector;
4203 enum port port = intel_dig_port->base.port;
4205 connector = intel_connector_alloc();
4209 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4210 intel_hdmi_init_connector(intel_dig_port, connector);
4215 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4217 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4219 if (dport->base.port != PORT_A)
4222 if (dport->saved_port_bits & DDI_A_4_LANES)
4225 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4226 * supported configuration
4228 if (IS_GEN9_LP(dev_priv))
4231 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4232 * one who does also have a full A/E split called
4233 * DDI_F what makes DDI_E useless. However for this
4234 * case let's trust VBT info.
4236 if (IS_CANNONLAKE(dev_priv) &&
4237 !intel_bios_is_port_present(dev_priv, PORT_E))
4244 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4246 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4247 enum port port = intel_dport->base.port;
4250 if (INTEL_GEN(dev_priv) >= 11)
4253 if (port == PORT_A || port == PORT_E) {
4254 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4255 max_lanes = port == PORT_A ? 4 : 0;
4257 /* Both A and E share 2 lanes */
4262 * Some BIOS might fail to set this bit on port A if eDP
4263 * wasn't lit up at boot. Force this bit set when needed
4264 * so we use the proper lane count for our calculations.
4266 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4267 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4268 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4275 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4277 struct ddi_vbt_port_info *port_info =
4278 &dev_priv->vbt.ddi_port_info[port];
4279 struct intel_digital_port *intel_dig_port;
4280 struct intel_encoder *intel_encoder;
4281 struct drm_encoder *encoder;
4282 bool init_hdmi, init_dp, init_lspcon = false;
4284 enum phy phy = intel_port_to_phy(dev_priv, port);
4286 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4287 init_dp = port_info->supports_dp;
4289 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4291 * Lspcon device needs to be driven with DP connector
4292 * with special detection sequence. So make sure DP
4293 * is initialized before lspcon.
4298 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4301 if (!init_dp && !init_hdmi) {
4302 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4307 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4308 if (!intel_dig_port)
4311 intel_encoder = &intel_dig_port->base;
4312 encoder = &intel_encoder->base;
4314 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4315 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4317 intel_encoder->hotplug = intel_ddi_hotplug;
4318 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4319 intel_encoder->compute_config = intel_ddi_compute_config;
4320 intel_encoder->enable = intel_enable_ddi;
4321 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4322 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4323 intel_encoder->pre_enable = intel_ddi_pre_enable;
4324 intel_encoder->disable = intel_disable_ddi;
4325 intel_encoder->post_disable = intel_ddi_post_disable;
4326 intel_encoder->update_pipe = intel_ddi_update_pipe;
4327 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4328 intel_encoder->get_config = intel_ddi_get_config;
4329 intel_encoder->suspend = intel_dp_encoder_suspend;
4330 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4331 intel_encoder->type = INTEL_OUTPUT_DDI;
4332 intel_encoder->power_domain = intel_port_to_power_domain(port);
4333 intel_encoder->port = port;
4334 intel_encoder->cloneable = 0;
4335 for_each_pipe(dev_priv, pipe)
4336 intel_encoder->crtc_mask |= BIT(pipe);
4338 if (INTEL_GEN(dev_priv) >= 11)
4339 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4340 DDI_BUF_PORT_REVERSAL;
4342 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4343 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4344 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4345 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4346 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4348 if (intel_phy_is_tc(dev_priv, phy)) {
4349 bool is_legacy = !port_info->supports_typec_usb &&
4350 !port_info->supports_tbt;
4352 intel_tc_port_init(intel_dig_port, is_legacy);
4354 intel_encoder->update_prepare = intel_ddi_update_prepare;
4355 intel_encoder->update_complete = intel_ddi_update_complete;
4360 intel_dig_port->ddi_io_power_domain =
4361 POWER_DOMAIN_PORT_DDI_A_IO;
4364 intel_dig_port->ddi_io_power_domain =
4365 POWER_DOMAIN_PORT_DDI_B_IO;
4368 intel_dig_port->ddi_io_power_domain =
4369 POWER_DOMAIN_PORT_DDI_C_IO;
4372 intel_dig_port->ddi_io_power_domain =
4373 POWER_DOMAIN_PORT_DDI_D_IO;
4376 intel_dig_port->ddi_io_power_domain =
4377 POWER_DOMAIN_PORT_DDI_E_IO;
4380 intel_dig_port->ddi_io_power_domain =
4381 POWER_DOMAIN_PORT_DDI_F_IO;
4384 intel_dig_port->ddi_io_power_domain =
4385 POWER_DOMAIN_PORT_DDI_G_IO;
4388 intel_dig_port->ddi_io_power_domain =
4389 POWER_DOMAIN_PORT_DDI_H_IO;
4392 intel_dig_port->ddi_io_power_domain =
4393 POWER_DOMAIN_PORT_DDI_I_IO;
4400 if (!intel_ddi_init_dp_connector(intel_dig_port))
4403 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4406 /* In theory we don't need the encoder->type check, but leave it just in
4407 * case we have some really bad VBTs... */
4408 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4409 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4414 if (lspcon_init(intel_dig_port))
4415 /* TODO: handle hdmi info frame part */
4416 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4420 * LSPCON init faied, but DP init was success, so
4421 * lets try to drive as DP++ port.
4423 DRM_ERROR("LSPCON init failed on port %c\n",
4427 intel_infoframe_init(intel_dig_port);
4432 drm_encoder_cleanup(encoder);
4433 kfree(intel_dig_port);