1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Traphandler
4 * Copyright (C) 2014 Free Electrons
5 * Copyright (C) 2014 Atmel
7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
11 #include <linux/clk.h>
12 #include <linux/irq.h>
13 #include <linux/irqchip.h>
14 #include <linux/mfd/atmel-hlcdc.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/platform_device.h>
19 #include <drm/drm_atomic.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_drv.h>
22 #include <drm/drm_fb_helper.h>
23 #include <drm/drm_gem_cma_helper.h>
24 #include <drm/drm_gem_framebuffer_helper.h>
25 #include <drm/drm_irq.h>
26 #include <drm/drm_probe_helper.h>
27 #include <drm/drm_vblank.h>
29 #include "atmel_hlcdc_dc.h"
31 #define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
33 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
36 .formats = &atmel_hlcdc_plane_rgb_formats,
39 .type = ATMEL_HLCDC_BASE_LAYER,
50 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
58 .conflicting_output_formats = true,
59 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
60 .layers = atmel_hlcdc_at91sam9n12_layers,
63 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
66 .formats = &atmel_hlcdc_plane_rgb_formats,
69 .type = ATMEL_HLCDC_BASE_LAYER,
82 .formats = &atmel_hlcdc_plane_rgb_formats,
85 .type = ATMEL_HLCDC_OVERLAY_LAYER,
100 .name = "high-end-overlay",
101 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
102 .regs_offset = 0x280,
104 .type = ATMEL_HLCDC_OVERLAY_LAYER,
114 .chroma_key_mask = 11,
115 .general_config = 12,
119 .clut_offset = 0x1000,
123 .formats = &atmel_hlcdc_plane_rgb_formats,
124 .regs_offset = 0x340,
126 .type = ATMEL_HLCDC_CURSOR_LAYER,
136 .chroma_key_mask = 8,
139 .clut_offset = 0x1400,
143 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
151 .conflicting_output_formats = true,
152 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
153 .layers = atmel_hlcdc_at91sam9x5_layers,
156 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
159 .formats = &atmel_hlcdc_plane_rgb_formats,
162 .type = ATMEL_HLCDC_BASE_LAYER,
171 .clut_offset = 0x600,
175 .formats = &atmel_hlcdc_plane_rgb_formats,
176 .regs_offset = 0x140,
178 .type = ATMEL_HLCDC_OVERLAY_LAYER,
187 .chroma_key_mask = 8,
190 .clut_offset = 0xa00,
194 .formats = &atmel_hlcdc_plane_rgb_formats,
195 .regs_offset = 0x240,
197 .type = ATMEL_HLCDC_OVERLAY_LAYER,
206 .chroma_key_mask = 8,
209 .clut_offset = 0xe00,
212 .name = "high-end-overlay",
213 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
214 .regs_offset = 0x340,
216 .type = ATMEL_HLCDC_OVERLAY_LAYER,
226 .chroma_key_mask = 11,
227 .general_config = 12,
235 .clut_offset = 0x1200,
239 .formats = &atmel_hlcdc_plane_rgb_formats,
240 .regs_offset = 0x440,
242 .type = ATMEL_HLCDC_CURSOR_LAYER,
253 .chroma_key_mask = 8,
257 .clut_offset = 0x1600,
261 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
269 .conflicting_output_formats = true,
270 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
271 .layers = atmel_hlcdc_sama5d3_layers,
274 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
277 .formats = &atmel_hlcdc_plane_rgb_formats,
280 .type = ATMEL_HLCDC_BASE_LAYER,
289 .clut_offset = 0x600,
293 .formats = &atmel_hlcdc_plane_rgb_formats,
294 .regs_offset = 0x140,
296 .type = ATMEL_HLCDC_OVERLAY_LAYER,
305 .chroma_key_mask = 8,
308 .clut_offset = 0xa00,
312 .formats = &atmel_hlcdc_plane_rgb_formats,
313 .regs_offset = 0x240,
315 .type = ATMEL_HLCDC_OVERLAY_LAYER,
324 .chroma_key_mask = 8,
327 .clut_offset = 0xe00,
330 .name = "high-end-overlay",
331 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
332 .regs_offset = 0x340,
334 .type = ATMEL_HLCDC_OVERLAY_LAYER,
344 .chroma_key_mask = 11,
345 .general_config = 12,
353 .clut_offset = 0x1200,
357 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
365 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
366 .layers = atmel_hlcdc_sama5d4_layers,
369 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sam9x60_layers[] = {
372 .formats = &atmel_hlcdc_plane_rgb_formats,
375 .type = ATMEL_HLCDC_BASE_LAYER,
384 .clut_offset = 0x600,
388 .formats = &atmel_hlcdc_plane_rgb_formats,
389 .regs_offset = 0x160,
391 .type = ATMEL_HLCDC_OVERLAY_LAYER,
400 .chroma_key_mask = 8,
403 .clut_offset = 0xa00,
407 .formats = &atmel_hlcdc_plane_rgb_formats,
408 .regs_offset = 0x260,
410 .type = ATMEL_HLCDC_OVERLAY_LAYER,
419 .chroma_key_mask = 8,
422 .clut_offset = 0xe00,
425 .name = "high-end-overlay",
426 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
427 .regs_offset = 0x360,
429 .type = ATMEL_HLCDC_OVERLAY_LAYER,
439 .chroma_key_mask = 11,
440 .general_config = 12,
448 .clut_offset = 0x1200,
452 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = {
460 .fixed_clksrc = true,
461 .nlayers = ARRAY_SIZE(atmel_hlcdc_sam9x60_layers),
462 .layers = atmel_hlcdc_sam9x60_layers,
465 static const struct of_device_id atmel_hlcdc_of_match[] = {
467 .compatible = "atmel,at91sam9n12-hlcdc",
468 .data = &atmel_hlcdc_dc_at91sam9n12,
471 .compatible = "atmel,at91sam9x5-hlcdc",
472 .data = &atmel_hlcdc_dc_at91sam9x5,
475 .compatible = "atmel,sama5d2-hlcdc",
476 .data = &atmel_hlcdc_dc_sama5d4,
479 .compatible = "atmel,sama5d3-hlcdc",
480 .data = &atmel_hlcdc_dc_sama5d3,
483 .compatible = "atmel,sama5d4-hlcdc",
484 .data = &atmel_hlcdc_dc_sama5d4,
487 .compatible = "microchip,sam9x60-hlcdc",
488 .data = &atmel_hlcdc_dc_sam9x60,
492 MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
495 atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
496 const struct drm_display_mode *mode)
498 int vfront_porch = mode->vsync_start - mode->vdisplay;
499 int vback_porch = mode->vtotal - mode->vsync_end;
500 int vsync_len = mode->vsync_end - mode->vsync_start;
501 int hfront_porch = mode->hsync_start - mode->hdisplay;
502 int hback_porch = mode->htotal - mode->hsync_end;
503 int hsync_len = mode->hsync_end - mode->hsync_start;
505 if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)
508 if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)
511 if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||
512 hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||
514 return MODE_H_ILLEGAL;
516 if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||
517 vback_porch > dc->desc->max_vpw || vback_porch < 0 ||
519 return MODE_V_ILLEGAL;
524 static void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)
529 if (layer->desc->type == ATMEL_HLCDC_BASE_LAYER ||
530 layer->desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
531 layer->desc->type == ATMEL_HLCDC_CURSOR_LAYER)
532 atmel_hlcdc_plane_irq(atmel_hlcdc_layer_to_plane(layer));
535 static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
537 struct drm_device *dev = data;
538 struct atmel_hlcdc_dc *dc = dev->dev_private;
539 unsigned long status;
540 unsigned int imr, isr;
543 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
544 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
549 if (status & ATMEL_HLCDC_SOF)
550 atmel_hlcdc_crtc_irq(dc->crtc);
552 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
553 if (ATMEL_HLCDC_LAYER_STATUS(i) & status)
554 atmel_hlcdc_layer_irq(dc->layers[i]);
560 static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
561 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
563 return drm_gem_fb_create(dev, file_priv, mode_cmd);
566 struct atmel_hlcdc_dc_commit {
567 struct work_struct work;
568 struct drm_device *dev;
569 struct drm_atomic_state *state;
573 atmel_hlcdc_dc_atomic_complete(struct atmel_hlcdc_dc_commit *commit)
575 struct drm_device *dev = commit->dev;
576 struct atmel_hlcdc_dc *dc = dev->dev_private;
577 struct drm_atomic_state *old_state = commit->state;
579 /* Apply the atomic update. */
580 drm_atomic_helper_commit_modeset_disables(dev, old_state);
581 drm_atomic_helper_commit_planes(dev, old_state, 0);
582 drm_atomic_helper_commit_modeset_enables(dev, old_state);
584 drm_atomic_helper_wait_for_vblanks(dev, old_state);
586 drm_atomic_helper_cleanup_planes(dev, old_state);
588 drm_atomic_state_put(old_state);
590 /* Complete the commit, wake up any waiter. */
591 spin_lock(&dc->commit.wait.lock);
592 dc->commit.pending = false;
593 wake_up_all_locked(&dc->commit.wait);
594 spin_unlock(&dc->commit.wait.lock);
599 static void atmel_hlcdc_dc_atomic_work(struct work_struct *work)
601 struct atmel_hlcdc_dc_commit *commit =
602 container_of(work, struct atmel_hlcdc_dc_commit, work);
604 atmel_hlcdc_dc_atomic_complete(commit);
607 static int atmel_hlcdc_dc_atomic_commit(struct drm_device *dev,
608 struct drm_atomic_state *state,
611 struct atmel_hlcdc_dc *dc = dev->dev_private;
612 struct atmel_hlcdc_dc_commit *commit;
615 ret = drm_atomic_helper_prepare_planes(dev, state);
619 /* Allocate the commit object. */
620 commit = kzalloc(sizeof(*commit), GFP_KERNEL);
626 INIT_WORK(&commit->work, atmel_hlcdc_dc_atomic_work);
628 commit->state = state;
630 spin_lock(&dc->commit.wait.lock);
631 ret = wait_event_interruptible_locked(dc->commit.wait,
632 !dc->commit.pending);
634 dc->commit.pending = true;
635 spin_unlock(&dc->commit.wait.lock);
640 /* We have our own synchronization through the commit lock. */
641 BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
643 /* Swap state succeeded, this is the point of no return. */
644 drm_atomic_state_get(state);
646 queue_work(dc->wq, &commit->work);
648 atmel_hlcdc_dc_atomic_complete(commit);
655 drm_atomic_helper_cleanup_planes(dev, state);
659 static const struct drm_mode_config_funcs mode_config_funcs = {
660 .fb_create = atmel_hlcdc_fb_create,
661 .atomic_check = drm_atomic_helper_check,
662 .atomic_commit = atmel_hlcdc_dc_atomic_commit,
665 static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
667 struct atmel_hlcdc_dc *dc = dev->dev_private;
670 drm_mode_config_init(dev);
672 ret = atmel_hlcdc_create_outputs(dev);
674 dev_err(dev->dev, "failed to create HLCDC outputs: %d\n", ret);
678 ret = atmel_hlcdc_create_planes(dev);
680 dev_err(dev->dev, "failed to create planes: %d\n", ret);
684 ret = atmel_hlcdc_crtc_create(dev);
686 dev_err(dev->dev, "failed to create crtc\n");
690 dev->mode_config.min_width = dc->desc->min_width;
691 dev->mode_config.min_height = dc->desc->min_height;
692 dev->mode_config.max_width = dc->desc->max_width;
693 dev->mode_config.max_height = dc->desc->max_height;
694 dev->mode_config.funcs = &mode_config_funcs;
699 static int atmel_hlcdc_dc_load(struct drm_device *dev)
701 struct platform_device *pdev = to_platform_device(dev->dev);
702 const struct of_device_id *match;
703 struct atmel_hlcdc_dc *dc;
706 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
708 dev_err(&pdev->dev, "invalid compatible string\n");
713 dev_err(&pdev->dev, "invalid hlcdc description\n");
717 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
721 dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
725 init_waitqueue_head(&dc->commit.wait);
726 dc->desc = match->data;
727 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
728 dev->dev_private = dc;
730 if (dc->desc->fixed_clksrc) {
731 ret = clk_prepare_enable(dc->hlcdc->sys_clk);
733 dev_err(dev->dev, "failed to enable sys_clk\n");
738 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
740 dev_err(dev->dev, "failed to enable periph_clk\n");
741 goto err_sys_clk_disable;
744 pm_runtime_enable(dev->dev);
746 ret = drm_vblank_init(dev, 1);
748 dev_err(dev->dev, "failed to initialize vblank\n");
749 goto err_periph_clk_disable;
752 ret = atmel_hlcdc_dc_modeset_init(dev);
754 dev_err(dev->dev, "failed to initialize mode setting\n");
755 goto err_periph_clk_disable;
758 drm_mode_config_reset(dev);
760 pm_runtime_get_sync(dev->dev);
761 ret = drm_irq_install(dev, dc->hlcdc->irq);
762 pm_runtime_put_sync(dev->dev);
764 dev_err(dev->dev, "failed to install IRQ handler\n");
765 goto err_periph_clk_disable;
768 platform_set_drvdata(pdev, dev);
770 drm_kms_helper_poll_init(dev);
774 err_periph_clk_disable:
775 pm_runtime_disable(dev->dev);
776 clk_disable_unprepare(dc->hlcdc->periph_clk);
778 if (dc->desc->fixed_clksrc)
779 clk_disable_unprepare(dc->hlcdc->sys_clk);
782 destroy_workqueue(dc->wq);
787 static void atmel_hlcdc_dc_unload(struct drm_device *dev)
789 struct atmel_hlcdc_dc *dc = dev->dev_private;
791 flush_workqueue(dc->wq);
792 drm_kms_helper_poll_fini(dev);
793 drm_atomic_helper_shutdown(dev);
794 drm_mode_config_cleanup(dev);
796 pm_runtime_get_sync(dev->dev);
797 drm_irq_uninstall(dev);
798 pm_runtime_put_sync(dev->dev);
800 dev->dev_private = NULL;
802 pm_runtime_disable(dev->dev);
803 clk_disable_unprepare(dc->hlcdc->periph_clk);
804 if (dc->desc->fixed_clksrc)
805 clk_disable_unprepare(dc->hlcdc->sys_clk);
806 destroy_workqueue(dc->wq);
809 static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
811 struct atmel_hlcdc_dc *dc = dev->dev_private;
812 unsigned int cfg = 0;
815 /* Enable interrupts on activated layers */
816 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
818 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
821 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
826 static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
828 struct atmel_hlcdc_dc *dc = dev->dev_private;
831 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
832 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
835 DEFINE_DRM_GEM_CMA_FOPS(fops);
837 static struct drm_driver atmel_hlcdc_dc_driver = {
838 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
839 .irq_handler = atmel_hlcdc_dc_irq_handler,
840 .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
841 .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
842 .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
843 .gem_free_object_unlocked = drm_gem_cma_free_object,
844 .gem_vm_ops = &drm_gem_cma_vm_ops,
845 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
846 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
847 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
848 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
849 .gem_prime_vmap = drm_gem_cma_prime_vmap,
850 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
851 .gem_prime_mmap = drm_gem_cma_prime_mmap,
852 .dumb_create = drm_gem_cma_dumb_create,
854 .name = "atmel-hlcdc",
855 .desc = "Atmel HLCD Controller DRM",
861 static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
863 struct drm_device *ddev;
866 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
868 return PTR_ERR(ddev);
870 ret = atmel_hlcdc_dc_load(ddev);
874 ret = drm_dev_register(ddev, 0);
878 drm_fbdev_generic_setup(ddev, 24);
883 atmel_hlcdc_dc_unload(ddev);
891 static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
893 struct drm_device *ddev = platform_get_drvdata(pdev);
895 drm_dev_unregister(ddev);
896 atmel_hlcdc_dc_unload(ddev);
902 #ifdef CONFIG_PM_SLEEP
903 static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
905 struct drm_device *drm_dev = dev_get_drvdata(dev);
906 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
907 struct regmap *regmap = dc->hlcdc->regmap;
908 struct drm_atomic_state *state;
910 state = drm_atomic_helper_suspend(drm_dev);
912 return PTR_ERR(state);
914 dc->suspend.state = state;
916 regmap_read(regmap, ATMEL_HLCDC_IMR, &dc->suspend.imr);
917 regmap_write(regmap, ATMEL_HLCDC_IDR, dc->suspend.imr);
918 clk_disable_unprepare(dc->hlcdc->periph_clk);
919 if (dc->desc->fixed_clksrc)
920 clk_disable_unprepare(dc->hlcdc->sys_clk);
925 static int atmel_hlcdc_dc_drm_resume(struct device *dev)
927 struct drm_device *drm_dev = dev_get_drvdata(dev);
928 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
930 if (dc->desc->fixed_clksrc)
931 clk_prepare_enable(dc->hlcdc->sys_clk);
932 clk_prepare_enable(dc->hlcdc->periph_clk);
933 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, dc->suspend.imr);
935 return drm_atomic_helper_resume(drm_dev, dc->suspend.state);
939 static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
940 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
942 static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
943 { .compatible = "atmel,hlcdc-display-controller" },
947 static struct platform_driver atmel_hlcdc_dc_platform_driver = {
948 .probe = atmel_hlcdc_dc_drm_probe,
949 .remove = atmel_hlcdc_dc_drm_remove,
951 .name = "atmel-hlcdc-display-controller",
952 .pm = &atmel_hlcdc_dc_drm_pm_ops,
953 .of_match_table = atmel_hlcdc_dc_of_match,
956 module_platform_driver(atmel_hlcdc_dc_platform_driver);
958 MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
959 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
960 MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
961 MODULE_LICENSE("GPL");
962 MODULE_ALIAS("platform:atmel-hlcdc-dc");