drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <drm/drmP.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_plane_helper.h>
  16 #include "armada_crtc.h"
  17 #include "armada_drm.h"
  18 #include "armada_fb.h"
  19 #include "armada_gem.h"
  20 #include "armada_hw.h"
  21 #include "armada_trace.h"
  22
  23 struct armada_frame_work {
  24         struct armada_plane_work work;
  25         struct drm_pending_vblank_event *event;
  26         struct armada_regs regs[4];
  27         struct drm_framebuffer *old_fb;
  28 };
  29
  30 enum csc_mode {
  31         CSC_AUTO = 0,
  32         CSC_YUV_CCIR601 = 1,
  33         CSC_YUV_CCIR709 = 2,
  34         CSC_RGB_COMPUTER = 1,
  35         CSC_RGB_STUDIO = 2,
  36 };
  37
  38 static const uint32_t armada_primary_formats[] = {
  39         DRM_FORMAT_UYVY,
  40         DRM_FORMAT_YUYV,
  41         DRM_FORMAT_VYUY,
  42         DRM_FORMAT_YVYU,
  43         DRM_FORMAT_ARGB8888,
  44         DRM_FORMAT_ABGR8888,
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_XBGR8888,
  47         DRM_FORMAT_RGB888,
  48         DRM_FORMAT_BGR888,
  49         DRM_FORMAT_ARGB1555,
  50         DRM_FORMAT_ABGR1555,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53 };
  54
  55 /*
  56  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  57  * The timing parameters we have from X are:
  58  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  59  *  1920 2448 2492 2640  1080 1084 1094 1125
  60  * Which get translated to:
  61  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  62  *  1920 2448 2492 2640   540  542  547  562
  63  *
  64  * This is how it is defined by CEA-861-D - line and pixel numbers are
  65  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  66  * line: 2640.  The odd frame, the first active line is at line 21, and
  67  * the even frame, the first active line is 584.
  68  *
  69  * LN:    560     561     562     563             567     568    569
  70  * DE:    ~~~|____________________________//__________________________
  71  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  72  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  73  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  74  *
  75  * LN:    1123   1124    1125      1               5       6      7
  76  * DE:    ~~~|____________________________//__________________________
  77  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  78  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  79  *  23 blanking lines
  80  *
  81  * The Armada LCD Controller line and pixel numbers are, like X timings,
  82  * referenced to the top left of the active frame.
  83  *
  84  * So, translating these to our LCD controller:
  85  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  86  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  87  * Note: Vsync front porch remains constant!
  88  *
  89  * if (odd_frame) {
  90  *   vtotal = mode->crtc_vtotal + 1;
  91  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  92  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  93  * } else {
  94  *   vtotal = mode->crtc_vtotal;
  95  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  96  *   vhorizpos = mode->crtc_hsync_start;
  97  * }
  98  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  99  *
 100  * So, we need to reprogram these registers on each vsync event:
 101  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
 102  *
 103  * Note: we do not use the frame done interrupts because these appear
 104  * to happen too early, and lead to jitter on the display (presumably
 105  * they occur at the end of the last active line, before the vsync back
 106  * porch, which we're reprogramming.)
 107  */
 108
 109 void
 110 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
 111 {
 112         while (regs->offset != ~0) {
 113                 void __iomem *reg = dcrtc->base + regs->offset;
 114                 uint32_t val;
 115
 116                 val = regs->mask;
 117                 if (val != 0)
 118                         val &= readl_relaxed(reg);
 119                 writel_relaxed(val | regs->val, reg);
 120                 ++regs;
 121         }
 122 }
 123
 124 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 125
 126 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 127 {
 128         uint32_t dumb_ctrl;
 129
 130         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 131
 132         if (!dpms_blanked(dcrtc->dpms))
 133                 dumb_ctrl |= CFG_DUMB_ENA;
 134
 135         /*
 136          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 137          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 138          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 139          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 140          */
 141         if (dpms_blanked(dcrtc->dpms) &&
 142             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 143                 dumb_ctrl &= ~DUMB_MASK;
 144                 dumb_ctrl |= DUMB_BLANK;
 145         }
 146
 147         /*
 148          * The documentation doesn't indicate what the normal state of
 149          * the sync signals are.  Sebastian Hesselbart kindly probed
 150          * these signals on his board to determine their state.
 151          *
 152          * The non-inverted state of the sync signals is active high.
 153          * Setting these bits makes the appropriate signal active low.
 154          */
 155         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 156                 dumb_ctrl |= CFG_INV_CSYNC;
 157         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 158                 dumb_ctrl |= CFG_INV_HSYNC;
 159         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 160                 dumb_ctrl |= CFG_INV_VSYNC;
 161
 162         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 163                 dcrtc->dumb_ctrl = dumb_ctrl;
 164                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 165         }
 166 }
 167
 168 void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
 169         int x, int y)
 170 {
 171         u32 addr = drm_fb_obj(fb)->dev_addr;
 172         int num_planes = fb->format->num_planes;
 173         int i;
 174
 175         if (num_planes > 3)
 176                 num_planes = 3;
 177
 178         for (i = 0; i < num_planes; i++)
 179                 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
 180                              x * fb->format->cpp[i];
 181         for (; i < 3; i++)
 182                 addrs[i] = 0;
 183 }
 184
 185 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 186         int x, int y, struct armada_regs *regs, bool interlaced)
 187 {
 188         unsigned pitch = fb->pitches[0];
 189         u32 addrs[3], addr_odd, addr_even;
 190         unsigned i = 0;
 191
 192         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 193                 pitch, x, y, fb->format->cpp[0] * 8);
 194
 195         armada_drm_plane_calc_addrs(addrs, fb, x, y);
 196
 197         addr_odd = addr_even = addrs[0];
 198
 199         if (interlaced) {
 200                 addr_even += pitch;
 201                 pitch *= 2;
 202         }
 203
 204         /* write offset, base, and pitch */
 205         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 206         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 207         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 208
 209         return i;
 210 }
 211
 212 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
 213         struct drm_plane *plane)
 214 {
 215         struct armada_plane *dplane = drm_to_armada_plane(plane);
 216         struct armada_plane_work *work = xchg(&dplane->work, NULL);
 217
 218         /* Handle any pending frame work. */
 219         if (work) {
 220                 work->fn(dcrtc, dplane, work);
 221                 drm_crtc_vblank_put(&dcrtc->crtc);
 222         }
 223
 224         wake_up(&dplane->frame_wait);
 225 }
 226
 227 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
 228         struct armada_plane *plane, struct armada_plane_work *work)
 229 {
 230         int ret;
 231
 232         ret = drm_crtc_vblank_get(&dcrtc->crtc);
 233         if (ret) {
 234                 DRM_ERROR("failed to acquire vblank counter\n");
 235                 return ret;
 236         }
 237
 238         ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
 239         if (ret)
 240                 drm_crtc_vblank_put(&dcrtc->crtc);
 241
 242         return ret;
 243 }
 244
 245 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
 246 {
 247         return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
 248 }
 249
 250 struct armada_plane_work *armada_drm_plane_work_cancel(
 251         struct armada_crtc *dcrtc, struct armada_plane *plane)
 252 {
 253         struct armada_plane_work *work = xchg(&plane->work, NULL);
 254
 255         if (work)
 256                 drm_crtc_vblank_put(&dcrtc->crtc);
 257
 258         return work;
 259 }
 260
 261 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
 262         struct armada_frame_work *work)
 263 {
 264         struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
 265
 266         return armada_drm_plane_work_queue(dcrtc, plane, &work->work);
 267 }
 268
 269 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
 270         struct armada_plane *plane, struct armada_plane_work *work)
 271 {
 272         struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work);
 273         struct drm_device *dev = dcrtc->crtc.dev;
 274         unsigned long flags;
 275
 276         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 277         armada_drm_crtc_update_regs(dcrtc, fwork->regs);
 278         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 279
 280         if (fwork->event) {
 281                 spin_lock_irqsave(&dev->event_lock, flags);
 282                 drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event);
 283                 spin_unlock_irqrestore(&dev->event_lock, flags);
 284         }
 285
 286         /* Finally, queue the process-half of the cleanup. */
 287         __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb);
 288         kfree(fwork);
 289 }
 290
 291 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 292         struct drm_framebuffer *fb, bool force)
 293 {
 294         struct armada_frame_work *work;
 295
 296         if (!fb)
 297                 return;
 298
 299         if (force) {
 300                 /* Display is disabled, so just drop the old fb */
 301                 drm_framebuffer_unreference(fb);
 302                 return;
 303         }
 304
 305         work = kmalloc(sizeof(*work), GFP_KERNEL);
 306         if (work) {
 307                 int i = 0;
 308                 work->work.fn = armada_drm_crtc_complete_frame_work;
 309                 work->event = NULL;
 310                 work->old_fb = fb;
 311                 armada_reg_queue_end(work->regs, i);
 312
 313                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
 314                         return;
 315
 316                 kfree(work);
 317         }
 318
 319         /*
 320          * Oops - just drop the reference immediately and hope for
 321          * the best.  The worst that will happen is the buffer gets
 322          * reused before it has finished being displayed.
 323          */
 324         drm_framebuffer_unreference(fb);
 325 }
 326
 327 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 328 {
 329         /*
 330          * Tell the DRM core that vblank IRQs aren't going to happen for
 331          * a while.  This cleans up any pending vblank events for us.
 332          */
 333         drm_crtc_vblank_off(&dcrtc->crtc);
 334         armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 335 }
 336
 337 /* The mode_config.mutex will be held for this call */
 338 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 339 {
 340         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 341
 342         if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
 343                 if (dpms_blanked(dpms))
 344                         armada_drm_vblank_off(dcrtc);
 345                 else if (!IS_ERR(dcrtc->clk))
 346                         WARN_ON(clk_prepare_enable(dcrtc->clk));
 347                 dcrtc->dpms = dpms;
 348                 armada_drm_crtc_update(dcrtc);
 349                 if (!dpms_blanked(dpms))
 350                         drm_crtc_vblank_on(&dcrtc->crtc);
 351                 else if (!IS_ERR(dcrtc->clk))
 352                         clk_disable_unprepare(dcrtc->clk);
 353         } else if (dcrtc->dpms != dpms) {
 354                 dcrtc->dpms = dpms;
 355         }
 356 }
 357
 358 /*
 359  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 360  * up with the overlay size being bigger than the active screen size.
 361  * We rely upon X refreshing this state after the mode set has completed.
 362  *
 363  * The mode_config.mutex will be held for this call
 364  */
 365 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 366 {
 367         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 368         struct drm_plane *plane;
 369
 370         /*
 371          * If we have an overlay plane associated with this CRTC, disable
 372          * it before the modeset to avoid its coordinates being outside
 373          * the new mode parameters.
 374          */
 375         plane = dcrtc->plane;
 376         if (plane)
 377                 drm_plane_force_disable(plane);
 378 }
 379
 380 /* The mode_config.mutex will be held for this call */
 381 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 382 {
 383         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 384
 385         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 386                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 387                 armada_drm_crtc_update(dcrtc);
 388         }
 389 }
 390
 391 /* The mode_config.mutex will be held for this call */
 392 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 393         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 394 {
 395         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 396         int ret;
 397
 398         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 399         if (!dcrtc->variant->has_spu_adv_reg &&
 400             adj->flags & DRM_MODE_FLAG_INTERLACE)
 401                 return false;
 402
 403         /* Check whether the display mode is possible */
 404         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
 405         if (ret)
 406                 return false;
 407
 408         return true;
 409 }
 410
 411 /* These are locked by dev->vbl_lock */
 412 static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 413 {
 414         if (dcrtc->irq_ena & mask) {
 415                 dcrtc->irq_ena &= ~mask;
 416                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 417         }
 418 }
 419
 420 static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 421 {
 422         if ((dcrtc->irq_ena & mask) != mask) {
 423                 dcrtc->irq_ena |= mask;
 424                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 425                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 426                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 427         }
 428 }
 429
 430 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 431 {
 432         void __iomem *base = dcrtc->base;
 433         struct drm_plane *ovl_plane;
 434
 435         if (stat & DMA_FF_UNDERFLOW)
 436                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 437         if (stat & GRA_FF_UNDERFLOW)
 438                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 439
 440         if (stat & VSYNC_IRQ)
 441                 drm_crtc_handle_vblank(&dcrtc->crtc);
 442
 443         spin_lock(&dcrtc->irq_lock);
 444         ovl_plane = dcrtc->plane;
 445         if (ovl_plane)
 446                 armada_drm_plane_work_run(dcrtc, ovl_plane);
 447
 448         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 449                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 450                 uint32_t val;
 451
 452                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 453                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 454                                base + LCD_SPUT_V_H_TOTAL);
 455
 456                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 457                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 458                 val |= dcrtc->v[i].spu_adv_reg;
 459                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 460         }
 461
 462         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 463                 writel_relaxed(dcrtc->cursor_hw_pos,
 464                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 465                 writel_relaxed(dcrtc->cursor_hw_sz,
 466                                base + LCD_SPU_HWC_HPXL_VLN);
 467                 armada_updatel(CFG_HWC_ENA,
 468                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 469                                base + LCD_SPU_DMA_CTRL0);
 470                 dcrtc->cursor_update = false;
 471                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 472         }
 473
 474         spin_unlock(&dcrtc->irq_lock);
 475
 476         if (stat & GRA_FRAME_IRQ)
 477                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 478 }
 479
 480 static irqreturn_t armada_drm_irq(int irq, void *arg)
 481 {
 482         struct armada_crtc *dcrtc = arg;
 483         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 484
 485         /*
 486          * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR
 487          * is set.  Writing has some other effect to acknowledge the IRQ -
 488          * without this, we only get a single IRQ.
 489          */
 490         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 491
 492         trace_armada_drm_irq(&dcrtc->crtc, stat);
 493
 494         /* Mask out those interrupts we haven't enabled */
 495         v = stat & dcrtc->irq_ena;
 496
 497         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
 498                 armada_drm_crtc_irq(dcrtc, stat);
 499                 return IRQ_HANDLED;
 500         }
 501         return IRQ_NONE;
 502 }
 503
 504 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 505 {
 506         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 507         uint32_t val = 0;
 508
 509         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 510                 val |= CFG_CSC_YUV_CCIR709;
 511         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 512                 val |= CFG_CSC_RGB_STUDIO;
 513
 514         /*
 515          * In auto mode, set the colorimetry, based upon the HDMI spec.
 516          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 517          * ITU601.  It may be more appropriate to set this depending on
 518          * the source - but what if the graphic frame is YUV and the
 519          * video frame is RGB?
 520          */
 521         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 522              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 523             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 524                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 525                         val |= CFG_CSC_YUV_CCIR709;
 526         }
 527
 528         /*
 529          * We assume we're connected to a TV-like device, so the YUV->RGB
 530          * conversion should produce a limited range.  We should set this
 531          * depending on the connectors attached to this CRTC, and what
 532          * kind of device they report being connected.
 533          */
 534         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 535                 val |= CFG_CSC_RGB_STUDIO;
 536
 537         return val;
 538 }
 539
 540 static void armada_drm_primary_set(struct drm_crtc *crtc,
 541         struct drm_plane *plane, int x, int y)
 542 {
 543         struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
 544         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 545         struct armada_regs regs[8];
 546         bool interlaced = dcrtc->interlaced;
 547         unsigned i;
 548         u32 ctrl0;
 549
 550         i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced);
 551
 552         armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
 553         armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
 554         armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
 555
 556         ctrl0 = state->ctrl0;
 557         if (interlaced)
 558                 ctrl0 |= CFG_GRA_FTOGGLE;
 559
 560         armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
 561                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 562                                          CFG_SWAPYU | CFG_YUV2RGB) |
 563                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
 564                              LCD_SPU_DMA_CTRL0);
 565         armada_reg_queue_end(regs, i);
 566         armada_drm_crtc_update_regs(dcrtc, regs);
 567 }
 568
 569 /* The mode_config.mutex will be held for this call */
 570 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 571         struct drm_display_mode *mode, struct drm_display_mode *adj,
 572         int x, int y, struct drm_framebuffer *old_fb)
 573 {
 574         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 575         struct armada_regs regs[17];
 576         uint32_t lm, rm, tm, bm, val, sclk;
 577         unsigned long flags;
 578         unsigned i;
 579         bool interlaced;
 580
 581         drm_framebuffer_reference(crtc->primary->fb);
 582
 583         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 584
 585         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
 586         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
 587         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
 588
 589         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
 590                 val |= CFG_PALETTE_ENA;
 591
 592         drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
 593         drm_to_armada_plane(crtc->primary)->state.src_hw =
 594         drm_to_armada_plane(crtc->primary)->state.dst_hw =
 595                 adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 596         drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
 597
 598         i = 0;
 599         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 600         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 601         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 602         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 603
 604         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 605                 adj->crtc_hdisplay,
 606                 adj->crtc_hsync_start,
 607                 adj->crtc_hsync_end,
 608                 adj->crtc_htotal, lm, rm);
 609         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 610                 adj->crtc_vdisplay,
 611                 adj->crtc_vsync_start,
 612                 adj->crtc_vsync_end,
 613                 adj->crtc_vtotal, tm, bm);
 614
 615         /* Wait for pending flips to complete */
 616         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 617                                    MAX_SCHEDULE_TIMEOUT);
 618
 619         drm_crtc_vblank_off(crtc);
 620
 621         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 622         if (val != dcrtc->dumb_ctrl) {
 623                 dcrtc->dumb_ctrl = val;
 624                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 625         }
 626
 627         /*
 628          * If we are blanked, we would have disabled the clock.  Re-enable
 629          * it so that compute_clock() does the right thing.
 630          */
 631         if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
 632                 WARN_ON(clk_prepare_enable(dcrtc->clk));
 633
 634         /* Now compute the divider for real */
 635         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
 636
 637         /* Ensure graphic fifo is enabled */
 638         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 639         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 640
 641         if (interlaced ^ dcrtc->interlaced) {
 642                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 643                         drm_crtc_vblank_get(&dcrtc->crtc);
 644                 else
 645                         drm_crtc_vblank_put(&dcrtc->crtc);
 646                 dcrtc->interlaced = interlaced;
 647         }
 648
 649         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 650
 651         /* Even interlaced/progressive frame */
 652         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 653                                     adj->crtc_htotal;
 654         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 655         val = adj->crtc_hsync_start;
 656         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 657                 dcrtc->variant->spu_adv_reg;
 658
 659         if (interlaced) {
 660                 /* Odd interlaced frame */
 661                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 662                                                 (1 << 16);
 663                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 664                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 665                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 666                         dcrtc->variant->spu_adv_reg;
 667         } else {
 668                 dcrtc->v[0] = dcrtc->v[1];
 669         }
 670
 671         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 672
 673         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 674         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 675         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 676         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 677                            LCD_SPUT_V_H_TOTAL);
 678
 679         if (dcrtc->variant->has_spu_adv_reg) {
 680                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 681                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 682                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 683         }
 684
 685         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 686         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 687
 688         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 689         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 690         armada_reg_queue_end(regs, i);
 691
 692         armada_drm_crtc_update_regs(dcrtc, regs);
 693
 694         armada_drm_primary_set(crtc, crtc->primary, x, y);
 695         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 696
 697         armada_drm_crtc_update(dcrtc);
 698
 699         drm_crtc_vblank_on(crtc);
 700         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 701
 702         return 0;
 703 }
 704
 705 /* The mode_config.mutex will be held for this call */
 706 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 707         struct drm_framebuffer *old_fb)
 708 {
 709         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 710         struct armada_regs regs[4];
 711         unsigned i;
 712
 713         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
 714                                     dcrtc->interlaced);
 715         armada_reg_queue_end(regs, i);
 716
 717         /* Wait for pending flips to complete */
 718         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 719                                    MAX_SCHEDULE_TIMEOUT);
 720
 721         /* Take a reference to the new fb as we're using it */
 722         drm_framebuffer_reference(crtc->primary->fb);
 723
 724         /* Update the base in the CRTC */
 725         armada_drm_crtc_update_regs(dcrtc, regs);
 726
 727         /* Drop our previously held reference */
 728         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 729
 730         return 0;
 731 }
 732
 733 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
 734         struct drm_plane *plane)
 735 {
 736         u32 sram_para1, dma_ctrl0_mask;
 737
 738         /*
 739          * Drop our reference on any framebuffer attached to this plane.
 740          * We don't need to NULL this out as drm_plane_force_disable(),
 741          * and __setplane_internal() will do so for an overlay plane, and
 742          * __drm_helper_disable_unused_functions() will do so for the
 743          * primary plane.
 744          */
 745         if (plane->fb)
 746                 drm_framebuffer_unreference(plane->fb);
 747
 748         /* Power down the Y/U/V FIFOs */
 749         sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
 750
 751         /* Power down most RAMs and FIFOs if this is the primary plane */
 752         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 753                 sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 754                               CFG_PDWN32x32 | CFG_PDWN64x66;
 755                 dma_ctrl0_mask = CFG_GRA_ENA;
 756         } else {
 757                 dma_ctrl0_mask = CFG_DMA_ENA;
 758         }
 759
 760         spin_lock_irq(&dcrtc->irq_lock);
 761         armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
 762         spin_unlock_irq(&dcrtc->irq_lock);
 763
 764         armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
 765 }
 766
 767 /* The mode_config.mutex will be held for this call */
 768 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 769 {
 770         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 771
 772         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 773         armada_drm_crtc_plane_disable(dcrtc, crtc->primary);
 774 }
 775
 776 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 777         .dpms           = armada_drm_crtc_dpms,
 778         .prepare        = armada_drm_crtc_prepare,
 779         .commit         = armada_drm_crtc_commit,
 780         .mode_fixup     = armada_drm_crtc_mode_fixup,
 781         .mode_set       = armada_drm_crtc_mode_set,
 782         .mode_set_base  = armada_drm_crtc_mode_set_base,
 783         .disable        = armada_drm_crtc_disable,
 784 };
 785
 786 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 787         unsigned stride, unsigned width, unsigned height)
 788 {
 789         uint32_t addr;
 790         unsigned y;
 791
 792         addr = SRAM_HWC32_RAM1;
 793         for (y = 0; y < height; y++) {
 794                 uint32_t *p = &pix[y * stride];
 795                 unsigned x;
 796
 797                 for (x = 0; x < width; x++, p++) {
 798                         uint32_t val = *p;
 799
 800                         val = (val & 0xff00ff00) |
 801                               (val & 0x000000ff) << 16 |
 802                               (val & 0x00ff0000) >> 16;
 803
 804                         writel_relaxed(val,
 805                                        base + LCD_SPU_SRAM_WRDAT);
 806                         writel_relaxed(addr | SRAM_WRITE,
 807                                        base + LCD_SPU_SRAM_CTRL);
 808                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 809                         addr += 1;
 810                         if ((addr & 0x00ff) == 0)
 811                                 addr += 0xf00;
 812                         if ((addr & 0x30ff) == 0)
 813                                 addr = SRAM_HWC32_RAM2;
 814                 }
 815         }
 816 }
 817
 818 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 819 {
 820         unsigned addr;
 821
 822         for (addr = 0; addr < 256; addr++) {
 823                 /* write the default value */
 824                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 825                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 826                                base + LCD_SPU_SRAM_CTRL);
 827         }
 828 }
 829
 830 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 831 {
 832         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 833         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 834         uint32_t para1;
 835
 836         /*
 837          * Calculate the visible width and height of the cursor,
 838          * screen position, and the position in the cursor bitmap.
 839          */
 840         if (dcrtc->cursor_x < 0) {
 841                 xoff = -dcrtc->cursor_x;
 842                 xscr = 0;
 843                 w -= min(xoff, w);
 844         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 845                 xoff = 0;
 846                 xscr = dcrtc->cursor_x;
 847                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 848         } else {
 849                 xoff = 0;
 850                 xscr = dcrtc->cursor_x;
 851         }
 852
 853         if (dcrtc->cursor_y < 0) {
 854                 yoff = -dcrtc->cursor_y;
 855                 yscr = 0;
 856                 h -= min(yoff, h);
 857         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 858                 yoff = 0;
 859                 yscr = dcrtc->cursor_y;
 860                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 861         } else {
 862                 yoff = 0;
 863                 yscr = dcrtc->cursor_y;
 864         }
 865
 866         /* On interlaced modes, the vertical cursor size must be halved */
 867         s = dcrtc->cursor_w;
 868         if (dcrtc->interlaced) {
 869                 s *= 2;
 870                 yscr /= 2;
 871                 h /= 2;
 872         }
 873
 874         if (!dcrtc->cursor_obj || !h || !w) {
 875                 spin_lock_irq(&dcrtc->irq_lock);
 876                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 877                 dcrtc->cursor_update = false;
 878                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 879                 spin_unlock_irq(&dcrtc->irq_lock);
 880                 return 0;
 881         }
 882
 883         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 884         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 885                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 886
 887         /*
 888          * Initialize the transparency if the SRAM was powered down.
 889          * We must also reload the cursor data as well.
 890          */
 891         if (!(para1 & CFG_CSB_256x32)) {
 892                 armada_drm_crtc_cursor_tran(dcrtc->base);
 893                 reload = true;
 894         }
 895
 896         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 897                 spin_lock_irq(&dcrtc->irq_lock);
 898                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 899                 dcrtc->cursor_update = false;
 900                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 901                 spin_unlock_irq(&dcrtc->irq_lock);
 902                 reload = true;
 903         }
 904         if (reload) {
 905                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 906                 uint32_t *pix;
 907                 /* Set the top-left corner of the cursor image */
 908                 pix = obj->addr;
 909                 pix += yoff * s + xoff;
 910                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 911         }
 912
 913         /* Reload the cursor position, size and enable in the IRQ handler */
 914         spin_lock_irq(&dcrtc->irq_lock);
 915         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 916         dcrtc->cursor_hw_sz = h << 16 | w;
 917         dcrtc->cursor_update = true;
 918         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 919         spin_unlock_irq(&dcrtc->irq_lock);
 920
 921         return 0;
 922 }
 923
 924 static void cursor_update(void *data)
 925 {
 926         armada_drm_crtc_cursor_update(data, true);
 927 }
 928
 929 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 930         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 931 {
 932         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 933         struct armada_gem_object *obj = NULL;
 934         int ret;
 935
 936         /* If no cursor support, replicate drm's return value */
 937         if (!dcrtc->variant->has_spu_adv_reg)
 938                 return -ENXIO;
 939
 940         if (handle && w > 0 && h > 0) {
 941                 /* maximum size is 64x32 or 32x64 */
 942                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 943                         return -ENOMEM;
 944
 945                 obj = armada_gem_object_lookup(file, handle);
 946                 if (!obj)
 947                         return -ENOENT;
 948
 949                 /* Must be a kernel-mapped object */
 950                 if (!obj->addr) {
 951                         drm_gem_object_unreference_unlocked(&obj->obj);
 952                         return -EINVAL;
 953                 }
 954
 955                 if (obj->obj.size < w * h * 4) {
 956                         DRM_ERROR("buffer is too small\n");
 957                         drm_gem_object_unreference_unlocked(&obj->obj);
 958                         return -ENOMEM;
 959                 }
 960         }
 961
 962         if (dcrtc->cursor_obj) {
 963                 dcrtc->cursor_obj->update = NULL;
 964                 dcrtc->cursor_obj->update_data = NULL;
 965                 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj);
 966         }
 967         dcrtc->cursor_obj = obj;
 968         dcrtc->cursor_w = w;
 969         dcrtc->cursor_h = h;
 970         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 971         if (obj) {
 972                 obj->update_data = dcrtc;
 973                 obj->update = cursor_update;
 974         }
 975
 976         return ret;
 977 }
 978
 979 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 980 {
 981         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 982         int ret;
 983
 984         /* If no cursor support, replicate drm's return value */
 985         if (!dcrtc->variant->has_spu_adv_reg)
 986                 return -EFAULT;
 987
 988         dcrtc->cursor_x = x;
 989         dcrtc->cursor_y = y;
 990         ret = armada_drm_crtc_cursor_update(dcrtc, false);
 991
 992         return ret;
 993 }
 994
 995 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
 996 {
 997         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 998         struct armada_private *priv = crtc->dev->dev_private;
 999
1000         if (dcrtc->cursor_obj)
1001                 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj);
1002
1003         priv->dcrtc[dcrtc->num] = NULL;
1004         drm_crtc_cleanup(&dcrtc->crtc);
1005
1006         if (!IS_ERR(dcrtc->clk))
1007                 clk_disable_unprepare(dcrtc->clk);
1008
1009         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
1010
1011         of_node_put(dcrtc->crtc.port);
1012
1013         kfree(dcrtc);
1014 }
1015
1016 /*
1017  * The mode_config lock is held here, to prevent races between this
1018  * and a mode_set.
1019  */
1020 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
1021         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags,
1022         struct drm_modeset_acquire_ctx *ctx)
1023 {
1024         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1025         struct armada_frame_work *work;
1026         unsigned i;
1027         int ret;
1028
1029         /* We don't support changing the pixel format */
1030         if (fb->format != crtc->primary->fb->format)
1031                 return -EINVAL;
1032
1033         work = kmalloc(sizeof(*work), GFP_KERNEL);
1034         if (!work)
1035                 return -ENOMEM;
1036
1037         work->work.fn = armada_drm_crtc_complete_frame_work;
1038         work->event = event;
1039         work->old_fb = dcrtc->crtc.primary->fb;
1040
1041         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1042                                     dcrtc->interlaced);
1043         armada_reg_queue_end(work->regs, i);
1044
1045         /*
1046          * Ensure that we hold a reference on the new framebuffer.
1047          * This has to match the behaviour in mode_set.
1048          */
1049         drm_framebuffer_reference(fb);
1050
1051         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
1052         if (ret) {
1053                 /* Undo our reference above */
1054                 drm_framebuffer_unreference(fb);
1055                 kfree(work);
1056                 return ret;
1057         }
1058
1059         /*
1060          * Don't take a reference on the new framebuffer;
1061          * drm_mode_page_flip_ioctl() has already grabbed a reference and
1062          * will _not_ drop that reference on successful return from this
1063          * function.  Simply mark this new framebuffer as the current one.
1064          */
1065         dcrtc->crtc.primary->fb = fb;
1066
1067         /*
1068          * Finally, if the display is blanked, we won't receive an
1069          * interrupt, so complete it now.
1070          */
1071         if (dpms_blanked(dcrtc->dpms))
1072                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
1073
1074         return 0;
1075 }
1076
1077 static int
1078 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1079         struct drm_property *property, uint64_t val)
1080 {
1081         struct armada_private *priv = crtc->dev->dev_private;
1082         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1083         bool update_csc = false;
1084
1085         if (property == priv->csc_yuv_prop) {
1086                 dcrtc->csc_yuv_mode = val;
1087                 update_csc = true;
1088         } else if (property == priv->csc_rgb_prop) {
1089                 dcrtc->csc_rgb_mode = val;
1090                 update_csc = true;
1091         }
1092
1093         if (update_csc) {
1094                 uint32_t val;
1095
1096                 val = dcrtc->spu_iopad_ctrl |
1097                       armada_drm_crtc_calculate_csc(dcrtc);
1098                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1099         }
1100
1101         return 0;
1102 }
1103
1104 /* These are called under the vbl_lock. */
1105 static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
1106 {
1107         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1108         unsigned long flags;
1109
1110         spin_lock_irqsave(&dcrtc->irq_lock, flags);
1111         armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
1112         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
1113         return 0;
1114 }
1115
1116 static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
1117 {
1118         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1119         unsigned long flags;
1120
1121         spin_lock_irqsave(&dcrtc->irq_lock, flags);
1122         armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
1123         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
1124 }
1125
1126 static const struct drm_crtc_funcs armada_crtc_funcs = {
1127         .cursor_set     = armada_drm_crtc_cursor_set,
1128         .cursor_move    = armada_drm_crtc_cursor_move,
1129         .destroy        = armada_drm_crtc_destroy,
1130         .set_config     = drm_crtc_helper_set_config,
1131         .page_flip      = armada_drm_crtc_page_flip,
1132         .set_property   = armada_drm_crtc_set_property,
1133         .enable_vblank  = armada_drm_crtc_enable_vblank,
1134         .disable_vblank = armada_drm_crtc_disable_vblank,
1135 };
1136
1137 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1138         .update_plane   = drm_primary_helper_update,
1139         .disable_plane  = drm_primary_helper_disable,
1140         .destroy        = drm_primary_helper_destroy,
1141 };
1142
1143 int armada_drm_plane_init(struct armada_plane *plane)
1144 {
1145         init_waitqueue_head(&plane->frame_wait);
1146
1147         return 0;
1148 }
1149
1150 static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1151         { CSC_AUTO,        "Auto" },
1152         { CSC_YUV_CCIR601, "CCIR601" },
1153         { CSC_YUV_CCIR709, "CCIR709" },
1154 };
1155
1156 static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1157         { CSC_AUTO,         "Auto" },
1158         { CSC_RGB_COMPUTER, "Computer system" },
1159         { CSC_RGB_STUDIO,   "Studio" },
1160 };
1161
1162 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1163 {
1164         struct armada_private *priv = dev->dev_private;
1165
1166         if (priv->csc_yuv_prop)
1167                 return 0;
1168
1169         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1170                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1171                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1172         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1173                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1174                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1175
1176         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1177                 return -ENOMEM;
1178
1179         return 0;
1180 }
1181
1182 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1183         struct resource *res, int irq, const struct armada_variant *variant,
1184         struct device_node *port)
1185 {
1186         struct armada_private *priv = drm->dev_private;
1187         struct armada_crtc *dcrtc;
1188         struct armada_plane *primary;
1189         void __iomem *base;
1190         int ret;
1191
1192         ret = armada_drm_crtc_create_properties(drm);
1193         if (ret)
1194                 return ret;
1195
1196         base = devm_ioremap_resource(dev, res);
1197         if (IS_ERR(base))
1198                 return PTR_ERR(base);
1199
1200         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1201         if (!dcrtc) {
1202                 DRM_ERROR("failed to allocate Armada crtc\n");
1203                 return -ENOMEM;
1204         }
1205
1206         if (dev != drm->dev)
1207                 dev_set_drvdata(dev, dcrtc);
1208
1209         dcrtc->variant = variant;
1210         dcrtc->base = base;
1211         dcrtc->num = drm->mode_config.num_crtc;
1212         dcrtc->clk = ERR_PTR(-EINVAL);
1213         dcrtc->csc_yuv_mode = CSC_AUTO;
1214         dcrtc->csc_rgb_mode = CSC_AUTO;
1215         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1216         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1217         spin_lock_init(&dcrtc->irq_lock);
1218         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1219
1220         /* Initialize some registers which we don't otherwise set */
1221         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1222         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1223         writel_relaxed(dcrtc->spu_iopad_ctrl,
1224                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1225         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1226         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1227                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1228                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1229         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1230         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1231         readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
1232         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1233
1234         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1235                                dcrtc);
1236         if (ret < 0)
1237                 goto err_crtc;
1238
1239         if (dcrtc->variant->init) {
1240                 ret = dcrtc->variant->init(dcrtc, dev);
1241                 if (ret)
1242                         goto err_crtc;
1243         }
1244
1245         /* Ensure AXI pipeline is enabled */
1246         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1247
1248         priv->dcrtc[dcrtc->num] = dcrtc;
1249
1250         dcrtc->crtc.port = port;
1251
1252         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1253         if (!primary) {
1254                 ret = -ENOMEM;
1255                 goto err_crtc;
1256         }
1257
1258         ret = armada_drm_plane_init(primary);
1259         if (ret) {
1260                 kfree(primary);
1261                 goto err_crtc;
1262         }
1263
1264         ret = drm_universal_plane_init(drm, &primary->base, 0,
1265                                        &armada_primary_plane_funcs,
1266                                        armada_primary_formats,
1267                                        ARRAY_SIZE(armada_primary_formats),
1268                                        NULL,
1269                                        DRM_PLANE_TYPE_PRIMARY, NULL);
1270         if (ret) {
1271                 kfree(primary);
1272                 goto err_crtc;
1273         }
1274
1275         ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1276                                         &armada_crtc_funcs, NULL);
1277         if (ret)
1278                 goto err_crtc_init;
1279
1280         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1281
1282         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1283                                    dcrtc->csc_yuv_mode);
1284         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1285                                    dcrtc->csc_rgb_mode);
1286
1287         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1288
1289 err_crtc_init:
1290         primary->base.funcs->destroy(&primary->base);
1291 err_crtc:
1292         kfree(dcrtc);
1293
1294         return ret;
1295 }
1296
1297 static int
1298 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1299 {
1300         struct platform_device *pdev = to_platform_device(dev);
1301         struct drm_device *drm = data;
1302         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1303         int irq = platform_get_irq(pdev, 0);
1304         const struct armada_variant *variant;
1305         struct device_node *port = NULL;
1306
1307         if (irq < 0)
1308                 return irq;
1309
1310         if (!dev->of_node) {
1311                 const struct platform_device_id *id;
1312
1313                 id = platform_get_device_id(pdev);
1314                 if (!id)
1315                         return -ENXIO;
1316
1317                 variant = (const struct armada_variant *)id->driver_data;
1318         } else {
1319                 const struct of_device_id *match;
1320                 struct device_node *np, *parent = dev->of_node;
1321
1322                 match = of_match_device(dev->driver->of_match_table, dev);
1323                 if (!match)
1324                         return -ENXIO;
1325
1326                 np = of_get_child_by_name(parent, "ports");
1327                 if (np)
1328                         parent = np;
1329                 port = of_get_child_by_name(parent, "port");
1330                 of_node_put(np);
1331                 if (!port) {
1332                         dev_err(dev, "no port node found in %pOF\n", parent);
1333                         return -ENXIO;
1334                 }
1335
1336                 variant = match->data;
1337         }
1338
1339         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1340 }
1341
1342 static void
1343 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1344 {
1345         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1346
1347         armada_drm_crtc_destroy(&dcrtc->crtc);
1348 }
1349
1350 static const struct component_ops armada_lcd_ops = {
1351         .bind = armada_lcd_bind,
1352         .unbind = armada_lcd_unbind,
1353 };
1354
1355 static int armada_lcd_probe(struct platform_device *pdev)
1356 {
1357         return component_add(&pdev->dev, &armada_lcd_ops);
1358 }
1359
1360 static int armada_lcd_remove(struct platform_device *pdev)
1361 {
1362         component_del(&pdev->dev, &armada_lcd_ops);
1363         return 0;
1364 }
1365
1366 static const struct of_device_id armada_lcd_of_match[] = {
1367         {
1368                 .compatible     = "marvell,dove-lcd",
1369                 .data           = &armada510_ops,
1370         },
1371         {}
1372 };
1373 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1374
1375 static const struct platform_device_id armada_lcd_platform_ids[] = {
1376         {
1377                 .name           = "armada-lcd",
1378                 .driver_data    = (unsigned long)&armada510_ops,
1379         }, {
1380                 .name           = "armada-510-lcd",
1381                 .driver_data    = (unsigned long)&armada510_ops,
1382         },
1383         { },
1384 };
1385 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1386
1387 struct platform_driver armada_lcd_platform_driver = {
1388         .probe  = armada_lcd_probe,
1389         .remove = armada_lcd_remove,
1390         .driver = {
1391                 .name   = "armada-lcd",
1392                 .owner  =  THIS_MODULE,
1393                 .of_match_table = armada_lcd_of_match,
1394         },
1395         .id_table = armada_lcd_platform_ids,
1396 };