drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _AMD_POWERPLAY_H_
  24 #define _AMD_POWERPLAY_H_
  25
  26 #include <linux/seq_file.h>
  27 #include <linux/types.h>
  28 #include <linux/errno.h>
  29 #include "amd_shared.h"
  30 #include "cgs_common.h"
  31 #include "dm_pp_interface.h"
  32
  33 extern const struct amd_ip_funcs pp_ip_funcs;
  34 extern const struct amd_powerplay_funcs pp_dpm_funcs;
  35
  36 #define PP_DPM_DISABLED 0xCCCC
  37
  38 enum amd_pp_sensors {
  39         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
  40         AMDGPU_PP_SENSOR_VDDNB,
  41         AMDGPU_PP_SENSOR_VDDGFX,
  42         AMDGPU_PP_SENSOR_UVD_VCLK,
  43         AMDGPU_PP_SENSOR_UVD_DCLK,
  44         AMDGPU_PP_SENSOR_VCE_ECCLK,
  45         AMDGPU_PP_SENSOR_GPU_LOAD,
  46         AMDGPU_PP_SENSOR_GFX_MCLK,
  47         AMDGPU_PP_SENSOR_GPU_TEMP,
  48         AMDGPU_PP_SENSOR_VCE_POWER,
  49         AMDGPU_PP_SENSOR_UVD_POWER,
  50         AMDGPU_PP_SENSOR_GPU_POWER,
  51 };
  52
  53 enum amd_pp_event {
  54         AMD_PP_EVENT_INITIALIZE = 0,
  55         AMD_PP_EVENT_UNINITIALIZE,
  56         AMD_PP_EVENT_POWER_SOURCE_CHANGE,
  57         AMD_PP_EVENT_SUSPEND,
  58         AMD_PP_EVENT_RESUME,
  59         AMD_PP_EVENT_ENTER_REST_STATE,
  60         AMD_PP_EVENT_EXIT_REST_STATE,
  61         AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
  62         AMD_PP_EVENT_THERMAL_NOTIFICATION,
  63         AMD_PP_EVENT_VBIOS_NOTIFICATION,
  64         AMD_PP_EVENT_ENTER_THERMAL_STATE,
  65         AMD_PP_EVENT_EXIT_THERMAL_STATE,
  66         AMD_PP_EVENT_ENTER_FORCED_STATE,
  67         AMD_PP_EVENT_EXIT_FORCED_STATE,
  68         AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
  69         AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
  70         AMD_PP_EVENT_ENTER_SCREEN_SAVER,
  71         AMD_PP_EVENT_EXIT_SCREEN_SAVER,
  72         AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
  73         AMD_PP_EVENT_VPU_RECOVERY_END,
  74         AMD_PP_EVENT_ENABLE_POWER_PLAY,
  75         AMD_PP_EVENT_DISABLE_POWER_PLAY,
  76         AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
  77         AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
  78         AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
  79         AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
  80         AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
  81         AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
  82         AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
  83         AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
  84         AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
  85         AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
  86         AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
  87         AMD_PP_EVENT_ENABLE_CGPG,
  88         AMD_PP_EVENT_DISABLE_CGPG,
  89         AMD_PP_EVENT_ENTER_TEXT_MODE,
  90         AMD_PP_EVENT_EXIT_TEXT_MODE,
  91         AMD_PP_EVENT_VIDEO_START,
  92         AMD_PP_EVENT_VIDEO_STOP,
  93         AMD_PP_EVENT_ENABLE_USER_STATE,
  94         AMD_PP_EVENT_DISABLE_USER_STATE,
  95         AMD_PP_EVENT_READJUST_POWER_STATE,
  96         AMD_PP_EVENT_START_INACTIVITY,
  97         AMD_PP_EVENT_STOP_INACTIVITY,
  98         AMD_PP_EVENT_LINKED_ADAPTERS_READY,
  99         AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
 100         AMD_PP_EVENT_COMPLETE_INIT,
 101         AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
 102         AMD_PP_EVENT_BACKLIGHT_CHANGED,
 103         AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
 104         AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
 105         AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
 106         AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
 107         AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
 108         AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
 109         AMD_PP_EVENT_SCREEN_ON,
 110         AMD_PP_EVENT_SCREEN_OFF,
 111         AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
 112         AMD_PP_EVENT_ENTER_ULP_STATE,
 113         AMD_PP_EVENT_EXIT_ULP_STATE,
 114         AMD_PP_EVENT_REGISTER_IP_STATE,
 115         AMD_PP_EVENT_UNREGISTER_IP_STATE,
 116         AMD_PP_EVENT_ENTER_MGPU_MODE,
 117         AMD_PP_EVENT_EXIT_MGPU_MODE,
 118         AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
 119         AMD_PP_EVENT_PRE_SUSPEND,
 120         AMD_PP_EVENT_PRE_RESUME,
 121         AMD_PP_EVENT_ENTER_BACOS,
 122         AMD_PP_EVENT_EXIT_BACOS,
 123         AMD_PP_EVENT_RESUME_BACO,
 124         AMD_PP_EVENT_RESET_BACO,
 125         AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
 126         AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
 127         AMD_PP_EVENT_START_COMPUTE_APPLICATION,
 128         AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
 129         AMD_PP_EVENT_REDUCE_POWER_LIMIT,
 130         AMD_PP_EVENT_ENTER_FRAME_LOCK,
 131         AMD_PP_EVENT_EXIT_FRAME_LOOCK,
 132         AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
 133         AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
 134         AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
 135         AMD_PP_EVENT_HIBERNATE,
 136         AMD_PP_EVENT_CONNECTED_STANDBY,
 137         AMD_PP_EVENT_ENTER_SELF_REFRESH,
 138         AMD_PP_EVENT_EXIT_SELF_REFRESH,
 139         AMD_PP_EVENT_START_AVFS_BTC,
 140         AMD_PP_EVENT_MAX
 141 };
 142
 143 struct amd_pp_init {
 144         struct cgs_device *device;
 145         uint32_t chip_family;
 146         uint32_t chip_id;
 147         bool pm_en;
 148         uint32_t feature_mask;
 149 };
 150
 151 enum amd_pp_display_config_type{
 152         AMD_PP_DisplayConfigType_None = 0,
 153         AMD_PP_DisplayConfigType_DP54 ,
 154         AMD_PP_DisplayConfigType_DP432 ,
 155         AMD_PP_DisplayConfigType_DP324 ,
 156         AMD_PP_DisplayConfigType_DP27,
 157         AMD_PP_DisplayConfigType_DP243,
 158         AMD_PP_DisplayConfigType_DP216,
 159         AMD_PP_DisplayConfigType_DP162,
 160         AMD_PP_DisplayConfigType_HDMI6G ,
 161         AMD_PP_DisplayConfigType_HDMI297 ,
 162         AMD_PP_DisplayConfigType_HDMI162,
 163         AMD_PP_DisplayConfigType_LVDS,
 164         AMD_PP_DisplayConfigType_DVI,
 165         AMD_PP_DisplayConfigType_WIRELESS,
 166         AMD_PP_DisplayConfigType_VGA
 167 };
 168
 169 struct single_display_configuration
 170 {
 171         uint32_t controller_index;
 172         uint32_t controller_id;
 173         uint32_t signal_type;
 174         uint32_t display_state;
 175         /* phy id for the primary internal transmitter */
 176         uint8_t primary_transmitter_phyi_d;
 177         /* bitmap with the active lanes */
 178         uint8_t primary_transmitter_active_lanemap;
 179         /* phy id for the secondary internal transmitter (for dual-link dvi) */
 180         uint8_t secondary_transmitter_phy_id;
 181         /* bitmap with the active lanes */
 182         uint8_t secondary_transmitter_active_lanemap;
 183         /* misc phy settings for SMU. */
 184         uint32_t config_flags;
 185         uint32_t display_type;
 186         uint32_t view_resolution_cx;
 187         uint32_t view_resolution_cy;
 188         enum amd_pp_display_config_type displayconfigtype;
 189         uint32_t vertical_refresh; /* for active display */
 190 };
 191
 192 #define MAX_NUM_DISPLAY 32
 193
 194 struct amd_pp_display_configuration {
 195         bool nb_pstate_switch_disable;/* controls NB PState switch */
 196         bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
 197         bool cpu_pstate_disable;
 198         uint32_t cpu_pstate_separation_time;
 199
 200         uint32_t num_display;  /* total number of display*/
 201         uint32_t num_path_including_non_display;
 202         uint32_t crossfire_display_index;
 203         uint32_t min_mem_set_clock;
 204         uint32_t min_core_set_clock;
 205         /* unit 10KHz x bit*/
 206         uint32_t min_bus_bandwidth;
 207         /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
 208         uint32_t min_core_set_clock_in_sr;
 209
 210         struct single_display_configuration displays[MAX_NUM_DISPLAY];
 211
 212         uint32_t vrefresh; /* for active display*/
 213
 214         uint32_t min_vblank_time; /* for active display*/
 215         bool multi_monitor_in_sync;
 216         /* Controller Index of primary display - used in MCLK SMC switching hang
 217          * SW Workaround*/
 218         uint32_t crtc_index;
 219         /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
 220         uint32_t line_time_in_us;
 221         bool invalid_vblank_time;
 222
 223         uint32_t display_clk;
 224         /*
 225          * for given display configuration if multimonitormnsync == false then
 226          * Memory clock DPMS with this latency or below is allowed, DPMS with
 227          * higher latency not allowed.
 228          */
 229         uint32_t dce_tolerable_mclk_in_active_latency;
 230         uint32_t min_dcef_set_clk;
 231         uint32_t min_dcef_deep_sleep_set_clk;
 232 };
 233
 234 struct amd_pp_simple_clock_info {
 235         uint32_t        engine_max_clock;
 236         uint32_t        memory_max_clock;
 237         uint32_t        level;
 238 };
 239
 240 enum PP_DAL_POWERLEVEL {
 241         PP_DAL_POWERLEVEL_INVALID = 0,
 242         PP_DAL_POWERLEVEL_ULTRALOW,
 243         PP_DAL_POWERLEVEL_LOW,
 244         PP_DAL_POWERLEVEL_NOMINAL,
 245         PP_DAL_POWERLEVEL_PERFORMANCE,
 246
 247         PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
 248         PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
 249         PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
 250         PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
 251         PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
 252         PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
 253         PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
 254         PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
 255 };
 256
 257 struct amd_pp_clock_info {
 258         uint32_t min_engine_clock;
 259         uint32_t max_engine_clock;
 260         uint32_t min_memory_clock;
 261         uint32_t max_memory_clock;
 262         uint32_t min_bus_bandwidth;
 263         uint32_t max_bus_bandwidth;
 264         uint32_t max_engine_clock_in_sr;
 265         uint32_t min_engine_clock_in_sr;
 266         enum PP_DAL_POWERLEVEL max_clocks_state;
 267 };
 268
 269 enum amd_pp_clock_type {
 270         amd_pp_disp_clock = 1,
 271         amd_pp_sys_clock,
 272         amd_pp_mem_clock,
 273         amd_pp_dcef_clock,
 274         amd_pp_soc_clock,
 275         amd_pp_pixel_clock,
 276         amd_pp_phy_clock,
 277         amd_pp_dcf_clock,
 278         amd_pp_dpp_clock,
 279         amd_pp_f_clock = amd_pp_dcef_clock,
 280 };
 281
 282 #define MAX_NUM_CLOCKS 16
 283
 284 struct amd_pp_clocks {
 285         uint32_t count;
 286         uint32_t clock[MAX_NUM_CLOCKS];
 287         uint32_t latency[MAX_NUM_CLOCKS];
 288 };
 289
 290
 291 enum {
 292         PP_GROUP_UNKNOWN = 0,
 293         PP_GROUP_GFX = 1,
 294         PP_GROUP_SYS,
 295         PP_GROUP_MAX
 296 };
 297
 298 enum pp_clock_type {
 299         PP_SCLK,
 300         PP_MCLK,
 301         PP_PCIE,
 302 };
 303
 304 struct pp_states_info {
 305         uint32_t nums;
 306         uint32_t states[16];
 307 };
 308
 309 struct pp_gpu_power {
 310         uint32_t vddc_power;
 311         uint32_t vddci_power;
 312         uint32_t max_gpu_power;
 313         uint32_t average_gpu_power;
 314 };
 315
 316 struct pp_display_clock_request {
 317         enum amd_pp_clock_type clock_type;
 318         uint32_t clock_freq_in_khz;
 319 };
 320
 321 #define PP_GROUP_MASK        0xF0000000
 322 #define PP_GROUP_SHIFT       28
 323
 324 #define PP_BLOCK_MASK        0x0FFFFF00
 325 #define PP_BLOCK_SHIFT       8
 326
 327 #define PP_BLOCK_GFX_CG         0x01
 328 #define PP_BLOCK_GFX_MG         0x02
 329 #define PP_BLOCK_GFX_3D         0x04
 330 #define PP_BLOCK_GFX_RLC        0x08
 331 #define PP_BLOCK_GFX_CP         0x10
 332 #define PP_BLOCK_SYS_BIF        0x01
 333 #define PP_BLOCK_SYS_MC         0x02
 334 #define PP_BLOCK_SYS_ROM        0x04
 335 #define PP_BLOCK_SYS_DRM        0x08
 336 #define PP_BLOCK_SYS_HDP        0x10
 337 #define PP_BLOCK_SYS_SDMA       0x20
 338
 339 #define PP_STATE_MASK           0x0000000F
 340 #define PP_STATE_SHIFT          0
 341 #define PP_STATE_SUPPORT_MASK   0x000000F0
 342 #define PP_STATE_SUPPORT_SHIFT  0
 343
 344 #define PP_STATE_CG             0x01
 345 #define PP_STATE_LS             0x02
 346 #define PP_STATE_DS             0x04
 347 #define PP_STATE_SD             0x08
 348 #define PP_STATE_SUPPORT_CG     0x10
 349 #define PP_STATE_SUPPORT_LS     0x20
 350 #define PP_STATE_SUPPORT_DS     0x40
 351 #define PP_STATE_SUPPORT_SD     0x80
 352
 353 #define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
 354                                                                 block << PP_BLOCK_SHIFT |\
 355                                                                 support << PP_STATE_SUPPORT_SHIFT |\
 356                                                                 state << PP_STATE_SHIFT)
 357
 358 struct amd_powerplay_funcs {
 359         int (*get_temperature)(void *handle);
 360         int (*load_firmware)(void *handle);
 361         int (*wait_for_fw_loading_complete)(void *handle);
 362         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 363         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 364         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 365         int (*get_sclk)(void *handle, bool low);
 366         int (*get_mclk)(void *handle, bool low);
 367         int (*powergate_vce)(void *handle, bool gate);
 368         int (*powergate_uvd)(void *handle, bool gate);
 369         int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
 370                                    void *input, void *output);
 371         int (*set_fan_control_mode)(void *handle, uint32_t mode);
 372         int (*get_fan_control_mode)(void *handle);
 373         int (*set_fan_speed_percent)(void *handle, uint32_t percent);
 374         int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
 375         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 376         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 377         int (*get_pp_table)(void *handle, char **table);
 378         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 379         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 380         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 381         int (*get_sclk_od)(void *handle);
 382         int (*set_sclk_od)(void *handle, uint32_t value);
 383         int (*get_mclk_od)(void *handle);
 384         int (*set_mclk_od)(void *handle, uint32_t value);
 385         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 386         struct amd_vce_state* (*get_vce_clock_state)(void *handle, unsigned idx);
 387         int (*reset_power_profile_state)(void *handle,
 388                         struct amd_pp_profile *request);
 389         int (*get_power_profile_state)(void *handle,
 390                         struct amd_pp_profile *query);
 391         int (*set_power_profile_state)(void *handle,
 392                         struct amd_pp_profile *request);
 393         int (*switch_power_profile)(void *handle,
 394                         enum amd_pp_profile_type type);
 395 };
 396
 397 struct amd_powerplay {
 398         void *pp_handle;
 399         const struct amd_ip_funcs *ip_funcs;
 400         const struct amd_powerplay_funcs *pp_funcs;
 401 };
 402
 403 int amd_powerplay_create(struct amd_pp_init *pp_init,
 404                                 void **handle);
 405
 406 int amd_powerplay_destroy(void *handle);
 407
 408 int amd_powerplay_reset(void *handle);
 409
 410 int amd_powerplay_display_configuration_change(void *handle,
 411                 const struct amd_pp_display_configuration *input);
 412
 413 int amd_powerplay_get_display_power_level(void *handle,
 414                 struct amd_pp_simple_clock_info *output);
 415
 416 int amd_powerplay_get_current_clocks(void *handle,
 417                 struct amd_pp_clock_info *output);
 418
 419 int amd_powerplay_get_clock_by_type(void *handle,
 420                 enum amd_pp_clock_type type,
 421                 struct amd_pp_clocks *clocks);
 422
 423 int amd_powerplay_get_clock_by_type_with_latency(void *handle,
 424                 enum amd_pp_clock_type type,
 425                 struct pp_clock_levels_with_latency *clocks);
 426
 427 int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
 428                 enum amd_pp_clock_type type,
 429                 struct pp_clock_levels_with_voltage *clocks);
 430
 431 int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
 432                 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
 433
 434 int amd_powerplay_display_clock_voltage_request(void *handle,
 435                 struct pp_display_clock_request *clock);
 436
 437 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
 438                 struct amd_pp_simple_clock_info *output);
 439
 440 int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
 441
 442 #endif /* _AMD_POWERPLAY_H_ */