drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_9_0.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __IRQSRCS_GFX_9_0_H__
  27 #define __IRQSRCS_GFX_9_0_H__
  28
  29
  30 #define GFX_9_0__SRCID__CP_RB_INTERRUPT_PKT                                     176             /* B0 CP_INTERRUPT pkt in RB */
  31 #define GFX_9_0__SRCID__CP_IB1_INTERRUPT_PKT                            177             /* B1 CP_INTERRUPT pkt in IB1 */
  32 #define GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT                            178             /* B2 CP_INTERRUPT pkt in IB2 */
  33 #define GFX_9_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR                       180             /* B4 PM4 Pkt Rsvd Bits Error */
  34 #define GFX_9_0__SRCID__CP_EOP_INTERRUPT                                        181             /* B5 End-of-Pipe Interrupt */
  35 #define GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR                                     183             /* B7 Bad Opcode Error */
  36 #define GFX_9_0__SRCID__CP_PRIV_REG_FAULT                                       184             /* B8 Privileged Register Fault */
  37 #define GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT                                     185             /* B9 Privileged Instr Fault */
  38 #define GFX_9_0__SRCID__CP_WAIT_MEM_SEM_FAULT                           186             /* BA Wait Memory Semaphore Fault (Synchronization Object Fault) */
  39 #define GFX_9_0__SRCID__CP_CTX_EMPTY_INTERRUPT                          187             /* BB Context Empty Interrupt */
  40 #define GFX_9_0__SRCID__CP_CTX_BUSY_INTERRUPT                           188             /* BC Context Busy Interrupt */
  41 #define GFX_9_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT         192             /* C0 CP.ME Wait_Reg_Mem Poll Timeout */
  42 #define GFX_9_0__SRCID__CP_SIG_INCOMPLETE                                       193             /* C1 "Surface Probe Fault Signal Incomplete" */
  43 #define GFX_9_0__SRCID__CP_PREEMPT_ACK                                      194         /* C2 Preemption Ack-wledge */
  44 #define GFX_9_0__SRCID__CP_GPF                                              195         /* C3 General Protection Fault (GPF) */
  45 #define GFX_9_0__SRCID__CP_GDS_ALLOC_ERROR                                      196             /* C4 GDS Alloc Error */
  46 #define GFX_9_0__SRCID__CP_ECC_ERROR                                        197         /* C5 ECC  Error */
  47 #define GFX_9_0__SRCID__CP_COMPUTE_QUERY_STATUS             199     /* C7 Compute query status */
  48 #define GFX_9_0__SRCID__CP_VM_DOORBELL                                      200         /* C8 Unattached VM Doorbell Received */
  49 #define GFX_9_0__SRCID__CP_FUE_ERROR                                        201         /* C9 ECC FUE Error */
  50 #define GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT         202             /* CA Streaming Perf Monitor Interrupt */
  51 #define GFX_9_0__SRCID__GRBM_RD_TIMEOUT_ERROR                           232             /* E8 CRead timeout error */
  52 #define GFX_9_0__SRCID__GRBM_REG_GUI_IDLE                                       233             /* E9 Register GUI Idle */
  53 #define GFX_9_0__SRCID__SQ_INTERRUPT_ID                                     239         /* EF SQ Interrupt (ttrace wrap, errors) */
  54
  55 #endif /* __IRQSRCS_GFX_9_0_H__ */