2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 #ifndef _mp_10_0_SH_MASK_HEADER
22 #define _mp_10_0_SH_MASK_HEADER
25 // addressBlock: mp_SmuMp0_SmnDec
27 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
28 #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
30 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
31 #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
33 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
34 #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
36 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
37 #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
39 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
40 #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
42 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
43 #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
45 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
46 #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
48 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
49 #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
51 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
52 #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
54 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
55 #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
57 #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
58 #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
60 #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
61 #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
63 #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
64 #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
66 #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
67 #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
69 #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
70 #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
72 #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
73 #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
75 #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
76 #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
78 #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
79 #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
81 #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
82 #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
84 #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
85 #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
87 #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
88 #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
90 #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
91 #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
93 #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
94 #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
96 #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
97 #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
99 #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
100 #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
102 #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
103 #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
105 #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
106 #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
108 #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
109 #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
111 #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
112 #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
114 #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
115 #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
117 #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
118 #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
120 #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
121 #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
123 #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
124 #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
126 #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
127 #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
129 #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
130 #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
132 #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
133 #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
135 #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
136 #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
138 #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
139 #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
141 #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
142 #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
144 #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
145 #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
147 #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
148 #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
150 #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
151 #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
153 #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
154 #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
156 #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
157 #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
159 #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
160 #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
162 #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
163 #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
165 #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
166 #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
168 #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
169 #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
171 #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
172 #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
174 #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
175 #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
177 #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
178 #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
180 #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
181 #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
183 #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
184 #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
186 #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
187 #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
189 #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
190 #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
192 #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
193 #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
195 #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
196 #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
198 #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
199 #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
201 #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
202 #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
204 #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
205 #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
207 #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
208 #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
210 #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
211 #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
213 #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
214 #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
216 #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
217 #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
219 #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
220 #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
222 #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
223 #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
225 #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
226 #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
228 #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
229 #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
231 #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
232 #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
234 #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
235 #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
237 #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
238 #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
240 #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
241 #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
243 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
244 #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
245 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
246 #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
248 #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0
249 #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1
250 #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L
251 #define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL
252 //MP0_SMN_IH_SW_INT_CTRL
253 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
254 #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
255 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
256 #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
259 // addressBlock: mp_SmuMp1_SmnDec
261 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
262 #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
264 #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
265 #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
267 #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
268 #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
270 #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
271 #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
273 #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
274 #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
276 #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
277 #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
279 #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
280 #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
282 #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
283 #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
285 #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
286 #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
288 #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
289 #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
291 #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
292 #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
294 #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
295 #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
297 #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
298 #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
300 #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
301 #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
303 #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
304 #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
306 #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
307 #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
309 #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
310 #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
312 #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
313 #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
315 #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
316 #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
318 #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
319 #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
321 #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
322 #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
324 #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
325 #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
327 #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
328 #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
330 #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
331 #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
333 #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
334 #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
336 #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
337 #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
339 #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
340 #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
342 #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
343 #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
345 #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
346 #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
348 #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
349 #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
351 #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
352 #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
354 #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
355 #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
357 #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
358 #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
360 #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
361 #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
363 #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
364 #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
366 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
367 #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
369 #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
370 #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
372 #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
373 #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
375 #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
376 #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
378 #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
379 #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
381 #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
382 #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
384 #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
385 #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
387 #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
388 #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
390 #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
391 #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
393 #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
394 #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
396 #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
397 #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
399 #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
400 #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
402 #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
403 #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
405 #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
406 #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
408 #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
409 #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
411 #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
412 #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
414 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
415 #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
417 #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
418 #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
420 #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
421 #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
423 #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
424 #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
426 #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
427 #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
429 #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
430 #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
432 #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
433 #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
435 #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
436 #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
438 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
439 #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
441 #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
442 #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
444 #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
445 #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
447 #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
448 #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
450 #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
451 #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
453 #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
454 #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
456 #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
457 #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
459 #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
460 #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
462 #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
463 #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
465 #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
466 #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
468 #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
469 #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
471 #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
472 #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
474 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
475 #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
477 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
478 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
479 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
480 #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
482 #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0
483 #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1
484 #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L
485 #define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL
486 //MP1_SMN_IH_SW_INT_CTRL
487 #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0
488 #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8
489 #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L
490 #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L
492 #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
493 #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
496 // addressBlock: mp_SmuMp0Pub_CruDec
498 #define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
499 #define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
500 #define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
501 #define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
503 #define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
504 #define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10
505 #define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
506 #define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
508 #define MP0_IH_SW_INT__ID__SHIFT 0x0
509 #define MP0_IH_SW_INT__VALID__SHIFT 0x8
510 #define MP0_IH_SW_INT__ID_MASK 0x000000FFL
511 #define MP0_IH_SW_INT__VALID_MASK 0x00000100L
513 #define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
514 #define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
515 #define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
516 #define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
519 // addressBlock: mp_SmuMp1Pub_CruDec
521 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
522 #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
523 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
524 #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
526 #define MP1_C2PMSG_0__CONTENT__SHIFT 0x0
527 #define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
529 #define MP1_C2PMSG_1__CONTENT__SHIFT 0x0
530 #define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
532 #define MP1_C2PMSG_2__CONTENT__SHIFT 0x0
533 #define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
535 #define MP1_C2PMSG_3__CONTENT__SHIFT 0x0
536 #define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
538 #define MP1_C2PMSG_4__CONTENT__SHIFT 0x0
539 #define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
541 #define MP1_C2PMSG_5__CONTENT__SHIFT 0x0
542 #define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
544 #define MP1_C2PMSG_6__CONTENT__SHIFT 0x0
545 #define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
547 #define MP1_C2PMSG_7__CONTENT__SHIFT 0x0
548 #define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
550 #define MP1_C2PMSG_8__CONTENT__SHIFT 0x0
551 #define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
553 #define MP1_C2PMSG_9__CONTENT__SHIFT 0x0
554 #define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
556 #define MP1_C2PMSG_10__CONTENT__SHIFT 0x0
557 #define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
559 #define MP1_C2PMSG_11__CONTENT__SHIFT 0x0
560 #define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
562 #define MP1_C2PMSG_12__CONTENT__SHIFT 0x0
563 #define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
565 #define MP1_C2PMSG_13__CONTENT__SHIFT 0x0
566 #define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
568 #define MP1_C2PMSG_14__CONTENT__SHIFT 0x0
569 #define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
571 #define MP1_C2PMSG_15__CONTENT__SHIFT 0x0
572 #define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
574 #define MP1_C2PMSG_16__CONTENT__SHIFT 0x0
575 #define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
577 #define MP1_C2PMSG_17__CONTENT__SHIFT 0x0
578 #define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
580 #define MP1_C2PMSG_18__CONTENT__SHIFT 0x0
581 #define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
583 #define MP1_C2PMSG_19__CONTENT__SHIFT 0x0
584 #define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
586 #define MP1_C2PMSG_20__CONTENT__SHIFT 0x0
587 #define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
589 #define MP1_C2PMSG_21__CONTENT__SHIFT 0x0
590 #define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
592 #define MP1_C2PMSG_22__CONTENT__SHIFT 0x0
593 #define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
595 #define MP1_C2PMSG_23__CONTENT__SHIFT 0x0
596 #define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
598 #define MP1_C2PMSG_24__CONTENT__SHIFT 0x0
599 #define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
601 #define MP1_C2PMSG_25__CONTENT__SHIFT 0x0
602 #define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
604 #define MP1_C2PMSG_26__CONTENT__SHIFT 0x0
605 #define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
607 #define MP1_C2PMSG_27__CONTENT__SHIFT 0x0
608 #define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
610 #define MP1_C2PMSG_28__CONTENT__SHIFT 0x0
611 #define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
613 #define MP1_C2PMSG_29__CONTENT__SHIFT 0x0
614 #define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
616 #define MP1_C2PMSG_30__CONTENT__SHIFT 0x0
617 #define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
619 #define MP1_C2PMSG_31__CONTENT__SHIFT 0x0
620 #define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
622 #define MP1_P2CMSG_0__CONTENT__SHIFT 0x0
623 #define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
625 #define MP1_P2CMSG_1__CONTENT__SHIFT 0x0
626 #define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
628 #define MP1_P2CMSG_2__CONTENT__SHIFT 0x0
629 #define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
631 #define MP1_P2CMSG_3__CONTENT__SHIFT 0x0
632 #define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
634 #define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0
635 #define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
637 #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
638 #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
639 #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
640 #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
641 #define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
642 #define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
643 #define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
644 #define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
646 #define MP1_C2PMSG_32__CONTENT__SHIFT 0x0
647 #define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
649 #define MP1_C2PMSG_33__CONTENT__SHIFT 0x0
650 #define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
652 #define MP1_C2PMSG_34__CONTENT__SHIFT 0x0
653 #define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
655 #define MP1_C2PMSG_35__CONTENT__SHIFT 0x0
656 #define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
658 #define MP1_C2PMSG_36__CONTENT__SHIFT 0x0
659 #define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
661 #define MP1_C2PMSG_37__CONTENT__SHIFT 0x0
662 #define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
664 #define MP1_C2PMSG_38__CONTENT__SHIFT 0x0
665 #define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
667 #define MP1_C2PMSG_39__CONTENT__SHIFT 0x0
668 #define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
670 #define MP1_C2PMSG_40__CONTENT__SHIFT 0x0
671 #define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
673 #define MP1_C2PMSG_41__CONTENT__SHIFT 0x0
674 #define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
676 #define MP1_C2PMSG_42__CONTENT__SHIFT 0x0
677 #define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
679 #define MP1_C2PMSG_43__CONTENT__SHIFT 0x0
680 #define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
682 #define MP1_C2PMSG_44__CONTENT__SHIFT 0x0
683 #define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
685 #define MP1_C2PMSG_45__CONTENT__SHIFT 0x0
686 #define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
688 #define MP1_C2PMSG_46__CONTENT__SHIFT 0x0
689 #define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
691 #define MP1_C2PMSG_47__CONTENT__SHIFT 0x0
692 #define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
694 #define MP1_C2PMSG_48__CONTENT__SHIFT 0x0
695 #define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
697 #define MP1_C2PMSG_49__CONTENT__SHIFT 0x0
698 #define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
700 #define MP1_C2PMSG_50__CONTENT__SHIFT 0x0
701 #define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
703 #define MP1_C2PMSG_51__CONTENT__SHIFT 0x0
704 #define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
706 #define MP1_C2PMSG_52__CONTENT__SHIFT 0x0
707 #define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
709 #define MP1_C2PMSG_53__CONTENT__SHIFT 0x0
710 #define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
712 #define MP1_C2PMSG_54__CONTENT__SHIFT 0x0
713 #define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
715 #define MP1_C2PMSG_55__CONTENT__SHIFT 0x0
716 #define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
718 #define MP1_C2PMSG_56__CONTENT__SHIFT 0x0
719 #define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
721 #define MP1_C2PMSG_57__CONTENT__SHIFT 0x0
722 #define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
724 #define MP1_C2PMSG_58__CONTENT__SHIFT 0x0
725 #define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
727 #define MP1_C2PMSG_59__CONTENT__SHIFT 0x0
728 #define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
730 #define MP1_C2PMSG_60__CONTENT__SHIFT 0x0
731 #define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
733 #define MP1_C2PMSG_61__CONTENT__SHIFT 0x0
734 #define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
736 #define MP1_C2PMSG_62__CONTENT__SHIFT 0x0
737 #define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
739 #define MP1_C2PMSG_63__CONTENT__SHIFT 0x0
740 #define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
742 #define MP1_C2PMSG_64__CONTENT__SHIFT 0x0
743 #define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
745 #define MP1_C2PMSG_65__CONTENT__SHIFT 0x0
746 #define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
748 #define MP1_C2PMSG_66__CONTENT__SHIFT 0x0
749 #define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
751 #define MP1_C2PMSG_67__CONTENT__SHIFT 0x0
752 #define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
754 #define MP1_C2PMSG_68__CONTENT__SHIFT 0x0
755 #define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
757 #define MP1_C2PMSG_69__CONTENT__SHIFT 0x0
758 #define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
760 #define MP1_C2PMSG_70__CONTENT__SHIFT 0x0
761 #define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
763 #define MP1_C2PMSG_71__CONTENT__SHIFT 0x0
764 #define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
766 #define MP1_C2PMSG_72__CONTENT__SHIFT 0x0
767 #define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
769 #define MP1_C2PMSG_73__CONTENT__SHIFT 0x0
770 #define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
772 #define MP1_C2PMSG_74__CONTENT__SHIFT 0x0
773 #define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
775 #define MP1_C2PMSG_75__CONTENT__SHIFT 0x0
776 #define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
778 #define MP1_C2PMSG_76__CONTENT__SHIFT 0x0
779 #define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
781 #define MP1_C2PMSG_77__CONTENT__SHIFT 0x0
782 #define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
784 #define MP1_C2PMSG_78__CONTENT__SHIFT 0x0
785 #define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
787 #define MP1_C2PMSG_79__CONTENT__SHIFT 0x0
788 #define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
790 #define MP1_C2PMSG_80__CONTENT__SHIFT 0x0
791 #define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
793 #define MP1_C2PMSG_81__CONTENT__SHIFT 0x0
794 #define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
796 #define MP1_C2PMSG_82__CONTENT__SHIFT 0x0
797 #define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
799 #define MP1_C2PMSG_83__CONTENT__SHIFT 0x0
800 #define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
802 #define MP1_C2PMSG_84__CONTENT__SHIFT 0x0
803 #define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
805 #define MP1_C2PMSG_85__CONTENT__SHIFT 0x0
806 #define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
808 #define MP1_C2PMSG_86__CONTENT__SHIFT 0x0
809 #define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
811 #define MP1_C2PMSG_87__CONTENT__SHIFT 0x0
812 #define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
814 #define MP1_C2PMSG_88__CONTENT__SHIFT 0x0
815 #define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
817 #define MP1_C2PMSG_89__CONTENT__SHIFT 0x0
818 #define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
820 #define MP1_C2PMSG_90__CONTENT__SHIFT 0x0
821 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
823 #define MP1_C2PMSG_91__CONTENT__SHIFT 0x0
824 #define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
826 #define MP1_C2PMSG_92__CONTENT__SHIFT 0x0
827 #define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
829 #define MP1_C2PMSG_93__CONTENT__SHIFT 0x0
830 #define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
832 #define MP1_C2PMSG_94__CONTENT__SHIFT 0x0
833 #define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
835 #define MP1_C2PMSG_95__CONTENT__SHIFT 0x0
836 #define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
838 #define MP1_C2PMSG_96__CONTENT__SHIFT 0x0
839 #define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
841 #define MP1_C2PMSG_97__CONTENT__SHIFT 0x0
842 #define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
844 #define MP1_C2PMSG_98__CONTENT__SHIFT 0x0
845 #define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
847 #define MP1_C2PMSG_99__CONTENT__SHIFT 0x0
848 #define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
850 #define MP1_C2PMSG_100__CONTENT__SHIFT 0x0
851 #define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
853 #define MP1_C2PMSG_101__CONTENT__SHIFT 0x0
854 #define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
856 #define MP1_C2PMSG_102__CONTENT__SHIFT 0x0
857 #define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
859 #define MP1_C2PMSG_103__CONTENT__SHIFT 0x0
860 #define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
862 #define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
863 #define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
864 #define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
865 #define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
867 #define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
868 #define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10
869 #define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
870 #define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
872 #define MP1_IH_SW_INT__ID__SHIFT 0x0
873 #define MP1_IH_SW_INT__VALID__SHIFT 0x8
874 #define MP1_IH_SW_INT__ID_MASK 0x000000FFL
875 #define MP1_IH_SW_INT__VALID_MASK 0x00000100L
877 #define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
878 #define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
879 #define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
880 #define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
882 #define MP1_FPS_CNT__COUNT__SHIFT 0x0
883 #define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL