2 * Copyright 2012-15 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 #include "dm_services.h"
28 #include "include/logger_interface.h"
30 #include "irq_service_dce80.h"
31 #include "../dce110/irq_service_dce110.h"
33 #include "dce/dce_8_0_d.h"
34 #include "dce/dce_8_0_sh_mask.h"
36 #include "ivsrcid/ivsrcid_vislands30.h"
41 struct irq_service *irq_service,
42 const struct irq_source_info *info)
44 uint32_t addr = info->status_reg;
45 uint32_t value = dm_read_reg(irq_service->ctx, addr);
46 uint32_t current_status =
50 DC_HPD1_SENSE_DELAYED);
52 dal_irq_service_ack_generic(irq_service, info);
54 value = dm_read_reg(irq_service->ctx, info->enable_reg);
58 current_status ? 0 : 1,
60 DC_HPD1_INT_POLARITY);
62 dm_write_reg(irq_service->ctx, info->enable_reg, value);
67 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
72 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
77 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
82 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
83 .set = dce110_vblank_set,
88 #define hpd_int_entry(reg_num)\
89 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
90 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
91 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
93 DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
94 ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
96 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
97 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
98 .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
99 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
100 .funcs = &hpd_irq_info_funcs\
103 #define hpd_rx_int_entry(reg_num)\
104 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
105 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
106 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
108 DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
109 ~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
110 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
111 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
112 .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
113 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
114 .funcs = &hpd_rx_irq_info_funcs\
117 #define pflip_int_entry(reg_num)\
118 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
119 .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
121 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
123 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
124 ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
125 .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
126 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
127 .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
128 .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
129 .funcs = &pflip_irq_info_funcs\
132 #define vupdate_int_entry(reg_num)\
133 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
134 .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
136 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
138 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
139 ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
140 .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
142 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
144 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
145 .funcs = &vblank_irq_info_funcs\
148 #define vblank_int_entry(reg_num)\
149 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
150 .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
152 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
154 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
155 ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
156 .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
158 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
160 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
161 .funcs = &vblank_irq_info_funcs,\
162 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
165 #define dummy_irq_entry() \
167 .funcs = &dummy_irq_info_funcs\
170 #define i2c_int_entry(reg_num) \
171 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
173 #define dp_sink_int_entry(reg_num) \
174 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
176 #define gpio_pad_int_entry(reg_num) \
177 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
179 #define dc_underflow_int_entry(reg_num) \
180 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
183 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
184 .set = dal_irq_service_dummy_set,
185 .ack = dal_irq_service_dummy_ack
188 static const struct irq_source_info
189 irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
190 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
209 dp_sink_int_entry(1),
210 dp_sink_int_entry(2),
211 dp_sink_int_entry(3),
212 dp_sink_int_entry(4),
213 dp_sink_int_entry(5),
214 dp_sink_int_entry(6),
215 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
222 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
223 gpio_pad_int_entry(0),
224 gpio_pad_int_entry(1),
225 gpio_pad_int_entry(2),
226 gpio_pad_int_entry(3),
227 gpio_pad_int_entry(4),
228 gpio_pad_int_entry(5),
229 gpio_pad_int_entry(6),
230 gpio_pad_int_entry(7),
231 gpio_pad_int_entry(8),
232 gpio_pad_int_entry(9),
233 gpio_pad_int_entry(10),
234 gpio_pad_int_entry(11),
235 gpio_pad_int_entry(12),
236 gpio_pad_int_entry(13),
237 gpio_pad_int_entry(14),
238 gpio_pad_int_entry(15),
239 gpio_pad_int_entry(16),
240 gpio_pad_int_entry(17),
241 gpio_pad_int_entry(18),
242 gpio_pad_int_entry(19),
243 gpio_pad_int_entry(20),
244 gpio_pad_int_entry(21),
245 gpio_pad_int_entry(22),
246 gpio_pad_int_entry(23),
247 gpio_pad_int_entry(24),
248 gpio_pad_int_entry(25),
249 gpio_pad_int_entry(26),
250 gpio_pad_int_entry(27),
251 gpio_pad_int_entry(28),
252 gpio_pad_int_entry(29),
253 gpio_pad_int_entry(30),
254 dc_underflow_int_entry(1),
255 dc_underflow_int_entry(2),
256 dc_underflow_int_entry(3),
257 dc_underflow_int_entry(4),
258 dc_underflow_int_entry(5),
259 dc_underflow_int_entry(6),
260 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
261 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
262 vupdate_int_entry(0),
263 vupdate_int_entry(1),
264 vupdate_int_entry(2),
265 vupdate_int_entry(3),
266 vupdate_int_entry(4),
267 vupdate_int_entry(5),
276 static const struct irq_service_funcs irq_service_funcs_dce80 = {
277 .to_dal_irq_source = to_dal_irq_source_dce110
280 static void construct(
281 struct irq_service *irq_service,
282 struct irq_service_init_data *init_data)
284 dal_irq_service_construct(irq_service, init_data);
286 irq_service->info = irq_source_info_dce80;
287 irq_service->funcs = &irq_service_funcs_dce80;
290 struct irq_service *dal_irq_service_dce80_create(
291 struct irq_service_init_data *init_data)
293 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
299 construct(irq_service, init_data);