2 * Copyright 2012-16 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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27 #ifndef _DCE_CLK_MGR_H_
28 #define _DCE_CLK_MGR_H_
33 #define MEMORY_TYPE_MULTIPLIER_CZ 4
35 #define CLK_COMMON_REG_LIST_DCE_BASE() \
36 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
37 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
39 #define CLK_COMMON_REG_LIST_DCN_BASE() \
40 SR(DENTIST_DISPCLK_CNTL)
42 #define CLK_SF(reg_name, field_name, post_fix)\
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
46 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
47 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
49 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
50 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
51 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
53 #define CLK_REG_FIELD_LIST(type) \
54 type DPREFCLK_SRC_SEL; \
55 type DENTIST_DPREFCLK_WDIVIDER; \
56 type DENTIST_DISPCLK_WDIVIDER; \
57 type DENTIST_DISPCLK_CHG_DONE;
59 struct clk_mgr_shift {
60 CLK_REG_FIELD_LIST(uint8_t)
64 CLK_REG_FIELD_LIST(uint32_t)
67 struct clk_mgr_registers {
68 uint32_t DPREFCLK_CNTL;
69 uint32_t DENTIST_DISPCLK_CNTL;
72 struct state_dependent_clocks {
79 const struct clk_mgr_registers *regs;
80 const struct clk_mgr_shift *clk_mgr_shift;
81 const struct clk_mgr_mask *clk_mgr_mask;
85 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
87 int dentist_vco_freq_khz;
89 /* Cache the status of DFS-bypass feature*/
90 bool dfs_bypass_enabled;
91 /* True if the DFS-bypass feature is enabled and active. */
92 bool dfs_bypass_active;
93 /* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
94 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
95 int dfs_bypass_disp_clk;
97 /* Flag for Enabled SS on DPREFCLK */
99 /* DPREFCLK SS percentage (if down-spread enabled) */
100 int dprefclk_ss_percentage;
101 /* DPREFCLK SS percentage Divider (100 or 1000) */
102 int dprefclk_ss_divider;
105 enum dm_pp_clocks_state max_clks_state;
106 enum dm_pp_clocks_state cur_min_clks_state;
109 /* Starting DID for each range */
110 enum dentist_base_divider_id {
111 DENTIST_BASE_DID_1 = 0x08,
112 DENTIST_BASE_DID_2 = 0x40,
113 DENTIST_BASE_DID_3 = 0x60,
114 DENTIST_BASE_DID_4 = 0x7e,
115 DENTIST_MAX_DID = 0x7f
118 /* Starting point and step size for each divider range.*/
119 enum dentist_divider_range {
120 DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */
121 DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */
122 DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */
123 DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
124 DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
125 DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
126 DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
127 DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */
128 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
131 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
133 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
136 void dce_clock_read_ss_info(struct dce_clk_mgr *dccg_dce);
138 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
140 void dce110_fill_display_configs(
141 const struct dc_state *context,
142 struct dm_pp_display_configuration *pp_display_cfg);
144 int dce112_set_clock(struct clk_mgr *dccg, int requested_clk_khz);
146 struct clk_mgr *dce_clk_mgr_create(
147 struct dc_context *ctx,
148 const struct clk_mgr_registers *regs,
149 const struct clk_mgr_shift *clk_shift,
150 const struct clk_mgr_mask *clk_mask);
152 struct clk_mgr *dce110_clk_mgr_create(
153 struct dc_context *ctx,
154 const struct clk_mgr_registers *regs,
155 const struct clk_mgr_shift *clk_shift,
156 const struct clk_mgr_mask *clk_mask);
158 struct clk_mgr *dce112_clk_mgr_create(
159 struct dc_context *ctx,
160 const struct clk_mgr_registers *regs,
161 const struct clk_mgr_shift *clk_shift,
162 const struct clk_mgr_mask *clk_mask);
164 struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx);
166 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
168 int dentist_get_divider_from_did(int did);
170 #endif /* _DCE_CLK_MGR_H_ */