2 * Copyright 2016 Advanced Micro Devices, Inc.
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
32 LANE_COUNT_UNKNOWN = 0,
37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
40 /* This is actually a reference clock (27MHz) multiplier
41 * 162MBps bandwidth for 1.62GHz like rate,
42 * 270MBps for 2.70GHz,
43 * 324MBps for 3.24Ghz,
48 LINK_RATE_UNKNOWN = 0,
49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane
54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane
56 LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane
60 LINK_SPREAD_DISABLED = 0x00,
61 /* 0.5 % downspread 30 kHz */
62 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
63 /* 0.5 % downspread 33 kHz */
64 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
67 enum dc_voltage_swing {
68 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */
72 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
75 enum dc_pre_emphasis {
76 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */
80 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
82 /* Post Cursor 2 is optional for transmitter
83 * and it applies only to the main link operating at HBR2
85 enum dc_post_cursor2 {
86 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */
90 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
93 enum dc_dp_training_pattern {
94 DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
95 DP_TRAINING_PATTERN_SEQUENCE_2,
96 DP_TRAINING_PATTERN_SEQUENCE_3,
97 DP_TRAINING_PATTERN_SEQUENCE_4,
100 struct dc_link_settings {
101 enum dc_lane_count lane_count;
102 enum dc_link_rate link_rate;
103 enum dc_link_spread link_spread;
104 bool use_link_rate_set;
105 uint8_t link_rate_set;
108 struct dc_lane_settings {
109 enum dc_voltage_swing VOLTAGE_SWING;
110 enum dc_pre_emphasis PRE_EMPHASIS;
111 enum dc_post_cursor2 POST_CURSOR2;
114 struct dc_link_training_settings {
115 struct dc_link_settings link;
116 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
119 struct dc_link_training_overrides {
120 enum dc_voltage_swing *voltage_swing;
121 enum dc_pre_emphasis *pre_emphasis;
122 enum dc_post_cursor2 *post_cursor2;
124 uint16_t *cr_pattern_time;
125 uint16_t *eq_pattern_time;
126 enum dc_dp_training_pattern *pattern_for_eq;
128 enum dc_link_spread *downspread;
129 bool *alternate_scrambler_reset;
130 bool *enhanced_framing;
132 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
145 union max_lane_count {
147 uint8_t MAX_LANE_COUNT:5;
148 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
149 uint8_t TPS3_SUPPORTED:1;
150 uint8_t ENHANCED_FRAME_CAP:1;
155 union max_down_spread {
157 uint8_t MAX_DOWN_SPREAD:1;
159 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
160 uint8_t TPS4_SUPPORTED:1;
173 union lane_count_set {
175 uint8_t LANE_COUNT_SET:5;
176 uint8_t POST_LT_ADJ_REQ_GRANTED:1;
178 uint8_t ENHANCED_FRAMING:1;
186 uint8_t CHANNEL_EQ_DONE_0:1;
187 uint8_t SYMBOL_LOCKED_0:1;
190 uint8_t CHANNEL_EQ_DONE_1:1;
191 uint8_t SYMBOL_LOCKED_1:1;
192 uint8_t RESERVED_1:1;
197 union device_service_irq {
199 uint8_t REMOTE_CONTROL_CMD_PENDING:1;
200 uint8_t AUTOMATED_TEST:1;
203 uint8_t DOWN_REP_MSG_RDY:1;
204 uint8_t UP_REQ_MSG_RDY:1;
205 uint8_t SINK_SPECIFIC:1;
213 uint8_t SINK_COUNT:6;
220 union lane_align_status_updated {
222 uint8_t INTERLANE_ALIGN_DONE:1;
223 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
225 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
226 uint8_t LINK_STATUS_UPDATED:1;
233 uint8_t VOLTAGE_SWING_LANE:2;
234 uint8_t PRE_EMPHASIS_LANE:2;
240 union dpcd_training_pattern {
242 uint8_t TRAINING_PATTERN_SET:4;
243 uint8_t RECOVERED_CLOCK_OUT_EN:1;
244 uint8_t SCRAMBLING_DISABLE:1;
245 uint8_t SYMBOL_ERROR_COUNT_SEL:2;
248 uint8_t TRAINING_PATTERN_SET:2;
249 uint8_t LINK_QUAL_PATTERN_SET:2;
255 /* Training Lane is used to configure downstream DP device's voltage swing
256 and pre-emphasis levels*/
257 /* The DPCD addresses are from 0x103 to 0x106*/
258 union dpcd_training_lane {
260 uint8_t VOLTAGE_SWING_SET:2;
261 uint8_t MAX_SWING_REACHED:1;
262 uint8_t PRE_EMPHASIS_SET:2;
263 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
269 /* TMDS-converter related */
270 union dwnstream_port_caps_byte0 {
272 uint8_t DWN_STRM_PORTX_TYPE:3;
273 uint8_t DWN_STRM_PORTX_HPD:1;
279 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
280 enum dpcd_downstream_port_detailed_type {
281 DOWN_STREAM_DETAILED_DP = 0,
282 DOWN_STREAM_DETAILED_VGA,
283 DOWN_STREAM_DETAILED_DVI,
284 DOWN_STREAM_DETAILED_HDMI,
285 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
286 DOWN_STREAM_DETAILED_DP_PLUS_PLUS
289 union dwnstream_port_caps_byte2 {
291 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
297 union dp_downstream_port_present {
300 uint8_t PORT_PRESENT:1;
302 uint8_t FMT_CONVERSION:1;
303 uint8_t DETAILED_CAPS:1;
308 union dwnstream_port_caps_byte3_dvi {
312 uint8_t HIGH_COLOR_DEPTH:1;
318 union dwnstream_port_caps_byte3_hdmi {
320 uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
321 uint8_t YCrCr422_PASS_THROUGH:1;
322 uint8_t YCrCr420_PASS_THROUGH:1;
323 uint8_t YCrCr422_CONVERSION:1;
324 uint8_t YCrCr420_CONVERSION:1;
330 /*4-byte structure for detailed capabilities of a down-stream port
331 (DP-to-TMDS converter).*/
332 union dwnstream_portxcaps {
334 union dwnstream_port_caps_byte0 byte0;
335 unsigned char max_TMDS_clock; //byte1
336 union dwnstream_port_caps_byte2 byte2;
339 union dwnstream_port_caps_byte3_dvi byteDVI;
340 union dwnstream_port_caps_byte3_hdmi byteHDMI;
344 unsigned char raw[4];
347 union downstream_port {
349 unsigned char present:1;
350 unsigned char type:2;
351 unsigned char format_conv:1;
352 unsigned char detailed_caps:1;
353 unsigned char reserved:3;
361 uint8_t RX_PORT0_STATUS:1;
362 uint8_t RX_PORT1_STATUS:1;
368 /*6-byte structure corresponding to 6 registers (200h-205h)
369 read during handling of HPD-IRQ*/
372 union sink_count sink_cnt;/* 200h */
373 union device_service_irq device_service_irq;/* 201h */
374 union lane_status lane01_status;/* 202h */
375 union lane_status lane23_status;/* 203h */
376 union lane_align_status_updated lane_status_updated;/* 204h */
377 union sink_status sink_status;
382 union down_stream_port_count {
384 uint8_t DOWN_STR_PORT_COUNT:4;
385 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
386 /*Bit 6 = MSA_TIMING_PAR_IGNORED
387 0 = Sink device requires the MSA timing parameters
388 1 = Sink device is capable of rendering incoming video
389 stream without MSA timing parameters*/
390 uint8_t IGNORE_MSA_TIMING_PARAM:1;
391 /*Bit 7 = OUI Support
392 0 = OUI not supported
394 (OUI and Device Identification mandatory for DP 1.2)*/
395 uint8_t OUI_SUPPORT:1;
400 union down_spread_ctrl {
402 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
403 /* Bits 4 = SPREAD_AMP. Spreading amplitude
404 0 = Main link signal is not downspread
405 1 = Main link signal is downspread <= 0.5%
406 with frequency in the range of 30kHz ~ 33kHz*/
407 uint8_t SPREAD_AMP:1;
408 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
409 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
410 0 = Source device will send valid data for the MSA Timing Params
411 1 = Source device may send invalid data for these MSA Timing Params*/
412 uint8_t IGNORE_MSA_TIMING_PARAM:1;
417 union dpcd_edp_config {
419 uint8_t PANEL_MODE_EDP:1;
420 uint8_t FRAMING_CHANGE_ENABLE:1;
422 uint8_t PANEL_SELF_TEST_ENABLE:1;
427 struct dp_device_vendor_id {
428 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
429 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
432 struct dp_sink_hw_fw_revision {
434 uint8_t ieee_fw_rev[2];
437 /*DPCD register of DP receiver capability field bits-*/
438 union edp_configuration_cap {
440 uint8_t ALT_SCRAMBLER_RESET:1;
441 uint8_t FRAMING_CHANGE:1;
443 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
451 uint8_t GTC_CAP:1; // bit 0: DP 1.3+
452 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4
453 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+
454 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+
455 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4
456 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
457 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4
458 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4
463 union training_aux_rd_interval {
465 uint8_t TRAINIG_AUX_RD_INTERVAL:7;
466 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
471 /* Automated test structures */
474 uint8_t LINK_TRAINING :1;
475 uint8_t LINK_TEST_PATTRN :1;
476 uint8_t EDID_READ :1;
477 uint8_t PHY_TEST_PATTERN :1;
478 uint8_t AUDIO_TEST_PATTERN :1;
480 uint8_t TEST_STEREO_3D :1;
485 union test_response {
489 uint8_t EDID_CHECKSUM_WRITE:1;
495 union phy_test_pattern {
497 /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
498 * and 3 bits for DP1.2.
501 /* BY speci, bit7:2 is 0 for DP1.1. */
507 /* States of Compliance Test Specification (CTS DP1.2). */
508 union compliance_test_state {
510 unsigned char STEREO_3D_RUNNING : 1;
511 unsigned char RESERVED : 7;
516 union link_test_pattern {
518 /* dpcd_link_test_patterns */
519 unsigned char PATTERN :2;
520 unsigned char RESERVED:6;
526 struct dpcd_test_misc_bits {
527 unsigned char SYNC_CLOCK :1;
528 /* dpcd_test_color_format */
529 unsigned char CLR_FORMAT :2;
530 /* dpcd_test_dyn_range */
531 unsigned char DYN_RANGE :1;
532 unsigned char YCBCR :1;
533 /* dpcd_test_bit_depth */
534 unsigned char BPC :3;
539 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
540 /* FEC capability DPCD register field bits-*/
541 union dpcd_fec_capability {
543 uint8_t FEC_CAPABLE:1;
544 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
545 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
546 uint8_t BIT_ERROR_COUNT_CAPABLE:1;
552 /* DSC capability DPCD register field bits-*/
553 struct dpcd_dsc_support {
554 uint8_t DSC_SUPPORT :1;
555 uint8_t DSC_PASSTHROUGH_SUPPORT :1;
559 struct dpcd_dsc_algorithm_revision {
560 uint8_t DSC_VERSION_MAJOR :4;
561 uint8_t DSC_VERSION_MINOR :4;
564 struct dpcd_dsc_rc_buffer_block_size {
565 uint8_t RC_BLOCK_BUFFER_SIZE :2;
569 struct dpcd_dsc_slice_capability1 {
570 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1;
571 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1;
573 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1;
574 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1;
575 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1;
576 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1;
577 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1;
580 struct dpcd_dsc_line_buffer_bit_depth {
581 uint8_t LINE_BUFFER_BIT_DEPTH :4;
585 struct dpcd_dsc_block_prediction_support {
586 uint8_t BLOCK_PREDICTION_SUPPORT:1;
590 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
591 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7;
592 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7;
596 struct dpcd_dsc_decoder_color_format_capabilities {
597 uint8_t RGB_SUPPORT :1;
598 uint8_t Y_CB_CR_444_SUPPORT :1;
599 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1;
600 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1;
601 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1;
605 struct dpcd_dsc_decoder_color_depth_capabilities {
606 uint8_t RESERVED0 :1;
607 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1;
608 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1;
609 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1;
610 uint8_t RESERVED1 :4;
613 struct dpcd_peak_dsc_throughput_dsc_sink {
614 uint8_t THROUGHPUT_MODE_0:4;
615 uint8_t THROUGHPUT_MODE_1:4;
618 struct dpcd_dsc_slice_capabilities_2 {
619 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1;
620 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1;
621 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1;
625 struct dpcd_bits_per_pixel_increment{
626 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3;
629 union dpcd_dsc_basic_capabilities {
631 struct dpcd_dsc_support dsc_support;
632 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
633 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
634 uint8_t dsc_rc_buffer_size;
635 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
636 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
637 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
638 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
639 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
640 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
641 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
642 uint8_t dsc_maximum_slice_width;
643 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
645 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
650 union dpcd_dsc_ext_capabilities {
652 uint8_t BRANCH_OVERALL_THROUGHPUT_0;
653 uint8_t BRANCH_OVERALL_THROUGHPUT_1;
654 uint8_t BRANCH_MAX_LINE_WIDTH;
659 struct dpcd_dsc_capabilities {
660 union dpcd_dsc_basic_capabilities dsc_basic_caps;
661 union dpcd_dsc_ext_capabilities dsc_ext_caps;
664 #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
666 #endif /* DC_DP_TYPES_H */