2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
30 #include "atomfirmware.h"
32 #include "include/bios_parser_interface.h"
34 #include "command_table2.h"
35 #include "command_table_helper2.h"
36 #include "bios_parser_helper.h"
37 #include "bios_parser_types_internal2.h"
44 #define GET_INDEX_INTO_MASTER_TABLE(MasterOrData, FieldName)\
46 struct atom_master_list_of_##MasterOrData##_functions_v2_1 *)0)\
47 ->FieldName)-(char *)0)/sizeof(uint16_t))
49 #define EXEC_BIOS_CMD_TABLE(fname, params)\
50 (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
51 GET_INDEX_INTO_MASTER_TABLE(command, fname), \
52 (uint32_t *)¶ms) == 0)
54 #define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\
55 amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
56 GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev)
58 #define BIOS_CMD_TABLE_PARA_REVISION(fname)\
59 bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
60 GET_INDEX_INTO_MASTER_TABLE(command, fname))
64 static uint32_t bios_cmd_table_para_revision(void *dev,
67 struct amdgpu_device *adev = dev;
70 if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
78 /******************************************************************************
79 ******************************************************************************
81 ** D I G E N C O D E R C O N T R O L
83 ******************************************************************************
84 *****************************************************************************/
86 static enum bp_result encoder_control_digx_v1_5(
87 struct bios_parser *bp,
88 struct bp_encoder_control *cntl);
90 static void init_dig_encoder_control(struct bios_parser *bp)
93 BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol);
97 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5;
100 dm_output_to_console("Don't have dig_encoder_control for v%d\n", version);
101 bp->cmd_tbl.dig_encoder_control = NULL;
106 static enum bp_result encoder_control_digx_v1_5(
107 struct bios_parser *bp,
108 struct bp_encoder_control *cntl)
110 enum bp_result result = BP_RESULT_FAILURE;
111 struct dig_encoder_stream_setup_parameters_v1_5 params = {0};
113 params.digid = (uint8_t)(cntl->engine_id);
114 params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action);
116 params.pclk_10khz = cntl->pixel_clock / 10;
118 (uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
120 cntl->enable_dp_audio));
121 params.lanenum = (uint8_t)(cntl->lanes_number);
123 switch (cntl->color_depth) {
124 case COLOR_DEPTH_888:
125 params.bitpercolor = PANEL_8BIT_PER_COLOR;
127 case COLOR_DEPTH_101010:
128 params.bitpercolor = PANEL_10BIT_PER_COLOR;
130 case COLOR_DEPTH_121212:
131 params.bitpercolor = PANEL_12BIT_PER_COLOR;
133 case COLOR_DEPTH_161616:
134 params.bitpercolor = PANEL_16BIT_PER_COLOR;
140 if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
141 switch (cntl->color_depth) {
142 case COLOR_DEPTH_101010:
144 (params.pclk_10khz * 30) / 24;
146 case COLOR_DEPTH_121212:
148 (params.pclk_10khz * 36) / 24;
150 case COLOR_DEPTH_161616:
152 (params.pclk_10khz * 48) / 24;
158 if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
159 result = BP_RESULT_OK;
164 /*****************************************************************************
165 ******************************************************************************
167 ** TRANSMITTER CONTROL
169 ******************************************************************************
170 *****************************************************************************/
172 static enum bp_result transmitter_control_v1_6(
173 struct bios_parser *bp,
174 struct bp_transmitter_control *cntl);
176 static void init_transmitter_control(struct bios_parser *bp)
181 if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) == false)
185 bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
188 dm_output_to_console("Don't have transmitter_control for v%d\n", crev);
189 bp->cmd_tbl.transmitter_control = NULL;
194 static enum bp_result transmitter_control_v1_6(
195 struct bios_parser *bp,
196 struct bp_transmitter_control *cntl)
198 enum bp_result result = BP_RESULT_FAILURE;
199 const struct command_table_helper *cmd = bp->cmd_helper;
200 struct dig_transmitter_control_ps_allocation_v1_6 ps = { { 0 } };
202 ps.param.phyid = cmd->phy_id_to_atom(cntl->transmitter);
203 ps.param.action = (uint8_t)cntl->action;
205 if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
206 ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;
208 ps.param.mode_laneset.digmode =
209 cmd->signal_type_to_atom_dig_mode(cntl->signal);
211 ps.param.lanenum = (uint8_t)cntl->lanes_number;
212 ps.param.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
213 ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
214 ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id;
215 ps.param.symclk_10khz = cntl->pixel_clock/10;
218 if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
219 cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
220 cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
221 DC_LOG_BIOS("%s:ps.param.symclk_10khz = %d\n",\
222 __func__, ps.param.symclk_10khz);
226 /*color_depth not used any more, driver has deep color factor in the Phyclk*/
227 if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
228 result = BP_RESULT_OK;
232 /******************************************************************************
233 ******************************************************************************
237 ******************************************************************************
238 *****************************************************************************/
240 static enum bp_result set_pixel_clock_v7(
241 struct bios_parser *bp,
242 struct bp_pixel_clock_parameters *bp_params);
244 static void init_set_pixel_clock(struct bios_parser *bp)
246 switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) {
248 bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
251 dm_output_to_console("Don't have set_pixel_clock for v%d\n",
252 BIOS_CMD_TABLE_PARA_REVISION(setpixelclock));
253 bp->cmd_tbl.set_pixel_clock = NULL;
260 static enum bp_result set_pixel_clock_v7(
261 struct bios_parser *bp,
262 struct bp_pixel_clock_parameters *bp_params)
264 enum bp_result result = BP_RESULT_FAILURE;
265 struct set_pixel_clock_parameter_v1_7 clk;
266 uint8_t controller_id;
269 memset(&clk, 0, sizeof(clk));
271 if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
272 && bp->cmd_helper->controller_id_to_atom(bp_params->
273 controller_id, &controller_id)) {
274 /* Note: VBIOS still wants to use ucCRTC name which is now
276 *typedef struct _CRTC_PIXEL_CLOCK_FREQ
278 * target the pixel clock to drive the CRTC timing.
279 * ULONG ulPixelClock:24;
280 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
282 * ATOM_CRTC1~6, indicate the CRTC controller to
284 * drive the pixel clock. not used for DCPLL case.
285 *}CRTC_PIXEL_CLOCK_FREQ;
288 * pixel clock and CRTC id frequency
289 * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
290 * ULONG ulDispEngClkFreq; dispclk frequency
293 clk.crtc_id = controller_id;
294 clk.pll_id = (uint8_t) pll_id;
296 bp->cmd_helper->encoder_id_to_atom(
297 dal_graphics_object_id_get_encoder_id(
298 bp_params->encoder_object_id));
300 clk.encoder_mode = (uint8_t) bp->
301 cmd_helper->encoder_mode_bp_to_atom(
302 bp_params->signal_type, false);
304 clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock_100hz);
306 clk.deep_color_ratio =
307 (uint8_t) bp->cmd_helper->
308 transmitter_color_depth_to_atom(
309 bp_params->color_depth);
311 DC_LOG_BIOS("%s:program display clock = %d, tg = %d, pll = %d, "\
312 "colorDepth = %d\n", __func__,
313 bp_params->target_pixel_clock_100hz, (int)controller_id,
314 pll_id, bp_params->color_depth);
316 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
317 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
319 if (bp_params->flags.PROGRAM_PHY_PLL_ONLY)
320 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;
322 if (bp_params->flags.SUPPORT_YUV_420)
323 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;
325 if (bp_params->flags.SET_XTALIN_REF_SRC)
326 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;
328 if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC)
329 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;
331 if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
332 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
334 if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
335 result = BP_RESULT_OK;
340 /******************************************************************************
341 ******************************************************************************
345 ******************************************************************************
346 *****************************************************************************/
348 static enum bp_result set_crtc_using_dtd_timing_v3(
349 struct bios_parser *bp,
350 struct bp_hw_crtc_timing_parameters *bp_params);
352 static void init_set_crtc_timing(struct bios_parser *bp)
354 uint32_t dtd_version =
355 BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);
357 switch (dtd_version) {
359 bp->cmd_tbl.set_crtc_timing =
360 set_crtc_using_dtd_timing_v3;
363 dm_output_to_console("Don't have set_crtc_timing for v%d\n", dtd_version);
364 bp->cmd_tbl.set_crtc_timing = NULL;
369 static enum bp_result set_crtc_using_dtd_timing_v3(
370 struct bios_parser *bp,
371 struct bp_hw_crtc_timing_parameters *bp_params)
373 enum bp_result result = BP_RESULT_FAILURE;
374 struct set_crtc_using_dtd_timing_parameters params = {0};
375 uint8_t atom_controller_id;
377 if (bp->cmd_helper->controller_id_to_atom(
378 bp_params->controller_id, &atom_controller_id))
379 params.crtc_id = atom_controller_id;
381 /* bios usH_Size wants h addressable size */
382 params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable);
383 /* bios usH_Blanking_Time wants borders included in blanking */
384 params.h_blanking_time =
385 cpu_to_le16((uint16_t)(bp_params->h_total -
386 bp_params->h_addressable));
387 /* bios usV_Size wants v addressable size */
388 params.v_size = cpu_to_le16((uint16_t)bp_params->v_addressable);
389 /* bios usV_Blanking_Time wants borders included in blanking */
390 params.v_blanking_time =
391 cpu_to_le16((uint16_t)(bp_params->v_total -
392 bp_params->v_addressable));
393 /* bios usHSyncOffset is the offset from the end of h addressable,
394 * our horizontalSyncStart is the offset from the beginning
397 params.h_syncoffset =
398 cpu_to_le16((uint16_t)(bp_params->h_sync_start -
399 bp_params->h_addressable));
400 params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
401 /* bios usHSyncOffset is the offset from the end of v addressable,
402 * our verticalSyncStart is the offset from the beginning of
405 params.v_syncoffset =
406 cpu_to_le16((uint16_t)(bp_params->v_sync_start -
407 bp_params->v_addressable));
408 params.v_syncwidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
410 /* we assume that overscan from original timing does not get bigger
412 * we will program all the borders in the Set CRTC Overscan call below
415 if (bp_params->flags.HSYNC_POSITIVE_POLARITY == 0)
416 params.modemiscinfo =
417 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
418 ATOM_HSYNC_POLARITY);
420 if (bp_params->flags.VSYNC_POSITIVE_POLARITY == 0)
421 params.modemiscinfo =
422 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
423 ATOM_VSYNC_POLARITY);
425 if (bp_params->flags.INTERLACE) {
426 params.modemiscinfo =
427 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
430 /* original DAL code has this condition to apply this
432 * due to complex MV testing for possible impact
433 * if ( pACParameters->signal != SignalType_YPbPr &&
434 * pACParameters->signal != SignalType_Composite &&
435 * pACParameters->signal != SignalType_SVideo)
438 /* HW will deduct 0.5 line from 2nd feild.
439 * i.e. for 1080i, it is 2 lines for 1st field,
440 * 2.5 lines for the 2nd feild. we need input as 5
442 * but it is 4 either from Edid data (spec CEA 861)
443 * or CEA timing table.
445 params.v_syncoffset =
446 cpu_to_le16(le16_to_cpu(params.v_syncoffset) +
452 if (bp_params->flags.HORZ_COUNT_BY_TWO)
453 params.modemiscinfo =
454 cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
455 0x100); /* ATOM_DOUBLE_CLOCK_MODE */
457 if (EXEC_BIOS_CMD_TABLE(setcrtc_usingdtdtiming, params))
458 result = BP_RESULT_OK;
463 /******************************************************************************
464 ******************************************************************************
468 ******************************************************************************
469 *****************************************************************************/
471 static enum bp_result enable_crtc_v1(
472 struct bios_parser *bp,
473 enum controller_id controller_id,
476 static void init_enable_crtc(struct bios_parser *bp)
478 switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) {
480 bp->cmd_tbl.enable_crtc = enable_crtc_v1;
483 dm_output_to_console("Don't have enable_crtc for v%d\n",
484 BIOS_CMD_TABLE_PARA_REVISION(enablecrtc));
485 bp->cmd_tbl.enable_crtc = NULL;
490 static enum bp_result enable_crtc_v1(
491 struct bios_parser *bp,
492 enum controller_id controller_id,
495 bool result = BP_RESULT_FAILURE;
496 struct enable_crtc_parameters params = {0};
499 if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
502 return BP_RESULT_BADINPUT;
505 params.enable = ATOM_ENABLE;
507 params.enable = ATOM_DISABLE;
509 if (EXEC_BIOS_CMD_TABLE(enablecrtc, params))
510 result = BP_RESULT_OK;
515 /******************************************************************************
516 ******************************************************************************
520 ******************************************************************************
521 *****************************************************************************/
525 /******************************************************************************
526 ******************************************************************************
528 ** EXTERNAL ENCODER CONTROL
530 ******************************************************************************
531 *****************************************************************************/
533 static enum bp_result external_encoder_control_v3(
534 struct bios_parser *bp,
535 struct bp_external_encoder_control *cntl);
537 static void init_external_encoder_control(
538 struct bios_parser *bp)
540 switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) {
542 bp->cmd_tbl.external_encoder_control =
543 external_encoder_control_v3;
546 bp->cmd_tbl.external_encoder_control = NULL;
551 static enum bp_result external_encoder_control_v3(
552 struct bios_parser *bp,
553 struct bp_external_encoder_control *cntl)
559 /******************************************************************************
560 ******************************************************************************
562 ** ENABLE DISPLAY POWER GATING
564 ******************************************************************************
565 *****************************************************************************/
567 static enum bp_result enable_disp_power_gating_v2_1(
568 struct bios_parser *bp,
569 enum controller_id crtc_id,
570 enum bp_pipe_control_action action);
572 static void init_enable_disp_power_gating(
573 struct bios_parser *bp)
575 switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) {
577 bp->cmd_tbl.enable_disp_power_gating =
578 enable_disp_power_gating_v2_1;
581 dm_output_to_console("Don't enable_disp_power_gating enable_crtc for v%d\n",
582 BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating));
583 bp->cmd_tbl.enable_disp_power_gating = NULL;
588 static enum bp_result enable_disp_power_gating_v2_1(
589 struct bios_parser *bp,
590 enum controller_id crtc_id,
591 enum bp_pipe_control_action action)
593 enum bp_result result = BP_RESULT_FAILURE;
596 struct enable_disp_power_gating_ps_allocation ps = { { 0 } };
597 uint8_t atom_crtc_id;
599 if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id))
600 ps.param.disp_pipe_id = atom_crtc_id;
602 return BP_RESULT_BADINPUT;
605 bp->cmd_helper->disp_power_gating_action_to_atom(action);
607 if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
608 result = BP_RESULT_OK;
613 /******************************************************************************
614 *******************************************************************************
618 *******************************************************************************
619 *******************************************************************************/
621 static enum bp_result set_dce_clock_v2_1(
622 struct bios_parser *bp,
623 struct bp_set_dce_clock_parameters *bp_params);
625 static void init_set_dce_clock(struct bios_parser *bp)
627 switch (BIOS_CMD_TABLE_PARA_REVISION(setdceclock)) {
629 bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
632 dm_output_to_console("Don't have set_dce_clock for v%d\n",
633 BIOS_CMD_TABLE_PARA_REVISION(setdceclock));
634 bp->cmd_tbl.set_dce_clock = NULL;
639 static enum bp_result set_dce_clock_v2_1(
640 struct bios_parser *bp,
641 struct bp_set_dce_clock_parameters *bp_params)
643 enum bp_result result = BP_RESULT_FAILURE;
645 struct set_dce_clock_ps_allocation_v2_1 params;
646 uint32_t atom_pll_id;
647 uint32_t atom_clock_type;
648 const struct command_table_helper *cmd = bp->cmd_helper;
650 memset(¶ms, 0, sizeof(params));
652 if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
653 !cmd->dc_clock_type_to_atom(bp_params->clock_type,
655 return BP_RESULT_BADINPUT;
657 params.param.dceclksrc = atom_pll_id;
658 params.param.dceclktype = atom_clock_type;
660 if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
661 if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
662 params.param.dceclkflag |=
663 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK;
665 if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK)
666 params.param.dceclkflag |=
667 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE;
669 if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK)
670 params.param.dceclkflag |=
671 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN;
673 if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK)
674 params.param.dceclkflag |=
675 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA;
677 /* only program clock frequency if display clock is used;
678 * VBIOS will program DPREFCLK
679 * We need to convert from KHz units into 10KHz units
681 params.param.dceclk_10khz = cpu_to_le32(
682 bp_params->target_clock_frequency / 10);
683 DC_LOG_BIOS("%s:target_clock_frequency = %d"\
684 "clock_type = %d \n", __func__,\
685 bp_params->target_clock_frequency,\
686 bp_params->clock_type);
688 if (EXEC_BIOS_CMD_TABLE(setdceclock, params)) {
689 /* Convert from 10KHz units back to KHz */
690 bp_params->target_clock_frequency = le32_to_cpu(
691 params.param.dceclk_10khz) * 10;
692 result = BP_RESULT_OK;
699 /******************************************************************************
700 ******************************************************************************
702 ** GET SMU CLOCK INFO
704 ******************************************************************************
705 *****************************************************************************/
707 static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id);
709 static void init_get_smu_clock_info(struct bios_parser *bp)
711 /* TODO add switch for table vrsion */
712 bp->cmd_tbl.get_smu_clock_info = get_smu_clock_info_v3_1;
716 static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)
718 struct atom_get_smu_clock_info_parameters_v3_1 smu_input = {0};
719 struct atom_get_smu_clock_info_output_parameters_v3_1 smu_output;
721 smu_input.command = GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ;
722 smu_input.syspll_id = id;
724 /* Get Specific Clock */
725 if (EXEC_BIOS_CMD_TABLE(getsmuclockinfo, smu_input)) {
726 memmove(&smu_output, &smu_input, sizeof(
727 struct atom_get_smu_clock_info_parameters_v3_1));
728 return smu_output.atom_smu_outputclkfreq.syspllvcofreq_10khz;
734 void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
736 init_dig_encoder_control(bp);
737 init_transmitter_control(bp);
738 init_set_pixel_clock(bp);
740 init_set_crtc_timing(bp);
742 init_enable_crtc(bp);
744 init_external_encoder_control(bp);
745 init_enable_disp_power_gating(bp);
746 init_set_dce_clock(bp);
747 init_get_smu_clock_info(bp);