drivers/gpu/drm/amd/amdgpu/ta_xgmi_if.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef _TA_XGMI_IF_H
  25 #define _TA_XGMI_IF_H
  26
  27 /* Responses have bit 31 set */
  28 #define RSP_ID_MASK (1U << 31)
  29 #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
  30
  31 enum ta_command_xgmi {
  32         TA_COMMAND_XGMI__INITIALIZE                     = 0x00,
  33         TA_COMMAND_XGMI__GET_NODE_ID                    = 0x01,
  34         TA_COMMAND_XGMI__GET_HIVE_ID                    = 0x02,
  35         TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO          = 0x03,
  36         TA_COMMAND_XGMI__SET_TOPOLOGY_INFO              = 0x04
  37 };
  38
  39 /* XGMI related enumerations */
  40 /**********************************************************/;
  41 enum ta_xgmi_connected_nodes {
  42         TA_XGMI__MAX_CONNECTED_NODES                    = 64
  43 };
  44
  45 enum ta_xgmi_status {
  46         TA_XGMI_STATUS__SUCCESS                         = 0x00,
  47         TA_XGMI_STATUS__GENERIC_FAILURE                 = 0x01,
  48         TA_XGMI_STATUS__NULL_POINTER                    = 0x02,
  49         TA_XGMI_STATUS__INVALID_PARAMETER               = 0x03,
  50         TA_XGMI_STATUS__NOT_INITIALIZED                 = 0x04,
  51         TA_XGMI_STATUS__INVALID_NODE_NUM                = 0x05,
  52         TA_XGMI_STATUS__INVALID_NODE_ID                 = 0x06,
  53         TA_XGMI_STATUS__INVALID_TOPOLOGY                = 0x07,
  54         TA_XGMI_STATUS__FAILED_ID_GEN                   = 0x08,
  55         TA_XGMI_STATUS__FAILED_TOPOLOGY_INIT            = 0x09,
  56         TA_XGMI_STATUS__SET_SHARING_ERROR               = 0x0A
  57 };
  58
  59 enum ta_xgmi_assigned_sdma_engine {
  60         TA_XGMI_ASSIGNED_SDMA_ENGINE__NOT_ASSIGNED      = -1,
  61         TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA0             = 0,
  62         TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA1             = 1,
  63         TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA2             = 2,
  64         TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA3             = 3,
  65         TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA4             = 4,
  66         TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA5             = 5
  67 };
  68
  69 /* input/output structures for XGMI commands */
  70 /**********************************************************/
  71 struct ta_xgmi_node_info {
  72         uint64_t                                node_id;
  73         uint8_t                                 num_hops;
  74         uint8_t                                 is_sharing_enabled;
  75         enum ta_xgmi_assigned_sdma_engine       sdma_engine;
  76 };
  77
  78 struct ta_xgmi_cmd_initialize_output {
  79         uint32_t        status;
  80 };
  81
  82 struct ta_xgmi_cmd_get_node_id_output {
  83         uint64_t        node_id;
  84 };
  85
  86 struct ta_xgmi_cmd_get_hive_id_output {
  87         uint64_t        hive_id;
  88 };
  89
  90 struct ta_xgmi_cmd_get_topology_info_input {
  91         uint32_t                        num_nodes;
  92         struct ta_xgmi_node_info        nodes[TA_XGMI__MAX_CONNECTED_NODES];
  93 };
  94
  95 struct ta_xgmi_cmd_get_topology_info_output {
  96         uint32_t                        num_nodes;
  97         struct ta_xgmi_node_info        nodes[TA_XGMI__MAX_CONNECTED_NODES];
  98 };
  99
 100 struct ta_xgmi_cmd_set_topology_info_input {
 101         uint32_t                        num_nodes;
 102         struct ta_xgmi_node_info        nodes[TA_XGMI__MAX_CONNECTED_NODES];
 103 };
 104
 105 /**********************************************************/
 106 /* Common input structure for XGMI callbacks */
 107 union ta_xgmi_cmd_input {
 108         struct ta_xgmi_cmd_get_topology_info_input      get_topology_info;
 109         struct ta_xgmi_cmd_set_topology_info_input      set_topology_info;
 110 };
 111
 112 /* Common output structure for XGMI callbacks */
 113 union ta_xgmi_cmd_output {
 114         struct ta_xgmi_cmd_initialize_output            initialize;
 115         struct ta_xgmi_cmd_get_node_id_output           get_node_id;
 116         struct ta_xgmi_cmd_get_hive_id_output           get_hive_id;
 117         struct ta_xgmi_cmd_get_topology_info_output     get_topology_info;
 118 };
 119 /**********************************************************/
 120
 121 struct ta_xgmi_shared_memory {
 122         uint32_t                        cmd_id;
 123         uint32_t                        resp_id;
 124         enum ta_xgmi_status             xgmi_status;
 125         uint32_t                        reserved;
 126         union ta_xgmi_cmd_input         xgmi_in_message;
 127         union ta_xgmi_cmd_output        xgmi_out_message;
 128 };
 129
 130 #endif   //_TA_XGMI_IF_H