drivers/gpu/drm/amd/amdgpu/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "amdgpu_atombios.h"
  29 #include "si/sid.h"
  30 #include "r600_dpm.h"
  31 #include "si_dpm.h"
  32 #include "atom.h"
  33 #include "../include/pptable.h"
  34 #include <linux/math64.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/firmware.h>
  37
  38 #define MC_CG_ARB_FREQ_F0           0x0a
  39 #define MC_CG_ARB_FREQ_F1           0x0b
  40 #define MC_CG_ARB_FREQ_F2           0x0c
  41 #define MC_CG_ARB_FREQ_F3           0x0d
  42
  43 #define SMC_RAM_END                 0x20000
  44
  45 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  46
  47
  48 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  49 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  55
  56 #define BIOS_SCRATCH_4                                    0x5cd
  57
  58 /*(DEBLOBBED)*/
  59
  60 union power_info {
  61         struct _ATOM_POWERPLAY_INFO info;
  62         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  63         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  64         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  65         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  66         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  67         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  68         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  69 };
  70
  71 union fan_info {
  72         struct _ATOM_PPLIB_FANTABLE fan;
  73         struct _ATOM_PPLIB_FANTABLE2 fan2;
  74         struct _ATOM_PPLIB_FANTABLE3 fan3;
  75 };
  76
  77 union pplib_clock_info {
  78         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  79         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  80         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  81         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  82         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  83 };
  84
  85 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  86 {
  87         R600_UTC_DFLT_00,
  88         R600_UTC_DFLT_01,
  89         R600_UTC_DFLT_02,
  90         R600_UTC_DFLT_03,
  91         R600_UTC_DFLT_04,
  92         R600_UTC_DFLT_05,
  93         R600_UTC_DFLT_06,
  94         R600_UTC_DFLT_07,
  95         R600_UTC_DFLT_08,
  96         R600_UTC_DFLT_09,
  97         R600_UTC_DFLT_10,
  98         R600_UTC_DFLT_11,
  99         R600_UTC_DFLT_12,
 100         R600_UTC_DFLT_13,
 101         R600_UTC_DFLT_14,
 102 };
 103
 104 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 105 {
 106         R600_DTC_DFLT_00,
 107         R600_DTC_DFLT_01,
 108         R600_DTC_DFLT_02,
 109         R600_DTC_DFLT_03,
 110         R600_DTC_DFLT_04,
 111         R600_DTC_DFLT_05,
 112         R600_DTC_DFLT_06,
 113         R600_DTC_DFLT_07,
 114         R600_DTC_DFLT_08,
 115         R600_DTC_DFLT_09,
 116         R600_DTC_DFLT_10,
 117         R600_DTC_DFLT_11,
 118         R600_DTC_DFLT_12,
 119         R600_DTC_DFLT_13,
 120         R600_DTC_DFLT_14,
 121 };
 122
 123 static const struct si_cac_config_reg cac_weights_tahiti[] =
 124 {
 125         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 126         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 127         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 128         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 129         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 130         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 131         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 132         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 133         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 134         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 135         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 136         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 137         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 138         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 139         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 140         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 141         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 142         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 143         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 144         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 145         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 146         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 147         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 148         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 149         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 150         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 151         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 152         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 153         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 154         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 155         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 156         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 157         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 159         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 160         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 161         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 164         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 165         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 166         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 168         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 169         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 170         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 171         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 172         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 173         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 174         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 175         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 177         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 179         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 185         { 0xFFFFFFFF }
 186 };
 187
 188 static const struct si_cac_config_reg lcac_tahiti[] =
 189 {
 190         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 191         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 193         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 195         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 197         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 198         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 199         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 200         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 201         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 202         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 203         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 204         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 205         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 206         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 207         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 208         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 209         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 210         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 211         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 212         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 213         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 214         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 215         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 216         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 217         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 218         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 219         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 220         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 221         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 222         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 223         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 224         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 225         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 226         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 227         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 228         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 229         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 230         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 231         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 232         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 233         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 234         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 235         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 236         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 237         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 238         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 239         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 240         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 241         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 242         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 243         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 244         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 245         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 246         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 247         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 248         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 249         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 250         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 251         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 252         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 253         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 254         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 255         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 256         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 257         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 258         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 259         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 260         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 261         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 262         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 263         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 264         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 265         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 266         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 267         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 268         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 269         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 270         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 271         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 272         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 273         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 274         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 275         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 276         { 0xFFFFFFFF }
 277
 278 };
 279
 280 static const struct si_cac_config_reg cac_override_tahiti[] =
 281 {
 282         { 0xFFFFFFFF }
 283 };
 284
 285 static const struct si_powertune_data powertune_data_tahiti =
 286 {
 287         ((1 << 16) | 27027),
 288         6,
 289         0,
 290         4,
 291         95,
 292         {
 293                 0UL,
 294                 0UL,
 295                 4521550UL,
 296                 309631529UL,
 297                 -1270850L,
 298                 4513710L,
 299                 40
 300         },
 301         595000000UL,
 302         12,
 303         {
 304                 0,
 305                 0,
 306                 0,
 307                 0,
 308                 0,
 309                 0,
 310                 0,
 311                 0
 312         },
 313         true
 314 };
 315
 316 static const struct si_dte_data dte_data_tahiti =
 317 {
 318         { 1159409, 0, 0, 0, 0 },
 319         { 777, 0, 0, 0, 0 },
 320         2,
 321         54000,
 322         127000,
 323         25,
 324         2,
 325         10,
 326         13,
 327         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 328         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 329         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 330         85,
 331         false
 332 };
 333
 334 #if 0
 335 static const struct si_dte_data dte_data_tahiti_le =
 336 {
 337         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 338         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 339         0x5,
 340         0xAFC8,
 341         0x64,
 342         0x32,
 343         1,
 344         0,
 345         0x10,
 346         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 347         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 348         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 349         85,
 350         true
 351 };
 352 #endif
 353
 354 static const struct si_dte_data dte_data_tahiti_pro =
 355 {
 356         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 357         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 358         5,
 359         45000,
 360         100,
 361         0xA,
 362         1,
 363         0,
 364         0x10,
 365         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 366         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 367         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 368         90,
 369         true
 370 };
 371
 372 static const struct si_dte_data dte_data_new_zealand =
 373 {
 374         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 375         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 376         0x5,
 377         0xAFC8,
 378         0x69,
 379         0x32,
 380         1,
 381         0,
 382         0x10,
 383         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 384         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 385         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 386         85,
 387         true
 388 };
 389
 390 static const struct si_dte_data dte_data_aruba_pro =
 391 {
 392         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 393         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 394         5,
 395         45000,
 396         100,
 397         0xA,
 398         1,
 399         0,
 400         0x10,
 401         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 402         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 403         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 404         90,
 405         true
 406 };
 407
 408 static const struct si_dte_data dte_data_malta =
 409 {
 410         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 411         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 412         5,
 413         45000,
 414         100,
 415         0xA,
 416         1,
 417         0,
 418         0x10,
 419         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 420         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 421         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 422         90,
 423         true
 424 };
 425
 426 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 427 {
 428         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 429         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 430         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 431         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 432         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 433         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 434         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 435         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 436         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 437         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 438         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 439         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 440         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 441         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 442         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 443         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 444         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 445         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 446         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 447         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 448         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 449         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 450         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 451         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 452         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 453         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 454         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 455         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 456         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 457         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 458         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 460         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 461         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 462         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 463         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 464         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 465         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 466         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 467         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 468         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 469         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 470         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 471         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 472         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 473         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 474         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 475         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 476         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 477         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 482         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 483         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 484         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 485         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 486         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 487         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 488         { 0xFFFFFFFF }
 489 };
 490
 491 static const struct si_cac_config_reg lcac_pitcairn[] =
 492 {
 493         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 498         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 499         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 500         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 501         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 502         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 503         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 504         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 505         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 506         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 507         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 508         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 509         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 510         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 511         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 512         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 513         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 514         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 515         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 516         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 517         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 518         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 519         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 520         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 521         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 522         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 523         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 524         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 525         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 526         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 527         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 528         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 529         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 530         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 531         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 532         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 533         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 534         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 535         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 536         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 537         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 538         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 539         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 540         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 541         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 542         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 543         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 544         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 545         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 546         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 547         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 548         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 549         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 550         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 551         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 552         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 553         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 554         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 555         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 556         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 557         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 558         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 559         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 560         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 561         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 562         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 563         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 564         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 565         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 566         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 567         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 568         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 569         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 570         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 571         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 572         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 573         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 574         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 575         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 576         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 577         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 578         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 579         { 0xFFFFFFFF }
 580 };
 581
 582 static const struct si_cac_config_reg cac_override_pitcairn[] =
 583 {
 584     { 0xFFFFFFFF }
 585 };
 586
 587 static const struct si_powertune_data powertune_data_pitcairn =
 588 {
 589         ((1 << 16) | 27027),
 590         5,
 591         0,
 592         6,
 593         100,
 594         {
 595                 51600000UL,
 596                 1800000UL,
 597                 7194395UL,
 598                 309631529UL,
 599                 -1270850L,
 600                 4513710L,
 601                 100
 602         },
 603         117830498UL,
 604         12,
 605         {
 606                 0,
 607                 0,
 608                 0,
 609                 0,
 610                 0,
 611                 0,
 612                 0,
 613                 0
 614         },
 615         true
 616 };
 617
 618 static const struct si_dte_data dte_data_pitcairn =
 619 {
 620         { 0, 0, 0, 0, 0 },
 621         { 0, 0, 0, 0, 0 },
 622         0,
 623         0,
 624         0,
 625         0,
 626         0,
 627         0,
 628         0,
 629         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 630         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 631         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 632         0,
 633         false
 634 };
 635
 636 static const struct si_dte_data dte_data_curacao_xt =
 637 {
 638         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 639         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 640         5,
 641         45000,
 642         100,
 643         0xA,
 644         1,
 645         0,
 646         0x10,
 647         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 648         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 649         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 650         90,
 651         true
 652 };
 653
 654 static const struct si_dte_data dte_data_curacao_pro =
 655 {
 656         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 657         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 658         5,
 659         45000,
 660         100,
 661         0xA,
 662         1,
 663         0,
 664         0x10,
 665         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 666         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 667         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 668         90,
 669         true
 670 };
 671
 672 static const struct si_dte_data dte_data_neptune_xt =
 673 {
 674         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 675         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 676         5,
 677         45000,
 678         100,
 679         0xA,
 680         1,
 681         0,
 682         0x10,
 683         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 684         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 685         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 686         90,
 687         true
 688 };
 689
 690 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 691 {
 692         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 693         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 694         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 695         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 696         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 697         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 698         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 699         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 700         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 701         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 702         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 703         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 704         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 705         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 706         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 707         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 708         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 709         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 710         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 711         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 712         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 713         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 714         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 715         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 716         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 717         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 718         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 719         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 721         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 722         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 723         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 724         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 725         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 726         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 727         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 728         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 730         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 732         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 733         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 735         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 736         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 737         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 738         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 739         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 740         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 741         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 748         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 749         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 750         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 752         { 0xFFFFFFFF }
 753 };
 754
 755 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 756 {
 757         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 758         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 759         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 760         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 761         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 762         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 763         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 764         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 765         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 766         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 767         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 768         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 769         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 770         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 771         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 772         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 773         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 774         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 775         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 776         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 777         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 778         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 779         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 780         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 781         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 782         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 783         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 784         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 786         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 787         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 788         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 789         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 790         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 791         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 792         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 793         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 795         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 797         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 798         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 800         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 801         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 802         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 803         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 804         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 805         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 806         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 813         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 814         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 815         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 817         { 0xFFFFFFFF }
 818 };
 819
 820 static const struct si_cac_config_reg cac_weights_heathrow[] =
 821 {
 822         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 823         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 824         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 825         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 826         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 827         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 828         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 829         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 830         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 831         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 832         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 833         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 834         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 835         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 836         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 837         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 838         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 839         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 840         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 841         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 842         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 843         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 844         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 845         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 846         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 847         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 848         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 849         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 851         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 852         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 853         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 854         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 855         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 856         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 857         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 858         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 860         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 862         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 863         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 865         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 866         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 867         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 868         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 869         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 870         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 871         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 878         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 879         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 880         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 882         { 0xFFFFFFFF }
 883 };
 884
 885 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 886 {
 887         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 888         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 889         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 890         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 891         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 892         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 893         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 894         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 895         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 896         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 897         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 898         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 899         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 900         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 901         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 902         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 903         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 904         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 905         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 906         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 907         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 908         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 909         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 910         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 911         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 912         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 913         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 914         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 916         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 917         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 918         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 919         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 920         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 921         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 922         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 923         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 925         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 927         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 928         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 930         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 931         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 932         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 933         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 934         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 935         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 936         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 937         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 938         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 941         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 942         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 943         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 944         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 945         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 946         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 947         { 0xFFFFFFFF }
 948 };
 949
 950 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 951 {
 952         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 953         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 954         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 955         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 956         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 957         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 958         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 959         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 960         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 961         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 962         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 963         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 964         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 965         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 966         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 967         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 968         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 969         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 970         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 971         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 972         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 973         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 974         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 975         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 976         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 977         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 978         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 979         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 980         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 983         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 984         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 985         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 986         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 987         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 988         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 989         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 990         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 991         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 992         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 993         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 994         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 995         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 996         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 997         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 998         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 999         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1000         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1001         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1002         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1003         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1006         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1007         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1008         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1009         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1010         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1011         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1012         { 0xFFFFFFFF }
1013 };
1014
1015 static const struct si_cac_config_reg lcac_cape_verde[] =
1016 {
1017         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1018         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1019         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1020         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1021         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1022         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1023         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1024         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1025         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1026         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1027         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1028         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1029         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1030         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1031         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1032         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1033         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1034         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1035         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1036         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1037         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1038         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1039         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1040         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1041         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1042         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1043         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1044         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1045         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1046         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1047         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1048         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1049         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1050         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1051         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1052         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1053         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1054         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1055         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1056         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1057         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1058         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1059         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1060         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1061         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1062         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1063         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1064         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1065         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1066         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1067         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1068         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1069         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1070         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1071         { 0xFFFFFFFF }
1072 };
1073
1074 static const struct si_cac_config_reg cac_override_cape_verde[] =
1075 {
1076     { 0xFFFFFFFF }
1077 };
1078
1079 static const struct si_powertune_data powertune_data_cape_verde =
1080 {
1081         ((1 << 16) | 0x6993),
1082         5,
1083         0,
1084         7,
1085         105,
1086         {
1087                 0UL,
1088                 0UL,
1089                 7194395UL,
1090                 309631529UL,
1091                 -1270850L,
1092                 4513710L,
1093                 100
1094         },
1095         117830498UL,
1096         12,
1097         {
1098                 0,
1099                 0,
1100                 0,
1101                 0,
1102                 0,
1103                 0,
1104                 0,
1105                 0
1106         },
1107         true
1108 };
1109
1110 static const struct si_dte_data dte_data_cape_verde =
1111 {
1112         { 0, 0, 0, 0, 0 },
1113         { 0, 0, 0, 0, 0 },
1114         0,
1115         0,
1116         0,
1117         0,
1118         0,
1119         0,
1120         0,
1121         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1122         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1123         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1124         0,
1125         false
1126 };
1127
1128 static const struct si_dte_data dte_data_venus_xtx =
1129 {
1130         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1131         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1132         5,
1133         55000,
1134         0x69,
1135         0xA,
1136         1,
1137         0,
1138         0x3,
1139         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1140         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1141         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1142         90,
1143         true
1144 };
1145
1146 static const struct si_dte_data dte_data_venus_xt =
1147 {
1148         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1149         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1150         5,
1151         55000,
1152         0x69,
1153         0xA,
1154         1,
1155         0,
1156         0x3,
1157         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1158         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1159         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1160         90,
1161         true
1162 };
1163
1164 static const struct si_dte_data dte_data_venus_pro =
1165 {
1166         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1167         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1168         5,
1169         55000,
1170         0x69,
1171         0xA,
1172         1,
1173         0,
1174         0x3,
1175         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1176         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1177         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1178         90,
1179         true
1180 };
1181
1182 static const struct si_cac_config_reg cac_weights_oland[] =
1183 {
1184         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1185         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1186         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1187         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1188         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1189         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1190         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1191         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1192         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1193         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1194         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1195         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1196         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1197         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1198         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1199         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1200         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1201         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1202         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1203         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1204         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1205         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1206         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1207         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1208         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1209         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1210         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1211         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1213         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1214         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1215         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1216         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1217         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1218         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1219         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1220         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1222         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1224         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1225         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1227         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1228         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1229         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1230         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1231         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1232         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1233         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1244         { 0xFFFFFFFF }
1245 };
1246
1247 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1248 {
1249         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1250         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1251         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1252         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1253         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1254         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1255         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1256         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1257         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1258         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1259         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1260         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1261         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1262         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1263         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1264         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1265         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1266         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1267         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1268         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1269         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1270         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1271         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1272         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1273         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1274         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1275         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1276         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1277         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1278         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1279         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1280         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1281         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1282         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1283         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1284         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1285         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1287         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1289         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1290         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1292         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1293         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1294         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1295         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1296         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1297         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1298         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1301         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1306         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1309         { 0xFFFFFFFF }
1310 };
1311
1312 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1313 {
1314         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1315         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1316         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1317         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1318         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1319         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1320         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1321         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1322         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1323         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1324         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1325         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1326         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1327         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1328         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1329         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1330         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1331         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1332         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1333         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1334         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1335         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1336         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1337         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1338         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1339         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1340         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1341         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1342         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1343         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1344         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1345         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1346         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1347         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1348         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1349         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1350         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1352         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1354         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1355         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1357         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1358         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1359         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1360         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1361         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1362         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1363         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1366         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1371         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1374         { 0xFFFFFFFF }
1375 };
1376
1377 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1378 {
1379         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1380         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1381         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1382         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1383         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1384         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1385         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1386         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1387         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1388         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1389         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1390         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1391         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1392         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1393         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1394         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1395         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1396         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1397         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1398         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1399         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1400         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1401         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1402         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1403         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1404         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1405         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1406         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1407         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1408         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1409         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1410         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1411         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1412         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1413         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1414         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1415         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1417         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1419         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1420         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1422         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1423         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1424         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1425         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1426         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1427         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1428         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1429         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1430         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1431         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1432         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1433         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1434         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1435         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1436         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1437         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1438         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1439         { 0xFFFFFFFF }
1440 };
1441
1442 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1443 {
1444         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1445         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1446         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1447         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1448         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1449         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1450         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1451         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1452         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1453         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1454         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1455         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1456         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1457         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1458         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1459         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1460         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1461         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1462         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1463         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1464         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1465         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1466         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1467         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1468         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1469         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1470         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1471         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1472         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1473         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1474         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1475         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1476         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1477         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1478         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1479         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1480         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1481         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1482         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1483         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1484         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1485         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1486         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1487         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1488         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1489         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1490         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1491         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1492         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1493         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1494         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1495         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1496         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1497         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1498         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1499         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1500         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1501         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1502         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1503         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1504         { 0xFFFFFFFF }
1505 };
1506
1507 static const struct si_cac_config_reg lcac_oland[] =
1508 {
1509         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1510         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1512         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1514         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1516         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1517         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1518         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1519         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1520         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1521         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1522         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1523         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1524         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1525         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1526         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1527         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1528         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1529         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1530         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1531         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1532         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1533         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1534         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1538         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1539         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1541         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1546         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1547         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1548         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1549         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1550         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1551         { 0xFFFFFFFF }
1552 };
1553
1554 static const struct si_cac_config_reg lcac_mars_pro[] =
1555 {
1556         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1557         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1559         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1561         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1562         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1563         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1564         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1565         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1566         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1567         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1569         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1571         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1573         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1575         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1577         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1578         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1579         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1580         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1581         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1585         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1586         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1588         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1593         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1594         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1595         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1596         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1597         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1598         { 0xFFFFFFFF }
1599 };
1600
1601 static const struct si_cac_config_reg cac_override_oland[] =
1602 {
1603         { 0xFFFFFFFF }
1604 };
1605
1606 static const struct si_powertune_data powertune_data_oland =
1607 {
1608         ((1 << 16) | 0x6993),
1609         5,
1610         0,
1611         7,
1612         105,
1613         {
1614                 0UL,
1615                 0UL,
1616                 7194395UL,
1617                 309631529UL,
1618                 -1270850L,
1619                 4513710L,
1620                 100
1621         },
1622         117830498UL,
1623         12,
1624         {
1625                 0,
1626                 0,
1627                 0,
1628                 0,
1629                 0,
1630                 0,
1631                 0,
1632                 0
1633         },
1634         true
1635 };
1636
1637 static const struct si_powertune_data powertune_data_mars_pro =
1638 {
1639         ((1 << 16) | 0x6993),
1640         5,
1641         0,
1642         7,
1643         105,
1644         {
1645                 0UL,
1646                 0UL,
1647                 7194395UL,
1648                 309631529UL,
1649                 -1270850L,
1650                 4513710L,
1651                 100
1652         },
1653         117830498UL,
1654         12,
1655         {
1656                 0,
1657                 0,
1658                 0,
1659                 0,
1660                 0,
1661                 0,
1662                 0,
1663                 0
1664         },
1665         true
1666 };
1667
1668 static const struct si_dte_data dte_data_oland =
1669 {
1670         { 0, 0, 0, 0, 0 },
1671         { 0, 0, 0, 0, 0 },
1672         0,
1673         0,
1674         0,
1675         0,
1676         0,
1677         0,
1678         0,
1679         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1680         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1681         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1682         0,
1683         false
1684 };
1685
1686 static const struct si_dte_data dte_data_mars_pro =
1687 {
1688         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1689         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1690         5,
1691         55000,
1692         105,
1693         0xA,
1694         1,
1695         0,
1696         0x10,
1697         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1698         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1699         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1700         90,
1701         true
1702 };
1703
1704 static const struct si_dte_data dte_data_sun_xt =
1705 {
1706         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1707         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1708         5,
1709         55000,
1710         105,
1711         0xA,
1712         1,
1713         0,
1714         0x10,
1715         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1716         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1717         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1718         90,
1719         true
1720 };
1721
1722
1723 static const struct si_cac_config_reg cac_weights_hainan[] =
1724 {
1725         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1726         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1727         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1728         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1729         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1730         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1731         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1732         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1733         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1734         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1735         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1736         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1737         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1738         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1740         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1743         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1744         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1745         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1746         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1747         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1748         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1749         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1751         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1752         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1753         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1754         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1755         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1756         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1757         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1758         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1759         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1760         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1761         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1762         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1763         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1765         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1767         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1769         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1770         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1771         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1772         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1773         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1774         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1775         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1776         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1777         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1779         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1780         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1781         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1782         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1783         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1784         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1785         { 0xFFFFFFFF }
1786 };
1787
1788 static const struct si_powertune_data powertune_data_hainan =
1789 {
1790         ((1 << 16) | 0x6993),
1791         5,
1792         0,
1793         9,
1794         105,
1795         {
1796                 0UL,
1797                 0UL,
1798                 7194395UL,
1799                 309631529UL,
1800                 -1270850L,
1801                 4513710L,
1802                 100
1803         },
1804         117830498UL,
1805         12,
1806         {
1807                 0,
1808                 0,
1809                 0,
1810                 0,
1811                 0,
1812                 0,
1813                 0,
1814                 0
1815         },
1816         true
1817 };
1818
1819 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1820 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1821 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1822 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1823
1824 static int si_populate_voltage_value(struct amdgpu_device *adev,
1825                                      const struct atom_voltage_table *table,
1826                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1827 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1828                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1829                                     u16 *std_voltage);
1830 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1831                                       u16 reg_offset, u32 value);
1832 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1833                                          struct rv7xx_pl *pl,
1834                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1835 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1836                                     u32 engine_clock,
1837                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1838
1839 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1840 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1841 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1842 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1843
1844 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1845 {
1846         struct si_power_info *pi = adev->pm.dpm.priv;
1847         return pi;
1848 }
1849
1850 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1851                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1852 {
1853         s64 kt, kv, leakage_w, i_leakage, vddc;
1854         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1855         s64 tmp;
1856
1857         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1858         vddc = div64_s64(drm_int2fixp(v), 1000);
1859         temperature = div64_s64(drm_int2fixp(t), 1000);
1860
1861         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1862         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1863         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1864         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1865         t_ref = drm_int2fixp(coeff->t_ref);
1866
1867         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1868         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1869         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1870         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1871
1872         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1873
1874         *leakage = drm_fixp2int(leakage_w * 1000);
1875 }
1876
1877 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1878                                              const struct ni_leakage_coeffients *coeff,
1879                                              u16 v,
1880                                              s32 t,
1881                                              u32 i_leakage,
1882                                              u32 *leakage)
1883 {
1884         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1885 }
1886
1887 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1888                                                const u32 fixed_kt, u16 v,
1889                                                u32 ileakage, u32 *leakage)
1890 {
1891         s64 kt, kv, leakage_w, i_leakage, vddc;
1892
1893         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1894         vddc = div64_s64(drm_int2fixp(v), 1000);
1895
1896         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1897         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1898                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1899
1900         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1901
1902         *leakage = drm_fixp2int(leakage_w * 1000);
1903 }
1904
1905 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1906                                        const struct ni_leakage_coeffients *coeff,
1907                                        const u32 fixed_kt,
1908                                        u16 v,
1909                                        u32 i_leakage,
1910                                        u32 *leakage)
1911 {
1912         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1913 }
1914
1915
1916 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1917                                    struct si_dte_data *dte_data)
1918 {
1919         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1920         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1921         u32 k = dte_data->k;
1922         u32 t_max = dte_data->max_t;
1923         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1924         u32 t_0 = dte_data->t0;
1925         u32 i;
1926
1927         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1928                 dte_data->tdep_count = 3;
1929
1930                 for (i = 0; i < k; i++) {
1931                         dte_data->r[i] =
1932                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1933                                 (p_limit2  * (u32)100);
1934                 }
1935
1936                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1937
1938                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1939                         dte_data->tdep_r[i] = dte_data->r[4];
1940                 }
1941         } else {
1942                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1943         }
1944 }
1945
1946 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1947 {
1948         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1949
1950         return pi;
1951 }
1952
1953 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1954 {
1955         struct ni_power_info *pi = adev->pm.dpm.priv;
1956
1957         return pi;
1958 }
1959
1960 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1961 {
1962         struct  si_ps *ps = aps->ps_priv;
1963
1964         return ps;
1965 }
1966
1967 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1968 {
1969         struct ni_power_info *ni_pi = ni_get_pi(adev);
1970         struct si_power_info *si_pi = si_get_pi(adev);
1971         bool update_dte_from_pl2 = false;
1972
1973         if (adev->asic_type == CHIP_TAHITI) {
1974                 si_pi->cac_weights = cac_weights_tahiti;
1975                 si_pi->lcac_config = lcac_tahiti;
1976                 si_pi->cac_override = cac_override_tahiti;
1977                 si_pi->powertune_data = &powertune_data_tahiti;
1978                 si_pi->dte_data = dte_data_tahiti;
1979
1980                 switch (adev->pdev->device) {
1981                 case 0x6798:
1982                         si_pi->dte_data.enable_dte_by_default = true;
1983                         break;
1984                 case 0x6799:
1985                         si_pi->dte_data = dte_data_new_zealand;
1986                         break;
1987                 case 0x6790:
1988                 case 0x6791:
1989                 case 0x6792:
1990                 case 0x679E:
1991                         si_pi->dte_data = dte_data_aruba_pro;
1992                         update_dte_from_pl2 = true;
1993                         break;
1994                 case 0x679B:
1995                         si_pi->dte_data = dte_data_malta;
1996                         update_dte_from_pl2 = true;
1997                         break;
1998                 case 0x679A:
1999                         si_pi->dte_data = dte_data_tahiti_pro;
2000                         update_dte_from_pl2 = true;
2001                         break;
2002                 default:
2003                         if (si_pi->dte_data.enable_dte_by_default == true)
2004                                 DRM_ERROR("DTE is not enabled!\n");
2005                         break;
2006                 }
2007         } else if (adev->asic_type == CHIP_PITCAIRN) {
2008                 si_pi->cac_weights = cac_weights_pitcairn;
2009                 si_pi->lcac_config = lcac_pitcairn;
2010                 si_pi->cac_override = cac_override_pitcairn;
2011                 si_pi->powertune_data = &powertune_data_pitcairn;
2012
2013                 switch (adev->pdev->device) {
2014                 case 0x6810:
2015                 case 0x6818:
2016                         si_pi->dte_data = dte_data_curacao_xt;
2017                         update_dte_from_pl2 = true;
2018                         break;
2019                 case 0x6819:
2020                 case 0x6811:
2021                         si_pi->dte_data = dte_data_curacao_pro;
2022                         update_dte_from_pl2 = true;
2023                         break;
2024                 case 0x6800:
2025                 case 0x6806:
2026                         si_pi->dte_data = dte_data_neptune_xt;
2027                         update_dte_from_pl2 = true;
2028                         break;
2029                 default:
2030                         si_pi->dte_data = dte_data_pitcairn;
2031                         break;
2032                 }
2033         } else if (adev->asic_type == CHIP_VERDE) {
2034                 si_pi->lcac_config = lcac_cape_verde;
2035                 si_pi->cac_override = cac_override_cape_verde;
2036                 si_pi->powertune_data = &powertune_data_cape_verde;
2037
2038                 switch (adev->pdev->device) {
2039                 case 0x683B:
2040                 case 0x683F:
2041                 case 0x6829:
2042                 case 0x6835:
2043                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2044                         si_pi->dte_data = dte_data_cape_verde;
2045                         break;
2046                 case 0x682C:
2047                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2048                         si_pi->dte_data = dte_data_sun_xt;
2049                         break;
2050                 case 0x6825:
2051                 case 0x6827:
2052                         si_pi->cac_weights = cac_weights_heathrow;
2053                         si_pi->dte_data = dte_data_cape_verde;
2054                         break;
2055                 case 0x6824:
2056                 case 0x682D:
2057                         si_pi->cac_weights = cac_weights_chelsea_xt;
2058                         si_pi->dte_data = dte_data_cape_verde;
2059                         break;
2060                 case 0x682F:
2061                         si_pi->cac_weights = cac_weights_chelsea_pro;
2062                         si_pi->dte_data = dte_data_cape_verde;
2063                         break;
2064                 case 0x6820:
2065                         si_pi->cac_weights = cac_weights_heathrow;
2066                         si_pi->dte_data = dte_data_venus_xtx;
2067                         break;
2068                 case 0x6821:
2069                         si_pi->cac_weights = cac_weights_heathrow;
2070                         si_pi->dte_data = dte_data_venus_xt;
2071                         break;
2072                 case 0x6823:
2073                 case 0x682B:
2074                 case 0x6822:
2075                 case 0x682A:
2076                         si_pi->cac_weights = cac_weights_chelsea_pro;
2077                         si_pi->dte_data = dte_data_venus_pro;
2078                         break;
2079                 default:
2080                         si_pi->cac_weights = cac_weights_cape_verde;
2081                         si_pi->dte_data = dte_data_cape_verde;
2082                         break;
2083                 }
2084         } else if (adev->asic_type == CHIP_OLAND) {
2085                 si_pi->lcac_config = lcac_mars_pro;
2086                 si_pi->cac_override = cac_override_oland;
2087                 si_pi->powertune_data = &powertune_data_mars_pro;
2088                 si_pi->dte_data = dte_data_mars_pro;
2089
2090                 switch (adev->pdev->device) {
2091                 case 0x6601:
2092                 case 0x6621:
2093                 case 0x6603:
2094                 case 0x6605:
2095                         si_pi->cac_weights = cac_weights_mars_pro;
2096                         update_dte_from_pl2 = true;
2097                         break;
2098                 case 0x6600:
2099                 case 0x6606:
2100                 case 0x6620:
2101                 case 0x6604:
2102                         si_pi->cac_weights = cac_weights_mars_xt;
2103                         update_dte_from_pl2 = true;
2104                         break;
2105                 case 0x6611:
2106                 case 0x6613:
2107                 case 0x6608:
2108                         si_pi->cac_weights = cac_weights_oland_pro;
2109                         update_dte_from_pl2 = true;
2110                         break;
2111                 case 0x6610:
2112                         si_pi->cac_weights = cac_weights_oland_xt;
2113                         update_dte_from_pl2 = true;
2114                         break;
2115                 default:
2116                         si_pi->cac_weights = cac_weights_oland;
2117                         si_pi->lcac_config = lcac_oland;
2118                         si_pi->cac_override = cac_override_oland;
2119                         si_pi->powertune_data = &powertune_data_oland;
2120                         si_pi->dte_data = dte_data_oland;
2121                         break;
2122                 }
2123         } else if (adev->asic_type == CHIP_HAINAN) {
2124                 si_pi->cac_weights = cac_weights_hainan;
2125                 si_pi->lcac_config = lcac_oland;
2126                 si_pi->cac_override = cac_override_oland;
2127                 si_pi->powertune_data = &powertune_data_hainan;
2128                 si_pi->dte_data = dte_data_sun_xt;
2129                 update_dte_from_pl2 = true;
2130         } else {
2131                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2132                 return;
2133         }
2134
2135         ni_pi->enable_power_containment = false;
2136         ni_pi->enable_cac = false;
2137         ni_pi->enable_sq_ramping = false;
2138         si_pi->enable_dte = false;
2139
2140         if (si_pi->powertune_data->enable_powertune_by_default) {
2141                 ni_pi->enable_power_containment = true;
2142                 ni_pi->enable_cac = true;
2143                 if (si_pi->dte_data.enable_dte_by_default) {
2144                         si_pi->enable_dte = true;
2145                         if (update_dte_from_pl2)
2146                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2147
2148                 }
2149                 ni_pi->enable_sq_ramping = true;
2150         }
2151
2152         ni_pi->driver_calculate_cac_leakage = true;
2153         ni_pi->cac_configuration_required = true;
2154
2155         if (ni_pi->cac_configuration_required) {
2156                 ni_pi->support_cac_long_term_average = true;
2157                 si_pi->dyn_powertune_data.l2_lta_window_size =
2158                         si_pi->powertune_data->l2_lta_window_size_default;
2159                 si_pi->dyn_powertune_data.lts_truncate =
2160                         si_pi->powertune_data->lts_truncate_default;
2161         } else {
2162                 ni_pi->support_cac_long_term_average = false;
2163                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2164                 si_pi->dyn_powertune_data.lts_truncate = 0;
2165         }
2166
2167         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2168 }
2169
2170 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2171 {
2172         return 1;
2173 }
2174
2175 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2176 {
2177         u32 xclk;
2178         u32 wintime;
2179         u32 cac_window;
2180         u32 cac_window_size;
2181
2182         xclk = amdgpu_asic_get_xclk(adev);
2183
2184         if (xclk == 0)
2185                 return 0;
2186
2187         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2188         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2189
2190         wintime = (cac_window_size * 100) / xclk;
2191
2192         return wintime;
2193 }
2194
2195 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2196 {
2197         return power_in_watts;
2198 }
2199
2200 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2201                                             bool adjust_polarity,
2202                                             u32 tdp_adjustment,
2203                                             u32 *tdp_limit,
2204                                             u32 *near_tdp_limit)
2205 {
2206         u32 adjustment_delta, max_tdp_limit;
2207
2208         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2209                 return -EINVAL;
2210
2211         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2212
2213         if (adjust_polarity) {
2214                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2215                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2216         } else {
2217                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2218                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2219                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2220                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2221                 else
2222                         *near_tdp_limit = 0;
2223         }
2224
2225         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2226                 return -EINVAL;
2227         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2228                 return -EINVAL;
2229
2230         return 0;
2231 }
2232
2233 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2234                                       struct amdgpu_ps *amdgpu_state)
2235 {
2236         struct ni_power_info *ni_pi = ni_get_pi(adev);
2237         struct si_power_info *si_pi = si_get_pi(adev);
2238
2239         if (ni_pi->enable_power_containment) {
2240                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2241                 PP_SIslands_PAPMParameters *papm_parm;
2242                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2243                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2244                 u32 tdp_limit;
2245                 u32 near_tdp_limit;
2246                 int ret;
2247
2248                 if (scaling_factor == 0)
2249                         return -EINVAL;
2250
2251                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2252
2253                 ret = si_calculate_adjusted_tdp_limits(adev,
2254                                                        false, /* ??? */
2255                                                        adev->pm.dpm.tdp_adjustment,
2256                                                        &tdp_limit,
2257                                                        &near_tdp_limit);
2258                 if (ret)
2259                         return ret;
2260
2261                 smc_table->dpm2Params.TDPLimit =
2262                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2263                 smc_table->dpm2Params.NearTDPLimit =
2264                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2265                 smc_table->dpm2Params.SafePowerLimit =
2266                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2267
2268                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2269                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2270                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2271                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2272                                                   sizeof(u32) * 3,
2273                                                   si_pi->sram_end);
2274                 if (ret)
2275                         return ret;
2276
2277                 if (si_pi->enable_ppm) {
2278                         papm_parm = &si_pi->papm_parm;
2279                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2280                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2281                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2282                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2283                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2284                         papm_parm->PlatformPowerLimit = 0xffffffff;
2285                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2286
2287                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2288                                                           (u8 *)papm_parm,
2289                                                           sizeof(PP_SIslands_PAPMParameters),
2290                                                           si_pi->sram_end);
2291                         if (ret)
2292                                 return ret;
2293                 }
2294         }
2295         return 0;
2296 }
2297
2298 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2299                                         struct amdgpu_ps *amdgpu_state)
2300 {
2301         struct ni_power_info *ni_pi = ni_get_pi(adev);
2302         struct si_power_info *si_pi = si_get_pi(adev);
2303
2304         if (ni_pi->enable_power_containment) {
2305                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2306                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2307                 int ret;
2308
2309                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2310
2311                 smc_table->dpm2Params.NearTDPLimit =
2312                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2313                 smc_table->dpm2Params.SafePowerLimit =
2314                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2315
2316                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2317                                                   (si_pi->state_table_start +
2318                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2319                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2320                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2321                                                   sizeof(u32) * 2,
2322                                                   si_pi->sram_end);
2323                 if (ret)
2324                         return ret;
2325         }
2326
2327         return 0;
2328 }
2329
2330 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2331                                                const u16 prev_std_vddc,
2332                                                const u16 curr_std_vddc)
2333 {
2334         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2335         u64 prev_vddc = (u64)prev_std_vddc;
2336         u64 curr_vddc = (u64)curr_std_vddc;
2337         u64 pwr_efficiency_ratio, n, d;
2338
2339         if ((prev_vddc == 0) || (curr_vddc == 0))
2340                 return 0;
2341
2342         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2343         d = prev_vddc * prev_vddc;
2344         pwr_efficiency_ratio = div64_u64(n, d);
2345
2346         if (pwr_efficiency_ratio > (u64)0xFFFF)
2347                 return 0;
2348
2349         return (u16)pwr_efficiency_ratio;
2350 }
2351
2352 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2353                                             struct amdgpu_ps *amdgpu_state)
2354 {
2355         struct si_power_info *si_pi = si_get_pi(adev);
2356
2357         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2358             amdgpu_state->vclk && amdgpu_state->dclk)
2359                 return true;
2360
2361         return false;
2362 }
2363
2364 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2365 {
2366         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2367
2368         return pi;
2369 }
2370
2371 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2372                                                 struct amdgpu_ps *amdgpu_state,
2373                                                 SISLANDS_SMC_SWSTATE *smc_state)
2374 {
2375         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2376         struct ni_power_info *ni_pi = ni_get_pi(adev);
2377         struct  si_ps *state = si_get_ps(amdgpu_state);
2378         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2379         u32 prev_sclk;
2380         u32 max_sclk;
2381         u32 min_sclk;
2382         u16 prev_std_vddc;
2383         u16 curr_std_vddc;
2384         int i;
2385         u16 pwr_efficiency_ratio;
2386         u8 max_ps_percent;
2387         bool disable_uvd_power_tune;
2388         int ret;
2389
2390         if (ni_pi->enable_power_containment == false)
2391                 return 0;
2392
2393         if (state->performance_level_count == 0)
2394                 return -EINVAL;
2395
2396         if (smc_state->levelCount != state->performance_level_count)
2397                 return -EINVAL;
2398
2399         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2400
2401         smc_state->levels[0].dpm2.MaxPS = 0;
2402         smc_state->levels[0].dpm2.NearTDPDec = 0;
2403         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2404         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2405         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2406
2407         for (i = 1; i < state->performance_level_count; i++) {
2408                 prev_sclk = state->performance_levels[i-1].sclk;
2409                 max_sclk  = state->performance_levels[i].sclk;
2410                 if (i == 1)
2411                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2412                 else
2413                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2414
2415                 if (prev_sclk > max_sclk)
2416                         return -EINVAL;
2417
2418                 if ((max_ps_percent == 0) ||
2419                     (prev_sclk == max_sclk) ||
2420                     disable_uvd_power_tune)
2421                         min_sclk = max_sclk;
2422                 else if (i == 1)
2423                         min_sclk = prev_sclk;
2424                 else
2425                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2426
2427                 if (min_sclk < state->performance_levels[0].sclk)
2428                         min_sclk = state->performance_levels[0].sclk;
2429
2430                 if (min_sclk == 0)
2431                         return -EINVAL;
2432
2433                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2434                                                 state->performance_levels[i-1].vddc, &vddc);
2435                 if (ret)
2436                         return ret;
2437
2438                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2439                 if (ret)
2440                         return ret;
2441
2442                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443                                                 state->performance_levels[i].vddc, &vddc);
2444                 if (ret)
2445                         return ret;
2446
2447                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2448                 if (ret)
2449                         return ret;
2450
2451                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2452                                                                            prev_std_vddc, curr_std_vddc);
2453
2454                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2455                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2456                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2457                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2458                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2459         }
2460
2461         return 0;
2462 }
2463
2464 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2465                                          struct amdgpu_ps *amdgpu_state,
2466                                          SISLANDS_SMC_SWSTATE *smc_state)
2467 {
2468         struct ni_power_info *ni_pi = ni_get_pi(adev);
2469         struct  si_ps *state = si_get_ps(amdgpu_state);
2470         u32 sq_power_throttle, sq_power_throttle2;
2471         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2472         int i;
2473
2474         if (state->performance_level_count == 0)
2475                 return -EINVAL;
2476
2477         if (smc_state->levelCount != state->performance_level_count)
2478                 return -EINVAL;
2479
2480         if (adev->pm.dpm.sq_ramping_threshold == 0)
2481                 return -EINVAL;
2482
2483         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2484                 enable_sq_ramping = false;
2485
2486         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2487                 enable_sq_ramping = false;
2488
2489         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2490                 enable_sq_ramping = false;
2491
2492         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2493                 enable_sq_ramping = false;
2494
2495         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2496                 enable_sq_ramping = false;
2497
2498         for (i = 0; i < state->performance_level_count; i++) {
2499                 sq_power_throttle = 0;
2500                 sq_power_throttle2 = 0;
2501
2502                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2503                     enable_sq_ramping) {
2504                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2505                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2506                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2507                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2508                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2509                 } else {
2510                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2511                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2512                 }
2513
2514                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2515                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2516         }
2517
2518         return 0;
2519 }
2520
2521 static int si_enable_power_containment(struct amdgpu_device *adev,
2522                                        struct amdgpu_ps *amdgpu_new_state,
2523                                        bool enable)
2524 {
2525         struct ni_power_info *ni_pi = ni_get_pi(adev);
2526         PPSMC_Result smc_result;
2527         int ret = 0;
2528
2529         if (ni_pi->enable_power_containment) {
2530                 if (enable) {
2531                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2532                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2533                                 if (smc_result != PPSMC_Result_OK) {
2534                                         ret = -EINVAL;
2535                                         ni_pi->pc_enabled = false;
2536                                 } else {
2537                                         ni_pi->pc_enabled = true;
2538                                 }
2539                         }
2540                 } else {
2541                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2542                         if (smc_result != PPSMC_Result_OK)
2543                                 ret = -EINVAL;
2544                         ni_pi->pc_enabled = false;
2545                 }
2546         }
2547
2548         return ret;
2549 }
2550
2551 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2552 {
2553         struct si_power_info *si_pi = si_get_pi(adev);
2554         int ret = 0;
2555         struct si_dte_data *dte_data = &si_pi->dte_data;
2556         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2557         u32 table_size;
2558         u8 tdep_count;
2559         u32 i;
2560
2561         if (dte_data == NULL)
2562                 si_pi->enable_dte = false;
2563
2564         if (si_pi->enable_dte == false)
2565                 return 0;
2566
2567         if (dte_data->k <= 0)
2568                 return -EINVAL;
2569
2570         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2571         if (dte_tables == NULL) {
2572                 si_pi->enable_dte = false;
2573                 return -ENOMEM;
2574         }
2575
2576         table_size = dte_data->k;
2577
2578         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2579                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2580
2581         tdep_count = dte_data->tdep_count;
2582         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2583                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2584
2585         dte_tables->K = cpu_to_be32(table_size);
2586         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2587         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2588         dte_tables->WindowSize = dte_data->window_size;
2589         dte_tables->temp_select = dte_data->temp_select;
2590         dte_tables->DTE_mode = dte_data->dte_mode;
2591         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2592
2593         if (tdep_count > 0)
2594                 table_size--;
2595
2596         for (i = 0; i < table_size; i++) {
2597                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2598                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2599         }
2600
2601         dte_tables->Tdep_count = tdep_count;
2602
2603         for (i = 0; i < (u32)tdep_count; i++) {
2604                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2605                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2606                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2607         }
2608
2609         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2610                                           (u8 *)dte_tables,
2611                                           sizeof(Smc_SIslands_DTE_Configuration),
2612                                           si_pi->sram_end);
2613         kfree(dte_tables);
2614
2615         return ret;
2616 }
2617
2618 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2619                                           u16 *max, u16 *min)
2620 {
2621         struct si_power_info *si_pi = si_get_pi(adev);
2622         struct amdgpu_cac_leakage_table *table =
2623                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2624         u32 i;
2625         u32 v0_loadline;
2626
2627         if (table == NULL)
2628                 return -EINVAL;
2629
2630         *max = 0;
2631         *min = 0xFFFF;
2632
2633         for (i = 0; i < table->count; i++) {
2634                 if (table->entries[i].vddc > *max)
2635                         *max = table->entries[i].vddc;
2636                 if (table->entries[i].vddc < *min)
2637                         *min = table->entries[i].vddc;
2638         }
2639
2640         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2641                 return -EINVAL;
2642
2643         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2644
2645         if (v0_loadline > 0xFFFFUL)
2646                 return -EINVAL;
2647
2648         *min = (u16)v0_loadline;
2649
2650         if ((*min > *max) || (*max == 0) || (*min == 0))
2651                 return -EINVAL;
2652
2653         return 0;
2654 }
2655
2656 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2657 {
2658         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2659                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2660 }
2661
2662 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2663                                      PP_SIslands_CacConfig *cac_tables,
2664                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2665                                      u16 t0, u16 t_step)
2666 {
2667         struct si_power_info *si_pi = si_get_pi(adev);
2668         u32 leakage;
2669         unsigned int i, j;
2670         s32 t;
2671         u32 smc_leakage;
2672         u32 scaling_factor;
2673         u16 voltage;
2674
2675         scaling_factor = si_get_smc_power_scaling_factor(adev);
2676
2677         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2678                 t = (1000 * (i * t_step + t0));
2679
2680                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2681                         voltage = vddc_max - (vddc_step * j);
2682
2683                         si_calculate_leakage_for_v_and_t(adev,
2684                                                          &si_pi->powertune_data->leakage_coefficients,
2685                                                          voltage,
2686                                                          t,
2687                                                          si_pi->dyn_powertune_data.cac_leakage,
2688                                                          &leakage);
2689
2690                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2691
2692                         if (smc_leakage > 0xFFFF)
2693                                 smc_leakage = 0xFFFF;
2694
2695                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2696                                 cpu_to_be16((u16)smc_leakage);
2697                 }
2698         }
2699         return 0;
2700 }
2701
2702 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2703                                             PP_SIslands_CacConfig *cac_tables,
2704                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2705 {
2706         struct si_power_info *si_pi = si_get_pi(adev);
2707         u32 leakage;
2708         unsigned int i, j;
2709         u32 smc_leakage;
2710         u32 scaling_factor;
2711         u16 voltage;
2712
2713         scaling_factor = si_get_smc_power_scaling_factor(adev);
2714
2715         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2716                 voltage = vddc_max - (vddc_step * j);
2717
2718                 si_calculate_leakage_for_v(adev,
2719                                            &si_pi->powertune_data->leakage_coefficients,
2720                                            si_pi->powertune_data->fixed_kt,
2721                                            voltage,
2722                                            si_pi->dyn_powertune_data.cac_leakage,
2723                                            &leakage);
2724
2725                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2726
2727                 if (smc_leakage > 0xFFFF)
2728                         smc_leakage = 0xFFFF;
2729
2730                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2731                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2732                                 cpu_to_be16((u16)smc_leakage);
2733         }
2734         return 0;
2735 }
2736
2737 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2738 {
2739         struct ni_power_info *ni_pi = ni_get_pi(adev);
2740         struct si_power_info *si_pi = si_get_pi(adev);
2741         PP_SIslands_CacConfig *cac_tables = NULL;
2742         u16 vddc_max, vddc_min, vddc_step;
2743         u16 t0, t_step;
2744         u32 load_line_slope, reg;
2745         int ret = 0;
2746         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2747
2748         if (ni_pi->enable_cac == false)
2749                 return 0;
2750
2751         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2752         if (!cac_tables)
2753                 return -ENOMEM;
2754
2755         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2756         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2757         WREG32(CG_CAC_CTRL, reg);
2758
2759         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2760         si_pi->dyn_powertune_data.dc_pwr_value =
2761                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2762         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2763         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2764
2765         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2766
2767         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2768         if (ret)
2769                 goto done_free;
2770
2771         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2772         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2773         t_step = 4;
2774         t0 = 60;
2775
2776         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2777                 ret = si_init_dte_leakage_table(adev, cac_tables,
2778                                                 vddc_max, vddc_min, vddc_step,
2779                                                 t0, t_step);
2780         else
2781                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2782                                                        vddc_max, vddc_min, vddc_step);
2783         if (ret)
2784                 goto done_free;
2785
2786         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2787
2788         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2789         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2790         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2791         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2792         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2793         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2794         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2795         cac_tables->calculation_repeats = cpu_to_be32(2);
2796         cac_tables->dc_cac = cpu_to_be32(0);
2797         cac_tables->log2_PG_LKG_SCALE = 12;
2798         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2799         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2800         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2801
2802         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2803                                           (u8 *)cac_tables,
2804                                           sizeof(PP_SIslands_CacConfig),
2805                                           si_pi->sram_end);
2806
2807         if (ret)
2808                 goto done_free;
2809
2810         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2811
2812 done_free:
2813         if (ret) {
2814                 ni_pi->enable_cac = false;
2815                 ni_pi->enable_power_containment = false;
2816         }
2817
2818         kfree(cac_tables);
2819
2820         return ret;
2821 }
2822
2823 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2824                                            const struct si_cac_config_reg *cac_config_regs)
2825 {
2826         const struct si_cac_config_reg *config_regs = cac_config_regs;
2827         u32 data = 0, offset;
2828
2829         if (!config_regs)
2830                 return -EINVAL;
2831
2832         while (config_regs->offset != 0xFFFFFFFF) {
2833                 switch (config_regs->type) {
2834                 case SISLANDS_CACCONFIG_CGIND:
2835                         offset = SMC_CG_IND_START + config_regs->offset;
2836                         if (offset < SMC_CG_IND_END)
2837                                 data = RREG32_SMC(offset);
2838                         break;
2839                 default:
2840                         data = RREG32(config_regs->offset);
2841                         break;
2842                 }
2843
2844                 data &= ~config_regs->mask;
2845                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2846
2847                 switch (config_regs->type) {
2848                 case SISLANDS_CACCONFIG_CGIND:
2849                         offset = SMC_CG_IND_START + config_regs->offset;
2850                         if (offset < SMC_CG_IND_END)
2851                                 WREG32_SMC(offset, data);
2852                         break;
2853                 default:
2854                         WREG32(config_regs->offset, data);
2855                         break;
2856                 }
2857                 config_regs++;
2858         }
2859         return 0;
2860 }
2861
2862 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2863 {
2864         struct ni_power_info *ni_pi = ni_get_pi(adev);
2865         struct si_power_info *si_pi = si_get_pi(adev);
2866         int ret;
2867
2868         if ((ni_pi->enable_cac == false) ||
2869             (ni_pi->cac_configuration_required == false))
2870                 return 0;
2871
2872         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2873         if (ret)
2874                 return ret;
2875         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2876         if (ret)
2877                 return ret;
2878         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2879         if (ret)
2880                 return ret;
2881
2882         return 0;
2883 }
2884
2885 static int si_enable_smc_cac(struct amdgpu_device *adev,
2886                              struct amdgpu_ps *amdgpu_new_state,
2887                              bool enable)
2888 {
2889         struct ni_power_info *ni_pi = ni_get_pi(adev);
2890         struct si_power_info *si_pi = si_get_pi(adev);
2891         PPSMC_Result smc_result;
2892         int ret = 0;
2893
2894         if (ni_pi->enable_cac) {
2895                 if (enable) {
2896                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2897                                 if (ni_pi->support_cac_long_term_average) {
2898                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2899                                         if (smc_result != PPSMC_Result_OK)
2900                                                 ni_pi->support_cac_long_term_average = false;
2901                                 }
2902
2903                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2904                                 if (smc_result != PPSMC_Result_OK) {
2905                                         ret = -EINVAL;
2906                                         ni_pi->cac_enabled = false;
2907                                 } else {
2908                                         ni_pi->cac_enabled = true;
2909                                 }
2910
2911                                 if (si_pi->enable_dte) {
2912                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2913                                         if (smc_result != PPSMC_Result_OK)
2914                                                 ret = -EINVAL;
2915                                 }
2916                         }
2917                 } else if (ni_pi->cac_enabled) {
2918                         if (si_pi->enable_dte)
2919                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2920
2921                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2922
2923                         ni_pi->cac_enabled = false;
2924
2925                         if (ni_pi->support_cac_long_term_average)
2926                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2927                 }
2928         }
2929         return ret;
2930 }
2931
2932 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2933 {
2934         struct ni_power_info *ni_pi = ni_get_pi(adev);
2935         struct si_power_info *si_pi = si_get_pi(adev);
2936         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2937         SISLANDS_SMC_SCLK_VALUE sclk_params;
2938         u32 fb_div, p_div;
2939         u32 clk_s, clk_v;
2940         u32 sclk = 0;
2941         int ret = 0;
2942         u32 tmp;
2943         int i;
2944
2945         if (si_pi->spll_table_start == 0)
2946                 return -EINVAL;
2947
2948         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2949         if (spll_table == NULL)
2950                 return -ENOMEM;
2951
2952         for (i = 0; i < 256; i++) {
2953                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2954                 if (ret)
2955                         break;
2956                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2957                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2958                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2959                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2960
2961                 fb_div &= ~0x00001FFF;
2962                 fb_div >>= 1;
2963                 clk_v >>= 6;
2964
2965                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2966                         ret = -EINVAL;
2967                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2968                         ret = -EINVAL;
2969                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2970                         ret = -EINVAL;
2971                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2972                         ret = -EINVAL;
2973
2974                 if (ret)
2975                         break;
2976
2977                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2978                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2979                 spll_table->freq[i] = cpu_to_be32(tmp);
2980
2981                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2982                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2983                 spll_table->ss[i] = cpu_to_be32(tmp);
2984
2985                 sclk += 512;
2986         }
2987
2988
2989         if (!ret)
2990                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2991                                                   (u8 *)spll_table,
2992                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2993                                                   si_pi->sram_end);
2994
2995         if (ret)
2996                 ni_pi->enable_power_containment = false;
2997
2998         kfree(spll_table);
2999
3000         return ret;
3001 }
3002
3003 struct si_dpm_quirk {
3004         u32 chip_vendor;
3005         u32 chip_device;
3006         u32 subsys_vendor;
3007         u32 subsys_device;
3008         u32 max_sclk;
3009         u32 max_mclk;
3010 };
3011
3012 /* cards with dpm stability problems */
3013 static struct si_dpm_quirk si_dpm_quirk_list[] = {
3014         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3015         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3016         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
3017         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
3018         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3019         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3020         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
3021         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
3022         { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
3023         { 0, 0, 0, 0 },
3024 };
3025
3026 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3027                                                    u16 vce_voltage)
3028 {
3029         u16 highest_leakage = 0;
3030         struct si_power_info *si_pi = si_get_pi(adev);
3031         int i;
3032
3033         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3034                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3035                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3036         }
3037
3038         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3039                 return highest_leakage;
3040
3041         return vce_voltage;
3042 }
3043
3044 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3045                                     u32 evclk, u32 ecclk, u16 *voltage)
3046 {
3047         u32 i;
3048         int ret = -EINVAL;
3049         struct amdgpu_vce_clock_voltage_dependency_table *table =
3050                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3051
3052         if (((evclk == 0) && (ecclk == 0)) ||
3053             (table && (table->count == 0))) {
3054                 *voltage = 0;
3055                 return 0;
3056         }
3057
3058         for (i = 0; i < table->count; i++) {
3059                 if ((evclk <= table->entries[i].evclk) &&
3060                     (ecclk <= table->entries[i].ecclk)) {
3061                         *voltage = table->entries[i].v;
3062                         ret = 0;
3063                         break;
3064                 }
3065         }
3066
3067         /* if no match return the highest voltage */
3068         if (ret)
3069                 *voltage = table->entries[table->count - 1].v;
3070
3071         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3072
3073         return ret;
3074 }
3075
3076 static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3077 {
3078
3079         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3080         /* we never hit the non-gddr5 limit so disable it */
3081         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3082
3083         if (vblank_time < switch_limit)
3084                 return true;
3085         else
3086                 return false;
3087
3088 }
3089
3090 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3091                                 u32 arb_freq_src, u32 arb_freq_dest)
3092 {
3093         u32 mc_arb_dram_timing;
3094         u32 mc_arb_dram_timing2;
3095         u32 burst_time;
3096         u32 mc_cg_config;
3097
3098         switch (arb_freq_src) {
3099         case MC_CG_ARB_FREQ_F0:
3100                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3101                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3102                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3103                 break;
3104         case MC_CG_ARB_FREQ_F1:
3105                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3106                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3107                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3108                 break;
3109         case MC_CG_ARB_FREQ_F2:
3110                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3111                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3112                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3113                 break;
3114         case MC_CG_ARB_FREQ_F3:
3115                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3116                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3117                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3118                 break;
3119         default:
3120                 return -EINVAL;
3121         }
3122
3123         switch (arb_freq_dest) {
3124         case MC_CG_ARB_FREQ_F0:
3125                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3126                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3127                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3128                 break;
3129         case MC_CG_ARB_FREQ_F1:
3130                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3131                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3132                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3133                 break;
3134         case MC_CG_ARB_FREQ_F2:
3135                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3136                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3137                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3138                 break;
3139         case MC_CG_ARB_FREQ_F3:
3140                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3141                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3142                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3143                 break;
3144         default:
3145                 return -EINVAL;
3146         }
3147
3148         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3149         WREG32(MC_CG_CONFIG, mc_cg_config);
3150         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3151
3152         return 0;
3153 }
3154
3155 static void ni_update_current_ps(struct amdgpu_device *adev,
3156                           struct amdgpu_ps *rps)
3157 {
3158         struct si_ps *new_ps = si_get_ps(rps);
3159         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3160         struct ni_power_info *ni_pi = ni_get_pi(adev);
3161
3162         eg_pi->current_rps = *rps;
3163         ni_pi->current_ps = *new_ps;
3164         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3165 }
3166
3167 static void ni_update_requested_ps(struct amdgpu_device *adev,
3168                             struct amdgpu_ps *rps)
3169 {
3170         struct si_ps *new_ps = si_get_ps(rps);
3171         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3172         struct ni_power_info *ni_pi = ni_get_pi(adev);
3173
3174         eg_pi->requested_rps = *rps;
3175         ni_pi->requested_ps = *new_ps;
3176         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3177 }
3178
3179 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3180                                            struct amdgpu_ps *new_ps,
3181                                            struct amdgpu_ps *old_ps)
3182 {
3183         struct si_ps *new_state = si_get_ps(new_ps);
3184         struct si_ps *current_state = si_get_ps(old_ps);
3185
3186         if ((new_ps->vclk == old_ps->vclk) &&
3187             (new_ps->dclk == old_ps->dclk))
3188                 return;
3189
3190         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3191             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3192                 return;
3193
3194         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3195 }
3196
3197 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3198                                           struct amdgpu_ps *new_ps,
3199                                           struct amdgpu_ps *old_ps)
3200 {
3201         struct si_ps *new_state = si_get_ps(new_ps);
3202         struct si_ps *current_state = si_get_ps(old_ps);
3203
3204         if ((new_ps->vclk == old_ps->vclk) &&
3205             (new_ps->dclk == old_ps->dclk))
3206                 return;
3207
3208         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3209             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3210                 return;
3211
3212         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3213 }
3214
3215 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3216 {
3217         unsigned int i;
3218
3219         for (i = 0; i < table->count; i++)
3220                 if (voltage <= table->entries[i].value)
3221                         return table->entries[i].value;
3222
3223         return table->entries[table->count - 1].value;
3224 }
3225
3226 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3227                                 u32 max_clock, u32 requested_clock)
3228 {
3229         unsigned int i;
3230
3231         if ((clocks == NULL) || (clocks->count == 0))
3232                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3233
3234         for (i = 0; i < clocks->count; i++) {
3235                 if (clocks->values[i] >= requested_clock)
3236                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3237         }
3238
3239         return (clocks->values[clocks->count - 1] < max_clock) ?
3240                 clocks->values[clocks->count - 1] : max_clock;
3241 }
3242
3243 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3244                               u32 max_mclk, u32 requested_mclk)
3245 {
3246         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3247                                     max_mclk, requested_mclk);
3248 }
3249
3250 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3251                               u32 max_sclk, u32 requested_sclk)
3252 {
3253         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3254                                     max_sclk, requested_sclk);
3255 }
3256
3257 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3258                                                             u32 *max_clock)
3259 {
3260         u32 i, clock = 0;
3261
3262         if ((table == NULL) || (table->count == 0)) {
3263                 *max_clock = clock;
3264                 return;
3265         }
3266
3267         for (i = 0; i < table->count; i++) {
3268                 if (clock < table->entries[i].clk)
3269                         clock = table->entries[i].clk;
3270         }
3271         *max_clock = clock;
3272 }
3273
3274 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3275                                                u32 clock, u16 max_voltage, u16 *voltage)
3276 {
3277         u32 i;
3278
3279         if ((table == NULL) || (table->count == 0))
3280                 return;
3281
3282         for (i= 0; i < table->count; i++) {
3283                 if (clock <= table->entries[i].clk) {
3284                         if (*voltage < table->entries[i].v)
3285                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3286                                            table->entries[i].v : max_voltage);
3287                         return;
3288                 }
3289         }
3290
3291         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3292 }
3293
3294 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3295                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3296                                           struct rv7xx_pl *pl)
3297 {
3298
3299         if ((pl->mclk == 0) || (pl->sclk == 0))
3300                 return;
3301
3302         if (pl->mclk == pl->sclk)
3303                 return;
3304
3305         if (pl->mclk > pl->sclk) {
3306                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3307                         pl->sclk = btc_get_valid_sclk(adev,
3308                                                       max_limits->sclk,
3309                                                       (pl->mclk +
3310                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3311                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3312         } else {
3313                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3314                         pl->mclk = btc_get_valid_mclk(adev,
3315                                                       max_limits->mclk,
3316                                                       pl->sclk -
3317                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3318         }
3319 }
3320
3321 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3322                                           u16 max_vddc, u16 max_vddci,
3323                                           u16 *vddc, u16 *vddci)
3324 {
3325         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3326         u16 new_voltage;
3327
3328         if ((0 == *vddc) || (0 == *vddci))
3329                 return;
3330
3331         if (*vddc > *vddci) {
3332                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3333                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3334                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3335                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3336                 }
3337         } else {
3338                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3339                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3340                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3341                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3342                 }
3343         }
3344 }
3345
3346 static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3347                                                u32 sys_mask,
3348                                                enum amdgpu_pcie_gen asic_gen,
3349                                                enum amdgpu_pcie_gen default_gen)
3350 {
3351         switch (asic_gen) {
3352         case AMDGPU_PCIE_GEN1:
3353                 return AMDGPU_PCIE_GEN1;
3354         case AMDGPU_PCIE_GEN2:
3355                 return AMDGPU_PCIE_GEN2;
3356         case AMDGPU_PCIE_GEN3:
3357                 return AMDGPU_PCIE_GEN3;
3358         default:
3359                 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3360                         return AMDGPU_PCIE_GEN3;
3361                 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3362                         return AMDGPU_PCIE_GEN2;
3363                 else
3364                         return AMDGPU_PCIE_GEN1;
3365         }
3366         return AMDGPU_PCIE_GEN1;
3367 }
3368
3369 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3370                             u32 *p, u32 *u)
3371 {
3372         u32 b_c = 0;
3373         u32 i_c;
3374         u32 tmp;
3375
3376         i_c = (i * r_c) / 100;
3377         tmp = i_c >> p_b;
3378
3379         while (tmp) {
3380                 b_c++;
3381                 tmp >>= 1;
3382         }
3383
3384         *u = (b_c + 1) / 2;
3385         *p = i_c / (1 << (2 * (*u)));
3386 }
3387
3388 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3389 {
3390         u32 k, a, ah, al;
3391         u32 t1;
3392
3393         if ((fl == 0) || (fh == 0) || (fl > fh))
3394                 return -EINVAL;
3395
3396         k = (100 * fh) / fl;
3397         t1 = (t * (k - 100));
3398         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3399         a = (a + 5) / 10;
3400         ah = ((a * t) + 5000) / 10000;
3401         al = a - ah;
3402
3403         *th = t - ah;
3404         *tl = t + al;
3405
3406         return 0;
3407 }
3408
3409 static bool r600_is_uvd_state(u32 class, u32 class2)
3410 {
3411         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3412                 return true;
3413         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3414                 return true;
3415         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3416                 return true;
3417         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3418                 return true;
3419         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3420                 return true;
3421         return false;
3422 }
3423
3424 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3425 {
3426         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3427 }
3428
3429 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3430 {
3431         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3432         u16 vddc;
3433
3434         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3435                 pi->max_vddc = 0;
3436         else
3437                 pi->max_vddc = vddc;
3438 }
3439
3440 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3441 {
3442         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3443         struct amdgpu_atom_ss ss;
3444
3445         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3446                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3447         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3448                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3449
3450         if (pi->sclk_ss || pi->mclk_ss)
3451                 pi->dynamic_ss = true;
3452         else
3453                 pi->dynamic_ss = false;
3454 }
3455
3456
3457 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3458                                         struct amdgpu_ps *rps)
3459 {
3460         struct  si_ps *ps = si_get_ps(rps);
3461         struct amdgpu_clock_and_voltage_limits *max_limits;
3462         bool disable_mclk_switching = false;
3463         bool disable_sclk_switching = false;
3464         u32 mclk, sclk;
3465         u16 vddc, vddci, min_vce_voltage = 0;
3466         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3467         u32 max_sclk = 0, max_mclk = 0;
3468         int i;
3469         struct si_dpm_quirk *p = si_dpm_quirk_list;
3470
3471         /* limit all SI kickers */
3472         if (adev->asic_type == CHIP_PITCAIRN) {
3473                 if ((adev->pdev->revision == 0x81) ||
3474                     (adev->pdev->device == 0x6810) ||
3475                     (adev->pdev->device == 0x6811) ||
3476                     (adev->pdev->device == 0x6816) ||
3477                     (adev->pdev->device == 0x6817) ||
3478                     (adev->pdev->device == 0x6806))
3479                         max_mclk = 120000;
3480         } else if (adev->asic_type == CHIP_OLAND) {
3481                 if ((adev->pdev->revision == 0xC7) ||
3482                     (adev->pdev->revision == 0x80) ||
3483                     (adev->pdev->revision == 0x81) ||
3484                     (adev->pdev->revision == 0x83) ||
3485                     (adev->pdev->revision == 0x87) ||
3486                     (adev->pdev->device == 0x6604) ||
3487                     (adev->pdev->device == 0x6605)) {
3488                         max_sclk = 75000;
3489                         max_mclk = 80000;
3490                 }
3491         } else if (adev->asic_type == CHIP_HAINAN) {
3492                 if ((adev->pdev->revision == 0x81) ||
3493                     (adev->pdev->revision == 0x83) ||
3494                     (adev->pdev->revision == 0xC3) ||
3495                     (adev->pdev->device == 0x6664) ||
3496                     (adev->pdev->device == 0x6665) ||
3497                     (adev->pdev->device == 0x6667)) {
3498                         max_sclk = 75000;
3499                         max_mclk = 80000;
3500                 }
3501                 if ((adev->pdev->revision == 0xC3) ||
3502                     (adev->pdev->device == 0x6665)) {
3503                         max_sclk = 60000;
3504                         max_mclk = 80000;
3505                 }
3506         } else if (adev->asic_type == CHIP_OLAND) {
3507                 if ((adev->pdev->revision == 0xC7) ||
3508                     (adev->pdev->revision == 0x80) ||
3509                     (adev->pdev->revision == 0x81) ||
3510                     (adev->pdev->revision == 0x83) ||
3511                     (adev->pdev->revision == 0x87) ||
3512                     (adev->pdev->device == 0x6604) ||
3513                     (adev->pdev->device == 0x6605)) {
3514                         max_sclk = 75000;
3515                 }
3516         }
3517         /* Apply dpm quirks */
3518         while (p && p->chip_device != 0) {
3519                 if (adev->pdev->vendor == p->chip_vendor &&
3520                     adev->pdev->device == p->chip_device &&
3521                     adev->pdev->subsystem_vendor == p->subsys_vendor &&
3522                     adev->pdev->subsystem_device == p->subsys_device) {
3523                         max_sclk = p->max_sclk;
3524                         max_mclk = p->max_mclk;
3525                         break;
3526                 }
3527                 ++p;
3528         }
3529
3530         if (rps->vce_active) {
3531                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3532                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3533                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3534                                          &min_vce_voltage);
3535         } else {
3536                 rps->evclk = 0;
3537                 rps->ecclk = 0;
3538         }
3539
3540         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3541             si_dpm_vblank_too_short(adev))
3542                 disable_mclk_switching = true;
3543
3544         if (rps->vclk || rps->dclk) {
3545                 disable_mclk_switching = true;
3546                 disable_sclk_switching = true;
3547         }
3548
3549         if (adev->pm.dpm.ac_power)
3550                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3551         else
3552                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3553
3554         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3555                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3556                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3557         }
3558         if (adev->pm.dpm.ac_power == false) {
3559                 for (i = 0; i < ps->performance_level_count; i++) {
3560                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3561                                 ps->performance_levels[i].mclk = max_limits->mclk;
3562                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3563                                 ps->performance_levels[i].sclk = max_limits->sclk;
3564                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3565                                 ps->performance_levels[i].vddc = max_limits->vddc;
3566                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3567                                 ps->performance_levels[i].vddci = max_limits->vddci;
3568                 }
3569         }
3570
3571         /* limit clocks to max supported clocks based on voltage dependency tables */
3572         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3573                                                         &max_sclk_vddc);
3574         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3575                                                         &max_mclk_vddci);
3576         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3577                                                         &max_mclk_vddc);
3578
3579         for (i = 0; i < ps->performance_level_count; i++) {
3580                 if (max_sclk_vddc) {
3581                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3582                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3583                 }
3584                 if (max_mclk_vddci) {
3585                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3586                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3587                 }
3588                 if (max_mclk_vddc) {
3589                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3590                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3591                 }
3592                 if (max_mclk) {
3593                         if (ps->performance_levels[i].mclk > max_mclk)
3594                                 ps->performance_levels[i].mclk = max_mclk;
3595                 }
3596                 if (max_sclk) {
3597                         if (ps->performance_levels[i].sclk > max_sclk)
3598                                 ps->performance_levels[i].sclk = max_sclk;
3599                 }
3600         }
3601
3602         /* XXX validate the min clocks required for display */
3603
3604         if (disable_mclk_switching) {
3605                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3606                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3607         } else {
3608                 mclk = ps->performance_levels[0].mclk;
3609                 vddci = ps->performance_levels[0].vddci;
3610         }
3611
3612         if (disable_sclk_switching) {
3613                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3614                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3615         } else {
3616                 sclk = ps->performance_levels[0].sclk;
3617                 vddc = ps->performance_levels[0].vddc;
3618         }
3619
3620         if (rps->vce_active) {
3621                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3622                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3623                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3624                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3625         }
3626
3627         /* adjusted low state */
3628         ps->performance_levels[0].sclk = sclk;
3629         ps->performance_levels[0].mclk = mclk;
3630         ps->performance_levels[0].vddc = vddc;
3631         ps->performance_levels[0].vddci = vddci;
3632
3633         if (disable_sclk_switching) {
3634                 sclk = ps->performance_levels[0].sclk;
3635                 for (i = 1; i < ps->performance_level_count; i++) {
3636                         if (sclk < ps->performance_levels[i].sclk)
3637                                 sclk = ps->performance_levels[i].sclk;
3638                 }
3639                 for (i = 0; i < ps->performance_level_count; i++) {
3640                         ps->performance_levels[i].sclk = sclk;
3641                         ps->performance_levels[i].vddc = vddc;
3642                 }
3643         } else {
3644                 for (i = 1; i < ps->performance_level_count; i++) {
3645                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3646                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3647                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3648                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3649                 }
3650         }
3651
3652         if (disable_mclk_switching) {
3653                 mclk = ps->performance_levels[0].mclk;
3654                 for (i = 1; i < ps->performance_level_count; i++) {
3655                         if (mclk < ps->performance_levels[i].mclk)
3656                                 mclk = ps->performance_levels[i].mclk;
3657                 }
3658                 for (i = 0; i < ps->performance_level_count; i++) {
3659                         ps->performance_levels[i].mclk = mclk;
3660                         ps->performance_levels[i].vddci = vddci;
3661                 }
3662         } else {
3663                 for (i = 1; i < ps->performance_level_count; i++) {
3664                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3665                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3666                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3667                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3668                 }
3669         }
3670
3671         for (i = 0; i < ps->performance_level_count; i++)
3672                 btc_adjust_clock_combinations(adev, max_limits,
3673                                               &ps->performance_levels[i]);
3674
3675         for (i = 0; i < ps->performance_level_count; i++) {
3676                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3677                         ps->performance_levels[i].vddc = min_vce_voltage;
3678                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3679                                                    ps->performance_levels[i].sclk,
3680                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3681                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3682                                                    ps->performance_levels[i].mclk,
3683                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3684                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3685                                                    ps->performance_levels[i].mclk,
3686                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3687                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3688                                                    adev->clock.current_dispclk,
3689                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3690         }
3691
3692         for (i = 0; i < ps->performance_level_count; i++) {
3693                 btc_apply_voltage_delta_rules(adev,
3694                                               max_limits->vddc, max_limits->vddci,
3695                                               &ps->performance_levels[i].vddc,
3696                                               &ps->performance_levels[i].vddci);
3697         }
3698
3699         ps->dc_compatible = true;
3700         for (i = 0; i < ps->performance_level_count; i++) {
3701                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3702                         ps->dc_compatible = false;
3703         }
3704 }
3705
3706 #if 0
3707 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3708                                      u16 reg_offset, u32 *value)
3709 {
3710         struct si_power_info *si_pi = si_get_pi(adev);
3711
3712         return amdgpu_si_read_smc_sram_dword(adev,
3713                                              si_pi->soft_regs_start + reg_offset, value,
3714                                              si_pi->sram_end);
3715 }
3716 #endif
3717
3718 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3719                                       u16 reg_offset, u32 value)
3720 {
3721         struct si_power_info *si_pi = si_get_pi(adev);
3722
3723         return amdgpu_si_write_smc_sram_dword(adev,
3724                                               si_pi->soft_regs_start + reg_offset,
3725                                               value, si_pi->sram_end);
3726 }
3727
3728 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3729 {
3730         bool ret = false;
3731         u32 tmp, width, row, column, bank, density;
3732         bool is_memory_gddr5, is_special;
3733
3734         tmp = RREG32(MC_SEQ_MISC0);
3735         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3736         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3737                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3738
3739         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3740         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3741
3742         tmp = RREG32(MC_ARB_RAMCFG);
3743         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3744         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3745         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3746
3747         density = (1 << (row + column - 20 + bank)) * width;
3748
3749         if ((adev->pdev->device == 0x6819) &&
3750             is_memory_gddr5 && is_special && (density == 0x400))
3751                 ret = true;
3752
3753         return ret;
3754 }
3755
3756 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3757 {
3758         struct si_power_info *si_pi = si_get_pi(adev);
3759         u16 vddc, count = 0;
3760         int i, ret;
3761
3762         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3763                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3764
3765                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3766                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3767                         si_pi->leakage_voltage.entries[count].leakage_index =
3768                                 SISLANDS_LEAKAGE_INDEX0 + i;
3769                         count++;
3770                 }
3771         }
3772         si_pi->leakage_voltage.count = count;
3773 }
3774
3775 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3776                                                      u32 index, u16 *leakage_voltage)
3777 {
3778         struct si_power_info *si_pi = si_get_pi(adev);
3779         int i;
3780
3781         if (leakage_voltage == NULL)
3782                 return -EINVAL;
3783
3784         if ((index & 0xff00) != 0xff00)
3785                 return -EINVAL;
3786
3787         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3788                 return -EINVAL;
3789
3790         if (index < SISLANDS_LEAKAGE_INDEX0)
3791                 return -EINVAL;
3792
3793         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3794                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3795                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3796                         return 0;
3797                 }
3798         }
3799         return -EAGAIN;
3800 }
3801
3802 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3803 {
3804         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3805         bool want_thermal_protection;
3806         enum amdgpu_dpm_event_src dpm_event_src;
3807
3808         switch (sources) {
3809         case 0:
3810         default:
3811                 want_thermal_protection = false;
3812                 break;
3813         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3814                 want_thermal_protection = true;
3815                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3816                 break;
3817         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3818                 want_thermal_protection = true;
3819                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3820                 break;
3821         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3822               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3823                 want_thermal_protection = true;
3824                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3825                 break;
3826         }
3827
3828         if (want_thermal_protection) {
3829                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3830                 if (pi->thermal_protection)
3831                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3832         } else {
3833                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3834         }
3835 }
3836
3837 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3838                                            enum amdgpu_dpm_auto_throttle_src source,
3839                                            bool enable)
3840 {
3841         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3842
3843         if (enable) {
3844                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3845                         pi->active_auto_throttle_sources |= 1 << source;
3846                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3847                 }
3848         } else {
3849                 if (pi->active_auto_throttle_sources & (1 << source)) {
3850                         pi->active_auto_throttle_sources &= ~(1 << source);
3851                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3852                 }
3853         }
3854 }
3855
3856 static void si_start_dpm(struct amdgpu_device *adev)
3857 {
3858         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3859 }
3860
3861 static void si_stop_dpm(struct amdgpu_device *adev)
3862 {
3863         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3864 }
3865
3866 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3867 {
3868         if (enable)
3869                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3870         else
3871                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3872
3873 }
3874
3875 #if 0
3876 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3877                                                u32 thermal_level)
3878 {
3879         PPSMC_Result ret;
3880
3881         if (thermal_level == 0) {
3882                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3883                 if (ret == PPSMC_Result_OK)
3884                         return 0;
3885                 else
3886                         return -EINVAL;
3887         }
3888         return 0;
3889 }
3890
3891 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3892 {
3893         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3894 }
3895 #endif
3896
3897 #if 0
3898 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3899 {
3900         if (ac_power)
3901                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3902                         0 : -EINVAL;
3903
3904         return 0;
3905 }
3906 #endif
3907
3908 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3909                                                       PPSMC_Msg msg, u32 parameter)
3910 {
3911         WREG32(SMC_SCRATCH0, parameter);
3912         return amdgpu_si_send_msg_to_smc(adev, msg);
3913 }
3914
3915 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3916 {
3917         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3918                 return -EINVAL;
3919
3920         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3921                 0 : -EINVAL;
3922 }
3923
3924 static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3925                                    enum amdgpu_dpm_forced_level level)
3926 {
3927         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3928         struct  si_ps *ps = si_get_ps(rps);
3929         u32 levels = ps->performance_level_count;
3930
3931         if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3932                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3933                         return -EINVAL;
3934
3935                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3936                         return -EINVAL;
3937         } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3938                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3939                         return -EINVAL;
3940
3941                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3942                         return -EINVAL;
3943         } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3944                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3945                         return -EINVAL;
3946
3947                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3948                         return -EINVAL;
3949         }
3950
3951         adev->pm.dpm.forced_level = level;
3952
3953         return 0;
3954 }
3955
3956 #if 0
3957 static int si_set_boot_state(struct amdgpu_device *adev)
3958 {
3959         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3960                 0 : -EINVAL;
3961 }
3962 #endif
3963
3964 static int si_set_sw_state(struct amdgpu_device *adev)
3965 {
3966         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3967                 0 : -EINVAL;
3968 }
3969
3970 static int si_halt_smc(struct amdgpu_device *adev)
3971 {
3972         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3973                 return -EINVAL;
3974
3975         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3976                 0 : -EINVAL;
3977 }
3978
3979 static int si_resume_smc(struct amdgpu_device *adev)
3980 {
3981         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3982                 return -EINVAL;
3983
3984         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3985                 0 : -EINVAL;
3986 }
3987
3988 static void si_dpm_start_smc(struct amdgpu_device *adev)
3989 {
3990         amdgpu_si_program_jump_on_start(adev);
3991         amdgpu_si_start_smc(adev);
3992         amdgpu_si_smc_clock(adev, true);
3993 }
3994
3995 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3996 {
3997         amdgpu_si_reset_smc(adev);
3998         amdgpu_si_smc_clock(adev, false);
3999 }
4000
4001 static int si_process_firmware_header(struct amdgpu_device *adev)
4002 {
4003         struct si_power_info *si_pi = si_get_pi(adev);
4004         u32 tmp;
4005         int ret;
4006
4007         ret = amdgpu_si_read_smc_sram_dword(adev,
4008                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4009                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
4010                                             &tmp, si_pi->sram_end);
4011         if (ret)
4012                 return ret;
4013
4014         si_pi->state_table_start = tmp;
4015
4016         ret = amdgpu_si_read_smc_sram_dword(adev,
4017                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4018                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4019                                             &tmp, si_pi->sram_end);
4020         if (ret)
4021                 return ret;
4022
4023         si_pi->soft_regs_start = tmp;
4024
4025         ret = amdgpu_si_read_smc_sram_dword(adev,
4026                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4027                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4028                                             &tmp, si_pi->sram_end);
4029         if (ret)
4030                 return ret;
4031
4032         si_pi->mc_reg_table_start = tmp;
4033
4034         ret = amdgpu_si_read_smc_sram_dword(adev,
4035                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4036                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4037                                             &tmp, si_pi->sram_end);
4038         if (ret)
4039                 return ret;
4040
4041         si_pi->fan_table_start = tmp;
4042
4043         ret = amdgpu_si_read_smc_sram_dword(adev,
4044                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4045                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4046                                             &tmp, si_pi->sram_end);
4047         if (ret)
4048                 return ret;
4049
4050         si_pi->arb_table_start = tmp;
4051
4052         ret = amdgpu_si_read_smc_sram_dword(adev,
4053                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4054                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4055                                             &tmp, si_pi->sram_end);
4056         if (ret)
4057                 return ret;
4058
4059         si_pi->cac_table_start = tmp;
4060
4061         ret = amdgpu_si_read_smc_sram_dword(adev,
4062                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4063                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4064                                             &tmp, si_pi->sram_end);
4065         if (ret)
4066                 return ret;
4067
4068         si_pi->dte_table_start = tmp;
4069
4070         ret = amdgpu_si_read_smc_sram_dword(adev,
4071                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4072                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4073                                             &tmp, si_pi->sram_end);
4074         if (ret)
4075                 return ret;
4076
4077         si_pi->spll_table_start = tmp;
4078
4079         ret = amdgpu_si_read_smc_sram_dword(adev,
4080                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4081                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4082                                             &tmp, si_pi->sram_end);
4083         if (ret)
4084                 return ret;
4085
4086         si_pi->papm_cfg_table_start = tmp;
4087
4088         return ret;
4089 }
4090
4091 static void si_read_clock_registers(struct amdgpu_device *adev)
4092 {
4093         struct si_power_info *si_pi = si_get_pi(adev);
4094
4095         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4096         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4097         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4098         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4099         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4100         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4101         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4102         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4103         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4104         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4105         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4106         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4107         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4108         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4109         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4110 }
4111
4112 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4113                                           bool enable)
4114 {
4115         if (enable)
4116                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4117         else
4118                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4119 }
4120
4121 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4122 {
4123         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4124 }
4125
4126 #if 0
4127 static int si_enter_ulp_state(struct amdgpu_device *adev)
4128 {
4129         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4130
4131         udelay(25000);
4132
4133         return 0;
4134 }
4135
4136 static int si_exit_ulp_state(struct amdgpu_device *adev)
4137 {
4138         int i;
4139
4140         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4141
4142         udelay(7000);
4143
4144         for (i = 0; i < adev->usec_timeout; i++) {
4145                 if (RREG32(SMC_RESP_0) == 1)
4146                         break;
4147                 udelay(1000);
4148         }
4149
4150         return 0;
4151 }
4152 #endif
4153
4154 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4155                                      bool has_display)
4156 {
4157         PPSMC_Msg msg = has_display ?
4158                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4159
4160         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4161                 0 : -EINVAL;
4162 }
4163
4164 static void si_program_response_times(struct amdgpu_device *adev)
4165 {
4166         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4167         u32 vddc_dly, acpi_dly, vbi_dly;
4168         u32 reference_clock;
4169
4170         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4171
4172         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4173         backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4174
4175         if (voltage_response_time == 0)
4176                 voltage_response_time = 1000;
4177
4178         acpi_delay_time = 15000;
4179         vbi_time_out = 100000;
4180
4181         reference_clock = amdgpu_asic_get_xclk(adev);
4182
4183         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4184         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4185         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4186
4187         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4188         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4189         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4190         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4191 }
4192
4193 static void si_program_ds_registers(struct amdgpu_device *adev)
4194 {
4195         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4196         u32 tmp;
4197
4198         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4199         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4200                 tmp = 0x10;
4201         else
4202                 tmp = 0x1;
4203
4204         if (eg_pi->sclk_deep_sleep) {
4205                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4206                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4207                          ~AUTOSCALE_ON_SS_CLEAR);
4208         }
4209 }
4210
4211 static void si_program_display_gap(struct amdgpu_device *adev)
4212 {
4213         u32 tmp, pipe;
4214         int i;
4215
4216         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4217         if (adev->pm.dpm.new_active_crtc_count > 0)
4218                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4219         else
4220                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4221
4222         if (adev->pm.dpm.new_active_crtc_count > 1)
4223                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4224         else
4225                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4226
4227         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4228
4229         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4230         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4231
4232         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4233             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4234                 /* find the first active crtc */
4235                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4236                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4237                                 break;
4238                 }
4239                 if (i == adev->mode_info.num_crtc)
4240                         pipe = 0;
4241                 else
4242                         pipe = i;
4243
4244                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4245                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4246                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4247         }
4248
4249         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4250          * This can be a problem on PowerXpress systems or if you want to use the card
4251          * for offscreen rendering or compute if there are no crtcs enabled.
4252          */
4253         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4254 }
4255
4256 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4257 {
4258         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4259
4260         if (enable) {
4261                 if (pi->sclk_ss)
4262                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4263         } else {
4264                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4265                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4266         }
4267 }
4268
4269 static void si_setup_bsp(struct amdgpu_device *adev)
4270 {
4271         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4272         u32 xclk = amdgpu_asic_get_xclk(adev);
4273
4274         r600_calculate_u_and_p(pi->asi,
4275                                xclk,
4276                                16,
4277                                &pi->bsp,
4278                                &pi->bsu);
4279
4280         r600_calculate_u_and_p(pi->pasi,
4281                                xclk,
4282                                16,
4283                                &pi->pbsp,
4284                                &pi->pbsu);
4285
4286
4287         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4288         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4289
4290         WREG32(CG_BSP, pi->dsp);
4291 }
4292
4293 static void si_program_git(struct amdgpu_device *adev)
4294 {
4295         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4296 }
4297
4298 static void si_program_tp(struct amdgpu_device *adev)
4299 {
4300         int i;
4301         enum r600_td td = R600_TD_DFLT;
4302
4303         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4304                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4305
4306         if (td == R600_TD_AUTO)
4307                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4308         else
4309                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4310
4311         if (td == R600_TD_UP)
4312                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4313
4314         if (td == R600_TD_DOWN)
4315                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4316 }
4317
4318 static void si_program_tpp(struct amdgpu_device *adev)
4319 {
4320         WREG32(CG_TPC, R600_TPC_DFLT);
4321 }
4322
4323 static void si_program_sstp(struct amdgpu_device *adev)
4324 {
4325         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4326 }
4327
4328 static void si_enable_display_gap(struct amdgpu_device *adev)
4329 {
4330         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4331
4332         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4333         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4334                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4335
4336         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4337         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4338                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4339         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4340 }
4341
4342 static void si_program_vc(struct amdgpu_device *adev)
4343 {
4344         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4345
4346         WREG32(CG_FTV, pi->vrc);
4347 }
4348
4349 static void si_clear_vc(struct amdgpu_device *adev)
4350 {
4351         WREG32(CG_FTV, 0);
4352 }
4353
4354 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4355 {
4356         u8 mc_para_index;
4357
4358         if (memory_clock < 10000)
4359                 mc_para_index = 0;
4360         else if (memory_clock >= 80000)
4361                 mc_para_index = 0x0f;
4362         else
4363                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4364         return mc_para_index;
4365 }
4366
4367 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4368 {
4369         u8 mc_para_index;
4370
4371         if (strobe_mode) {
4372                 if (memory_clock < 12500)
4373                         mc_para_index = 0x00;
4374                 else if (memory_clock > 47500)
4375                         mc_para_index = 0x0f;
4376                 else
4377                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4378         } else {
4379                 if (memory_clock < 65000)
4380                         mc_para_index = 0x00;
4381                 else if (memory_clock > 135000)
4382                         mc_para_index = 0x0f;
4383                 else
4384                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4385         }
4386         return mc_para_index;
4387 }
4388
4389 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4390 {
4391         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4392         bool strobe_mode = false;
4393         u8 result = 0;
4394
4395         if (mclk <= pi->mclk_strobe_mode_threshold)
4396                 strobe_mode = true;
4397
4398         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4399                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4400         else
4401                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4402
4403         if (strobe_mode)
4404                 result |= SISLANDS_SMC_STROBE_ENABLE;
4405
4406         return result;
4407 }
4408
4409 static int si_upload_firmware(struct amdgpu_device *adev)
4410 {
4411         struct si_power_info *si_pi = si_get_pi(adev);
4412
4413         amdgpu_si_reset_smc(adev);
4414         amdgpu_si_smc_clock(adev, false);
4415
4416         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4417 }
4418
4419 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4420                                               const struct atom_voltage_table *table,
4421                                               const struct amdgpu_phase_shedding_limits_table *limits)
4422 {
4423         u32 data, num_bits, num_levels;
4424
4425         if ((table == NULL) || (limits == NULL))
4426                 return false;
4427
4428         data = table->mask_low;
4429
4430         num_bits = hweight32(data);
4431
4432         if (num_bits == 0)
4433                 return false;
4434
4435         num_levels = (1 << num_bits);
4436
4437         if (table->count != num_levels)
4438                 return false;
4439
4440         if (limits->count != (num_levels - 1))
4441                 return false;
4442
4443         return true;
4444 }
4445
4446 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4447                                               u32 max_voltage_steps,
4448                                               struct atom_voltage_table *voltage_table)
4449 {
4450         unsigned int i, diff;
4451
4452         if (voltage_table->count <= max_voltage_steps)
4453                 return;
4454
4455         diff = voltage_table->count - max_voltage_steps;
4456
4457         for (i= 0; i < max_voltage_steps; i++)
4458                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4459
4460         voltage_table->count = max_voltage_steps;
4461 }
4462
4463 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4464                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4465                                      struct atom_voltage_table *voltage_table)
4466 {
4467         u32 i;
4468
4469         if (voltage_dependency_table == NULL)
4470                 return -EINVAL;
4471
4472         voltage_table->mask_low = 0;
4473         voltage_table->phase_delay = 0;
4474
4475         voltage_table->count = voltage_dependency_table->count;
4476         for (i = 0; i < voltage_table->count; i++) {
4477                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4478                 voltage_table->entries[i].smio_low = 0;
4479         }
4480
4481         return 0;
4482 }
4483
4484 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4485 {
4486         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4487         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4488         struct si_power_info *si_pi = si_get_pi(adev);
4489         int ret;
4490
4491         if (pi->voltage_control) {
4492                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4493                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4494                 if (ret)
4495                         return ret;
4496
4497                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4498                         si_trim_voltage_table_to_fit_state_table(adev,
4499                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4500                                                                  &eg_pi->vddc_voltage_table);
4501         } else if (si_pi->voltage_control_svi2) {
4502                 ret = si_get_svi2_voltage_table(adev,
4503                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4504                                                 &eg_pi->vddc_voltage_table);
4505                 if (ret)
4506                         return ret;
4507         } else {
4508                 return -EINVAL;
4509         }
4510
4511         if (eg_pi->vddci_control) {
4512                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4513                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4514                 if (ret)
4515                         return ret;
4516
4517                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4518                         si_trim_voltage_table_to_fit_state_table(adev,
4519                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4520                                                                  &eg_pi->vddci_voltage_table);
4521         }
4522         if (si_pi->vddci_control_svi2) {
4523                 ret = si_get_svi2_voltage_table(adev,
4524                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4525                                                 &eg_pi->vddci_voltage_table);
4526                 if (ret)
4527                         return ret;
4528         }
4529
4530         if (pi->mvdd_control) {
4531                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4532                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4533
4534                 if (ret) {
4535                         pi->mvdd_control = false;
4536                         return ret;
4537                 }
4538
4539                 if (si_pi->mvdd_voltage_table.count == 0) {
4540                         pi->mvdd_control = false;
4541                         return -EINVAL;
4542                 }
4543
4544                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4545                         si_trim_voltage_table_to_fit_state_table(adev,
4546                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4547                                                                  &si_pi->mvdd_voltage_table);
4548         }
4549
4550         if (si_pi->vddc_phase_shed_control) {
4551                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4552                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4553                 if (ret)
4554                         si_pi->vddc_phase_shed_control = false;
4555
4556                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4557                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4558                         si_pi->vddc_phase_shed_control = false;
4559         }
4560
4561         return 0;
4562 }
4563
4564 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4565                                           const struct atom_voltage_table *voltage_table,
4566                                           SISLANDS_SMC_STATETABLE *table)
4567 {
4568         unsigned int i;
4569
4570         for (i = 0; i < voltage_table->count; i++)
4571                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4572 }
4573
4574 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4575                                           SISLANDS_SMC_STATETABLE *table)
4576 {
4577         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4578         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4579         struct si_power_info *si_pi = si_get_pi(adev);
4580         u8 i;
4581
4582         if (si_pi->voltage_control_svi2) {
4583                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4584                         si_pi->svc_gpio_id);
4585                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4586                         si_pi->svd_gpio_id);
4587                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4588                                            2);
4589         } else {
4590                 if (eg_pi->vddc_voltage_table.count) {
4591                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4592                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4593                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4594
4595                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4596                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4597                                         table->maxVDDCIndexInPPTable = i;
4598                                         break;
4599                                 }
4600                         }
4601                 }
4602
4603                 if (eg_pi->vddci_voltage_table.count) {
4604                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4605
4606                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4607                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4608                 }
4609
4610
4611                 if (si_pi->mvdd_voltage_table.count) {
4612                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4613
4614                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4615                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4616                 }
4617
4618                 if (si_pi->vddc_phase_shed_control) {
4619                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4620                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4621                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4622
4623                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4624                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4625
4626                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4627                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4628                         } else {
4629                                 si_pi->vddc_phase_shed_control = false;
4630                         }
4631                 }
4632         }
4633
4634         return 0;
4635 }
4636
4637 static int si_populate_voltage_value(struct amdgpu_device *adev,
4638                                      const struct atom_voltage_table *table,
4639                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4640 {
4641         unsigned int i;
4642
4643         for (i = 0; i < table->count; i++) {
4644                 if (value <= table->entries[i].value) {
4645                         voltage->index = (u8)i;
4646                         voltage->value = cpu_to_be16(table->entries[i].value);
4647                         break;
4648                 }
4649         }
4650
4651         if (i >= table->count)
4652                 return -EINVAL;
4653
4654         return 0;
4655 }
4656
4657 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4658                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4659 {
4660         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4661         struct si_power_info *si_pi = si_get_pi(adev);
4662
4663         if (pi->mvdd_control) {
4664                 if (mclk <= pi->mvdd_split_frequency)
4665                         voltage->index = 0;
4666                 else
4667                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4668
4669                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4670         }
4671         return 0;
4672 }
4673
4674 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4675                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4676                                     u16 *std_voltage)
4677 {
4678         u16 v_index;
4679         bool voltage_found = false;
4680         *std_voltage = be16_to_cpu(voltage->value);
4681
4682         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4683                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4684                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4685                                 return -EINVAL;
4686
4687                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4688                                 if (be16_to_cpu(voltage->value) ==
4689                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4690                                         voltage_found = true;
4691                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4692                                                 *std_voltage =
4693                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4694                                         else
4695                                                 *std_voltage =
4696                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4697                                         break;
4698                                 }
4699                         }
4700
4701                         if (!voltage_found) {
4702                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4703                                         if (be16_to_cpu(voltage->value) <=
4704                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4705                                                 voltage_found = true;
4706                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4707                                                         *std_voltage =
4708                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4709                                                 else
4710                                                         *std_voltage =
4711                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4712                                                 break;
4713                                         }
4714                                 }
4715                         }
4716                 } else {
4717                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4718                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4719                 }
4720         }
4721
4722         return 0;
4723 }
4724
4725 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4726                                          u16 value, u8 index,
4727                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4728 {
4729         voltage->index = index;
4730         voltage->value = cpu_to_be16(value);
4731
4732         return 0;
4733 }
4734
4735 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4736                                             const struct amdgpu_phase_shedding_limits_table *limits,
4737                                             u16 voltage, u32 sclk, u32 mclk,
4738                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4739 {
4740         unsigned int i;
4741
4742         for (i = 0; i < limits->count; i++) {
4743                 if ((voltage <= limits->entries[i].voltage) &&
4744                     (sclk <= limits->entries[i].sclk) &&
4745                     (mclk <= limits->entries[i].mclk))
4746                         break;
4747         }
4748
4749         smc_voltage->phase_settings = (u8)i;
4750
4751         return 0;
4752 }
4753
4754 static int si_init_arb_table_index(struct amdgpu_device *adev)
4755 {
4756         struct si_power_info *si_pi = si_get_pi(adev);
4757         u32 tmp;
4758         int ret;
4759
4760         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4761                                             &tmp, si_pi->sram_end);
4762         if (ret)
4763                 return ret;
4764
4765         tmp &= 0x00FFFFFF;
4766         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4767
4768         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4769                                               tmp, si_pi->sram_end);
4770 }
4771
4772 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4773 {
4774         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4775 }
4776
4777 static int si_reset_to_default(struct amdgpu_device *adev)
4778 {
4779         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4780                 0 : -EINVAL;
4781 }
4782
4783 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4784 {
4785         struct si_power_info *si_pi = si_get_pi(adev);
4786         u32 tmp;
4787         int ret;
4788
4789         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4790                                             &tmp, si_pi->sram_end);
4791         if (ret)
4792                 return ret;
4793
4794         tmp = (tmp >> 24) & 0xff;
4795
4796         if (tmp == MC_CG_ARB_FREQ_F0)
4797                 return 0;
4798
4799         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4800 }
4801
4802 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4803                                             u32 engine_clock)
4804 {
4805         u32 dram_rows;
4806         u32 dram_refresh_rate;
4807         u32 mc_arb_rfsh_rate;
4808         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4809
4810         if (tmp >= 4)
4811                 dram_rows = 16384;
4812         else
4813                 dram_rows = 1 << (tmp + 10);
4814
4815         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4816         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4817
4818         return mc_arb_rfsh_rate;
4819 }
4820
4821 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4822                                                 struct rv7xx_pl *pl,
4823                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4824 {
4825         u32 dram_timing;
4826         u32 dram_timing2;
4827         u32 burst_time;
4828
4829         arb_regs->mc_arb_rfsh_rate =
4830                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4831
4832         amdgpu_atombios_set_engine_dram_timings(adev,
4833                                             pl->sclk,
4834                                             pl->mclk);
4835
4836         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4837         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4838         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4839
4840         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4841         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4842         arb_regs->mc_arb_burst_time = (u8)burst_time;
4843
4844         return 0;
4845 }
4846
4847 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4848                                                   struct amdgpu_ps *amdgpu_state,
4849                                                   unsigned int first_arb_set)
4850 {
4851         struct si_power_info *si_pi = si_get_pi(adev);
4852         struct  si_ps *state = si_get_ps(amdgpu_state);
4853         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4854         int i, ret = 0;
4855
4856         for (i = 0; i < state->performance_level_count; i++) {
4857                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4858                 if (ret)
4859                         break;
4860                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4861                                                   si_pi->arb_table_start +
4862                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4863                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4864                                                   (u8 *)&arb_regs,
4865                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4866                                                   si_pi->sram_end);
4867                 if (ret)
4868                         break;
4869         }
4870
4871         return ret;
4872 }
4873
4874 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4875                                                struct amdgpu_ps *amdgpu_new_state)
4876 {
4877         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4878                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4879 }
4880
4881 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4882                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4883 {
4884         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4885         struct si_power_info *si_pi = si_get_pi(adev);
4886
4887         if (pi->mvdd_control)
4888                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4889                                                  si_pi->mvdd_bootup_value, voltage);
4890
4891         return 0;
4892 }
4893
4894 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4895                                          struct amdgpu_ps *amdgpu_initial_state,
4896                                          SISLANDS_SMC_STATETABLE *table)
4897 {
4898         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4899         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4900         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4901         struct si_power_info *si_pi = si_get_pi(adev);
4902         u32 reg;
4903         int ret;
4904
4905         table->initialState.levels[0].mclk.vDLL_CNTL =
4906                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4907         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4908                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4909         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4910                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4911         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4912                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4913         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4914                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4915         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4916                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4917         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4918                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4919         table->initialState.levels[0].mclk.vMPLL_SS =
4920                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4921         table->initialState.levels[0].mclk.vMPLL_SS2 =
4922                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4923
4924         table->initialState.levels[0].mclk.mclk_value =
4925                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4926
4927         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4928                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4929         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4930                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4931         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4932                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4933         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4934                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4935         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4936                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4937         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4938                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4939
4940         table->initialState.levels[0].sclk.sclk_value =
4941                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4942
4943         table->initialState.levels[0].arbRefreshState =
4944                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4945
4946         table->initialState.levels[0].ACIndex = 0;
4947
4948         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4949                                         initial_state->performance_levels[0].vddc,
4950                                         &table->initialState.levels[0].vddc);
4951
4952         if (!ret) {
4953                 u16 std_vddc;
4954
4955                 ret = si_get_std_voltage_value(adev,
4956                                                &table->initialState.levels[0].vddc,
4957                                                &std_vddc);
4958                 if (!ret)
4959                         si_populate_std_voltage_value(adev, std_vddc,
4960                                                       table->initialState.levels[0].vddc.index,
4961                                                       &table->initialState.levels[0].std_vddc);
4962         }
4963
4964         if (eg_pi->vddci_control)
4965                 si_populate_voltage_value(adev,
4966                                           &eg_pi->vddci_voltage_table,
4967                                           initial_state->performance_levels[0].vddci,
4968                                           &table->initialState.levels[0].vddci);
4969
4970         if (si_pi->vddc_phase_shed_control)
4971                 si_populate_phase_shedding_value(adev,
4972                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4973                                                  initial_state->performance_levels[0].vddc,
4974                                                  initial_state->performance_levels[0].sclk,
4975                                                  initial_state->performance_levels[0].mclk,
4976                                                  &table->initialState.levels[0].vddc);
4977
4978         si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4979
4980         reg = CG_R(0xffff) | CG_L(0);
4981         table->initialState.levels[0].aT = cpu_to_be32(reg);
4982         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4983         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4984
4985         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4986                 table->initialState.levels[0].strobeMode =
4987                         si_get_strobe_mode_settings(adev,
4988                                                     initial_state->performance_levels[0].mclk);
4989
4990                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4991                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4992                 else
4993                         table->initialState.levels[0].mcFlags =  0;
4994         }
4995
4996         table->initialState.levelCount = 1;
4997
4998         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4999
5000         table->initialState.levels[0].dpm2.MaxPS = 0;
5001         table->initialState.levels[0].dpm2.NearTDPDec = 0;
5002         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
5003         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
5004         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5005
5006         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5007         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5008
5009         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5010         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5011
5012         return 0;
5013 }
5014
5015 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5016                                       SISLANDS_SMC_STATETABLE *table)
5017 {
5018         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5019         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5020         struct si_power_info *si_pi = si_get_pi(adev);
5021         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5022         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5023         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5024         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5025         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5026         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5027         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5028         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5029         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5030         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5031         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5032         u32 reg;
5033         int ret;
5034
5035         table->ACPIState = table->initialState;
5036
5037         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5038
5039         if (pi->acpi_vddc) {
5040                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5041                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
5042                 if (!ret) {
5043                         u16 std_vddc;
5044
5045                         ret = si_get_std_voltage_value(adev,
5046                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5047                         if (!ret)
5048                                 si_populate_std_voltage_value(adev, std_vddc,
5049                                                               table->ACPIState.levels[0].vddc.index,
5050                                                               &table->ACPIState.levels[0].std_vddc);
5051                 }
5052                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5053
5054                 if (si_pi->vddc_phase_shed_control) {
5055                         si_populate_phase_shedding_value(adev,
5056                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5057                                                          pi->acpi_vddc,
5058                                                          0,
5059                                                          0,
5060                                                          &table->ACPIState.levels[0].vddc);
5061                 }
5062         } else {
5063                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5064                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5065                 if (!ret) {
5066                         u16 std_vddc;
5067
5068                         ret = si_get_std_voltage_value(adev,
5069                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5070
5071                         if (!ret)
5072                                 si_populate_std_voltage_value(adev, std_vddc,
5073                                                               table->ACPIState.levels[0].vddc.index,
5074                                                               &table->ACPIState.levels[0].std_vddc);
5075                 }
5076                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5077                                                                                     si_pi->sys_pcie_mask,
5078                                                                                     si_pi->boot_pcie_gen,
5079                                                                                     AMDGPU_PCIE_GEN1);
5080
5081                 if (si_pi->vddc_phase_shed_control)
5082                         si_populate_phase_shedding_value(adev,
5083                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5084                                                          pi->min_vddc_in_table,
5085                                                          0,
5086                                                          0,
5087                                                          &table->ACPIState.levels[0].vddc);
5088         }
5089
5090         if (pi->acpi_vddc) {
5091                 if (eg_pi->acpi_vddci)
5092                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5093                                                   eg_pi->acpi_vddci,
5094                                                   &table->ACPIState.levels[0].vddci);
5095         }
5096
5097         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5098         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5099
5100         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5101
5102         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5103         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5104
5105         table->ACPIState.levels[0].mclk.vDLL_CNTL =
5106                 cpu_to_be32(dll_cntl);
5107         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5108                 cpu_to_be32(mclk_pwrmgt_cntl);
5109         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5110                 cpu_to_be32(mpll_ad_func_cntl);
5111         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5112                 cpu_to_be32(mpll_dq_func_cntl);
5113         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5114                 cpu_to_be32(mpll_func_cntl);
5115         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5116                 cpu_to_be32(mpll_func_cntl_1);
5117         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5118                 cpu_to_be32(mpll_func_cntl_2);
5119         table->ACPIState.levels[0].mclk.vMPLL_SS =
5120                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5121         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5122                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5123
5124         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5125                 cpu_to_be32(spll_func_cntl);
5126         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5127                 cpu_to_be32(spll_func_cntl_2);
5128         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5129                 cpu_to_be32(spll_func_cntl_3);
5130         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5131                 cpu_to_be32(spll_func_cntl_4);
5132
5133         table->ACPIState.levels[0].mclk.mclk_value = 0;
5134         table->ACPIState.levels[0].sclk.sclk_value = 0;
5135
5136         si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5137
5138         if (eg_pi->dynamic_ac_timing)
5139                 table->ACPIState.levels[0].ACIndex = 0;
5140
5141         table->ACPIState.levels[0].dpm2.MaxPS = 0;
5142         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5143         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5144         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5145         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5146
5147         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5148         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5149
5150         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5151         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5152
5153         return 0;
5154 }
5155
5156 static int si_populate_ulv_state(struct amdgpu_device *adev,
5157                                  SISLANDS_SMC_SWSTATE *state)
5158 {
5159         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5160         struct si_power_info *si_pi = si_get_pi(adev);
5161         struct si_ulv_param *ulv = &si_pi->ulv;
5162         u32 sclk_in_sr = 1350; /* ??? */
5163         int ret;
5164
5165         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5166                                             &state->levels[0]);
5167         if (!ret) {
5168                 if (eg_pi->sclk_deep_sleep) {
5169                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5170                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5171                         else
5172                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5173                 }
5174                 if (ulv->one_pcie_lane_in_ulv)
5175                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5176                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5177                 state->levels[0].ACIndex = 1;
5178                 state->levels[0].std_vddc = state->levels[0].vddc;
5179                 state->levelCount = 1;
5180
5181                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5182         }
5183
5184         return ret;
5185 }
5186
5187 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5188 {
5189         struct si_power_info *si_pi = si_get_pi(adev);
5190         struct si_ulv_param *ulv = &si_pi->ulv;
5191         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5192         int ret;
5193
5194         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5195                                                    &arb_regs);
5196         if (ret)
5197                 return ret;
5198
5199         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5200                                    ulv->volt_change_delay);
5201
5202         ret = amdgpu_si_copy_bytes_to_smc(adev,
5203                                           si_pi->arb_table_start +
5204                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5205                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5206                                           (u8 *)&arb_regs,
5207                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5208                                           si_pi->sram_end);
5209
5210         return ret;
5211 }
5212
5213 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5214 {
5215         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5216
5217         pi->mvdd_split_frequency = 30000;
5218 }
5219
5220 static int si_init_smc_table(struct amdgpu_device *adev)
5221 {
5222         struct si_power_info *si_pi = si_get_pi(adev);
5223         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5224         const struct si_ulv_param *ulv = &si_pi->ulv;
5225         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5226         int ret;
5227         u32 lane_width;
5228         u32 vr_hot_gpio;
5229
5230         si_populate_smc_voltage_tables(adev, table);
5231
5232         switch (adev->pm.int_thermal_type) {
5233         case THERMAL_TYPE_SI:
5234         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5235                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5236                 break;
5237         case THERMAL_TYPE_NONE:
5238                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5239                 break;
5240         default:
5241                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5242                 break;
5243         }
5244
5245         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5246                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5247
5248         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5249                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5250                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5251         }
5252
5253         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5254                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5255
5256         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5257                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5258
5259         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5260                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5261
5262         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5263                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5264                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5265                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5266                                            vr_hot_gpio);
5267         }
5268
5269         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5270         if (ret)
5271                 return ret;
5272
5273         ret = si_populate_smc_acpi_state(adev, table);
5274         if (ret)
5275                 return ret;
5276
5277         table->driverState = table->initialState;
5278
5279         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5280                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5281         if (ret)
5282                 return ret;
5283
5284         if (ulv->supported && ulv->pl.vddc) {
5285                 ret = si_populate_ulv_state(adev, &table->ULVState);
5286                 if (ret)
5287                         return ret;
5288
5289                 ret = si_program_ulv_memory_timing_parameters(adev);
5290                 if (ret)
5291                         return ret;
5292
5293                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5294                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5295
5296                 lane_width = amdgpu_get_pcie_lanes(adev);
5297                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5298         } else {
5299                 table->ULVState = table->initialState;
5300         }
5301
5302         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5303                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5304                                            si_pi->sram_end);
5305 }
5306
5307 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5308                                     u32 engine_clock,
5309                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5310 {
5311         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5312         struct si_power_info *si_pi = si_get_pi(adev);
5313         struct atom_clock_dividers dividers;
5314         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5315         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5316         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5317         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5318         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5319         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5320         u64 tmp;
5321         u32 reference_clock = adev->clock.spll.reference_freq;
5322         u32 reference_divider;
5323         u32 fbdiv;
5324         int ret;
5325
5326         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5327                                              engine_clock, false, &dividers);
5328         if (ret)
5329                 return ret;
5330
5331         reference_divider = 1 + dividers.ref_div;
5332
5333         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5334         do_div(tmp, reference_clock);
5335         fbdiv = (u32) tmp;
5336
5337         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5338         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5339         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5340
5341         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5342         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5343
5344         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5345         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5346         spll_func_cntl_3 |= SPLL_DITHEN;
5347
5348         if (pi->sclk_ss) {
5349                 struct amdgpu_atom_ss ss;
5350                 u32 vco_freq = engine_clock * dividers.post_div;
5351
5352                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5353                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5354                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5355                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5356
5357                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5358                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5359                         cg_spll_spread_spectrum |= SSEN;
5360
5361                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5362                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5363                 }
5364         }
5365
5366         sclk->sclk_value = engine_clock;
5367         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5368         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5369         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5370         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5371         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5372         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5373
5374         return 0;
5375 }
5376
5377 static int si_populate_sclk_value(struct amdgpu_device *adev,
5378                                   u32 engine_clock,
5379                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5380 {
5381         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5382         int ret;
5383
5384         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5385         if (!ret) {
5386                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5387                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5388                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5389                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5390                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5391                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5392                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5393         }
5394
5395         return ret;
5396 }
5397
5398 static int si_populate_mclk_value(struct amdgpu_device *adev,
5399                                   u32 engine_clock,
5400                                   u32 memory_clock,
5401                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5402                                   bool strobe_mode,
5403                                   bool dll_state_on)
5404 {
5405         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5406         struct si_power_info *si_pi = si_get_pi(adev);
5407         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5408         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5409         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5410         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5411         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5412         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5413         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5414         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5415         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5416         struct atom_mpll_param mpll_param;
5417         int ret;
5418
5419         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5420         if (ret)
5421                 return ret;
5422
5423         mpll_func_cntl &= ~BWCTRL_MASK;
5424         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5425
5426         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5427         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5428                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5429
5430         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5431         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5432
5433         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5434                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5435                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5436                         YCLK_POST_DIV(mpll_param.post_div);
5437         }
5438
5439         if (pi->mclk_ss) {
5440                 struct amdgpu_atom_ss ss;
5441                 u32 freq_nom;
5442                 u32 tmp;
5443                 u32 reference_clock = adev->clock.mpll.reference_freq;
5444
5445                 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5446                         freq_nom = memory_clock * 4;
5447                 else
5448                         freq_nom = memory_clock * 2;
5449
5450                 tmp = freq_nom / reference_clock;
5451                 tmp = tmp * tmp;
5452                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5453                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5454                         u32 clks = reference_clock * 5 / ss.rate;
5455                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5456
5457                         mpll_ss1 &= ~CLKV_MASK;
5458                         mpll_ss1 |= CLKV(clkv);
5459
5460                         mpll_ss2 &= ~CLKS_MASK;
5461                         mpll_ss2 |= CLKS(clks);
5462                 }
5463         }
5464
5465         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5466         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5467
5468         if (dll_state_on)
5469                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5470         else
5471                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5472
5473         mclk->mclk_value = cpu_to_be32(memory_clock);
5474         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5475         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5476         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5477         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5478         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5479         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5480         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5481         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5482         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5483
5484         return 0;
5485 }
5486
5487 static void si_populate_smc_sp(struct amdgpu_device *adev,
5488                                struct amdgpu_ps *amdgpu_state,
5489                                SISLANDS_SMC_SWSTATE *smc_state)
5490 {
5491         struct  si_ps *ps = si_get_ps(amdgpu_state);
5492         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5493         int i;
5494
5495         for (i = 0; i < ps->performance_level_count - 1; i++)
5496                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5497
5498         smc_state->levels[ps->performance_level_count - 1].bSP =
5499                 cpu_to_be32(pi->psp);
5500 }
5501
5502 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5503                                          struct rv7xx_pl *pl,
5504                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5505 {
5506         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5507         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5508         struct si_power_info *si_pi = si_get_pi(adev);
5509         int ret;
5510         bool dll_state_on;
5511         u16 std_vddc;
5512         bool gmc_pg = false;
5513
5514         if (eg_pi->pcie_performance_request &&
5515             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5516                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5517         else
5518                 level->gen2PCIE = (u8)pl->pcie_gen;
5519
5520         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5521         if (ret)
5522                 return ret;
5523
5524         level->mcFlags =  0;
5525
5526         if (pi->mclk_stutter_mode_threshold &&
5527             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5528             !eg_pi->uvd_enabled &&
5529             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5530             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5531                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5532
5533                 if (gmc_pg)
5534                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5535         }
5536
5537         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5538                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5539                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5540
5541                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5542                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5543
5544                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5545
5546                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5547                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5548                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5549                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5550                         else
5551                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5552                 } else {
5553                         dll_state_on = false;
5554                 }
5555         } else {
5556                 level->strobeMode = si_get_strobe_mode_settings(adev,
5557                                                                 pl->mclk);
5558
5559                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5560         }
5561
5562         ret = si_populate_mclk_value(adev,
5563                                      pl->sclk,
5564                                      pl->mclk,
5565                                      &level->mclk,
5566                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5567         if (ret)
5568                 return ret;
5569
5570         ret = si_populate_voltage_value(adev,
5571                                         &eg_pi->vddc_voltage_table,
5572                                         pl->vddc, &level->vddc);
5573         if (ret)
5574                 return ret;
5575
5576
5577         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5578         if (ret)
5579                 return ret;
5580
5581         ret = si_populate_std_voltage_value(adev, std_vddc,
5582                                             level->vddc.index, &level->std_vddc);
5583         if (ret)
5584                 return ret;
5585
5586         if (eg_pi->vddci_control) {
5587                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5588                                                 pl->vddci, &level->vddci);
5589                 if (ret)
5590                         return ret;
5591         }
5592
5593         if (si_pi->vddc_phase_shed_control) {
5594                 ret = si_populate_phase_shedding_value(adev,
5595                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5596                                                        pl->vddc,
5597                                                        pl->sclk,
5598                                                        pl->mclk,
5599                                                        &level->vddc);
5600                 if (ret)
5601                         return ret;
5602         }
5603
5604         level->MaxPoweredUpCU = si_pi->max_cu;
5605
5606         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5607
5608         return ret;
5609 }
5610
5611 static int si_populate_smc_t(struct amdgpu_device *adev,
5612                              struct amdgpu_ps *amdgpu_state,
5613                              SISLANDS_SMC_SWSTATE *smc_state)
5614 {
5615         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5616         struct  si_ps *state = si_get_ps(amdgpu_state);
5617         u32 a_t;
5618         u32 t_l, t_h;
5619         u32 high_bsp;
5620         int i, ret;
5621
5622         if (state->performance_level_count >= 9)
5623                 return -EINVAL;
5624
5625         if (state->performance_level_count < 2) {
5626                 a_t = CG_R(0xffff) | CG_L(0);
5627                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5628                 return 0;
5629         }
5630
5631         smc_state->levels[0].aT = cpu_to_be32(0);
5632
5633         for (i = 0; i <= state->performance_level_count - 2; i++) {
5634                 ret = r600_calculate_at(
5635                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5636                         100 * R600_AH_DFLT,
5637                         state->performance_levels[i + 1].sclk,
5638                         state->performance_levels[i].sclk,
5639                         &t_l,
5640                         &t_h);
5641
5642                 if (ret) {
5643                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5644                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5645                 }
5646
5647                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5648                 a_t |= CG_R(t_l * pi->bsp / 20000);
5649                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5650
5651                 high_bsp = (i == state->performance_level_count - 2) ?
5652                         pi->pbsp : pi->bsp;
5653                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5654                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5655         }
5656
5657         return 0;
5658 }
5659
5660 static int si_disable_ulv(struct amdgpu_device *adev)
5661 {
5662         struct si_power_info *si_pi = si_get_pi(adev);
5663         struct si_ulv_param *ulv = &si_pi->ulv;
5664
5665         if (ulv->supported)
5666                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5667                         0 : -EINVAL;
5668
5669         return 0;
5670 }
5671
5672 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5673                                        struct amdgpu_ps *amdgpu_state)
5674 {
5675         const struct si_power_info *si_pi = si_get_pi(adev);
5676         const struct si_ulv_param *ulv = &si_pi->ulv;
5677         const struct  si_ps *state = si_get_ps(amdgpu_state);
5678         int i;
5679
5680         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5681                 return false;
5682
5683         /* XXX validate against display requirements! */
5684
5685         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5686                 if (adev->clock.current_dispclk <=
5687                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5688                         if (ulv->pl.vddc <
5689                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5690                                 return false;
5691                 }
5692         }
5693
5694         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5695                 return false;
5696
5697         return true;
5698 }
5699
5700 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5701                                                        struct amdgpu_ps *amdgpu_new_state)
5702 {
5703         const struct si_power_info *si_pi = si_get_pi(adev);
5704         const struct si_ulv_param *ulv = &si_pi->ulv;
5705
5706         if (ulv->supported) {
5707                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5708                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5709                                 0 : -EINVAL;
5710         }
5711         return 0;
5712 }
5713
5714 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5715                                          struct amdgpu_ps *amdgpu_state,
5716                                          SISLANDS_SMC_SWSTATE *smc_state)
5717 {
5718         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5719         struct ni_power_info *ni_pi = ni_get_pi(adev);
5720         struct si_power_info *si_pi = si_get_pi(adev);
5721         struct  si_ps *state = si_get_ps(amdgpu_state);
5722         int i, ret;
5723         u32 threshold;
5724         u32 sclk_in_sr = 1350; /* ??? */
5725
5726         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5727                 return -EINVAL;
5728
5729         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5730
5731         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5732                 eg_pi->uvd_enabled = true;
5733                 if (eg_pi->smu_uvd_hs)
5734                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5735         } else {
5736                 eg_pi->uvd_enabled = false;
5737         }
5738
5739         if (state->dc_compatible)
5740                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5741
5742         smc_state->levelCount = 0;
5743         for (i = 0; i < state->performance_level_count; i++) {
5744                 if (eg_pi->sclk_deep_sleep) {
5745                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5746                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5747                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5748                                 else
5749                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5750                         }
5751                 }
5752
5753                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5754                                                     &smc_state->levels[i]);
5755                 smc_state->levels[i].arbRefreshState =
5756                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5757
5758                 if (ret)
5759                         return ret;
5760
5761                 if (ni_pi->enable_power_containment)
5762                         smc_state->levels[i].displayWatermark =
5763                                 (state->performance_levels[i].sclk < threshold) ?
5764                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5765                 else
5766                         smc_state->levels[i].displayWatermark = (i < 2) ?
5767                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5768
5769                 if (eg_pi->dynamic_ac_timing)
5770                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5771                 else
5772                         smc_state->levels[i].ACIndex = 0;
5773
5774                 smc_state->levelCount++;
5775         }
5776
5777         si_write_smc_soft_register(adev,
5778                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5779                                    threshold / 512);
5780
5781         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5782
5783         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5784         if (ret)
5785                 ni_pi->enable_power_containment = false;
5786
5787         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5788         if (ret)
5789                 ni_pi->enable_sq_ramping = false;
5790
5791         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5792 }
5793
5794 static int si_upload_sw_state(struct amdgpu_device *adev,
5795                               struct amdgpu_ps *amdgpu_new_state)
5796 {
5797         struct si_power_info *si_pi = si_get_pi(adev);
5798         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5799         int ret;
5800         u32 address = si_pi->state_table_start +
5801                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5802         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5803                 ((new_state->performance_level_count - 1) *
5804                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5805         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5806
5807         memset(smc_state, 0, state_size);
5808
5809         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5810         if (ret)
5811                 return ret;
5812
5813         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5814                                            state_size, si_pi->sram_end);
5815 }
5816
5817 static int si_upload_ulv_state(struct amdgpu_device *adev)
5818 {
5819         struct si_power_info *si_pi = si_get_pi(adev);
5820         struct si_ulv_param *ulv = &si_pi->ulv;
5821         int ret = 0;
5822
5823         if (ulv->supported && ulv->pl.vddc) {
5824                 u32 address = si_pi->state_table_start +
5825                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5826                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5827                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5828
5829                 memset(smc_state, 0, state_size);
5830
5831                 ret = si_populate_ulv_state(adev, smc_state);
5832                 if (!ret)
5833                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5834                                                           state_size, si_pi->sram_end);
5835         }
5836
5837         return ret;
5838 }
5839
5840 static int si_upload_smc_data(struct amdgpu_device *adev)
5841 {
5842         struct amdgpu_crtc *amdgpu_crtc = NULL;
5843         int i;
5844
5845         if (adev->pm.dpm.new_active_crtc_count == 0)
5846                 return 0;
5847
5848         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5849                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5850                         amdgpu_crtc = adev->mode_info.crtcs[i];
5851                         break;
5852                 }
5853         }
5854
5855         if (amdgpu_crtc == NULL)
5856                 return 0;
5857
5858         if (amdgpu_crtc->line_time <= 0)
5859                 return 0;
5860
5861         if (si_write_smc_soft_register(adev,
5862                                        SI_SMC_SOFT_REGISTER_crtc_index,
5863                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5864                 return 0;
5865
5866         if (si_write_smc_soft_register(adev,
5867                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5868                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5869                 return 0;
5870
5871         if (si_write_smc_soft_register(adev,
5872                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5873                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5874                 return 0;
5875
5876         return 0;
5877 }
5878
5879 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5880                                        struct si_mc_reg_table *table)
5881 {
5882         u8 i, j, k;
5883         u32 temp_reg;
5884
5885         for (i = 0, j = table->last; i < table->last; i++) {
5886                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5887                         return -EINVAL;
5888                 switch (table->mc_reg_address[i].s1) {
5889                 case MC_SEQ_MISC1:
5890                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5891                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5892                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5893                         for (k = 0; k < table->num_entries; k++)
5894                                 table->mc_reg_table_entry[k].mc_data[j] =
5895                                         ((temp_reg & 0xffff0000)) |
5896                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5897                         j++;
5898                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5899                                 return -EINVAL;
5900
5901                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5902                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5903                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5904                         for (k = 0; k < table->num_entries; k++) {
5905                                 table->mc_reg_table_entry[k].mc_data[j] =
5906                                         (temp_reg & 0xffff0000) |
5907                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5908                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5909                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5910                         }
5911                         j++;
5912                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5913                                 return -EINVAL;
5914
5915                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5916                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5917                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5918                                 for (k = 0; k < table->num_entries; k++)
5919                                         table->mc_reg_table_entry[k].mc_data[j] =
5920                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5921                                 j++;
5922                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5923                                         return -EINVAL;
5924                         }
5925                         break;
5926                 case MC_SEQ_RESERVE_M:
5927                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5928                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5929                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5930                         for(k = 0; k < table->num_entries; k++)
5931                                 table->mc_reg_table_entry[k].mc_data[j] =
5932                                         (temp_reg & 0xffff0000) |
5933                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5934                         j++;
5935                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5936                                 return -EINVAL;
5937                         break;
5938                 default:
5939                         break;
5940                 }
5941         }
5942
5943         table->last = j;
5944
5945         return 0;
5946 }
5947
5948 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5949 {
5950         bool result = true;
5951         switch (in_reg) {
5952         case  MC_SEQ_RAS_TIMING:
5953                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5954                 break;
5955         case MC_SEQ_CAS_TIMING:
5956                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5957                 break;
5958         case MC_SEQ_MISC_TIMING:
5959                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5960                 break;
5961         case MC_SEQ_MISC_TIMING2:
5962                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5963                 break;
5964         case MC_SEQ_RD_CTL_D0:
5965                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5966                 break;
5967         case MC_SEQ_RD_CTL_D1:
5968                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5969                 break;
5970         case MC_SEQ_WR_CTL_D0:
5971                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5972                 break;
5973         case MC_SEQ_WR_CTL_D1:
5974                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5975                 break;
5976         case MC_PMG_CMD_EMRS:
5977                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5978                 break;
5979         case MC_PMG_CMD_MRS:
5980                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5981                 break;
5982         case MC_PMG_CMD_MRS1:
5983                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5984                 break;
5985         case MC_SEQ_PMG_TIMING:
5986                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5987                 break;
5988         case MC_PMG_CMD_MRS2:
5989                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5990                 break;
5991         case MC_SEQ_WR_CTL_2:
5992                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5993                 break;
5994         default:
5995                 result = false;
5996                 break;
5997         }
5998
5999         return result;
6000 }
6001
6002 static void si_set_valid_flag(struct si_mc_reg_table *table)
6003 {
6004         u8 i, j;
6005
6006         for (i = 0; i < table->last; i++) {
6007                 for (j = 1; j < table->num_entries; j++) {
6008                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
6009                                 table->valid_flag |= 1 << i;
6010                                 break;
6011                         }
6012                 }
6013         }
6014 }
6015
6016 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6017 {
6018         u32 i;
6019         u16 address;
6020
6021         for (i = 0; i < table->last; i++)
6022                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6023                         address : table->mc_reg_address[i].s1;
6024
6025 }
6026
6027 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6028                                       struct si_mc_reg_table *si_table)
6029 {
6030         u8 i, j;
6031
6032         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6033                 return -EINVAL;
6034         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6035                 return -EINVAL;
6036
6037         for (i = 0; i < table->last; i++)
6038                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6039         si_table->last = table->last;
6040
6041         for (i = 0; i < table->num_entries; i++) {
6042                 si_table->mc_reg_table_entry[i].mclk_max =
6043                         table->mc_reg_table_entry[i].mclk_max;
6044                 for (j = 0; j < table->last; j++) {
6045                         si_table->mc_reg_table_entry[i].mc_data[j] =
6046                                 table->mc_reg_table_entry[i].mc_data[j];
6047                 }
6048         }
6049         si_table->num_entries = table->num_entries;
6050
6051         return 0;
6052 }
6053
6054 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6055 {
6056         struct si_power_info *si_pi = si_get_pi(adev);
6057         struct atom_mc_reg_table *table;
6058         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6059         u8 module_index = rv770_get_memory_module_index(adev);
6060         int ret;
6061
6062         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6063         if (!table)
6064                 return -ENOMEM;
6065
6066         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6067         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6068         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6069         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6070         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6071         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6072         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6073         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6074         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6075         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6076         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6077         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6078         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6079         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6080
6081         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6082         if (ret)
6083                 goto init_mc_done;
6084
6085         ret = si_copy_vbios_mc_reg_table(table, si_table);
6086         if (ret)
6087                 goto init_mc_done;
6088
6089         si_set_s0_mc_reg_index(si_table);
6090
6091         ret = si_set_mc_special_registers(adev, si_table);
6092         if (ret)
6093                 goto init_mc_done;
6094
6095         si_set_valid_flag(si_table);
6096
6097 init_mc_done:
6098         kfree(table);
6099
6100         return ret;
6101
6102 }
6103
6104 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6105                                          SMC_SIslands_MCRegisters *mc_reg_table)
6106 {
6107         struct si_power_info *si_pi = si_get_pi(adev);
6108         u32 i, j;
6109
6110         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6111                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6112                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6113                                 break;
6114                         mc_reg_table->address[i].s0 =
6115                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6116                         mc_reg_table->address[i].s1 =
6117                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6118                         i++;
6119                 }
6120         }
6121         mc_reg_table->last = (u8)i;
6122 }
6123
6124 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6125                                     SMC_SIslands_MCRegisterSet *data,
6126                                     u32 num_entries, u32 valid_flag)
6127 {
6128         u32 i, j;
6129
6130         for(i = 0, j = 0; j < num_entries; j++) {
6131                 if (valid_flag & (1 << j)) {
6132                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6133                         i++;
6134                 }
6135         }
6136 }
6137
6138 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6139                                                  struct rv7xx_pl *pl,
6140                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6141 {
6142         struct si_power_info *si_pi = si_get_pi(adev);
6143         u32 i = 0;
6144
6145         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6146                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6147                         break;
6148         }
6149
6150         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6151                 --i;
6152
6153         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6154                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6155                                 si_pi->mc_reg_table.valid_flag);
6156 }
6157
6158 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6159                                            struct amdgpu_ps *amdgpu_state,
6160                                            SMC_SIslands_MCRegisters *mc_reg_table)
6161 {
6162         struct si_ps *state = si_get_ps(amdgpu_state);
6163         int i;
6164
6165         for (i = 0; i < state->performance_level_count; i++) {
6166                 si_convert_mc_reg_table_entry_to_smc(adev,
6167                                                      &state->performance_levels[i],
6168                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6169         }
6170 }
6171
6172 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6173                                     struct amdgpu_ps *amdgpu_boot_state)
6174 {
6175         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6176         struct si_power_info *si_pi = si_get_pi(adev);
6177         struct si_ulv_param *ulv = &si_pi->ulv;
6178         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6179
6180         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6181
6182         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6183
6184         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6185
6186         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6187                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6188
6189         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6190                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6191                                 si_pi->mc_reg_table.last,
6192                                 si_pi->mc_reg_table.valid_flag);
6193
6194         if (ulv->supported && ulv->pl.vddc != 0)
6195                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6196                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6197         else
6198                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6199                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6200                                         si_pi->mc_reg_table.last,
6201                                         si_pi->mc_reg_table.valid_flag);
6202
6203         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6204
6205         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6206                                            (u8 *)smc_mc_reg_table,
6207                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6208 }
6209
6210 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6211                                   struct amdgpu_ps *amdgpu_new_state)
6212 {
6213         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6214         struct si_power_info *si_pi = si_get_pi(adev);
6215         u32 address = si_pi->mc_reg_table_start +
6216                 offsetof(SMC_SIslands_MCRegisters,
6217                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6218         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6219
6220         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6221
6222         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6223
6224         return amdgpu_si_copy_bytes_to_smc(adev, address,
6225                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6226                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6227                                            si_pi->sram_end);
6228 }
6229
6230 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6231 {
6232         if (enable)
6233                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6234         else
6235                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6236 }
6237
6238 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6239                                                       struct amdgpu_ps *amdgpu_state)
6240 {
6241         struct si_ps *state = si_get_ps(amdgpu_state);
6242         int i;
6243         u16 pcie_speed, max_speed = 0;
6244
6245         for (i = 0; i < state->performance_level_count; i++) {
6246                 pcie_speed = state->performance_levels[i].pcie_gen;
6247                 if (max_speed < pcie_speed)
6248                         max_speed = pcie_speed;
6249         }
6250         return max_speed;
6251 }
6252
6253 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6254 {
6255         u32 speed_cntl;
6256
6257         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6258         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6259
6260         return (u16)speed_cntl;
6261 }
6262
6263 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6264                                                              struct amdgpu_ps *amdgpu_new_state,
6265                                                              struct amdgpu_ps *amdgpu_current_state)
6266 {
6267         struct si_power_info *si_pi = si_get_pi(adev);
6268         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6269         enum amdgpu_pcie_gen current_link_speed;
6270
6271         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6272                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6273         else
6274                 current_link_speed = si_pi->force_pcie_gen;
6275
6276         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6277         si_pi->pspp_notify_required = false;
6278         if (target_link_speed > current_link_speed) {
6279                 switch (target_link_speed) {
6280 #if defined(CONFIG_ACPI)
6281                 case AMDGPU_PCIE_GEN3:
6282                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6283                                 break;
6284                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6285                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6286                                 break;
6287                 case AMDGPU_PCIE_GEN2:
6288                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6289                                 break;
6290 #endif
6291                 default:
6292                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6293                         break;
6294                 }
6295         } else {
6296                 if (target_link_speed < current_link_speed)
6297                         si_pi->pspp_notify_required = true;
6298         }
6299 }
6300
6301 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6302                                                            struct amdgpu_ps *amdgpu_new_state,
6303                                                            struct amdgpu_ps *amdgpu_current_state)
6304 {
6305         struct si_power_info *si_pi = si_get_pi(adev);
6306         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6307         u8 request;
6308
6309         if (si_pi->pspp_notify_required) {
6310                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6311                         request = PCIE_PERF_REQ_PECI_GEN3;
6312                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6313                         request = PCIE_PERF_REQ_PECI_GEN2;
6314                 else
6315                         request = PCIE_PERF_REQ_PECI_GEN1;
6316
6317                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6318                     (si_get_current_pcie_speed(adev) > 0))
6319                         return;
6320
6321 #if defined(CONFIG_ACPI)
6322                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6323 #endif
6324         }
6325 }
6326
6327 #if 0
6328 static int si_ds_request(struct amdgpu_device *adev,
6329                          bool ds_status_on, u32 count_write)
6330 {
6331         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6332
6333         if (eg_pi->sclk_deep_sleep) {
6334                 if (ds_status_on)
6335                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6336                                 PPSMC_Result_OK) ?
6337                                 0 : -EINVAL;
6338                 else
6339                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6340                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6341         }
6342         return 0;
6343 }
6344 #endif
6345
6346 static void si_set_max_cu_value(struct amdgpu_device *adev)
6347 {
6348         struct si_power_info *si_pi = si_get_pi(adev);
6349
6350         if (adev->asic_type == CHIP_VERDE) {
6351                 switch (adev->pdev->device) {
6352                 case 0x6820:
6353                 case 0x6825:
6354                 case 0x6821:
6355                 case 0x6823:
6356                 case 0x6827:
6357                         si_pi->max_cu = 10;
6358                         break;
6359                 case 0x682D:
6360                 case 0x6824:
6361                 case 0x682F:
6362                 case 0x6826:
6363                         si_pi->max_cu = 8;
6364                         break;
6365                 case 0x6828:
6366                 case 0x6830:
6367                 case 0x6831:
6368                 case 0x6838:
6369                 case 0x6839:
6370                 case 0x683D:
6371                         si_pi->max_cu = 10;
6372                         break;
6373                 case 0x683B:
6374                 case 0x683F:
6375                 case 0x6829:
6376                         si_pi->max_cu = 8;
6377                         break;
6378                 default:
6379                         si_pi->max_cu = 0;
6380                         break;
6381                 }
6382         } else {
6383                 si_pi->max_cu = 0;
6384         }
6385 }
6386
6387 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6388                                                              struct amdgpu_clock_voltage_dependency_table *table)
6389 {
6390         u32 i;
6391         int j;
6392         u16 leakage_voltage;
6393
6394         if (table) {
6395                 for (i = 0; i < table->count; i++) {
6396                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6397                                                                           table->entries[i].v,
6398                                                                           &leakage_voltage)) {
6399                         case 0:
6400                                 table->entries[i].v = leakage_voltage;
6401                                 break;
6402                         case -EAGAIN:
6403                                 return -EINVAL;
6404                         case -EINVAL:
6405                         default:
6406                                 break;
6407                         }
6408                 }
6409
6410                 for (j = (table->count - 2); j >= 0; j--) {
6411                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6412                                 table->entries[j].v : table->entries[j + 1].v;
6413                 }
6414         }
6415         return 0;
6416 }
6417
6418 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6419 {
6420         int ret = 0;
6421
6422         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6423                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6424         if (ret)
6425                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6426         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6427                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6428         if (ret)
6429                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6430         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6431                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6432         if (ret)
6433                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6434         return ret;
6435 }
6436
6437 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6438                                           struct amdgpu_ps *amdgpu_new_state,
6439                                           struct amdgpu_ps *amdgpu_current_state)
6440 {
6441         u32 lane_width;
6442         u32 new_lane_width =
6443                 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6444         u32 current_lane_width =
6445                 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6446
6447         if (new_lane_width != current_lane_width) {
6448                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6449                 lane_width = amdgpu_get_pcie_lanes(adev);
6450                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6451         }
6452 }
6453
6454 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6455 {
6456         si_read_clock_registers(adev);
6457         si_enable_acpi_power_management(adev);
6458 }
6459
6460 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6461                                    bool enable)
6462 {
6463         u32 thermal_int = RREG32(CG_THERMAL_INT);
6464
6465         if (enable) {
6466                 PPSMC_Result result;
6467
6468                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6469                 WREG32(CG_THERMAL_INT, thermal_int);
6470                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6471                 if (result != PPSMC_Result_OK) {
6472                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6473                         return -EINVAL;
6474                 }
6475         } else {
6476                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6477                 WREG32(CG_THERMAL_INT, thermal_int);
6478         }
6479
6480         return 0;
6481 }
6482
6483 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6484                                             int min_temp, int max_temp)
6485 {
6486         int low_temp = 0 * 1000;
6487         int high_temp = 255 * 1000;
6488
6489         if (low_temp < min_temp)
6490                 low_temp = min_temp;
6491         if (high_temp > max_temp)
6492                 high_temp = max_temp;
6493         if (high_temp < low_temp) {
6494                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6495                 return -EINVAL;
6496         }
6497
6498         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6499         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6500         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6501
6502         adev->pm.dpm.thermal.min_temp = low_temp;
6503         adev->pm.dpm.thermal.max_temp = high_temp;
6504
6505         return 0;
6506 }
6507
6508 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6509 {
6510         struct si_power_info *si_pi = si_get_pi(adev);
6511         u32 tmp;
6512
6513         if (si_pi->fan_ctrl_is_in_default_mode) {
6514                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6515                 si_pi->fan_ctrl_default_mode = tmp;
6516                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6517                 si_pi->t_min = tmp;
6518                 si_pi->fan_ctrl_is_in_default_mode = false;
6519         }
6520
6521         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6522         tmp |= TMIN(0);
6523         WREG32(CG_FDO_CTRL2, tmp);
6524
6525         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6526         tmp |= FDO_PWM_MODE(mode);
6527         WREG32(CG_FDO_CTRL2, tmp);
6528 }
6529
6530 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6531 {
6532         struct si_power_info *si_pi = si_get_pi(adev);
6533         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6534         u32 duty100;
6535         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6536         u16 fdo_min, slope1, slope2;
6537         u32 reference_clock, tmp;
6538         int ret;
6539         u64 tmp64;
6540
6541         if (!si_pi->fan_table_start) {
6542                 adev->pm.dpm.fan.ucode_fan_control = false;
6543                 return 0;
6544         }
6545
6546         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6547
6548         if (duty100 == 0) {
6549                 adev->pm.dpm.fan.ucode_fan_control = false;
6550                 return 0;
6551         }
6552
6553         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6554         do_div(tmp64, 10000);
6555         fdo_min = (u16)tmp64;
6556
6557         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6558         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6559
6560         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6561         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6562
6563         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6564         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6565
6566         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6567         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6568         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6569         fan_table.slope1 = cpu_to_be16(slope1);
6570         fan_table.slope2 = cpu_to_be16(slope2);
6571         fan_table.fdo_min = cpu_to_be16(fdo_min);
6572         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6573         fan_table.hys_up = cpu_to_be16(1);
6574         fan_table.hys_slope = cpu_to_be16(1);
6575         fan_table.temp_resp_lim = cpu_to_be16(5);
6576         reference_clock = amdgpu_asic_get_xclk(adev);
6577
6578         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6579                                                 reference_clock) / 1600);
6580         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6581
6582         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6583         fan_table.temp_src = (uint8_t)tmp;
6584
6585         ret = amdgpu_si_copy_bytes_to_smc(adev,
6586                                           si_pi->fan_table_start,
6587                                           (u8 *)(&fan_table),
6588                                           sizeof(fan_table),
6589                                           si_pi->sram_end);
6590
6591         if (ret) {
6592                 DRM_ERROR("Failed to load fan table to the SMC.");
6593                 adev->pm.dpm.fan.ucode_fan_control = false;
6594         }
6595
6596         return ret;
6597 }
6598
6599 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6600 {
6601         struct si_power_info *si_pi = si_get_pi(adev);
6602         PPSMC_Result ret;
6603
6604         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6605         if (ret == PPSMC_Result_OK) {
6606                 si_pi->fan_is_controlled_by_smc = true;
6607                 return 0;
6608         } else {
6609                 return -EINVAL;
6610         }
6611 }
6612
6613 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6614 {
6615         struct si_power_info *si_pi = si_get_pi(adev);
6616         PPSMC_Result ret;
6617
6618         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6619
6620         if (ret == PPSMC_Result_OK) {
6621                 si_pi->fan_is_controlled_by_smc = false;
6622                 return 0;
6623         } else {
6624                 return -EINVAL;
6625         }
6626 }
6627
6628 static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6629                                       u32 *speed)
6630 {
6631         u32 duty, duty100;
6632         u64 tmp64;
6633
6634         if (adev->pm.no_fan)
6635                 return -ENOENT;
6636
6637         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6638         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6639
6640         if (duty100 == 0)
6641                 return -EINVAL;
6642
6643         tmp64 = (u64)duty * 100;
6644         do_div(tmp64, duty100);
6645         *speed = (u32)tmp64;
6646
6647         if (*speed > 100)
6648                 *speed = 100;
6649
6650         return 0;
6651 }
6652
6653 static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6654                                       u32 speed)
6655 {
6656         struct si_power_info *si_pi = si_get_pi(adev);
6657         u32 tmp;
6658         u32 duty, duty100;
6659         u64 tmp64;
6660
6661         if (adev->pm.no_fan)
6662                 return -ENOENT;
6663
6664         if (si_pi->fan_is_controlled_by_smc)
6665                 return -EINVAL;
6666
6667         if (speed > 100)
6668                 return -EINVAL;
6669
6670         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6671
6672         if (duty100 == 0)
6673                 return -EINVAL;
6674
6675         tmp64 = (u64)speed * duty100;
6676         do_div(tmp64, 100);
6677         duty = (u32)tmp64;
6678
6679         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6680         tmp |= FDO_STATIC_DUTY(duty);
6681         WREG32(CG_FDO_CTRL0, tmp);
6682
6683         return 0;
6684 }
6685
6686 static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6687 {
6688         if (mode) {
6689                 /* stop auto-manage */
6690                 if (adev->pm.dpm.fan.ucode_fan_control)
6691                         si_fan_ctrl_stop_smc_fan_control(adev);
6692                 si_fan_ctrl_set_static_mode(adev, mode);
6693         } else {
6694                 /* restart auto-manage */
6695                 if (adev->pm.dpm.fan.ucode_fan_control)
6696                         si_thermal_start_smc_fan_control(adev);
6697                 else
6698                         si_fan_ctrl_set_default_mode(adev);
6699         }
6700 }
6701
6702 static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6703 {
6704         struct si_power_info *si_pi = si_get_pi(adev);
6705         u32 tmp;
6706
6707         if (si_pi->fan_is_controlled_by_smc)
6708                 return 0;
6709
6710         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6711         return (tmp >> FDO_PWM_MODE_SHIFT);
6712 }
6713
6714 #if 0
6715 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6716                                          u32 *speed)
6717 {
6718         u32 tach_period;
6719         u32 xclk = amdgpu_asic_get_xclk(adev);
6720
6721         if (adev->pm.no_fan)
6722                 return -ENOENT;
6723
6724         if (adev->pm.fan_pulses_per_revolution == 0)
6725                 return -ENOENT;
6726
6727         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6728         if (tach_period == 0)
6729                 return -ENOENT;
6730
6731         *speed = 60 * xclk * 10000 / tach_period;
6732
6733         return 0;
6734 }
6735
6736 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6737                                          u32 speed)
6738 {
6739         u32 tach_period, tmp;
6740         u32 xclk = amdgpu_asic_get_xclk(adev);
6741
6742         if (adev->pm.no_fan)
6743                 return -ENOENT;
6744
6745         if (adev->pm.fan_pulses_per_revolution == 0)
6746                 return -ENOENT;
6747
6748         if ((speed < adev->pm.fan_min_rpm) ||
6749             (speed > adev->pm.fan_max_rpm))
6750                 return -EINVAL;
6751
6752         if (adev->pm.dpm.fan.ucode_fan_control)
6753                 si_fan_ctrl_stop_smc_fan_control(adev);
6754
6755         tach_period = 60 * xclk * 10000 / (8 * speed);
6756         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6757         tmp |= TARGET_PERIOD(tach_period);
6758         WREG32(CG_TACH_CTRL, tmp);
6759
6760         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6761
6762         return 0;
6763 }
6764 #endif
6765
6766 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6767 {
6768         struct si_power_info *si_pi = si_get_pi(adev);
6769         u32 tmp;
6770
6771         if (!si_pi->fan_ctrl_is_in_default_mode) {
6772                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6773                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6774                 WREG32(CG_FDO_CTRL2, tmp);
6775
6776                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6777                 tmp |= TMIN(si_pi->t_min);
6778                 WREG32(CG_FDO_CTRL2, tmp);
6779                 si_pi->fan_ctrl_is_in_default_mode = true;
6780         }
6781 }
6782
6783 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6784 {
6785         if (adev->pm.dpm.fan.ucode_fan_control) {
6786                 si_fan_ctrl_start_smc_fan_control(adev);
6787                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6788         }
6789 }
6790
6791 static void si_thermal_initialize(struct amdgpu_device *adev)
6792 {
6793         u32 tmp;
6794
6795         if (adev->pm.fan_pulses_per_revolution) {
6796                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6797                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6798                 WREG32(CG_TACH_CTRL, tmp);
6799         }
6800
6801         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6802         tmp |= TACH_PWM_RESP_RATE(0x28);
6803         WREG32(CG_FDO_CTRL2, tmp);
6804 }
6805
6806 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6807 {
6808         int ret;
6809
6810         si_thermal_initialize(adev);
6811         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6812         if (ret)
6813                 return ret;
6814         ret = si_thermal_enable_alert(adev, true);
6815         if (ret)
6816                 return ret;
6817         if (adev->pm.dpm.fan.ucode_fan_control) {
6818                 ret = si_halt_smc(adev);
6819                 if (ret)
6820                         return ret;
6821                 ret = si_thermal_setup_fan_table(adev);
6822                 if (ret)
6823                         return ret;
6824                 ret = si_resume_smc(adev);
6825                 if (ret)
6826                         return ret;
6827                 si_thermal_start_smc_fan_control(adev);
6828         }
6829
6830         return 0;
6831 }
6832
6833 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6834 {
6835         if (!adev->pm.no_fan) {
6836                 si_fan_ctrl_set_default_mode(adev);
6837                 si_fan_ctrl_stop_smc_fan_control(adev);
6838         }
6839 }
6840
6841 static int si_dpm_enable(struct amdgpu_device *adev)
6842 {
6843         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6844         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6845         struct si_power_info *si_pi = si_get_pi(adev);
6846         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6847         int ret;
6848
6849         if (amdgpu_si_is_smc_running(adev))
6850                 return -EINVAL;
6851         if (pi->voltage_control || si_pi->voltage_control_svi2)
6852                 si_enable_voltage_control(adev, true);
6853         if (pi->mvdd_control)
6854                 si_get_mvdd_configuration(adev);
6855         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6856                 ret = si_construct_voltage_tables(adev);
6857                 if (ret) {
6858                         DRM_ERROR("si_construct_voltage_tables failed\n");
6859                         return ret;
6860                 }
6861         }
6862         if (eg_pi->dynamic_ac_timing) {
6863                 ret = si_initialize_mc_reg_table(adev);
6864                 if (ret)
6865                         eg_pi->dynamic_ac_timing = false;
6866         }
6867         if (pi->dynamic_ss)
6868                 si_enable_spread_spectrum(adev, true);
6869         if (pi->thermal_protection)
6870                 si_enable_thermal_protection(adev, true);
6871         si_setup_bsp(adev);
6872         si_program_git(adev);
6873         si_program_tp(adev);
6874         si_program_tpp(adev);
6875         si_program_sstp(adev);
6876         si_enable_display_gap(adev);
6877         si_program_vc(adev);
6878         ret = si_upload_firmware(adev);
6879         if (ret) {
6880                 DRM_ERROR("si_upload_firmware failed\n");
6881                 return ret;
6882         }
6883         ret = si_process_firmware_header(adev);
6884         if (ret) {
6885                 DRM_ERROR("si_process_firmware_header failed\n");
6886                 return ret;
6887         }
6888         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6889         if (ret) {
6890                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6891                 return ret;
6892         }
6893         ret = si_init_smc_table(adev);
6894         if (ret) {
6895                 DRM_ERROR("si_init_smc_table failed\n");
6896                 return ret;
6897         }
6898         ret = si_init_smc_spll_table(adev);
6899         if (ret) {
6900                 DRM_ERROR("si_init_smc_spll_table failed\n");
6901                 return ret;
6902         }
6903         ret = si_init_arb_table_index(adev);
6904         if (ret) {
6905                 DRM_ERROR("si_init_arb_table_index failed\n");
6906                 return ret;
6907         }
6908         if (eg_pi->dynamic_ac_timing) {
6909                 ret = si_populate_mc_reg_table(adev, boot_ps);
6910                 if (ret) {
6911                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6912                         return ret;
6913                 }
6914         }
6915         ret = si_initialize_smc_cac_tables(adev);
6916         if (ret) {
6917                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6918                 return ret;
6919         }
6920         ret = si_initialize_hardware_cac_manager(adev);
6921         if (ret) {
6922                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6923                 return ret;
6924         }
6925         ret = si_initialize_smc_dte_tables(adev);
6926         if (ret) {
6927                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6928                 return ret;
6929         }
6930         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6931         if (ret) {
6932                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6933                 return ret;
6934         }
6935         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6936         if (ret) {
6937                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6938                 return ret;
6939         }
6940         si_program_response_times(adev);
6941         si_program_ds_registers(adev);
6942         si_dpm_start_smc(adev);
6943         ret = si_notify_smc_display_change(adev, false);
6944         if (ret) {
6945                 DRM_ERROR("si_notify_smc_display_change failed\n");
6946                 return ret;
6947         }
6948         si_enable_sclk_control(adev, true);
6949         si_start_dpm(adev);
6950
6951         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6952         si_thermal_start_thermal_controller(adev);
6953         ni_update_current_ps(adev, boot_ps);
6954
6955         return 0;
6956 }
6957
6958 static int si_set_temperature_range(struct amdgpu_device *adev)
6959 {
6960         int ret;
6961
6962         ret = si_thermal_enable_alert(adev, false);
6963         if (ret)
6964                 return ret;
6965         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6966         if (ret)
6967                 return ret;
6968         ret = si_thermal_enable_alert(adev, true);
6969         if (ret)
6970                 return ret;
6971
6972         return ret;
6973 }
6974
6975 static void si_dpm_disable(struct amdgpu_device *adev)
6976 {
6977         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6978         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6979
6980         if (!amdgpu_si_is_smc_running(adev))
6981                 return;
6982         si_thermal_stop_thermal_controller(adev);
6983         si_disable_ulv(adev);
6984         si_clear_vc(adev);
6985         if (pi->thermal_protection)
6986                 si_enable_thermal_protection(adev, false);
6987         si_enable_power_containment(adev, boot_ps, false);
6988         si_enable_smc_cac(adev, boot_ps, false);
6989         si_enable_spread_spectrum(adev, false);
6990         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6991         si_stop_dpm(adev);
6992         si_reset_to_default(adev);
6993         si_dpm_stop_smc(adev);
6994         si_force_switch_to_arb_f0(adev);
6995
6996         ni_update_current_ps(adev, boot_ps);
6997 }
6998
6999 static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
7000 {
7001         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7002         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
7003         struct amdgpu_ps *new_ps = &requested_ps;
7004
7005         ni_update_requested_ps(adev, new_ps);
7006         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
7007
7008         return 0;
7009 }
7010
7011 static int si_power_control_set_level(struct amdgpu_device *adev)
7012 {
7013         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
7014         int ret;
7015
7016         ret = si_restrict_performance_levels_before_switch(adev);
7017         if (ret)
7018                 return ret;
7019         ret = si_halt_smc(adev);
7020         if (ret)
7021                 return ret;
7022         ret = si_populate_smc_tdp_limits(adev, new_ps);
7023         if (ret)
7024                 return ret;
7025         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7026         if (ret)
7027                 return ret;
7028         ret = si_resume_smc(adev);
7029         if (ret)
7030                 return ret;
7031         ret = si_set_sw_state(adev);
7032         if (ret)
7033                 return ret;
7034         return 0;
7035 }
7036
7037 static int si_dpm_set_power_state(struct amdgpu_device *adev)
7038 {
7039         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7040         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7041         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7042         int ret;
7043
7044         ret = si_disable_ulv(adev);
7045         if (ret) {
7046                 DRM_ERROR("si_disable_ulv failed\n");
7047                 return ret;
7048         }
7049         ret = si_restrict_performance_levels_before_switch(adev);
7050         if (ret) {
7051                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7052                 return ret;
7053         }
7054         if (eg_pi->pcie_performance_request)
7055                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7056         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7057         ret = si_enable_power_containment(adev, new_ps, false);
7058         if (ret) {
7059                 DRM_ERROR("si_enable_power_containment failed\n");
7060                 return ret;
7061         }
7062         ret = si_enable_smc_cac(adev, new_ps, false);
7063         if (ret) {
7064                 DRM_ERROR("si_enable_smc_cac failed\n");
7065                 return ret;
7066         }
7067         ret = si_halt_smc(adev);
7068         if (ret) {
7069                 DRM_ERROR("si_halt_smc failed\n");
7070                 return ret;
7071         }
7072         ret = si_upload_sw_state(adev, new_ps);
7073         if (ret) {
7074                 DRM_ERROR("si_upload_sw_state failed\n");
7075                 return ret;
7076         }
7077         ret = si_upload_smc_data(adev);
7078         if (ret) {
7079                 DRM_ERROR("si_upload_smc_data failed\n");
7080                 return ret;
7081         }
7082         ret = si_upload_ulv_state(adev);
7083         if (ret) {
7084                 DRM_ERROR("si_upload_ulv_state failed\n");
7085                 return ret;
7086         }
7087         if (eg_pi->dynamic_ac_timing) {
7088                 ret = si_upload_mc_reg_table(adev, new_ps);
7089                 if (ret) {
7090                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7091                         return ret;
7092                 }
7093         }
7094         ret = si_program_memory_timing_parameters(adev, new_ps);
7095         if (ret) {
7096                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7097                 return ret;
7098         }
7099         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7100
7101         ret = si_resume_smc(adev);
7102         if (ret) {
7103                 DRM_ERROR("si_resume_smc failed\n");
7104                 return ret;
7105         }
7106         ret = si_set_sw_state(adev);
7107         if (ret) {
7108                 DRM_ERROR("si_set_sw_state failed\n");
7109                 return ret;
7110         }
7111         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7112         if (eg_pi->pcie_performance_request)
7113                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7114         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7115         if (ret) {
7116                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7117                 return ret;
7118         }
7119         ret = si_enable_smc_cac(adev, new_ps, true);
7120         if (ret) {
7121                 DRM_ERROR("si_enable_smc_cac failed\n");
7122                 return ret;
7123         }
7124         ret = si_enable_power_containment(adev, new_ps, true);
7125         if (ret) {
7126                 DRM_ERROR("si_enable_power_containment failed\n");
7127                 return ret;
7128         }
7129
7130         ret = si_power_control_set_level(adev);
7131         if (ret) {
7132                 DRM_ERROR("si_power_control_set_level failed\n");
7133                 return ret;
7134         }
7135
7136         return 0;
7137 }
7138
7139 static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7140 {
7141         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7142         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7143
7144         ni_update_current_ps(adev, new_ps);
7145 }
7146
7147 #if 0
7148 void si_dpm_reset_asic(struct amdgpu_device *adev)
7149 {
7150         si_restrict_performance_levels_before_switch(adev);
7151         si_disable_ulv(adev);
7152         si_set_boot_state(adev);
7153 }
7154 #endif
7155
7156 static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7157 {
7158         si_program_display_gap(adev);
7159 }
7160
7161
7162 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7163                                           struct amdgpu_ps *rps,
7164                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7165                                           u8 table_rev)
7166 {
7167         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7168         rps->class = le16_to_cpu(non_clock_info->usClassification);
7169         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7170
7171         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7172                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7173                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7174         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7175                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7176                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7177         } else {
7178                 rps->vclk = 0;
7179                 rps->dclk = 0;
7180         }
7181
7182         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7183                 adev->pm.dpm.boot_ps = rps;
7184         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7185                 adev->pm.dpm.uvd_ps = rps;
7186 }
7187
7188 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7189                                       struct amdgpu_ps *rps, int index,
7190                                       union pplib_clock_info *clock_info)
7191 {
7192         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7193         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7194         struct si_power_info *si_pi = si_get_pi(adev);
7195         struct  si_ps *ps = si_get_ps(rps);
7196         u16 leakage_voltage;
7197         struct rv7xx_pl *pl = &ps->performance_levels[index];
7198         int ret;
7199
7200         ps->performance_level_count = index + 1;
7201
7202         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7203         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7204         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7205         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7206
7207         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7208         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7209         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7210         pl->pcie_gen = r600_get_pcie_gen_support(adev,
7211                                                  si_pi->sys_pcie_mask,
7212                                                  si_pi->boot_pcie_gen,
7213                                                  clock_info->si.ucPCIEGen);
7214
7215         /* patch up vddc if necessary */
7216         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7217                                                         &leakage_voltage);
7218         if (ret == 0)
7219                 pl->vddc = leakage_voltage;
7220
7221         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7222                 pi->acpi_vddc = pl->vddc;
7223                 eg_pi->acpi_vddci = pl->vddci;
7224                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7225         }
7226
7227         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7228             index == 0) {
7229                 /* XXX disable for A0 tahiti */
7230                 si_pi->ulv.supported = false;
7231                 si_pi->ulv.pl = *pl;
7232                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7233                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7234                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7235                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7236         }
7237
7238         if (pi->min_vddc_in_table > pl->vddc)
7239                 pi->min_vddc_in_table = pl->vddc;
7240
7241         if (pi->max_vddc_in_table < pl->vddc)
7242                 pi->max_vddc_in_table = pl->vddc;
7243
7244         /* patch up boot state */
7245         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7246                 u16 vddc, vddci, mvdd;
7247                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7248                 pl->mclk = adev->clock.default_mclk;
7249                 pl->sclk = adev->clock.default_sclk;
7250                 pl->vddc = vddc;
7251                 pl->vddci = vddci;
7252                 si_pi->mvdd_bootup_value = mvdd;
7253         }
7254
7255         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7256             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7257                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7258                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7259                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7260                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7261         }
7262 }
7263
7264 union pplib_power_state {
7265         struct _ATOM_PPLIB_STATE v1;
7266         struct _ATOM_PPLIB_STATE_V2 v2;
7267 };
7268
7269 static int si_parse_power_table(struct amdgpu_device *adev)
7270 {
7271         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7272         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7273         union pplib_power_state *power_state;
7274         int i, j, k, non_clock_array_index, clock_array_index;
7275         union pplib_clock_info *clock_info;
7276         struct _StateArray *state_array;
7277         struct _ClockInfoArray *clock_info_array;
7278         struct _NonClockInfoArray *non_clock_info_array;
7279         union power_info *power_info;
7280         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7281         u16 data_offset;
7282         u8 frev, crev;
7283         u8 *power_state_offset;
7284         struct  si_ps *ps;
7285
7286         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7287                                    &frev, &crev, &data_offset))
7288                 return -EINVAL;
7289         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7290
7291         amdgpu_add_thermal_controller(adev);
7292
7293         state_array = (struct _StateArray *)
7294                 (mode_info->atom_context->bios + data_offset +
7295                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7296         clock_info_array = (struct _ClockInfoArray *)
7297                 (mode_info->atom_context->bios + data_offset +
7298                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7299         non_clock_info_array = (struct _NonClockInfoArray *)
7300                 (mode_info->atom_context->bios + data_offset +
7301                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7302
7303         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7304                                   state_array->ucNumEntries, GFP_KERNEL);
7305         if (!adev->pm.dpm.ps)
7306                 return -ENOMEM;
7307         power_state_offset = (u8 *)state_array->states;
7308         for (i = 0; i < state_array->ucNumEntries; i++) {
7309                 u8 *idx;
7310                 power_state = (union pplib_power_state *)power_state_offset;
7311                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7312                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7313                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7314                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7315                 if (ps == NULL) {
7316                         kfree(adev->pm.dpm.ps);
7317                         return -ENOMEM;
7318                 }
7319                 adev->pm.dpm.ps[i].ps_priv = ps;
7320                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7321                                               non_clock_info,
7322                                               non_clock_info_array->ucEntrySize);
7323                 k = 0;
7324                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7325                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7326                         clock_array_index = idx[j];
7327                         if (clock_array_index >= clock_info_array->ucNumEntries)
7328                                 continue;
7329                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7330                                 break;
7331                         clock_info = (union pplib_clock_info *)
7332                                 ((u8 *)&clock_info_array->clockInfo[0] +
7333                                  (clock_array_index * clock_info_array->ucEntrySize));
7334                         si_parse_pplib_clock_info(adev,
7335                                                   &adev->pm.dpm.ps[i], k,
7336                                                   clock_info);
7337                         k++;
7338                 }
7339                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7340         }
7341         adev->pm.dpm.num_ps = state_array->ucNumEntries;
7342
7343         /* fill in the vce power states */
7344         for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
7345                 u32 sclk, mclk;
7346                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7347                 clock_info = (union pplib_clock_info *)
7348                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7349                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7350                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7351                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7352                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7353                 adev->pm.dpm.vce_states[i].sclk = sclk;
7354                 adev->pm.dpm.vce_states[i].mclk = mclk;
7355         }
7356
7357         return 0;
7358 }
7359
7360 static int si_dpm_init(struct amdgpu_device *adev)
7361 {
7362         struct rv7xx_power_info *pi;
7363         struct evergreen_power_info *eg_pi;
7364         struct ni_power_info *ni_pi;
7365         struct si_power_info *si_pi;
7366         struct atom_clock_dividers dividers;
7367         int ret;
7368         u32 mask;
7369
7370         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7371         if (si_pi == NULL)
7372                 return -ENOMEM;
7373         adev->pm.dpm.priv = si_pi;
7374         ni_pi = &si_pi->ni;
7375         eg_pi = &ni_pi->eg;
7376         pi = &eg_pi->rv7xx;
7377
7378         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7379         if (ret)
7380                 si_pi->sys_pcie_mask = 0;
7381         else
7382                 si_pi->sys_pcie_mask = mask;
7383         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7384         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7385
7386         si_set_max_cu_value(adev);
7387
7388         rv770_get_max_vddc(adev);
7389         si_get_leakage_vddc(adev);
7390         si_patch_dependency_tables_based_on_leakage(adev);
7391
7392         pi->acpi_vddc = 0;
7393         eg_pi->acpi_vddci = 0;
7394         pi->min_vddc_in_table = 0;
7395         pi->max_vddc_in_table = 0;
7396
7397         ret = amdgpu_get_platform_caps(adev);
7398         if (ret)
7399                 return ret;
7400
7401         ret = amdgpu_parse_extended_power_table(adev);
7402         if (ret)
7403                 return ret;
7404
7405         ret = si_parse_power_table(adev);
7406         if (ret)
7407                 return ret;
7408
7409         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7410                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7411         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7412                 amdgpu_free_extended_power_table(adev);
7413                 return -ENOMEM;
7414         }
7415         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7416         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7417         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7418         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7419         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7420         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7421         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7422         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7423         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7424
7425         if (adev->pm.dpm.voltage_response_time == 0)
7426                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7427         if (adev->pm.dpm.backbias_response_time == 0)
7428                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7429
7430         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7431                                              0, false, &dividers);
7432         if (ret)
7433                 pi->ref_div = dividers.ref_div + 1;
7434         else
7435                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7436
7437         eg_pi->smu_uvd_hs = false;
7438
7439         pi->mclk_strobe_mode_threshold = 40000;
7440         if (si_is_special_1gb_platform(adev))
7441                 pi->mclk_stutter_mode_threshold = 0;
7442         else
7443                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7444         pi->mclk_edc_enable_threshold = 40000;
7445         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7446
7447         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7448
7449         pi->voltage_control =
7450                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7451                                             VOLTAGE_OBJ_GPIO_LUT);
7452         if (!pi->voltage_control) {
7453                 si_pi->voltage_control_svi2 =
7454                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7455                                                     VOLTAGE_OBJ_SVID2);
7456                 if (si_pi->voltage_control_svi2)
7457                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7458                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7459         }
7460
7461         pi->mvdd_control =
7462                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7463                                             VOLTAGE_OBJ_GPIO_LUT);
7464
7465         eg_pi->vddci_control =
7466                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7467                                             VOLTAGE_OBJ_GPIO_LUT);
7468         if (!eg_pi->vddci_control)
7469                 si_pi->vddci_control_svi2 =
7470                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7471                                                     VOLTAGE_OBJ_SVID2);
7472
7473         si_pi->vddc_phase_shed_control =
7474                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7475                                             VOLTAGE_OBJ_PHASE_LUT);
7476
7477         rv770_get_engine_memory_ss(adev);
7478
7479         pi->asi = RV770_ASI_DFLT;
7480         pi->pasi = CYPRESS_HASI_DFLT;
7481         pi->vrc = SISLANDS_VRC_DFLT;
7482
7483         pi->gfx_clock_gating = true;
7484
7485         eg_pi->sclk_deep_sleep = true;
7486         si_pi->sclk_deep_sleep_above_low = false;
7487
7488         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7489                 pi->thermal_protection = true;
7490         else
7491                 pi->thermal_protection = false;
7492
7493         eg_pi->dynamic_ac_timing = true;
7494
7495         eg_pi->light_sleep = true;
7496 #if defined(CONFIG_ACPI)
7497         eg_pi->pcie_performance_request =
7498                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7499 #else
7500         eg_pi->pcie_performance_request = false;
7501 #endif
7502
7503         si_pi->sram_end = SMC_RAM_END;
7504
7505         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7506         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7507         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7508         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7509         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7510         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7511         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7512
7513         si_initialize_powertune_defaults(adev);
7514
7515         /* make sure dc limits are valid */
7516         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7517             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7518                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7519                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7520
7521         si_pi->fan_ctrl_is_in_default_mode = true;
7522
7523         return 0;
7524 }
7525
7526 static void si_dpm_fini(struct amdgpu_device *adev)
7527 {
7528         int i;
7529
7530         if (adev->pm.dpm.ps)
7531                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7532                         kfree(adev->pm.dpm.ps[i].ps_priv);
7533         kfree(adev->pm.dpm.ps);
7534         kfree(adev->pm.dpm.priv);
7535         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7536         amdgpu_free_extended_power_table(adev);
7537 }
7538
7539 static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7540                                                     struct seq_file *m)
7541 {
7542         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7543         struct amdgpu_ps *rps = &eg_pi->current_rps;
7544         struct  si_ps *ps = si_get_ps(rps);
7545         struct rv7xx_pl *pl;
7546         u32 current_index =
7547                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7548                 CURRENT_STATE_INDEX_SHIFT;
7549
7550         if (current_index >= ps->performance_level_count) {
7551                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7552         } else {
7553                 pl = &ps->performance_levels[current_index];
7554                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7555                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7556                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7557         }
7558 }
7559
7560 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7561                                       struct amdgpu_irq_src *source,
7562                                       unsigned type,
7563                                       enum amdgpu_interrupt_state state)
7564 {
7565         u32 cg_thermal_int;
7566
7567         switch (type) {
7568         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7569                 switch (state) {
7570                 case AMDGPU_IRQ_STATE_DISABLE:
7571                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7572                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7573                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7574                         break;
7575                 case AMDGPU_IRQ_STATE_ENABLE:
7576                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7577                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7578                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7579                         break;
7580                 default:
7581                         break;
7582                 }
7583                 break;
7584
7585         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7586                 switch (state) {
7587                 case AMDGPU_IRQ_STATE_DISABLE:
7588                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7589                         cg_thermal_int |= THERM_INT_MASK_LOW;
7590                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7591                         break;
7592                 case AMDGPU_IRQ_STATE_ENABLE:
7593                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7594                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7595                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7596                         break;
7597                 default:
7598                         break;
7599                 }
7600                 break;
7601
7602         default:
7603                 break;
7604         }
7605         return 0;
7606 }
7607
7608 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7609                                     struct amdgpu_irq_src *source,
7610                                     struct amdgpu_iv_entry *entry)
7611 {
7612         bool queue_thermal = false;
7613
7614         if (entry == NULL)
7615                 return -EINVAL;
7616
7617         switch (entry->src_id) {
7618         case 230: /* thermal low to high */
7619                 DRM_DEBUG("IH: thermal low to high\n");
7620                 adev->pm.dpm.thermal.high_to_low = false;
7621                 queue_thermal = true;
7622                 break;
7623         case 231: /* thermal high to low */
7624                 DRM_DEBUG("IH: thermal high to low\n");
7625                 adev->pm.dpm.thermal.high_to_low = true;
7626                 queue_thermal = true;
7627                 break;
7628         default:
7629                 break;
7630         }
7631
7632         if (queue_thermal)
7633                 schedule_work(&adev->pm.dpm.thermal.work);
7634
7635         return 0;
7636 }
7637
7638 static int si_dpm_late_init(void *handle)
7639 {
7640         int ret;
7641         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7642
7643         if (!amdgpu_dpm)
7644                 return 0;
7645
7646         /* init the sysfs and debugfs files late */
7647         ret = amdgpu_pm_sysfs_init(adev);
7648         if (ret)
7649                 return ret;
7650
7651         ret = si_set_temperature_range(adev);
7652         if (ret)
7653                 return ret;
7654 #if 0 //TODO ?
7655         si_dpm_powergate_uvd(adev, true);
7656 #endif
7657         return 0;
7658 }
7659
7660 /**
7661  * si_dpm_init_microcode - load ucode images from disk
7662  *
7663  * @adev: amdgpu_device pointer
7664  *
7665  * Use the firmware interface to load the ucode images into
7666  * the driver (not loaded into hw).
7667  * Returns 0 on success, error on failure.
7668  */
7669 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7670 {
7671         const char *chip_name;
7672         char fw_name[30];
7673         int err;
7674
7675         DRM_DEBUG("\n");
7676         switch (adev->asic_type) {
7677         case CHIP_TAHITI:
7678                 chip_name = "tahiti";
7679                 break;
7680         case CHIP_PITCAIRN:
7681                 if ((adev->pdev->revision == 0x81) &&
7682                     ((adev->pdev->device == 0x6810) ||
7683                     (adev->pdev->device == 0x6811)))
7684                         chip_name = "pitcairn_k";
7685                 else
7686                         chip_name = "pitcairn";
7687                 break;
7688         case CHIP_VERDE:
7689                 if (((adev->pdev->device == 0x6820) &&
7690                         ((adev->pdev->revision == 0x81) ||
7691                         (adev->pdev->revision == 0x83))) ||
7692                     ((adev->pdev->device == 0x6821) &&
7693                         ((adev->pdev->revision == 0x83) ||
7694                         (adev->pdev->revision == 0x87))) ||
7695                     ((adev->pdev->revision == 0x87) &&
7696                         ((adev->pdev->device == 0x6823) ||
7697                         (adev->pdev->device == 0x682b))))
7698                         chip_name = "verde_k";
7699                 else
7700                         chip_name = "verde";
7701                 break;
7702         case CHIP_OLAND:
7703                 if (((adev->pdev->revision == 0x81) &&
7704                         ((adev->pdev->device == 0x6600) ||
7705                         (adev->pdev->device == 0x6604) ||
7706                         (adev->pdev->device == 0x6605) ||
7707                         (adev->pdev->device == 0x6610))) ||
7708                     ((adev->pdev->revision == 0x83) &&
7709                         (adev->pdev->device == 0x6610)))
7710                         chip_name = "oland_k";
7711                 else
7712                         chip_name = "oland";
7713                 break;
7714         case CHIP_HAINAN:
7715                 if (((adev->pdev->revision == 0x81) &&
7716                         (adev->pdev->device == 0x6660)) ||
7717                     ((adev->pdev->revision == 0x83) &&
7718                         ((adev->pdev->device == 0x6660) ||
7719                         (adev->pdev->device == 0x6663) ||
7720                         (adev->pdev->device == 0x6665) ||
7721                          (adev->pdev->device == 0x6667))))
7722                         chip_name = "hainan_k";
7723                 else if ((adev->pdev->revision == 0xc3) &&
7724                          (adev->pdev->device == 0x6665))
7725                         chip_name = "banks_k_2";
7726                 else
7727                         chip_name = "hainan";
7728                 break;
7729         default: BUG();
7730         }
7731
7732         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
7733         err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
7734         if (err)
7735                 goto out;
7736         err = amdgpu_ucode_validate(adev->pm.fw);
7737
7738 out:
7739         if (err) {
7740                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7741                           err, fw_name);
7742                 release_firmware(adev->pm.fw);
7743                 adev->pm.fw = NULL;
7744         }
7745         return err;
7746
7747 }
7748
7749 static int si_dpm_sw_init(void *handle)
7750 {
7751         int ret;
7752         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7753
7754         ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7755         if (ret)
7756                 return ret;
7757
7758         ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7759         if (ret)
7760                 return ret;
7761
7762         /* default to balanced state */
7763         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7764         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7765         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7766         adev->pm.default_sclk = adev->clock.default_sclk;
7767         adev->pm.default_mclk = adev->clock.default_mclk;
7768         adev->pm.current_sclk = adev->clock.default_sclk;
7769         adev->pm.current_mclk = adev->clock.default_mclk;
7770         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7771
7772         if (amdgpu_dpm == 0)
7773                 return 0;
7774
7775         ret = si_dpm_init_microcode(adev);
7776         if (ret)
7777                 return ret;
7778
7779         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7780         mutex_lock(&adev->pm.mutex);
7781         ret = si_dpm_init(adev);
7782         if (ret)
7783                 goto dpm_failed;
7784         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7785         if (amdgpu_dpm == 1)
7786                 amdgpu_pm_print_power_states(adev);
7787         mutex_unlock(&adev->pm.mutex);
7788         DRM_INFO("amdgpu: dpm initialized\n");
7789
7790         return 0;
7791
7792 dpm_failed:
7793         si_dpm_fini(adev);
7794         mutex_unlock(&adev->pm.mutex);
7795         DRM_ERROR("amdgpu: dpm initialization failed\n");
7796         return ret;
7797 }
7798
7799 static int si_dpm_sw_fini(void *handle)
7800 {
7801         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7802
7803         flush_work(&adev->pm.dpm.thermal.work);
7804
7805         mutex_lock(&adev->pm.mutex);
7806         amdgpu_pm_sysfs_fini(adev);
7807         si_dpm_fini(adev);
7808         mutex_unlock(&adev->pm.mutex);
7809
7810         return 0;
7811 }
7812
7813 static int si_dpm_hw_init(void *handle)
7814 {
7815         int ret;
7816
7817         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7818
7819         if (!amdgpu_dpm)
7820                 return 0;
7821
7822         mutex_lock(&adev->pm.mutex);
7823         si_dpm_setup_asic(adev);
7824         ret = si_dpm_enable(adev);
7825         if (ret)
7826                 adev->pm.dpm_enabled = false;
7827         else
7828                 adev->pm.dpm_enabled = true;
7829         mutex_unlock(&adev->pm.mutex);
7830
7831         return ret;
7832 }
7833
7834 static int si_dpm_hw_fini(void *handle)
7835 {
7836         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7837
7838         if (adev->pm.dpm_enabled) {
7839                 mutex_lock(&adev->pm.mutex);
7840                 si_dpm_disable(adev);
7841                 mutex_unlock(&adev->pm.mutex);
7842         }
7843
7844         return 0;
7845 }
7846
7847 static int si_dpm_suspend(void *handle)
7848 {
7849         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7850
7851         if (adev->pm.dpm_enabled) {
7852                 mutex_lock(&adev->pm.mutex);
7853                 /* disable dpm */
7854                 si_dpm_disable(adev);
7855                 /* reset the power state */
7856                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7857                 mutex_unlock(&adev->pm.mutex);
7858         }
7859         return 0;
7860 }
7861
7862 static int si_dpm_resume(void *handle)
7863 {
7864         int ret;
7865         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7866
7867         if (adev->pm.dpm_enabled) {
7868                 /* asic init will reset to the boot state */
7869                 mutex_lock(&adev->pm.mutex);
7870                 si_dpm_setup_asic(adev);
7871                 ret = si_dpm_enable(adev);
7872                 if (ret)
7873                         adev->pm.dpm_enabled = false;
7874                 else
7875                         adev->pm.dpm_enabled = true;
7876                 mutex_unlock(&adev->pm.mutex);
7877                 if (adev->pm.dpm_enabled)
7878                         amdgpu_pm_compute_clocks(adev);
7879         }
7880         return 0;
7881 }
7882
7883 static bool si_dpm_is_idle(void *handle)
7884 {
7885         /* XXX */
7886         return true;
7887 }
7888
7889 static int si_dpm_wait_for_idle(void *handle)
7890 {
7891         /* XXX */
7892         return 0;
7893 }
7894
7895 static int si_dpm_soft_reset(void *handle)
7896 {
7897         return 0;
7898 }
7899
7900 static int si_dpm_set_clockgating_state(void *handle,
7901                                         enum amd_clockgating_state state)
7902 {
7903         return 0;
7904 }
7905
7906 static int si_dpm_set_powergating_state(void *handle,
7907                                         enum amd_powergating_state state)
7908 {
7909         return 0;
7910 }
7911
7912 /* get temperature in millidegrees */
7913 static int si_dpm_get_temp(struct amdgpu_device *adev)
7914 {
7915         u32 temp;
7916         int actual_temp = 0;
7917
7918         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7919                 CTF_TEMP_SHIFT;
7920
7921         if (temp & 0x200)
7922                 actual_temp = 255;
7923         else
7924                 actual_temp = temp & 0x1ff;
7925
7926         actual_temp = (actual_temp * 1000);
7927
7928         return actual_temp;
7929 }
7930
7931 static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7932 {
7933         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7934         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7935
7936         if (low)
7937                 return requested_state->performance_levels[0].sclk;
7938         else
7939                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7940 }
7941
7942 static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7943 {
7944         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7945         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7946
7947         if (low)
7948                 return requested_state->performance_levels[0].mclk;
7949         else
7950                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7951 }
7952
7953 static void si_dpm_print_power_state(struct amdgpu_device *adev,
7954                                      struct amdgpu_ps *rps)
7955 {
7956         struct  si_ps *ps = si_get_ps(rps);
7957         struct rv7xx_pl *pl;
7958         int i;
7959
7960         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7961         amdgpu_dpm_print_cap_info(rps->caps);
7962         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7963         for (i = 0; i < ps->performance_level_count; i++) {
7964                 pl = &ps->performance_levels[i];
7965                 if (adev->asic_type >= CHIP_TAHITI)
7966                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7967                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7968                 else
7969                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7970                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7971         }
7972         amdgpu_dpm_print_ps_status(adev, rps);
7973 }
7974
7975 static int si_dpm_early_init(void *handle)
7976 {
7977
7978         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7979
7980         si_dpm_set_dpm_funcs(adev);
7981         si_dpm_set_irq_funcs(adev);
7982         return 0;
7983 }
7984
7985
7986 const struct amd_ip_funcs si_dpm_ip_funcs = {
7987         .name = "si_dpm",
7988         .early_init = si_dpm_early_init,
7989         .late_init = si_dpm_late_init,
7990         .sw_init = si_dpm_sw_init,
7991         .sw_fini = si_dpm_sw_fini,
7992         .hw_init = si_dpm_hw_init,
7993         .hw_fini = si_dpm_hw_fini,
7994         .suspend = si_dpm_suspend,
7995         .resume = si_dpm_resume,
7996         .is_idle = si_dpm_is_idle,
7997         .wait_for_idle = si_dpm_wait_for_idle,
7998         .soft_reset = si_dpm_soft_reset,
7999         .set_clockgating_state = si_dpm_set_clockgating_state,
8000         .set_powergating_state = si_dpm_set_powergating_state,
8001 };
8002
8003 static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8004         .get_temperature = &si_dpm_get_temp,
8005         .pre_set_power_state = &si_dpm_pre_set_power_state,
8006         .set_power_state = &si_dpm_set_power_state,
8007         .post_set_power_state = &si_dpm_post_set_power_state,
8008         .display_configuration_changed = &si_dpm_display_configuration_changed,
8009         .get_sclk = &si_dpm_get_sclk,
8010         .get_mclk = &si_dpm_get_mclk,
8011         .print_power_state = &si_dpm_print_power_state,
8012         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8013         .force_performance_level = &si_dpm_force_performance_level,
8014         .vblank_too_short = &si_dpm_vblank_too_short,
8015         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8016         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8017         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8018         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8019 };
8020
8021 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8022 {
8023         if (adev->pm.funcs == NULL)
8024                 adev->pm.funcs = &si_dpm_funcs;
8025 }
8026
8027 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8028         .set = si_dpm_set_interrupt_state,
8029         .process = si_dpm_process_interrupt,
8030 };
8031
8032 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8033 {
8034         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8035         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8036 }
8037