2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "amdgpu_pm.h"
27 #include "amdgpu_dpm.h"
28 #include "amdgpu_atombios.h"
33 #include "../include/pptable.h"
34 #include <linux/math64.h>
35 #include <linux/seq_file.h>
36 #include <linux/firmware.h>
38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define SMC_RAM_END 0x20000
45 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
48 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
49 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
56 #define BIOS_SCRATCH_4 0x5cd
61 struct _ATOM_POWERPLAY_INFO info;
62 struct _ATOM_POWERPLAY_INFO_V2 info_2;
63 struct _ATOM_POWERPLAY_INFO_V3 info_3;
64 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
65 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
66 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
67 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
68 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
72 struct _ATOM_PPLIB_FANTABLE fan;
73 struct _ATOM_PPLIB_FANTABLE2 fan2;
74 struct _ATOM_PPLIB_FANTABLE3 fan3;
77 union pplib_clock_info {
78 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
79 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
80 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
81 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
82 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
85 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
104 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
123 static const struct si_cac_config_reg cac_weights_tahiti[] =
125 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
126 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
127 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
128 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
129 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
130 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
131 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
132 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
133 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
134 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
135 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
136 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
137 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
138 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
139 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
140 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
141 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
143 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
144 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
145 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
146 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
147 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
148 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
149 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
150 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
151 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
152 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
154 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
155 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
156 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
157 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
160 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
161 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
165 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
168 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
169 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
172 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
174 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
188 static const struct si_cac_config_reg lcac_tahiti[] =
190 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
191 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
193 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
195 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
197 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
198 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
199 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
200 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
201 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
202 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
203 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
204 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
205 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
206 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
207 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
208 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
209 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
210 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
211 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
212 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
213 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
214 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
215 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
216 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
217 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
218 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
219 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
220 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
221 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
222 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
223 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
224 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
225 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
226 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
227 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
228 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
229 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
230 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
231 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
232 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
233 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
234 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
235 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
236 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
237 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
238 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
239 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
240 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
241 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
242 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
243 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
244 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
245 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
246 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
247 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
248 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
249 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
250 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
251 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
252 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
253 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
254 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
255 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
256 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
257 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
258 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
259 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
260 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
261 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
262 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
263 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
264 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
265 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
266 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
267 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
268 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
269 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
270 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
271 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
272 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
273 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
274 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
275 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
280 static const struct si_cac_config_reg cac_override_tahiti[] =
285 static const struct si_powertune_data powertune_data_tahiti =
316 static const struct si_dte_data dte_data_tahiti =
318 { 1159409, 0, 0, 0, 0 },
327 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
328 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
329 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
335 static const struct si_dte_data dte_data_tahiti_le =
337 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
338 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
346 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
347 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
348 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
354 static const struct si_dte_data dte_data_tahiti_pro =
356 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
357 { 0x0, 0x0, 0x0, 0x0, 0x0 },
365 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
366 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
367 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
372 static const struct si_dte_data dte_data_new_zealand =
374 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
375 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
383 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
384 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
385 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
390 static const struct si_dte_data dte_data_aruba_pro =
392 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
393 { 0x0, 0x0, 0x0, 0x0, 0x0 },
401 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
402 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
403 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
408 static const struct si_dte_data dte_data_malta =
410 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
411 { 0x0, 0x0, 0x0, 0x0, 0x0 },
419 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
420 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
421 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
426 static const struct si_cac_config_reg cac_weights_pitcairn[] =
428 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
429 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
430 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
431 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
432 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
433 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
434 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
435 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
436 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
437 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
438 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
439 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
440 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
441 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
442 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
443 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
444 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
445 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
446 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
447 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
448 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
449 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
450 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
451 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
452 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
453 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
454 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
455 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
456 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
457 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
458 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
459 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
460 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
461 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
463 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
464 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
465 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
466 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
467 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
468 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
470 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
472 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
473 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
474 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
476 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
491 static const struct si_cac_config_reg lcac_pitcairn[] =
493 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
497 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
498 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
499 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
500 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
501 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
502 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
503 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
504 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
505 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
506 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
507 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
508 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
509 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
510 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
511 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
512 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
513 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
514 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
515 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
516 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
517 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
518 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
519 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
520 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
521 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
522 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
523 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
524 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
525 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
526 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
527 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
528 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
529 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
530 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
531 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
532 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
533 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
534 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
535 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
536 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
537 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
538 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
539 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
540 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
541 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
542 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
543 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
544 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
545 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
546 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
547 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
548 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
549 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
550 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
551 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
552 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
553 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
554 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
555 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
556 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
557 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
558 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
559 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
560 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
561 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
562 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
563 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
564 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
565 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
566 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
567 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
568 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
569 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
570 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
571 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
572 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
573 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
574 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
575 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
576 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
577 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
578 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 static const struct si_cac_config_reg cac_override_pitcairn[] =
587 static const struct si_powertune_data powertune_data_pitcairn =
618 static const struct si_dte_data dte_data_pitcairn =
629 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
630 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
631 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
636 static const struct si_dte_data dte_data_curacao_xt =
638 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
639 { 0x0, 0x0, 0x0, 0x0, 0x0 },
647 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
648 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
649 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
654 static const struct si_dte_data dte_data_curacao_pro =
656 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
657 { 0x0, 0x0, 0x0, 0x0, 0x0 },
665 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
666 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
667 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
672 static const struct si_dte_data dte_data_neptune_xt =
674 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
675 { 0x0, 0x0, 0x0, 0x0, 0x0 },
683 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
684 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
685 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
690 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
692 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
693 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
694 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
695 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
696 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
697 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
698 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
699 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
700 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
701 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
702 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
703 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
704 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
705 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
706 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
707 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
708 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
709 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
710 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
711 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
712 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
713 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
714 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
715 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
716 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
717 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
718 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
719 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
721 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
722 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
723 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
724 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
725 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
726 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
727 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
728 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
729 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
730 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
731 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
732 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
733 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
734 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
735 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
736 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
737 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
738 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
739 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
740 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
741 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
742 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
743 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
744 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
745 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
746 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
755 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
757 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
758 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
759 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
760 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
761 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
762 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
763 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
764 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
765 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
766 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
767 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
768 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
769 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
770 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
771 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
772 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
773 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
774 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
775 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
776 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
777 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
778 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
779 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
780 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
781 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
782 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
783 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
784 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
786 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
787 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
788 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
789 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
790 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
791 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
792 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
793 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
794 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
795 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
796 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
797 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
798 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
799 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
800 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
801 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
802 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
803 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
804 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
805 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
806 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
807 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
808 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
809 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
810 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
811 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
820 static const struct si_cac_config_reg cac_weights_heathrow[] =
822 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
823 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
824 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
825 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
826 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
827 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
828 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
829 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
830 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
831 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
832 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
833 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
834 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
835 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
836 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
837 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
838 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
839 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
840 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
841 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
842 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
843 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
844 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
845 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
846 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
847 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
848 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
849 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
851 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
852 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
853 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
854 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
855 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
856 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
857 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
858 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
859 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
860 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
861 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
862 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
863 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
864 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
865 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
866 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
867 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
868 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
869 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
870 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
871 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
872 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
873 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
874 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
875 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
876 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
885 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
887 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
888 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
889 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
890 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
891 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
892 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
893 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
894 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
895 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
896 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
897 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
898 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
899 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
900 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
901 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
902 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
903 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
904 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
905 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
906 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
907 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
908 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
909 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
910 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
911 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
912 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
913 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
914 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
916 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
917 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
918 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
919 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
920 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
921 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
922 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
923 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
924 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
925 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
926 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
927 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
928 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
929 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
930 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
931 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
932 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
933 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
934 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
935 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
936 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
937 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
938 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
939 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
940 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
941 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
950 static const struct si_cac_config_reg cac_weights_cape_verde[] =
952 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
953 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
954 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
955 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
956 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
957 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
958 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
959 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
960 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
961 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
962 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
963 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
964 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
965 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
966 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
967 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
968 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
969 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
970 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
971 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
972 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
973 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
974 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
975 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
976 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
977 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
978 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
979 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
980 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
983 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
984 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
985 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
986 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
987 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
988 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
989 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
990 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
991 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
992 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
993 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
994 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
995 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
996 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
997 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
998 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
999 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1001 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1002 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1015 static const struct si_cac_config_reg lcac_cape_verde[] =
1017 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1018 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1019 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1020 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1021 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1022 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1023 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1024 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1025 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1026 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1027 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1029 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1030 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1031 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1032 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1033 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1034 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1035 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1036 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1037 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1039 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1041 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1042 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1043 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1044 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1045 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1046 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1047 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1048 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1049 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1050 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1051 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1052 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1053 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1054 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1055 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1056 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1057 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1058 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1059 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1061 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1062 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1063 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1065 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1067 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 static const struct si_cac_config_reg cac_override_cape_verde[] =
1079 static const struct si_powertune_data powertune_data_cape_verde =
1081 ((1 << 16) | 0x6993),
1110 static const struct si_dte_data dte_data_cape_verde =
1121 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1122 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1123 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1128 static const struct si_dte_data dte_data_venus_xtx =
1130 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1131 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1139 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1140 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1141 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1146 static const struct si_dte_data dte_data_venus_xt =
1148 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1149 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1157 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1158 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1159 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1164 static const struct si_dte_data dte_data_venus_pro =
1166 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1167 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1175 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1176 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1177 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1182 static const struct si_cac_config_reg cac_weights_oland[] =
1184 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1185 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1186 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1187 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1188 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1189 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1190 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1191 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1192 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1193 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1194 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1195 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1196 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1197 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1198 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1199 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1200 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1201 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1202 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1203 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1204 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1205 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1206 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1207 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1208 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1209 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1210 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1211 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1213 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1214 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1215 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1216 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1217 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1218 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1219 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1220 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1222 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1224 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1225 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1227 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1228 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1229 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1231 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1233 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1247 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1249 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1250 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1251 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1252 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1253 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1254 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1255 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1256 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1257 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1258 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1259 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1260 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1261 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1262 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1263 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1264 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1265 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1266 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1267 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1268 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1269 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1270 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1271 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1272 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1273 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1274 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1275 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1276 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1277 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1278 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1279 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1280 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1281 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1282 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1283 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1284 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1285 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1287 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1289 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1290 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1292 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1293 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1294 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1296 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1297 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1298 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1301 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1312 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1314 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1315 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1316 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1317 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1318 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1319 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1320 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1321 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1322 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1323 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1324 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1325 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1326 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1327 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1328 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1329 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1330 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1331 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1332 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1333 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1334 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1335 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1336 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1337 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1338 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1339 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1340 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1341 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1342 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1343 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1344 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1345 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1346 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1347 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1348 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1349 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1350 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1352 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1354 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1355 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1357 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1358 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1359 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1361 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1362 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1363 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1366 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1377 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1379 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1380 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1381 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1382 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1383 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1384 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1385 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1386 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1387 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1388 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1389 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1390 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1391 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1392 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1393 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1394 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1395 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1396 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1397 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1398 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1399 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1400 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1401 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1402 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1403 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1404 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1405 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1406 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1407 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1408 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1409 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1410 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1411 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1412 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1413 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1414 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1415 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1417 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1419 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1420 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1422 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1423 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1424 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1425 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1426 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1427 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1428 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1429 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1430 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1431 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1432 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1442 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1444 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1445 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1446 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1447 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1448 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1449 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1450 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1451 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1452 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1453 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1454 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1455 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1456 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1457 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1458 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1459 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1460 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1461 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1462 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1463 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1464 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1465 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1466 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1467 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1468 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1469 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1470 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1471 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1472 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1473 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1474 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1475 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1476 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1477 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1478 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1479 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1480 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1481 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1482 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1483 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1484 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1485 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1486 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1487 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1488 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1489 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1490 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1491 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1492 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1493 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1494 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1495 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1496 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1497 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1507 static const struct si_cac_config_reg lcac_oland[] =
1509 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1510 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1512 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1514 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1516 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1517 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1518 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1519 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1520 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1521 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1522 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1523 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1524 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1525 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1527 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1529 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1531 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1533 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1538 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1547 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 static const struct si_cac_config_reg lcac_mars_pro[] =
1556 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1557 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1559 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1561 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1562 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1563 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1564 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1565 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1566 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1567 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1569 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1571 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1578 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1580 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1585 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1594 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 static const struct si_cac_config_reg cac_override_oland[] =
1606 static const struct si_powertune_data powertune_data_oland =
1608 ((1 << 16) | 0x6993),
1637 static const struct si_powertune_data powertune_data_mars_pro =
1639 ((1 << 16) | 0x6993),
1668 static const struct si_dte_data dte_data_oland =
1679 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1680 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1681 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1686 static const struct si_dte_data dte_data_mars_pro =
1688 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1689 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1697 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1698 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1699 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1704 static const struct si_dte_data dte_data_sun_xt =
1706 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1707 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1715 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1716 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1717 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1723 static const struct si_cac_config_reg cac_weights_hainan[] =
1725 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1726 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1727 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1728 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1729 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1730 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1731 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1732 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1733 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1734 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1735 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1736 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1737 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1738 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1740 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1743 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1744 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1745 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1746 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1747 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1748 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1749 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1751 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1752 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1753 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1754 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1755 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1756 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1757 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1758 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1760 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1761 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1762 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1763 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1765 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1767 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1769 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1770 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1771 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1772 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1774 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1776 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1788 static const struct si_powertune_data powertune_data_hainan =
1790 ((1 << 16) | 0x6993),
1819 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1820 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1821 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1822 static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1824 static int si_populate_voltage_value(struct amdgpu_device *adev,
1825 const struct atom_voltage_table *table,
1826 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1827 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1828 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1830 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1831 u16 reg_offset, u32 value);
1832 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1833 struct rv7xx_pl *pl,
1834 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1835 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1837 SISLANDS_SMC_SCLK_VALUE *sclk);
1839 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1840 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1841 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1842 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1844 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1846 struct si_power_info *pi = adev->pm.dpm.priv;
1850 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1851 u16 v, s32 t, u32 ileakage, u32 *leakage)
1853 s64 kt, kv, leakage_w, i_leakage, vddc;
1854 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1857 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1858 vddc = div64_s64(drm_int2fixp(v), 1000);
1859 temperature = div64_s64(drm_int2fixp(t), 1000);
1861 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1862 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1863 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1864 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1865 t_ref = drm_int2fixp(coeff->t_ref);
1867 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1868 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1869 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1870 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1872 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1874 *leakage = drm_fixp2int(leakage_w * 1000);
1877 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1878 const struct ni_leakage_coeffients *coeff,
1884 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1887 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1888 const u32 fixed_kt, u16 v,
1889 u32 ileakage, u32 *leakage)
1891 s64 kt, kv, leakage_w, i_leakage, vddc;
1893 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1894 vddc = div64_s64(drm_int2fixp(v), 1000);
1896 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1897 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1898 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1900 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1902 *leakage = drm_fixp2int(leakage_w * 1000);
1905 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1906 const struct ni_leakage_coeffients *coeff,
1912 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1916 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1917 struct si_dte_data *dte_data)
1919 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1920 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1921 u32 k = dte_data->k;
1922 u32 t_max = dte_data->max_t;
1923 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1924 u32 t_0 = dte_data->t0;
1927 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1928 dte_data->tdep_count = 3;
1930 for (i = 0; i < k; i++) {
1932 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1933 (p_limit2 * (u32)100);
1936 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1938 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1939 dte_data->tdep_r[i] = dte_data->r[4];
1942 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1946 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1948 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1953 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1955 struct ni_power_info *pi = adev->pm.dpm.priv;
1960 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1962 struct si_ps *ps = aps->ps_priv;
1967 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1969 struct ni_power_info *ni_pi = ni_get_pi(adev);
1970 struct si_power_info *si_pi = si_get_pi(adev);
1971 bool update_dte_from_pl2 = false;
1973 if (adev->asic_type == CHIP_TAHITI) {
1974 si_pi->cac_weights = cac_weights_tahiti;
1975 si_pi->lcac_config = lcac_tahiti;
1976 si_pi->cac_override = cac_override_tahiti;
1977 si_pi->powertune_data = &powertune_data_tahiti;
1978 si_pi->dte_data = dte_data_tahiti;
1980 switch (adev->pdev->device) {
1982 si_pi->dte_data.enable_dte_by_default = true;
1985 si_pi->dte_data = dte_data_new_zealand;
1991 si_pi->dte_data = dte_data_aruba_pro;
1992 update_dte_from_pl2 = true;
1995 si_pi->dte_data = dte_data_malta;
1996 update_dte_from_pl2 = true;
1999 si_pi->dte_data = dte_data_tahiti_pro;
2000 update_dte_from_pl2 = true;
2003 if (si_pi->dte_data.enable_dte_by_default == true)
2004 DRM_ERROR("DTE is not enabled!\n");
2007 } else if (adev->asic_type == CHIP_PITCAIRN) {
2008 si_pi->cac_weights = cac_weights_pitcairn;
2009 si_pi->lcac_config = lcac_pitcairn;
2010 si_pi->cac_override = cac_override_pitcairn;
2011 si_pi->powertune_data = &powertune_data_pitcairn;
2013 switch (adev->pdev->device) {
2016 si_pi->dte_data = dte_data_curacao_xt;
2017 update_dte_from_pl2 = true;
2021 si_pi->dte_data = dte_data_curacao_pro;
2022 update_dte_from_pl2 = true;
2026 si_pi->dte_data = dte_data_neptune_xt;
2027 update_dte_from_pl2 = true;
2030 si_pi->dte_data = dte_data_pitcairn;
2033 } else if (adev->asic_type == CHIP_VERDE) {
2034 si_pi->lcac_config = lcac_cape_verde;
2035 si_pi->cac_override = cac_override_cape_verde;
2036 si_pi->powertune_data = &powertune_data_cape_verde;
2038 switch (adev->pdev->device) {
2043 si_pi->cac_weights = cac_weights_cape_verde_pro;
2044 si_pi->dte_data = dte_data_cape_verde;
2047 si_pi->cac_weights = cac_weights_cape_verde_pro;
2048 si_pi->dte_data = dte_data_sun_xt;
2052 si_pi->cac_weights = cac_weights_heathrow;
2053 si_pi->dte_data = dte_data_cape_verde;
2057 si_pi->cac_weights = cac_weights_chelsea_xt;
2058 si_pi->dte_data = dte_data_cape_verde;
2061 si_pi->cac_weights = cac_weights_chelsea_pro;
2062 si_pi->dte_data = dte_data_cape_verde;
2065 si_pi->cac_weights = cac_weights_heathrow;
2066 si_pi->dte_data = dte_data_venus_xtx;
2069 si_pi->cac_weights = cac_weights_heathrow;
2070 si_pi->dte_data = dte_data_venus_xt;
2076 si_pi->cac_weights = cac_weights_chelsea_pro;
2077 si_pi->dte_data = dte_data_venus_pro;
2080 si_pi->cac_weights = cac_weights_cape_verde;
2081 si_pi->dte_data = dte_data_cape_verde;
2084 } else if (adev->asic_type == CHIP_OLAND) {
2085 si_pi->lcac_config = lcac_mars_pro;
2086 si_pi->cac_override = cac_override_oland;
2087 si_pi->powertune_data = &powertune_data_mars_pro;
2088 si_pi->dte_data = dte_data_mars_pro;
2090 switch (adev->pdev->device) {
2095 si_pi->cac_weights = cac_weights_mars_pro;
2096 update_dte_from_pl2 = true;
2102 si_pi->cac_weights = cac_weights_mars_xt;
2103 update_dte_from_pl2 = true;
2108 si_pi->cac_weights = cac_weights_oland_pro;
2109 update_dte_from_pl2 = true;
2112 si_pi->cac_weights = cac_weights_oland_xt;
2113 update_dte_from_pl2 = true;
2116 si_pi->cac_weights = cac_weights_oland;
2117 si_pi->lcac_config = lcac_oland;
2118 si_pi->cac_override = cac_override_oland;
2119 si_pi->powertune_data = &powertune_data_oland;
2120 si_pi->dte_data = dte_data_oland;
2123 } else if (adev->asic_type == CHIP_HAINAN) {
2124 si_pi->cac_weights = cac_weights_hainan;
2125 si_pi->lcac_config = lcac_oland;
2126 si_pi->cac_override = cac_override_oland;
2127 si_pi->powertune_data = &powertune_data_hainan;
2128 si_pi->dte_data = dte_data_sun_xt;
2129 update_dte_from_pl2 = true;
2131 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2135 ni_pi->enable_power_containment = false;
2136 ni_pi->enable_cac = false;
2137 ni_pi->enable_sq_ramping = false;
2138 si_pi->enable_dte = false;
2140 if (si_pi->powertune_data->enable_powertune_by_default) {
2141 ni_pi->enable_power_containment = true;
2142 ni_pi->enable_cac = true;
2143 if (si_pi->dte_data.enable_dte_by_default) {
2144 si_pi->enable_dte = true;
2145 if (update_dte_from_pl2)
2146 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2149 ni_pi->enable_sq_ramping = true;
2152 ni_pi->driver_calculate_cac_leakage = true;
2153 ni_pi->cac_configuration_required = true;
2155 if (ni_pi->cac_configuration_required) {
2156 ni_pi->support_cac_long_term_average = true;
2157 si_pi->dyn_powertune_data.l2_lta_window_size =
2158 si_pi->powertune_data->l2_lta_window_size_default;
2159 si_pi->dyn_powertune_data.lts_truncate =
2160 si_pi->powertune_data->lts_truncate_default;
2162 ni_pi->support_cac_long_term_average = false;
2163 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2164 si_pi->dyn_powertune_data.lts_truncate = 0;
2167 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2170 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2175 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2180 u32 cac_window_size;
2182 xclk = amdgpu_asic_get_xclk(adev);
2187 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2188 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2190 wintime = (cac_window_size * 100) / xclk;
2195 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2197 return power_in_watts;
2200 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2201 bool adjust_polarity,
2204 u32 *near_tdp_limit)
2206 u32 adjustment_delta, max_tdp_limit;
2208 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2211 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2213 if (adjust_polarity) {
2214 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2215 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2217 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2218 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2219 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2220 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2222 *near_tdp_limit = 0;
2225 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2227 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2233 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2234 struct amdgpu_ps *amdgpu_state)
2236 struct ni_power_info *ni_pi = ni_get_pi(adev);
2237 struct si_power_info *si_pi = si_get_pi(adev);
2239 if (ni_pi->enable_power_containment) {
2240 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2241 PP_SIslands_PAPMParameters *papm_parm;
2242 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2243 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2248 if (scaling_factor == 0)
2251 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2253 ret = si_calculate_adjusted_tdp_limits(adev,
2255 adev->pm.dpm.tdp_adjustment,
2261 smc_table->dpm2Params.TDPLimit =
2262 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2263 smc_table->dpm2Params.NearTDPLimit =
2264 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2265 smc_table->dpm2Params.SafePowerLimit =
2266 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2268 ret = amdgpu_si_copy_bytes_to_smc(adev,
2269 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2270 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2271 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2277 if (si_pi->enable_ppm) {
2278 papm_parm = &si_pi->papm_parm;
2279 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2280 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2281 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2282 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2283 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2284 papm_parm->PlatformPowerLimit = 0xffffffff;
2285 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2287 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2289 sizeof(PP_SIslands_PAPMParameters),
2298 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2299 struct amdgpu_ps *amdgpu_state)
2301 struct ni_power_info *ni_pi = ni_get_pi(adev);
2302 struct si_power_info *si_pi = si_get_pi(adev);
2304 if (ni_pi->enable_power_containment) {
2305 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2306 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2309 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2311 smc_table->dpm2Params.NearTDPLimit =
2312 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2313 smc_table->dpm2Params.SafePowerLimit =
2314 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2316 ret = amdgpu_si_copy_bytes_to_smc(adev,
2317 (si_pi->state_table_start +
2318 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2319 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2320 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2331 const u16 prev_std_vddc,
2332 const u16 curr_std_vddc)
2334 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2335 u64 prev_vddc = (u64)prev_std_vddc;
2336 u64 curr_vddc = (u64)curr_std_vddc;
2337 u64 pwr_efficiency_ratio, n, d;
2339 if ((prev_vddc == 0) || (curr_vddc == 0))
2342 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2343 d = prev_vddc * prev_vddc;
2344 pwr_efficiency_ratio = div64_u64(n, d);
2346 if (pwr_efficiency_ratio > (u64)0xFFFF)
2349 return (u16)pwr_efficiency_ratio;
2352 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2353 struct amdgpu_ps *amdgpu_state)
2355 struct si_power_info *si_pi = si_get_pi(adev);
2357 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2358 amdgpu_state->vclk && amdgpu_state->dclk)
2364 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2366 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2371 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2372 struct amdgpu_ps *amdgpu_state,
2373 SISLANDS_SMC_SWSTATE *smc_state)
2375 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2376 struct ni_power_info *ni_pi = ni_get_pi(adev);
2377 struct si_ps *state = si_get_ps(amdgpu_state);
2378 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2385 u16 pwr_efficiency_ratio;
2387 bool disable_uvd_power_tune;
2390 if (ni_pi->enable_power_containment == false)
2393 if (state->performance_level_count == 0)
2396 if (smc_state->levelCount != state->performance_level_count)
2399 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2401 smc_state->levels[0].dpm2.MaxPS = 0;
2402 smc_state->levels[0].dpm2.NearTDPDec = 0;
2403 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2404 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2405 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2407 for (i = 1; i < state->performance_level_count; i++) {
2408 prev_sclk = state->performance_levels[i-1].sclk;
2409 max_sclk = state->performance_levels[i].sclk;
2411 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2413 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2415 if (prev_sclk > max_sclk)
2418 if ((max_ps_percent == 0) ||
2419 (prev_sclk == max_sclk) ||
2420 disable_uvd_power_tune)
2421 min_sclk = max_sclk;
2423 min_sclk = prev_sclk;
2425 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2427 if (min_sclk < state->performance_levels[0].sclk)
2428 min_sclk = state->performance_levels[0].sclk;
2433 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2434 state->performance_levels[i-1].vddc, &vddc);
2438 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2442 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443 state->performance_levels[i].vddc, &vddc);
2447 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2451 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2452 prev_std_vddc, curr_std_vddc);
2454 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2455 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2456 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2457 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2458 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2464 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2465 struct amdgpu_ps *amdgpu_state,
2466 SISLANDS_SMC_SWSTATE *smc_state)
2468 struct ni_power_info *ni_pi = ni_get_pi(adev);
2469 struct si_ps *state = si_get_ps(amdgpu_state);
2470 u32 sq_power_throttle, sq_power_throttle2;
2471 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2474 if (state->performance_level_count == 0)
2477 if (smc_state->levelCount != state->performance_level_count)
2480 if (adev->pm.dpm.sq_ramping_threshold == 0)
2483 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2484 enable_sq_ramping = false;
2486 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2487 enable_sq_ramping = false;
2489 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2490 enable_sq_ramping = false;
2492 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2493 enable_sq_ramping = false;
2495 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2496 enable_sq_ramping = false;
2498 for (i = 0; i < state->performance_level_count; i++) {
2499 sq_power_throttle = 0;
2500 sq_power_throttle2 = 0;
2502 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2503 enable_sq_ramping) {
2504 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2505 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2506 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2507 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2508 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2510 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2511 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2514 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2515 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2521 static int si_enable_power_containment(struct amdgpu_device *adev,
2522 struct amdgpu_ps *amdgpu_new_state,
2525 struct ni_power_info *ni_pi = ni_get_pi(adev);
2526 PPSMC_Result smc_result;
2529 if (ni_pi->enable_power_containment) {
2531 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2532 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2533 if (smc_result != PPSMC_Result_OK) {
2535 ni_pi->pc_enabled = false;
2537 ni_pi->pc_enabled = true;
2541 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2542 if (smc_result != PPSMC_Result_OK)
2544 ni_pi->pc_enabled = false;
2551 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2553 struct si_power_info *si_pi = si_get_pi(adev);
2555 struct si_dte_data *dte_data = &si_pi->dte_data;
2556 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2561 if (dte_data == NULL)
2562 si_pi->enable_dte = false;
2564 if (si_pi->enable_dte == false)
2567 if (dte_data->k <= 0)
2570 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2571 if (dte_tables == NULL) {
2572 si_pi->enable_dte = false;
2576 table_size = dte_data->k;
2578 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2579 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2581 tdep_count = dte_data->tdep_count;
2582 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2583 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2585 dte_tables->K = cpu_to_be32(table_size);
2586 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2587 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2588 dte_tables->WindowSize = dte_data->window_size;
2589 dte_tables->temp_select = dte_data->temp_select;
2590 dte_tables->DTE_mode = dte_data->dte_mode;
2591 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2596 for (i = 0; i < table_size; i++) {
2597 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2598 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2601 dte_tables->Tdep_count = tdep_count;
2603 for (i = 0; i < (u32)tdep_count; i++) {
2604 dte_tables->T_limits[i] = dte_data->t_limits[i];
2605 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2606 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2609 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2611 sizeof(Smc_SIslands_DTE_Configuration),
2618 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2621 struct si_power_info *si_pi = si_get_pi(adev);
2622 struct amdgpu_cac_leakage_table *table =
2623 &adev->pm.dpm.dyn_state.cac_leakage_table;
2633 for (i = 0; i < table->count; i++) {
2634 if (table->entries[i].vddc > *max)
2635 *max = table->entries[i].vddc;
2636 if (table->entries[i].vddc < *min)
2637 *min = table->entries[i].vddc;
2640 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2643 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2645 if (v0_loadline > 0xFFFFUL)
2648 *min = (u16)v0_loadline;
2650 if ((*min > *max) || (*max == 0) || (*min == 0))
2656 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2658 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2659 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2662 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2663 PP_SIslands_CacConfig *cac_tables,
2664 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2667 struct si_power_info *si_pi = si_get_pi(adev);
2675 scaling_factor = si_get_smc_power_scaling_factor(adev);
2677 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2678 t = (1000 * (i * t_step + t0));
2680 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2681 voltage = vddc_max - (vddc_step * j);
2683 si_calculate_leakage_for_v_and_t(adev,
2684 &si_pi->powertune_data->leakage_coefficients,
2687 si_pi->dyn_powertune_data.cac_leakage,
2690 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2692 if (smc_leakage > 0xFFFF)
2693 smc_leakage = 0xFFFF;
2695 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2696 cpu_to_be16((u16)smc_leakage);
2702 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2703 PP_SIslands_CacConfig *cac_tables,
2704 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2706 struct si_power_info *si_pi = si_get_pi(adev);
2713 scaling_factor = si_get_smc_power_scaling_factor(adev);
2715 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2716 voltage = vddc_max - (vddc_step * j);
2718 si_calculate_leakage_for_v(adev,
2719 &si_pi->powertune_data->leakage_coefficients,
2720 si_pi->powertune_data->fixed_kt,
2722 si_pi->dyn_powertune_data.cac_leakage,
2725 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2727 if (smc_leakage > 0xFFFF)
2728 smc_leakage = 0xFFFF;
2730 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2731 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2732 cpu_to_be16((u16)smc_leakage);
2737 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2739 struct ni_power_info *ni_pi = ni_get_pi(adev);
2740 struct si_power_info *si_pi = si_get_pi(adev);
2741 PP_SIslands_CacConfig *cac_tables = NULL;
2742 u16 vddc_max, vddc_min, vddc_step;
2744 u32 load_line_slope, reg;
2746 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2748 if (ni_pi->enable_cac == false)
2751 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2755 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2756 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2757 WREG32(CG_CAC_CTRL, reg);
2759 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2760 si_pi->dyn_powertune_data.dc_pwr_value =
2761 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2762 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2763 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2765 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2767 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2771 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2772 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2776 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2777 ret = si_init_dte_leakage_table(adev, cac_tables,
2778 vddc_max, vddc_min, vddc_step,
2781 ret = si_init_simplified_leakage_table(adev, cac_tables,
2782 vddc_max, vddc_min, vddc_step);
2786 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2788 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2789 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2790 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2791 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2792 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2793 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2794 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2795 cac_tables->calculation_repeats = cpu_to_be32(2);
2796 cac_tables->dc_cac = cpu_to_be32(0);
2797 cac_tables->log2_PG_LKG_SCALE = 12;
2798 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2799 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2800 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2802 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2804 sizeof(PP_SIslands_CacConfig),
2810 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2814 ni_pi->enable_cac = false;
2815 ni_pi->enable_power_containment = false;
2823 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2824 const struct si_cac_config_reg *cac_config_regs)
2826 const struct si_cac_config_reg *config_regs = cac_config_regs;
2827 u32 data = 0, offset;
2832 while (config_regs->offset != 0xFFFFFFFF) {
2833 switch (config_regs->type) {
2834 case SISLANDS_CACCONFIG_CGIND:
2835 offset = SMC_CG_IND_START + config_regs->offset;
2836 if (offset < SMC_CG_IND_END)
2837 data = RREG32_SMC(offset);
2840 data = RREG32(config_regs->offset);
2844 data &= ~config_regs->mask;
2845 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2847 switch (config_regs->type) {
2848 case SISLANDS_CACCONFIG_CGIND:
2849 offset = SMC_CG_IND_START + config_regs->offset;
2850 if (offset < SMC_CG_IND_END)
2851 WREG32_SMC(offset, data);
2854 WREG32(config_regs->offset, data);
2862 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2864 struct ni_power_info *ni_pi = ni_get_pi(adev);
2865 struct si_power_info *si_pi = si_get_pi(adev);
2868 if ((ni_pi->enable_cac == false) ||
2869 (ni_pi->cac_configuration_required == false))
2872 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2875 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2878 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2885 static int si_enable_smc_cac(struct amdgpu_device *adev,
2886 struct amdgpu_ps *amdgpu_new_state,
2889 struct ni_power_info *ni_pi = ni_get_pi(adev);
2890 struct si_power_info *si_pi = si_get_pi(adev);
2891 PPSMC_Result smc_result;
2894 if (ni_pi->enable_cac) {
2896 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2897 if (ni_pi->support_cac_long_term_average) {
2898 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2899 if (smc_result != PPSMC_Result_OK)
2900 ni_pi->support_cac_long_term_average = false;
2903 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2904 if (smc_result != PPSMC_Result_OK) {
2906 ni_pi->cac_enabled = false;
2908 ni_pi->cac_enabled = true;
2911 if (si_pi->enable_dte) {
2912 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2913 if (smc_result != PPSMC_Result_OK)
2917 } else if (ni_pi->cac_enabled) {
2918 if (si_pi->enable_dte)
2919 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2921 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2923 ni_pi->cac_enabled = false;
2925 if (ni_pi->support_cac_long_term_average)
2926 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2932 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2934 struct ni_power_info *ni_pi = ni_get_pi(adev);
2935 struct si_power_info *si_pi = si_get_pi(adev);
2936 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2937 SISLANDS_SMC_SCLK_VALUE sclk_params;
2945 if (si_pi->spll_table_start == 0)
2948 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2949 if (spll_table == NULL)
2952 for (i = 0; i < 256; i++) {
2953 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2956 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2957 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2958 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2959 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2961 fb_div &= ~0x00001FFF;
2965 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2967 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2969 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2971 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2977 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2978 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2979 spll_table->freq[i] = cpu_to_be32(tmp);
2981 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2982 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2983 spll_table->ss[i] = cpu_to_be32(tmp);
2990 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2992 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2996 ni_pi->enable_power_containment = false;
3003 struct si_dpm_quirk {
3012 /* cards with dpm stability problems */
3013 static struct si_dpm_quirk si_dpm_quirk_list[] = {
3014 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3015 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3016 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
3017 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
3018 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3019 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3020 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
3021 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
3022 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
3026 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3029 u16 highest_leakage = 0;
3030 struct si_power_info *si_pi = si_get_pi(adev);
3033 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3034 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3035 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3038 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3039 return highest_leakage;
3044 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3045 u32 evclk, u32 ecclk, u16 *voltage)
3049 struct amdgpu_vce_clock_voltage_dependency_table *table =
3050 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3052 if (((evclk == 0) && (ecclk == 0)) ||
3053 (table && (table->count == 0))) {
3058 for (i = 0; i < table->count; i++) {
3059 if ((evclk <= table->entries[i].evclk) &&
3060 (ecclk <= table->entries[i].ecclk)) {
3061 *voltage = table->entries[i].v;
3067 /* if no match return the highest voltage */
3069 *voltage = table->entries[table->count - 1].v;
3071 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3076 static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3079 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3080 /* we never hit the non-gddr5 limit so disable it */
3081 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3083 if (vblank_time < switch_limit)
3090 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3091 u32 arb_freq_src, u32 arb_freq_dest)
3093 u32 mc_arb_dram_timing;
3094 u32 mc_arb_dram_timing2;
3098 switch (arb_freq_src) {
3099 case MC_CG_ARB_FREQ_F0:
3100 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3101 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3102 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3104 case MC_CG_ARB_FREQ_F1:
3105 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3106 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3107 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3109 case MC_CG_ARB_FREQ_F2:
3110 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3111 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3112 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3114 case MC_CG_ARB_FREQ_F3:
3115 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3116 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3117 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3123 switch (arb_freq_dest) {
3124 case MC_CG_ARB_FREQ_F0:
3125 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3126 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3127 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3129 case MC_CG_ARB_FREQ_F1:
3130 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3131 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3132 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3134 case MC_CG_ARB_FREQ_F2:
3135 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3136 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3137 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3139 case MC_CG_ARB_FREQ_F3:
3140 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3141 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3142 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3148 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3149 WREG32(MC_CG_CONFIG, mc_cg_config);
3150 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3155 static void ni_update_current_ps(struct amdgpu_device *adev,
3156 struct amdgpu_ps *rps)
3158 struct si_ps *new_ps = si_get_ps(rps);
3159 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3160 struct ni_power_info *ni_pi = ni_get_pi(adev);
3162 eg_pi->current_rps = *rps;
3163 ni_pi->current_ps = *new_ps;
3164 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3167 static void ni_update_requested_ps(struct amdgpu_device *adev,
3168 struct amdgpu_ps *rps)
3170 struct si_ps *new_ps = si_get_ps(rps);
3171 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3172 struct ni_power_info *ni_pi = ni_get_pi(adev);
3174 eg_pi->requested_rps = *rps;
3175 ni_pi->requested_ps = *new_ps;
3176 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3179 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3180 struct amdgpu_ps *new_ps,
3181 struct amdgpu_ps *old_ps)
3183 struct si_ps *new_state = si_get_ps(new_ps);
3184 struct si_ps *current_state = si_get_ps(old_ps);
3186 if ((new_ps->vclk == old_ps->vclk) &&
3187 (new_ps->dclk == old_ps->dclk))
3190 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3191 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3194 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3197 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3198 struct amdgpu_ps *new_ps,
3199 struct amdgpu_ps *old_ps)
3201 struct si_ps *new_state = si_get_ps(new_ps);
3202 struct si_ps *current_state = si_get_ps(old_ps);
3204 if ((new_ps->vclk == old_ps->vclk) &&
3205 (new_ps->dclk == old_ps->dclk))
3208 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3209 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3212 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3215 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3219 for (i = 0; i < table->count; i++)
3220 if (voltage <= table->entries[i].value)
3221 return table->entries[i].value;
3223 return table->entries[table->count - 1].value;
3226 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3227 u32 max_clock, u32 requested_clock)
3231 if ((clocks == NULL) || (clocks->count == 0))
3232 return (requested_clock < max_clock) ? requested_clock : max_clock;
3234 for (i = 0; i < clocks->count; i++) {
3235 if (clocks->values[i] >= requested_clock)
3236 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3239 return (clocks->values[clocks->count - 1] < max_clock) ?
3240 clocks->values[clocks->count - 1] : max_clock;
3243 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3244 u32 max_mclk, u32 requested_mclk)
3246 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3247 max_mclk, requested_mclk);
3250 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3251 u32 max_sclk, u32 requested_sclk)
3253 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3254 max_sclk, requested_sclk);
3257 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3262 if ((table == NULL) || (table->count == 0)) {
3267 for (i = 0; i < table->count; i++) {
3268 if (clock < table->entries[i].clk)
3269 clock = table->entries[i].clk;
3274 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3275 u32 clock, u16 max_voltage, u16 *voltage)
3279 if ((table == NULL) || (table->count == 0))
3282 for (i= 0; i < table->count; i++) {
3283 if (clock <= table->entries[i].clk) {
3284 if (*voltage < table->entries[i].v)
3285 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3286 table->entries[i].v : max_voltage);
3291 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3294 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3295 const struct amdgpu_clock_and_voltage_limits *max_limits,
3296 struct rv7xx_pl *pl)
3299 if ((pl->mclk == 0) || (pl->sclk == 0))
3302 if (pl->mclk == pl->sclk)
3305 if (pl->mclk > pl->sclk) {
3306 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3307 pl->sclk = btc_get_valid_sclk(adev,
3310 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3311 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3313 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3314 pl->mclk = btc_get_valid_mclk(adev,
3317 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3321 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3322 u16 max_vddc, u16 max_vddci,
3323 u16 *vddc, u16 *vddci)
3325 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3328 if ((0 == *vddc) || (0 == *vddci))
3331 if (*vddc > *vddci) {
3332 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3333 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3334 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3335 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3338 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3339 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3340 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3341 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3346 static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3348 enum amdgpu_pcie_gen asic_gen,
3349 enum amdgpu_pcie_gen default_gen)
3352 case AMDGPU_PCIE_GEN1:
3353 return AMDGPU_PCIE_GEN1;
3354 case AMDGPU_PCIE_GEN2:
3355 return AMDGPU_PCIE_GEN2;
3356 case AMDGPU_PCIE_GEN3:
3357 return AMDGPU_PCIE_GEN3;
3359 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3360 return AMDGPU_PCIE_GEN3;
3361 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3362 return AMDGPU_PCIE_GEN2;
3364 return AMDGPU_PCIE_GEN1;
3366 return AMDGPU_PCIE_GEN1;
3369 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3376 i_c = (i * r_c) / 100;
3385 *p = i_c / (1 << (2 * (*u)));
3388 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3393 if ((fl == 0) || (fh == 0) || (fl > fh))
3396 k = (100 * fh) / fl;
3397 t1 = (t * (k - 100));
3398 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3400 ah = ((a * t) + 5000) / 10000;
3409 static bool r600_is_uvd_state(u32 class, u32 class2)
3411 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3413 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3415 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3417 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3419 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3424 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3426 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3429 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3431 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3434 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3437 pi->max_vddc = vddc;
3440 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3442 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3443 struct amdgpu_atom_ss ss;
3445 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3446 ASIC_INTERNAL_ENGINE_SS, 0);
3447 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3448 ASIC_INTERNAL_MEMORY_SS, 0);
3450 if (pi->sclk_ss || pi->mclk_ss)
3451 pi->dynamic_ss = true;
3453 pi->dynamic_ss = false;
3457 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3458 struct amdgpu_ps *rps)
3460 struct si_ps *ps = si_get_ps(rps);
3461 struct amdgpu_clock_and_voltage_limits *max_limits;
3462 bool disable_mclk_switching = false;
3463 bool disable_sclk_switching = false;
3465 u16 vddc, vddci, min_vce_voltage = 0;
3466 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3467 u32 max_sclk = 0, max_mclk = 0;
3469 struct si_dpm_quirk *p = si_dpm_quirk_list;
3471 /* limit all SI kickers */
3472 if (adev->asic_type == CHIP_PITCAIRN) {
3473 if ((adev->pdev->revision == 0x81) ||
3474 (adev->pdev->device == 0x6810) ||
3475 (adev->pdev->device == 0x6811) ||
3476 (adev->pdev->device == 0x6816) ||
3477 (adev->pdev->device == 0x6817) ||
3478 (adev->pdev->device == 0x6806))
3480 } else if (adev->asic_type == CHIP_OLAND) {
3481 if ((adev->pdev->revision == 0xC7) ||
3482 (adev->pdev->revision == 0x80) ||
3483 (adev->pdev->revision == 0x81) ||
3484 (adev->pdev->revision == 0x83) ||
3485 (adev->pdev->revision == 0x87) ||
3486 (adev->pdev->device == 0x6604) ||
3487 (adev->pdev->device == 0x6605)) {
3491 } else if (adev->asic_type == CHIP_HAINAN) {
3492 if ((adev->pdev->revision == 0x81) ||
3493 (adev->pdev->revision == 0x83) ||
3494 (adev->pdev->revision == 0xC3) ||
3495 (adev->pdev->device == 0x6664) ||
3496 (adev->pdev->device == 0x6665) ||
3497 (adev->pdev->device == 0x6667)) {
3501 } else if (adev->asic_type == CHIP_OLAND) {
3502 if ((adev->pdev->revision == 0xC7) ||
3503 (adev->pdev->revision == 0x80) ||
3504 (adev->pdev->revision == 0x81) ||
3505 (adev->pdev->revision == 0x83) ||
3506 (adev->pdev->revision == 0x87) ||
3507 (adev->pdev->device == 0x6604) ||
3508 (adev->pdev->device == 0x6605)) {
3512 /* Apply dpm quirks */
3513 while (p && p->chip_device != 0) {
3514 if (adev->pdev->vendor == p->chip_vendor &&
3515 adev->pdev->device == p->chip_device &&
3516 adev->pdev->subsystem_vendor == p->subsys_vendor &&
3517 adev->pdev->subsystem_device == p->subsys_device) {
3518 max_sclk = p->max_sclk;
3519 max_mclk = p->max_mclk;
3525 if (rps->vce_active) {
3526 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3527 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3528 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3535 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3536 si_dpm_vblank_too_short(adev))
3537 disable_mclk_switching = true;
3539 if (rps->vclk || rps->dclk) {
3540 disable_mclk_switching = true;
3541 disable_sclk_switching = true;
3544 if (adev->pm.dpm.ac_power)
3545 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3547 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3549 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3550 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3551 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3553 if (adev->pm.dpm.ac_power == false) {
3554 for (i = 0; i < ps->performance_level_count; i++) {
3555 if (ps->performance_levels[i].mclk > max_limits->mclk)
3556 ps->performance_levels[i].mclk = max_limits->mclk;
3557 if (ps->performance_levels[i].sclk > max_limits->sclk)
3558 ps->performance_levels[i].sclk = max_limits->sclk;
3559 if (ps->performance_levels[i].vddc > max_limits->vddc)
3560 ps->performance_levels[i].vddc = max_limits->vddc;
3561 if (ps->performance_levels[i].vddci > max_limits->vddci)
3562 ps->performance_levels[i].vddci = max_limits->vddci;
3566 /* limit clocks to max supported clocks based on voltage dependency tables */
3567 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3569 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3571 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3574 for (i = 0; i < ps->performance_level_count; i++) {
3575 if (max_sclk_vddc) {
3576 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3577 ps->performance_levels[i].sclk = max_sclk_vddc;
3579 if (max_mclk_vddci) {
3580 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3581 ps->performance_levels[i].mclk = max_mclk_vddci;
3583 if (max_mclk_vddc) {
3584 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3585 ps->performance_levels[i].mclk = max_mclk_vddc;
3588 if (ps->performance_levels[i].mclk > max_mclk)
3589 ps->performance_levels[i].mclk = max_mclk;
3592 if (ps->performance_levels[i].sclk > max_sclk)
3593 ps->performance_levels[i].sclk = max_sclk;
3597 /* XXX validate the min clocks required for display */
3599 if (disable_mclk_switching) {
3600 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3601 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3603 mclk = ps->performance_levels[0].mclk;
3604 vddci = ps->performance_levels[0].vddci;
3607 if (disable_sclk_switching) {
3608 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3609 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3611 sclk = ps->performance_levels[0].sclk;
3612 vddc = ps->performance_levels[0].vddc;
3615 if (rps->vce_active) {
3616 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3617 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3618 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3619 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3622 /* adjusted low state */
3623 ps->performance_levels[0].sclk = sclk;
3624 ps->performance_levels[0].mclk = mclk;
3625 ps->performance_levels[0].vddc = vddc;
3626 ps->performance_levels[0].vddci = vddci;
3628 if (disable_sclk_switching) {
3629 sclk = ps->performance_levels[0].sclk;
3630 for (i = 1; i < ps->performance_level_count; i++) {
3631 if (sclk < ps->performance_levels[i].sclk)
3632 sclk = ps->performance_levels[i].sclk;
3634 for (i = 0; i < ps->performance_level_count; i++) {
3635 ps->performance_levels[i].sclk = sclk;
3636 ps->performance_levels[i].vddc = vddc;
3639 for (i = 1; i < ps->performance_level_count; i++) {
3640 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3641 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3642 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3643 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3647 if (disable_mclk_switching) {
3648 mclk = ps->performance_levels[0].mclk;
3649 for (i = 1; i < ps->performance_level_count; i++) {
3650 if (mclk < ps->performance_levels[i].mclk)
3651 mclk = ps->performance_levels[i].mclk;
3653 for (i = 0; i < ps->performance_level_count; i++) {
3654 ps->performance_levels[i].mclk = mclk;
3655 ps->performance_levels[i].vddci = vddci;
3658 for (i = 1; i < ps->performance_level_count; i++) {
3659 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3660 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3661 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3662 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3666 for (i = 0; i < ps->performance_level_count; i++)
3667 btc_adjust_clock_combinations(adev, max_limits,
3668 &ps->performance_levels[i]);
3670 for (i = 0; i < ps->performance_level_count; i++) {
3671 if (ps->performance_levels[i].vddc < min_vce_voltage)
3672 ps->performance_levels[i].vddc = min_vce_voltage;
3673 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3674 ps->performance_levels[i].sclk,
3675 max_limits->vddc, &ps->performance_levels[i].vddc);
3676 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3677 ps->performance_levels[i].mclk,
3678 max_limits->vddci, &ps->performance_levels[i].vddci);
3679 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3680 ps->performance_levels[i].mclk,
3681 max_limits->vddc, &ps->performance_levels[i].vddc);
3682 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3683 adev->clock.current_dispclk,
3684 max_limits->vddc, &ps->performance_levels[i].vddc);
3687 for (i = 0; i < ps->performance_level_count; i++) {
3688 btc_apply_voltage_delta_rules(adev,
3689 max_limits->vddc, max_limits->vddci,
3690 &ps->performance_levels[i].vddc,
3691 &ps->performance_levels[i].vddci);
3694 ps->dc_compatible = true;
3695 for (i = 0; i < ps->performance_level_count; i++) {
3696 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3697 ps->dc_compatible = false;
3702 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3703 u16 reg_offset, u32 *value)
3705 struct si_power_info *si_pi = si_get_pi(adev);
3707 return amdgpu_si_read_smc_sram_dword(adev,
3708 si_pi->soft_regs_start + reg_offset, value,
3713 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3714 u16 reg_offset, u32 value)
3716 struct si_power_info *si_pi = si_get_pi(adev);
3718 return amdgpu_si_write_smc_sram_dword(adev,
3719 si_pi->soft_regs_start + reg_offset,
3720 value, si_pi->sram_end);
3723 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3726 u32 tmp, width, row, column, bank, density;
3727 bool is_memory_gddr5, is_special;
3729 tmp = RREG32(MC_SEQ_MISC0);
3730 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3731 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3732 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3734 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3735 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3737 tmp = RREG32(MC_ARB_RAMCFG);
3738 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3739 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3740 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3742 density = (1 << (row + column - 20 + bank)) * width;
3744 if ((adev->pdev->device == 0x6819) &&
3745 is_memory_gddr5 && is_special && (density == 0x400))
3751 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3753 struct si_power_info *si_pi = si_get_pi(adev);
3754 u16 vddc, count = 0;
3757 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3758 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3760 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3761 si_pi->leakage_voltage.entries[count].voltage = vddc;
3762 si_pi->leakage_voltage.entries[count].leakage_index =
3763 SISLANDS_LEAKAGE_INDEX0 + i;
3767 si_pi->leakage_voltage.count = count;
3770 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3771 u32 index, u16 *leakage_voltage)
3773 struct si_power_info *si_pi = si_get_pi(adev);
3776 if (leakage_voltage == NULL)
3779 if ((index & 0xff00) != 0xff00)
3782 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3785 if (index < SISLANDS_LEAKAGE_INDEX0)
3788 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3789 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3790 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3797 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3799 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3800 bool want_thermal_protection;
3801 enum amdgpu_dpm_event_src dpm_event_src;
3806 want_thermal_protection = false;
3808 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3809 want_thermal_protection = true;
3810 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3812 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3813 want_thermal_protection = true;
3814 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3816 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3817 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3818 want_thermal_protection = true;
3819 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3823 if (want_thermal_protection) {
3824 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3825 if (pi->thermal_protection)
3826 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3828 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3832 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3833 enum amdgpu_dpm_auto_throttle_src source,
3836 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3839 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3840 pi->active_auto_throttle_sources |= 1 << source;
3841 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3844 if (pi->active_auto_throttle_sources & (1 << source)) {
3845 pi->active_auto_throttle_sources &= ~(1 << source);
3846 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3851 static void si_start_dpm(struct amdgpu_device *adev)
3853 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3856 static void si_stop_dpm(struct amdgpu_device *adev)
3858 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3861 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3864 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3866 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3871 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3876 if (thermal_level == 0) {
3877 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3878 if (ret == PPSMC_Result_OK)
3886 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3888 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3893 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3896 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3903 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3904 PPSMC_Msg msg, u32 parameter)
3906 WREG32(SMC_SCRATCH0, parameter);
3907 return amdgpu_si_send_msg_to_smc(adev, msg);
3910 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3912 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3915 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3919 static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3920 enum amdgpu_dpm_forced_level level)
3922 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3923 struct si_ps *ps = si_get_ps(rps);
3924 u32 levels = ps->performance_level_count;
3926 if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3927 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3930 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3932 } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3933 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3936 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3938 } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3939 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3942 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3946 adev->pm.dpm.forced_level = level;
3952 static int si_set_boot_state(struct amdgpu_device *adev)
3954 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3959 static int si_set_sw_state(struct amdgpu_device *adev)
3961 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3965 static int si_halt_smc(struct amdgpu_device *adev)
3967 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3970 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3974 static int si_resume_smc(struct amdgpu_device *adev)
3976 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3979 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3983 static void si_dpm_start_smc(struct amdgpu_device *adev)
3985 amdgpu_si_program_jump_on_start(adev);
3986 amdgpu_si_start_smc(adev);
3987 amdgpu_si_smc_clock(adev, true);
3990 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3992 amdgpu_si_reset_smc(adev);
3993 amdgpu_si_smc_clock(adev, false);
3996 static int si_process_firmware_header(struct amdgpu_device *adev)
3998 struct si_power_info *si_pi = si_get_pi(adev);
4002 ret = amdgpu_si_read_smc_sram_dword(adev,
4003 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4004 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
4005 &tmp, si_pi->sram_end);
4009 si_pi->state_table_start = tmp;
4011 ret = amdgpu_si_read_smc_sram_dword(adev,
4012 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4013 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4014 &tmp, si_pi->sram_end);
4018 si_pi->soft_regs_start = tmp;
4020 ret = amdgpu_si_read_smc_sram_dword(adev,
4021 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4022 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4023 &tmp, si_pi->sram_end);
4027 si_pi->mc_reg_table_start = tmp;
4029 ret = amdgpu_si_read_smc_sram_dword(adev,
4030 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4031 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4032 &tmp, si_pi->sram_end);
4036 si_pi->fan_table_start = tmp;
4038 ret = amdgpu_si_read_smc_sram_dword(adev,
4039 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4040 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4041 &tmp, si_pi->sram_end);
4045 si_pi->arb_table_start = tmp;
4047 ret = amdgpu_si_read_smc_sram_dword(adev,
4048 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4049 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4050 &tmp, si_pi->sram_end);
4054 si_pi->cac_table_start = tmp;
4056 ret = amdgpu_si_read_smc_sram_dword(adev,
4057 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4058 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4059 &tmp, si_pi->sram_end);
4063 si_pi->dte_table_start = tmp;
4065 ret = amdgpu_si_read_smc_sram_dword(adev,
4066 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4067 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4068 &tmp, si_pi->sram_end);
4072 si_pi->spll_table_start = tmp;
4074 ret = amdgpu_si_read_smc_sram_dword(adev,
4075 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4076 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4077 &tmp, si_pi->sram_end);
4081 si_pi->papm_cfg_table_start = tmp;
4086 static void si_read_clock_registers(struct amdgpu_device *adev)
4088 struct si_power_info *si_pi = si_get_pi(adev);
4090 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4091 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4092 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4093 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4094 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4095 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4096 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4097 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4098 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4099 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4100 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4101 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4102 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4103 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4104 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4107 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4111 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4113 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4116 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4118 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4122 static int si_enter_ulp_state(struct amdgpu_device *adev)
4124 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4131 static int si_exit_ulp_state(struct amdgpu_device *adev)
4135 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4139 for (i = 0; i < adev->usec_timeout; i++) {
4140 if (RREG32(SMC_RESP_0) == 1)
4149 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4152 PPSMC_Msg msg = has_display ?
4153 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4155 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4159 static void si_program_response_times(struct amdgpu_device *adev)
4161 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4162 u32 vddc_dly, acpi_dly, vbi_dly;
4163 u32 reference_clock;
4165 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4167 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4168 backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4170 if (voltage_response_time == 0)
4171 voltage_response_time = 1000;
4173 acpi_delay_time = 15000;
4174 vbi_time_out = 100000;
4176 reference_clock = amdgpu_asic_get_xclk(adev);
4178 vddc_dly = (voltage_response_time * reference_clock) / 100;
4179 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4180 vbi_dly = (vbi_time_out * reference_clock) / 100;
4182 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4183 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4184 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4185 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4188 static void si_program_ds_registers(struct amdgpu_device *adev)
4190 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4193 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4194 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4199 if (eg_pi->sclk_deep_sleep) {
4200 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4201 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4202 ~AUTOSCALE_ON_SS_CLEAR);
4206 static void si_program_display_gap(struct amdgpu_device *adev)
4211 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4212 if (adev->pm.dpm.new_active_crtc_count > 0)
4213 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4215 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4217 if (adev->pm.dpm.new_active_crtc_count > 1)
4218 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4220 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4222 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4224 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4225 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4227 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4228 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4229 /* find the first active crtc */
4230 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4231 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4234 if (i == adev->mode_info.num_crtc)
4239 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4240 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4241 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4244 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4245 * This can be a problem on PowerXpress systems or if you want to use the card
4246 * for offscreen rendering or compute if there are no crtcs enabled.
4248 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4251 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4253 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4257 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4259 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4260 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4264 static void si_setup_bsp(struct amdgpu_device *adev)
4266 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4267 u32 xclk = amdgpu_asic_get_xclk(adev);
4269 r600_calculate_u_and_p(pi->asi,
4275 r600_calculate_u_and_p(pi->pasi,
4282 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4283 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4285 WREG32(CG_BSP, pi->dsp);
4288 static void si_program_git(struct amdgpu_device *adev)
4290 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4293 static void si_program_tp(struct amdgpu_device *adev)
4296 enum r600_td td = R600_TD_DFLT;
4298 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4299 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4301 if (td == R600_TD_AUTO)
4302 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4304 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4306 if (td == R600_TD_UP)
4307 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4309 if (td == R600_TD_DOWN)
4310 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4313 static void si_program_tpp(struct amdgpu_device *adev)
4315 WREG32(CG_TPC, R600_TPC_DFLT);
4318 static void si_program_sstp(struct amdgpu_device *adev)
4320 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4323 static void si_enable_display_gap(struct amdgpu_device *adev)
4325 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4327 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4328 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4329 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4331 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4332 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4333 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4334 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4337 static void si_program_vc(struct amdgpu_device *adev)
4339 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4341 WREG32(CG_FTV, pi->vrc);
4344 static void si_clear_vc(struct amdgpu_device *adev)
4349 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4353 if (memory_clock < 10000)
4355 else if (memory_clock >= 80000)
4356 mc_para_index = 0x0f;
4358 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4359 return mc_para_index;
4362 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4367 if (memory_clock < 12500)
4368 mc_para_index = 0x00;
4369 else if (memory_clock > 47500)
4370 mc_para_index = 0x0f;
4372 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4374 if (memory_clock < 65000)
4375 mc_para_index = 0x00;
4376 else if (memory_clock > 135000)
4377 mc_para_index = 0x0f;
4379 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4381 return mc_para_index;
4384 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4386 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4387 bool strobe_mode = false;
4390 if (mclk <= pi->mclk_strobe_mode_threshold)
4393 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4394 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4396 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4399 result |= SISLANDS_SMC_STROBE_ENABLE;
4404 static int si_upload_firmware(struct amdgpu_device *adev)
4406 struct si_power_info *si_pi = si_get_pi(adev);
4408 amdgpu_si_reset_smc(adev);
4409 amdgpu_si_smc_clock(adev, false);
4411 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4414 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4415 const struct atom_voltage_table *table,
4416 const struct amdgpu_phase_shedding_limits_table *limits)
4418 u32 data, num_bits, num_levels;
4420 if ((table == NULL) || (limits == NULL))
4423 data = table->mask_low;
4425 num_bits = hweight32(data);
4430 num_levels = (1 << num_bits);
4432 if (table->count != num_levels)
4435 if (limits->count != (num_levels - 1))
4441 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4442 u32 max_voltage_steps,
4443 struct atom_voltage_table *voltage_table)
4445 unsigned int i, diff;
4447 if (voltage_table->count <= max_voltage_steps)
4450 diff = voltage_table->count - max_voltage_steps;
4452 for (i= 0; i < max_voltage_steps; i++)
4453 voltage_table->entries[i] = voltage_table->entries[i + diff];
4455 voltage_table->count = max_voltage_steps;
4458 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4459 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4460 struct atom_voltage_table *voltage_table)
4464 if (voltage_dependency_table == NULL)
4467 voltage_table->mask_low = 0;
4468 voltage_table->phase_delay = 0;
4470 voltage_table->count = voltage_dependency_table->count;
4471 for (i = 0; i < voltage_table->count; i++) {
4472 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4473 voltage_table->entries[i].smio_low = 0;
4479 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4481 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4482 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4483 struct si_power_info *si_pi = si_get_pi(adev);
4486 if (pi->voltage_control) {
4487 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4488 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4492 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4493 si_trim_voltage_table_to_fit_state_table(adev,
4494 SISLANDS_MAX_NO_VREG_STEPS,
4495 &eg_pi->vddc_voltage_table);
4496 } else if (si_pi->voltage_control_svi2) {
4497 ret = si_get_svi2_voltage_table(adev,
4498 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4499 &eg_pi->vddc_voltage_table);
4506 if (eg_pi->vddci_control) {
4507 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4508 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4512 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4513 si_trim_voltage_table_to_fit_state_table(adev,
4514 SISLANDS_MAX_NO_VREG_STEPS,
4515 &eg_pi->vddci_voltage_table);
4517 if (si_pi->vddci_control_svi2) {
4518 ret = si_get_svi2_voltage_table(adev,
4519 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4520 &eg_pi->vddci_voltage_table);
4525 if (pi->mvdd_control) {
4526 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4527 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4530 pi->mvdd_control = false;
4534 if (si_pi->mvdd_voltage_table.count == 0) {
4535 pi->mvdd_control = false;
4539 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4540 si_trim_voltage_table_to_fit_state_table(adev,
4541 SISLANDS_MAX_NO_VREG_STEPS,
4542 &si_pi->mvdd_voltage_table);
4545 if (si_pi->vddc_phase_shed_control) {
4546 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4547 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4549 si_pi->vddc_phase_shed_control = false;
4551 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4552 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4553 si_pi->vddc_phase_shed_control = false;
4559 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4560 const struct atom_voltage_table *voltage_table,
4561 SISLANDS_SMC_STATETABLE *table)
4565 for (i = 0; i < voltage_table->count; i++)
4566 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4569 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4570 SISLANDS_SMC_STATETABLE *table)
4572 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4573 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4574 struct si_power_info *si_pi = si_get_pi(adev);
4577 if (si_pi->voltage_control_svi2) {
4578 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4579 si_pi->svc_gpio_id);
4580 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4581 si_pi->svd_gpio_id);
4582 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4585 if (eg_pi->vddc_voltage_table.count) {
4586 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4587 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4588 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4590 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4591 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4592 table->maxVDDCIndexInPPTable = i;
4598 if (eg_pi->vddci_voltage_table.count) {
4599 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4601 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4602 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4606 if (si_pi->mvdd_voltage_table.count) {
4607 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4609 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4610 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4613 if (si_pi->vddc_phase_shed_control) {
4614 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4615 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4616 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4618 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4619 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4621 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4622 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4624 si_pi->vddc_phase_shed_control = false;
4632 static int si_populate_voltage_value(struct amdgpu_device *adev,
4633 const struct atom_voltage_table *table,
4634 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4638 for (i = 0; i < table->count; i++) {
4639 if (value <= table->entries[i].value) {
4640 voltage->index = (u8)i;
4641 voltage->value = cpu_to_be16(table->entries[i].value);
4646 if (i >= table->count)
4652 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4653 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4655 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4656 struct si_power_info *si_pi = si_get_pi(adev);
4658 if (pi->mvdd_control) {
4659 if (mclk <= pi->mvdd_split_frequency)
4662 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4664 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4669 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4670 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4674 bool voltage_found = false;
4675 *std_voltage = be16_to_cpu(voltage->value);
4677 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4678 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4679 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4682 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4683 if (be16_to_cpu(voltage->value) ==
4684 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4685 voltage_found = true;
4686 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4688 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4691 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4696 if (!voltage_found) {
4697 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4698 if (be16_to_cpu(voltage->value) <=
4699 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4700 voltage_found = true;
4701 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4703 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4706 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4712 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4713 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4720 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4721 u16 value, u8 index,
4722 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4724 voltage->index = index;
4725 voltage->value = cpu_to_be16(value);
4730 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4731 const struct amdgpu_phase_shedding_limits_table *limits,
4732 u16 voltage, u32 sclk, u32 mclk,
4733 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4737 for (i = 0; i < limits->count; i++) {
4738 if ((voltage <= limits->entries[i].voltage) &&
4739 (sclk <= limits->entries[i].sclk) &&
4740 (mclk <= limits->entries[i].mclk))
4744 smc_voltage->phase_settings = (u8)i;
4749 static int si_init_arb_table_index(struct amdgpu_device *adev)
4751 struct si_power_info *si_pi = si_get_pi(adev);
4755 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4756 &tmp, si_pi->sram_end);
4761 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4763 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4764 tmp, si_pi->sram_end);
4767 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4769 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4772 static int si_reset_to_default(struct amdgpu_device *adev)
4774 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4778 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4780 struct si_power_info *si_pi = si_get_pi(adev);
4784 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4785 &tmp, si_pi->sram_end);
4789 tmp = (tmp >> 24) & 0xff;
4791 if (tmp == MC_CG_ARB_FREQ_F0)
4794 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4797 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4801 u32 dram_refresh_rate;
4802 u32 mc_arb_rfsh_rate;
4803 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4808 dram_rows = 1 << (tmp + 10);
4810 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4811 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4813 return mc_arb_rfsh_rate;
4816 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4817 struct rv7xx_pl *pl,
4818 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4824 arb_regs->mc_arb_rfsh_rate =
4825 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4827 amdgpu_atombios_set_engine_dram_timings(adev,
4831 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4832 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4833 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4835 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4836 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4837 arb_regs->mc_arb_burst_time = (u8)burst_time;
4842 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4843 struct amdgpu_ps *amdgpu_state,
4844 unsigned int first_arb_set)
4846 struct si_power_info *si_pi = si_get_pi(adev);
4847 struct si_ps *state = si_get_ps(amdgpu_state);
4848 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4851 for (i = 0; i < state->performance_level_count; i++) {
4852 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4855 ret = amdgpu_si_copy_bytes_to_smc(adev,
4856 si_pi->arb_table_start +
4857 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4858 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4860 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4869 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4870 struct amdgpu_ps *amdgpu_new_state)
4872 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4873 SISLANDS_DRIVER_STATE_ARB_INDEX);
4876 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4877 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4879 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4880 struct si_power_info *si_pi = si_get_pi(adev);
4882 if (pi->mvdd_control)
4883 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4884 si_pi->mvdd_bootup_value, voltage);
4889 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4890 struct amdgpu_ps *amdgpu_initial_state,
4891 SISLANDS_SMC_STATETABLE *table)
4893 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4894 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4895 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4896 struct si_power_info *si_pi = si_get_pi(adev);
4900 table->initialState.levels[0].mclk.vDLL_CNTL =
4901 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4902 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4903 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4904 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4905 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4906 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4907 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4908 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4909 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4910 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4911 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4912 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4913 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4914 table->initialState.levels[0].mclk.vMPLL_SS =
4915 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4916 table->initialState.levels[0].mclk.vMPLL_SS2 =
4917 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4919 table->initialState.levels[0].mclk.mclk_value =
4920 cpu_to_be32(initial_state->performance_levels[0].mclk);
4922 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4923 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4924 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4925 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4926 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4927 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4928 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4929 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4930 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4931 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4932 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4933 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4935 table->initialState.levels[0].sclk.sclk_value =
4936 cpu_to_be32(initial_state->performance_levels[0].sclk);
4938 table->initialState.levels[0].arbRefreshState =
4939 SISLANDS_INITIAL_STATE_ARB_INDEX;
4941 table->initialState.levels[0].ACIndex = 0;
4943 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4944 initial_state->performance_levels[0].vddc,
4945 &table->initialState.levels[0].vddc);
4950 ret = si_get_std_voltage_value(adev,
4951 &table->initialState.levels[0].vddc,
4954 si_populate_std_voltage_value(adev, std_vddc,
4955 table->initialState.levels[0].vddc.index,
4956 &table->initialState.levels[0].std_vddc);
4959 if (eg_pi->vddci_control)
4960 si_populate_voltage_value(adev,
4961 &eg_pi->vddci_voltage_table,
4962 initial_state->performance_levels[0].vddci,
4963 &table->initialState.levels[0].vddci);
4965 if (si_pi->vddc_phase_shed_control)
4966 si_populate_phase_shedding_value(adev,
4967 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4968 initial_state->performance_levels[0].vddc,
4969 initial_state->performance_levels[0].sclk,
4970 initial_state->performance_levels[0].mclk,
4971 &table->initialState.levels[0].vddc);
4973 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4975 reg = CG_R(0xffff) | CG_L(0);
4976 table->initialState.levels[0].aT = cpu_to_be32(reg);
4977 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4978 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4980 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4981 table->initialState.levels[0].strobeMode =
4982 si_get_strobe_mode_settings(adev,
4983 initial_state->performance_levels[0].mclk);
4985 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4986 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4988 table->initialState.levels[0].mcFlags = 0;
4991 table->initialState.levelCount = 1;
4993 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4995 table->initialState.levels[0].dpm2.MaxPS = 0;
4996 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4997 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4998 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4999 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5001 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5002 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5004 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5005 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5010 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5011 SISLANDS_SMC_STATETABLE *table)
5013 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5014 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5015 struct si_power_info *si_pi = si_get_pi(adev);
5016 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5017 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5018 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5019 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5020 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5021 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5022 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5023 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5024 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5025 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5026 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5030 table->ACPIState = table->initialState;
5032 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5034 if (pi->acpi_vddc) {
5035 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5036 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
5040 ret = si_get_std_voltage_value(adev,
5041 &table->ACPIState.levels[0].vddc, &std_vddc);
5043 si_populate_std_voltage_value(adev, std_vddc,
5044 table->ACPIState.levels[0].vddc.index,
5045 &table->ACPIState.levels[0].std_vddc);
5047 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5049 if (si_pi->vddc_phase_shed_control) {
5050 si_populate_phase_shedding_value(adev,
5051 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5055 &table->ACPIState.levels[0].vddc);
5058 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5059 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5063 ret = si_get_std_voltage_value(adev,
5064 &table->ACPIState.levels[0].vddc, &std_vddc);
5067 si_populate_std_voltage_value(adev, std_vddc,
5068 table->ACPIState.levels[0].vddc.index,
5069 &table->ACPIState.levels[0].std_vddc);
5071 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5072 si_pi->sys_pcie_mask,
5073 si_pi->boot_pcie_gen,
5076 if (si_pi->vddc_phase_shed_control)
5077 si_populate_phase_shedding_value(adev,
5078 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5079 pi->min_vddc_in_table,
5082 &table->ACPIState.levels[0].vddc);
5085 if (pi->acpi_vddc) {
5086 if (eg_pi->acpi_vddci)
5087 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5089 &table->ACPIState.levels[0].vddci);
5092 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5093 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5095 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5097 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5098 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5100 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5101 cpu_to_be32(dll_cntl);
5102 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5103 cpu_to_be32(mclk_pwrmgt_cntl);
5104 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5105 cpu_to_be32(mpll_ad_func_cntl);
5106 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5107 cpu_to_be32(mpll_dq_func_cntl);
5108 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5109 cpu_to_be32(mpll_func_cntl);
5110 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5111 cpu_to_be32(mpll_func_cntl_1);
5112 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5113 cpu_to_be32(mpll_func_cntl_2);
5114 table->ACPIState.levels[0].mclk.vMPLL_SS =
5115 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5116 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5117 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5119 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5120 cpu_to_be32(spll_func_cntl);
5121 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5122 cpu_to_be32(spll_func_cntl_2);
5123 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5124 cpu_to_be32(spll_func_cntl_3);
5125 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5126 cpu_to_be32(spll_func_cntl_4);
5128 table->ACPIState.levels[0].mclk.mclk_value = 0;
5129 table->ACPIState.levels[0].sclk.sclk_value = 0;
5131 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5133 if (eg_pi->dynamic_ac_timing)
5134 table->ACPIState.levels[0].ACIndex = 0;
5136 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5137 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5138 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5139 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5140 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5142 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5143 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5145 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5146 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5151 static int si_populate_ulv_state(struct amdgpu_device *adev,
5152 SISLANDS_SMC_SWSTATE *state)
5154 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5155 struct si_power_info *si_pi = si_get_pi(adev);
5156 struct si_ulv_param *ulv = &si_pi->ulv;
5157 u32 sclk_in_sr = 1350; /* ??? */
5160 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5163 if (eg_pi->sclk_deep_sleep) {
5164 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5165 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5167 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5169 if (ulv->one_pcie_lane_in_ulv)
5170 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5171 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5172 state->levels[0].ACIndex = 1;
5173 state->levels[0].std_vddc = state->levels[0].vddc;
5174 state->levelCount = 1;
5176 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5182 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5184 struct si_power_info *si_pi = si_get_pi(adev);
5185 struct si_ulv_param *ulv = &si_pi->ulv;
5186 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5189 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5194 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5195 ulv->volt_change_delay);
5197 ret = amdgpu_si_copy_bytes_to_smc(adev,
5198 si_pi->arb_table_start +
5199 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5200 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5202 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5208 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5210 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5212 pi->mvdd_split_frequency = 30000;
5215 static int si_init_smc_table(struct amdgpu_device *adev)
5217 struct si_power_info *si_pi = si_get_pi(adev);
5218 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5219 const struct si_ulv_param *ulv = &si_pi->ulv;
5220 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5225 si_populate_smc_voltage_tables(adev, table);
5227 switch (adev->pm.int_thermal_type) {
5228 case THERMAL_TYPE_SI:
5229 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5230 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5232 case THERMAL_TYPE_NONE:
5233 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5236 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5240 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5241 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5243 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5244 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5245 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5248 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5249 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5251 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5252 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5254 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5255 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5257 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5258 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5259 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5260 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5264 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5268 ret = si_populate_smc_acpi_state(adev, table);
5272 table->driverState = table->initialState;
5274 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5275 SISLANDS_INITIAL_STATE_ARB_INDEX);
5279 if (ulv->supported && ulv->pl.vddc) {
5280 ret = si_populate_ulv_state(adev, &table->ULVState);
5284 ret = si_program_ulv_memory_timing_parameters(adev);
5288 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5289 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5291 lane_width = amdgpu_get_pcie_lanes(adev);
5292 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5294 table->ULVState = table->initialState;
5297 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5298 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5302 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5304 SISLANDS_SMC_SCLK_VALUE *sclk)
5306 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5307 struct si_power_info *si_pi = si_get_pi(adev);
5308 struct atom_clock_dividers dividers;
5309 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5310 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5311 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5312 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5313 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5314 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5316 u32 reference_clock = adev->clock.spll.reference_freq;
5317 u32 reference_divider;
5321 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5322 engine_clock, false, ÷rs);
5326 reference_divider = 1 + dividers.ref_div;
5328 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5329 do_div(tmp, reference_clock);
5332 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5333 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5334 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5336 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5337 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5339 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5340 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5341 spll_func_cntl_3 |= SPLL_DITHEN;
5344 struct amdgpu_atom_ss ss;
5345 u32 vco_freq = engine_clock * dividers.post_div;
5347 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5348 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5349 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5350 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5352 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5353 cg_spll_spread_spectrum |= CLK_S(clk_s);
5354 cg_spll_spread_spectrum |= SSEN;
5356 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5357 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5361 sclk->sclk_value = engine_clock;
5362 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5363 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5364 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5365 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5366 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5367 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5372 static int si_populate_sclk_value(struct amdgpu_device *adev,
5374 SISLANDS_SMC_SCLK_VALUE *sclk)
5376 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5379 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5381 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5382 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5383 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5384 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5385 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5386 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5387 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5393 static int si_populate_mclk_value(struct amdgpu_device *adev,
5396 SISLANDS_SMC_MCLK_VALUE *mclk,
5400 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5401 struct si_power_info *si_pi = si_get_pi(adev);
5402 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5403 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5404 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5405 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5406 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5407 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5408 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5409 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5410 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5411 struct atom_mpll_param mpll_param;
5414 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5418 mpll_func_cntl &= ~BWCTRL_MASK;
5419 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5421 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5422 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5423 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5425 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5426 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5428 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5429 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5430 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5431 YCLK_POST_DIV(mpll_param.post_div);
5435 struct amdgpu_atom_ss ss;
5438 u32 reference_clock = adev->clock.mpll.reference_freq;
5440 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5441 freq_nom = memory_clock * 4;
5443 freq_nom = memory_clock * 2;
5445 tmp = freq_nom / reference_clock;
5447 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5448 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5449 u32 clks = reference_clock * 5 / ss.rate;
5450 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5452 mpll_ss1 &= ~CLKV_MASK;
5453 mpll_ss1 |= CLKV(clkv);
5455 mpll_ss2 &= ~CLKS_MASK;
5456 mpll_ss2 |= CLKS(clks);
5460 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5461 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5464 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5466 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5468 mclk->mclk_value = cpu_to_be32(memory_clock);
5469 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5470 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5471 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5472 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5473 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5474 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5475 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5476 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5477 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5482 static void si_populate_smc_sp(struct amdgpu_device *adev,
5483 struct amdgpu_ps *amdgpu_state,
5484 SISLANDS_SMC_SWSTATE *smc_state)
5486 struct si_ps *ps = si_get_ps(amdgpu_state);
5487 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5490 for (i = 0; i < ps->performance_level_count - 1; i++)
5491 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5493 smc_state->levels[ps->performance_level_count - 1].bSP =
5494 cpu_to_be32(pi->psp);
5497 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5498 struct rv7xx_pl *pl,
5499 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5501 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5502 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5503 struct si_power_info *si_pi = si_get_pi(adev);
5507 bool gmc_pg = false;
5509 if (eg_pi->pcie_performance_request &&
5510 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5511 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5513 level->gen2PCIE = (u8)pl->pcie_gen;
5515 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5521 if (pi->mclk_stutter_mode_threshold &&
5522 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5523 !eg_pi->uvd_enabled &&
5524 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5525 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5526 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5529 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5532 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5533 if (pl->mclk > pi->mclk_edc_enable_threshold)
5534 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5536 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5537 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5539 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5541 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5542 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5543 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5544 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5546 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5548 dll_state_on = false;
5551 level->strobeMode = si_get_strobe_mode_settings(adev,
5554 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5557 ret = si_populate_mclk_value(adev,
5561 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5565 ret = si_populate_voltage_value(adev,
5566 &eg_pi->vddc_voltage_table,
5567 pl->vddc, &level->vddc);
5572 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5576 ret = si_populate_std_voltage_value(adev, std_vddc,
5577 level->vddc.index, &level->std_vddc);
5581 if (eg_pi->vddci_control) {
5582 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5583 pl->vddci, &level->vddci);
5588 if (si_pi->vddc_phase_shed_control) {
5589 ret = si_populate_phase_shedding_value(adev,
5590 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5599 level->MaxPoweredUpCU = si_pi->max_cu;
5601 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5606 static int si_populate_smc_t(struct amdgpu_device *adev,
5607 struct amdgpu_ps *amdgpu_state,
5608 SISLANDS_SMC_SWSTATE *smc_state)
5610 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5611 struct si_ps *state = si_get_ps(amdgpu_state);
5617 if (state->performance_level_count >= 9)
5620 if (state->performance_level_count < 2) {
5621 a_t = CG_R(0xffff) | CG_L(0);
5622 smc_state->levels[0].aT = cpu_to_be32(a_t);
5626 smc_state->levels[0].aT = cpu_to_be32(0);
5628 for (i = 0; i <= state->performance_level_count - 2; i++) {
5629 ret = r600_calculate_at(
5630 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5632 state->performance_levels[i + 1].sclk,
5633 state->performance_levels[i].sclk,
5638 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5639 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5642 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5643 a_t |= CG_R(t_l * pi->bsp / 20000);
5644 smc_state->levels[i].aT = cpu_to_be32(a_t);
5646 high_bsp = (i == state->performance_level_count - 2) ?
5648 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5649 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5655 static int si_disable_ulv(struct amdgpu_device *adev)
5657 struct si_power_info *si_pi = si_get_pi(adev);
5658 struct si_ulv_param *ulv = &si_pi->ulv;
5661 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5667 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5668 struct amdgpu_ps *amdgpu_state)
5670 const struct si_power_info *si_pi = si_get_pi(adev);
5671 const struct si_ulv_param *ulv = &si_pi->ulv;
5672 const struct si_ps *state = si_get_ps(amdgpu_state);
5675 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5678 /* XXX validate against display requirements! */
5680 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5681 if (adev->clock.current_dispclk <=
5682 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5684 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5689 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5695 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5696 struct amdgpu_ps *amdgpu_new_state)
5698 const struct si_power_info *si_pi = si_get_pi(adev);
5699 const struct si_ulv_param *ulv = &si_pi->ulv;
5701 if (ulv->supported) {
5702 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5703 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5709 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5710 struct amdgpu_ps *amdgpu_state,
5711 SISLANDS_SMC_SWSTATE *smc_state)
5713 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5714 struct ni_power_info *ni_pi = ni_get_pi(adev);
5715 struct si_power_info *si_pi = si_get_pi(adev);
5716 struct si_ps *state = si_get_ps(amdgpu_state);
5719 u32 sclk_in_sr = 1350; /* ??? */
5721 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5724 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5726 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5727 eg_pi->uvd_enabled = true;
5728 if (eg_pi->smu_uvd_hs)
5729 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5731 eg_pi->uvd_enabled = false;
5734 if (state->dc_compatible)
5735 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5737 smc_state->levelCount = 0;
5738 for (i = 0; i < state->performance_level_count; i++) {
5739 if (eg_pi->sclk_deep_sleep) {
5740 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5741 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5742 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5744 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5748 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5749 &smc_state->levels[i]);
5750 smc_state->levels[i].arbRefreshState =
5751 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5756 if (ni_pi->enable_power_containment)
5757 smc_state->levels[i].displayWatermark =
5758 (state->performance_levels[i].sclk < threshold) ?
5759 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5761 smc_state->levels[i].displayWatermark = (i < 2) ?
5762 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5764 if (eg_pi->dynamic_ac_timing)
5765 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5767 smc_state->levels[i].ACIndex = 0;
5769 smc_state->levelCount++;
5772 si_write_smc_soft_register(adev,
5773 SI_SMC_SOFT_REGISTER_watermark_threshold,
5776 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5778 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5780 ni_pi->enable_power_containment = false;
5782 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5784 ni_pi->enable_sq_ramping = false;
5786 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5789 static int si_upload_sw_state(struct amdgpu_device *adev,
5790 struct amdgpu_ps *amdgpu_new_state)
5792 struct si_power_info *si_pi = si_get_pi(adev);
5793 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5795 u32 address = si_pi->state_table_start +
5796 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5797 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5798 ((new_state->performance_level_count - 1) *
5799 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5800 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5802 memset(smc_state, 0, state_size);
5804 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5808 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5809 state_size, si_pi->sram_end);
5812 static int si_upload_ulv_state(struct amdgpu_device *adev)
5814 struct si_power_info *si_pi = si_get_pi(adev);
5815 struct si_ulv_param *ulv = &si_pi->ulv;
5818 if (ulv->supported && ulv->pl.vddc) {
5819 u32 address = si_pi->state_table_start +
5820 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5821 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5822 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5824 memset(smc_state, 0, state_size);
5826 ret = si_populate_ulv_state(adev, smc_state);
5828 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5829 state_size, si_pi->sram_end);
5835 static int si_upload_smc_data(struct amdgpu_device *adev)
5837 struct amdgpu_crtc *amdgpu_crtc = NULL;
5840 if (adev->pm.dpm.new_active_crtc_count == 0)
5843 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5844 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5845 amdgpu_crtc = adev->mode_info.crtcs[i];
5850 if (amdgpu_crtc == NULL)
5853 if (amdgpu_crtc->line_time <= 0)
5856 if (si_write_smc_soft_register(adev,
5857 SI_SMC_SOFT_REGISTER_crtc_index,
5858 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5861 if (si_write_smc_soft_register(adev,
5862 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5863 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5866 if (si_write_smc_soft_register(adev,
5867 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5868 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5874 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5875 struct si_mc_reg_table *table)
5880 for (i = 0, j = table->last; i < table->last; i++) {
5881 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5883 switch (table->mc_reg_address[i].s1) {
5885 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5886 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5887 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5888 for (k = 0; k < table->num_entries; k++)
5889 table->mc_reg_table_entry[k].mc_data[j] =
5890 ((temp_reg & 0xffff0000)) |
5891 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5893 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5896 temp_reg = RREG32(MC_PMG_CMD_MRS);
5897 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5898 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5899 for (k = 0; k < table->num_entries; k++) {
5900 table->mc_reg_table_entry[k].mc_data[j] =
5901 (temp_reg & 0xffff0000) |
5902 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5903 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5904 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5907 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5910 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5911 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5912 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5913 for (k = 0; k < table->num_entries; k++)
5914 table->mc_reg_table_entry[k].mc_data[j] =
5915 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5917 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5921 case MC_SEQ_RESERVE_M:
5922 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5923 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5924 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5925 for(k = 0; k < table->num_entries; k++)
5926 table->mc_reg_table_entry[k].mc_data[j] =
5927 (temp_reg & 0xffff0000) |
5928 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5930 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5943 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5947 case MC_SEQ_RAS_TIMING:
5948 *out_reg = MC_SEQ_RAS_TIMING_LP;
5950 case MC_SEQ_CAS_TIMING:
5951 *out_reg = MC_SEQ_CAS_TIMING_LP;
5953 case MC_SEQ_MISC_TIMING:
5954 *out_reg = MC_SEQ_MISC_TIMING_LP;
5956 case MC_SEQ_MISC_TIMING2:
5957 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5959 case MC_SEQ_RD_CTL_D0:
5960 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5962 case MC_SEQ_RD_CTL_D1:
5963 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5965 case MC_SEQ_WR_CTL_D0:
5966 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5968 case MC_SEQ_WR_CTL_D1:
5969 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5971 case MC_PMG_CMD_EMRS:
5972 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5974 case MC_PMG_CMD_MRS:
5975 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5977 case MC_PMG_CMD_MRS1:
5978 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5980 case MC_SEQ_PMG_TIMING:
5981 *out_reg = MC_SEQ_PMG_TIMING_LP;
5983 case MC_PMG_CMD_MRS2:
5984 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5986 case MC_SEQ_WR_CTL_2:
5987 *out_reg = MC_SEQ_WR_CTL_2_LP;
5997 static void si_set_valid_flag(struct si_mc_reg_table *table)
6001 for (i = 0; i < table->last; i++) {
6002 for (j = 1; j < table->num_entries; j++) {
6003 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
6004 table->valid_flag |= 1 << i;
6011 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6016 for (i = 0; i < table->last; i++)
6017 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6018 address : table->mc_reg_address[i].s1;
6022 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6023 struct si_mc_reg_table *si_table)
6027 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6029 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6032 for (i = 0; i < table->last; i++)
6033 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6034 si_table->last = table->last;
6036 for (i = 0; i < table->num_entries; i++) {
6037 si_table->mc_reg_table_entry[i].mclk_max =
6038 table->mc_reg_table_entry[i].mclk_max;
6039 for (j = 0; j < table->last; j++) {
6040 si_table->mc_reg_table_entry[i].mc_data[j] =
6041 table->mc_reg_table_entry[i].mc_data[j];
6044 si_table->num_entries = table->num_entries;
6049 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6051 struct si_power_info *si_pi = si_get_pi(adev);
6052 struct atom_mc_reg_table *table;
6053 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6054 u8 module_index = rv770_get_memory_module_index(adev);
6057 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6061 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6062 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6063 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6064 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6065 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6066 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6067 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6068 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6069 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6070 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6071 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6072 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6073 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6074 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6076 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6080 ret = si_copy_vbios_mc_reg_table(table, si_table);
6084 si_set_s0_mc_reg_index(si_table);
6086 ret = si_set_mc_special_registers(adev, si_table);
6090 si_set_valid_flag(si_table);
6099 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6100 SMC_SIslands_MCRegisters *mc_reg_table)
6102 struct si_power_info *si_pi = si_get_pi(adev);
6105 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6106 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6107 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6109 mc_reg_table->address[i].s0 =
6110 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6111 mc_reg_table->address[i].s1 =
6112 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6116 mc_reg_table->last = (u8)i;
6119 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6120 SMC_SIslands_MCRegisterSet *data,
6121 u32 num_entries, u32 valid_flag)
6125 for(i = 0, j = 0; j < num_entries; j++) {
6126 if (valid_flag & (1 << j)) {
6127 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6133 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6134 struct rv7xx_pl *pl,
6135 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6137 struct si_power_info *si_pi = si_get_pi(adev);
6140 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6141 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6145 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6148 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6149 mc_reg_table_data, si_pi->mc_reg_table.last,
6150 si_pi->mc_reg_table.valid_flag);
6153 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6154 struct amdgpu_ps *amdgpu_state,
6155 SMC_SIslands_MCRegisters *mc_reg_table)
6157 struct si_ps *state = si_get_ps(amdgpu_state);
6160 for (i = 0; i < state->performance_level_count; i++) {
6161 si_convert_mc_reg_table_entry_to_smc(adev,
6162 &state->performance_levels[i],
6163 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6167 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6168 struct amdgpu_ps *amdgpu_boot_state)
6170 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6171 struct si_power_info *si_pi = si_get_pi(adev);
6172 struct si_ulv_param *ulv = &si_pi->ulv;
6173 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6175 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6177 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6179 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6181 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6182 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6184 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6185 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6186 si_pi->mc_reg_table.last,
6187 si_pi->mc_reg_table.valid_flag);
6189 if (ulv->supported && ulv->pl.vddc != 0)
6190 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6191 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6193 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6194 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6195 si_pi->mc_reg_table.last,
6196 si_pi->mc_reg_table.valid_flag);
6198 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6200 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6201 (u8 *)smc_mc_reg_table,
6202 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6205 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6206 struct amdgpu_ps *amdgpu_new_state)
6208 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6209 struct si_power_info *si_pi = si_get_pi(adev);
6210 u32 address = si_pi->mc_reg_table_start +
6211 offsetof(SMC_SIslands_MCRegisters,
6212 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6213 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6215 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6217 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6219 return amdgpu_si_copy_bytes_to_smc(adev, address,
6220 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6221 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6225 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6228 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6230 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6233 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6234 struct amdgpu_ps *amdgpu_state)
6236 struct si_ps *state = si_get_ps(amdgpu_state);
6238 u16 pcie_speed, max_speed = 0;
6240 for (i = 0; i < state->performance_level_count; i++) {
6241 pcie_speed = state->performance_levels[i].pcie_gen;
6242 if (max_speed < pcie_speed)
6243 max_speed = pcie_speed;
6248 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6252 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6253 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6255 return (u16)speed_cntl;
6258 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6259 struct amdgpu_ps *amdgpu_new_state,
6260 struct amdgpu_ps *amdgpu_current_state)
6262 struct si_power_info *si_pi = si_get_pi(adev);
6263 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6264 enum amdgpu_pcie_gen current_link_speed;
6266 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6267 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6269 current_link_speed = si_pi->force_pcie_gen;
6271 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6272 si_pi->pspp_notify_required = false;
6273 if (target_link_speed > current_link_speed) {
6274 switch (target_link_speed) {
6275 #if defined(CONFIG_ACPI)
6276 case AMDGPU_PCIE_GEN3:
6277 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6279 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6280 if (current_link_speed == AMDGPU_PCIE_GEN2)
6282 case AMDGPU_PCIE_GEN2:
6283 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6287 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6291 if (target_link_speed < current_link_speed)
6292 si_pi->pspp_notify_required = true;
6296 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6297 struct amdgpu_ps *amdgpu_new_state,
6298 struct amdgpu_ps *amdgpu_current_state)
6300 struct si_power_info *si_pi = si_get_pi(adev);
6301 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6304 if (si_pi->pspp_notify_required) {
6305 if (target_link_speed == AMDGPU_PCIE_GEN3)
6306 request = PCIE_PERF_REQ_PECI_GEN3;
6307 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6308 request = PCIE_PERF_REQ_PECI_GEN2;
6310 request = PCIE_PERF_REQ_PECI_GEN1;
6312 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6313 (si_get_current_pcie_speed(adev) > 0))
6316 #if defined(CONFIG_ACPI)
6317 amdgpu_acpi_pcie_performance_request(adev, request, false);
6323 static int si_ds_request(struct amdgpu_device *adev,
6324 bool ds_status_on, u32 count_write)
6326 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6328 if (eg_pi->sclk_deep_sleep) {
6330 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6334 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6335 PPSMC_Result_OK) ? 0 : -EINVAL;
6341 static void si_set_max_cu_value(struct amdgpu_device *adev)
6343 struct si_power_info *si_pi = si_get_pi(adev);
6345 if (adev->asic_type == CHIP_VERDE) {
6346 switch (adev->pdev->device) {
6382 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6383 struct amdgpu_clock_voltage_dependency_table *table)
6387 u16 leakage_voltage;
6390 for (i = 0; i < table->count; i++) {
6391 switch (si_get_leakage_voltage_from_leakage_index(adev,
6392 table->entries[i].v,
6393 &leakage_voltage)) {
6395 table->entries[i].v = leakage_voltage;
6405 for (j = (table->count - 2); j >= 0; j--) {
6406 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6407 table->entries[j].v : table->entries[j + 1].v;
6413 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6417 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6418 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6420 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6421 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6422 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6424 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6425 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6426 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6428 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6432 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6433 struct amdgpu_ps *amdgpu_new_state,
6434 struct amdgpu_ps *amdgpu_current_state)
6437 u32 new_lane_width =
6438 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6439 u32 current_lane_width =
6440 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6442 if (new_lane_width != current_lane_width) {
6443 amdgpu_set_pcie_lanes(adev, new_lane_width);
6444 lane_width = amdgpu_get_pcie_lanes(adev);
6445 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6449 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6451 si_read_clock_registers(adev);
6452 si_enable_acpi_power_management(adev);
6455 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6458 u32 thermal_int = RREG32(CG_THERMAL_INT);
6461 PPSMC_Result result;
6463 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6464 WREG32(CG_THERMAL_INT, thermal_int);
6465 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6466 if (result != PPSMC_Result_OK) {
6467 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6471 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6472 WREG32(CG_THERMAL_INT, thermal_int);
6478 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6479 int min_temp, int max_temp)
6481 int low_temp = 0 * 1000;
6482 int high_temp = 255 * 1000;
6484 if (low_temp < min_temp)
6485 low_temp = min_temp;
6486 if (high_temp > max_temp)
6487 high_temp = max_temp;
6488 if (high_temp < low_temp) {
6489 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6493 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6494 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6495 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6497 adev->pm.dpm.thermal.min_temp = low_temp;
6498 adev->pm.dpm.thermal.max_temp = high_temp;
6503 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6505 struct si_power_info *si_pi = si_get_pi(adev);
6508 if (si_pi->fan_ctrl_is_in_default_mode) {
6509 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6510 si_pi->fan_ctrl_default_mode = tmp;
6511 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6513 si_pi->fan_ctrl_is_in_default_mode = false;
6516 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6518 WREG32(CG_FDO_CTRL2, tmp);
6520 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6521 tmp |= FDO_PWM_MODE(mode);
6522 WREG32(CG_FDO_CTRL2, tmp);
6525 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6527 struct si_power_info *si_pi = si_get_pi(adev);
6528 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6530 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6531 u16 fdo_min, slope1, slope2;
6532 u32 reference_clock, tmp;
6536 if (!si_pi->fan_table_start) {
6537 adev->pm.dpm.fan.ucode_fan_control = false;
6541 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6544 adev->pm.dpm.fan.ucode_fan_control = false;
6548 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6549 do_div(tmp64, 10000);
6550 fdo_min = (u16)tmp64;
6552 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6553 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6555 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6556 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6558 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6559 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6561 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6562 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6563 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6564 fan_table.slope1 = cpu_to_be16(slope1);
6565 fan_table.slope2 = cpu_to_be16(slope2);
6566 fan_table.fdo_min = cpu_to_be16(fdo_min);
6567 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6568 fan_table.hys_up = cpu_to_be16(1);
6569 fan_table.hys_slope = cpu_to_be16(1);
6570 fan_table.temp_resp_lim = cpu_to_be16(5);
6571 reference_clock = amdgpu_asic_get_xclk(adev);
6573 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6574 reference_clock) / 1600);
6575 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6577 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6578 fan_table.temp_src = (uint8_t)tmp;
6580 ret = amdgpu_si_copy_bytes_to_smc(adev,
6581 si_pi->fan_table_start,
6587 DRM_ERROR("Failed to load fan table to the SMC.");
6588 adev->pm.dpm.fan.ucode_fan_control = false;
6594 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6596 struct si_power_info *si_pi = si_get_pi(adev);
6599 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6600 if (ret == PPSMC_Result_OK) {
6601 si_pi->fan_is_controlled_by_smc = true;
6608 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6610 struct si_power_info *si_pi = si_get_pi(adev);
6613 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6615 if (ret == PPSMC_Result_OK) {
6616 si_pi->fan_is_controlled_by_smc = false;
6623 static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6629 if (adev->pm.no_fan)
6632 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6633 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6638 tmp64 = (u64)duty * 100;
6639 do_div(tmp64, duty100);
6640 *speed = (u32)tmp64;
6648 static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6651 struct si_power_info *si_pi = si_get_pi(adev);
6656 if (adev->pm.no_fan)
6659 if (si_pi->fan_is_controlled_by_smc)
6665 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6670 tmp64 = (u64)speed * duty100;
6674 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6675 tmp |= FDO_STATIC_DUTY(duty);
6676 WREG32(CG_FDO_CTRL0, tmp);
6681 static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6684 /* stop auto-manage */
6685 if (adev->pm.dpm.fan.ucode_fan_control)
6686 si_fan_ctrl_stop_smc_fan_control(adev);
6687 si_fan_ctrl_set_static_mode(adev, mode);
6689 /* restart auto-manage */
6690 if (adev->pm.dpm.fan.ucode_fan_control)
6691 si_thermal_start_smc_fan_control(adev);
6693 si_fan_ctrl_set_default_mode(adev);
6697 static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6699 struct si_power_info *si_pi = si_get_pi(adev);
6702 if (si_pi->fan_is_controlled_by_smc)
6705 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6706 return (tmp >> FDO_PWM_MODE_SHIFT);
6710 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6714 u32 xclk = amdgpu_asic_get_xclk(adev);
6716 if (adev->pm.no_fan)
6719 if (adev->pm.fan_pulses_per_revolution == 0)
6722 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6723 if (tach_period == 0)
6726 *speed = 60 * xclk * 10000 / tach_period;
6731 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6734 u32 tach_period, tmp;
6735 u32 xclk = amdgpu_asic_get_xclk(adev);
6737 if (adev->pm.no_fan)
6740 if (adev->pm.fan_pulses_per_revolution == 0)
6743 if ((speed < adev->pm.fan_min_rpm) ||
6744 (speed > adev->pm.fan_max_rpm))
6747 if (adev->pm.dpm.fan.ucode_fan_control)
6748 si_fan_ctrl_stop_smc_fan_control(adev);
6750 tach_period = 60 * xclk * 10000 / (8 * speed);
6751 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6752 tmp |= TARGET_PERIOD(tach_period);
6753 WREG32(CG_TACH_CTRL, tmp);
6755 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6761 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6763 struct si_power_info *si_pi = si_get_pi(adev);
6766 if (!si_pi->fan_ctrl_is_in_default_mode) {
6767 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6768 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6769 WREG32(CG_FDO_CTRL2, tmp);
6771 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6772 tmp |= TMIN(si_pi->t_min);
6773 WREG32(CG_FDO_CTRL2, tmp);
6774 si_pi->fan_ctrl_is_in_default_mode = true;
6778 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6780 if (adev->pm.dpm.fan.ucode_fan_control) {
6781 si_fan_ctrl_start_smc_fan_control(adev);
6782 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6786 static void si_thermal_initialize(struct amdgpu_device *adev)
6790 if (adev->pm.fan_pulses_per_revolution) {
6791 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6792 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6793 WREG32(CG_TACH_CTRL, tmp);
6796 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6797 tmp |= TACH_PWM_RESP_RATE(0x28);
6798 WREG32(CG_FDO_CTRL2, tmp);
6801 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6805 si_thermal_initialize(adev);
6806 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6809 ret = si_thermal_enable_alert(adev, true);
6812 if (adev->pm.dpm.fan.ucode_fan_control) {
6813 ret = si_halt_smc(adev);
6816 ret = si_thermal_setup_fan_table(adev);
6819 ret = si_resume_smc(adev);
6822 si_thermal_start_smc_fan_control(adev);
6828 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6830 if (!adev->pm.no_fan) {
6831 si_fan_ctrl_set_default_mode(adev);
6832 si_fan_ctrl_stop_smc_fan_control(adev);
6836 static int si_dpm_enable(struct amdgpu_device *adev)
6838 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6839 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6840 struct si_power_info *si_pi = si_get_pi(adev);
6841 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6844 if (amdgpu_si_is_smc_running(adev))
6846 if (pi->voltage_control || si_pi->voltage_control_svi2)
6847 si_enable_voltage_control(adev, true);
6848 if (pi->mvdd_control)
6849 si_get_mvdd_configuration(adev);
6850 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6851 ret = si_construct_voltage_tables(adev);
6853 DRM_ERROR("si_construct_voltage_tables failed\n");
6857 if (eg_pi->dynamic_ac_timing) {
6858 ret = si_initialize_mc_reg_table(adev);
6860 eg_pi->dynamic_ac_timing = false;
6863 si_enable_spread_spectrum(adev, true);
6864 if (pi->thermal_protection)
6865 si_enable_thermal_protection(adev, true);
6867 si_program_git(adev);
6868 si_program_tp(adev);
6869 si_program_tpp(adev);
6870 si_program_sstp(adev);
6871 si_enable_display_gap(adev);
6872 si_program_vc(adev);
6873 ret = si_upload_firmware(adev);
6875 DRM_ERROR("si_upload_firmware failed\n");
6878 ret = si_process_firmware_header(adev);
6880 DRM_ERROR("si_process_firmware_header failed\n");
6883 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6885 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6888 ret = si_init_smc_table(adev);
6890 DRM_ERROR("si_init_smc_table failed\n");
6893 ret = si_init_smc_spll_table(adev);
6895 DRM_ERROR("si_init_smc_spll_table failed\n");
6898 ret = si_init_arb_table_index(adev);
6900 DRM_ERROR("si_init_arb_table_index failed\n");
6903 if (eg_pi->dynamic_ac_timing) {
6904 ret = si_populate_mc_reg_table(adev, boot_ps);
6906 DRM_ERROR("si_populate_mc_reg_table failed\n");
6910 ret = si_initialize_smc_cac_tables(adev);
6912 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6915 ret = si_initialize_hardware_cac_manager(adev);
6917 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6920 ret = si_initialize_smc_dte_tables(adev);
6922 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6925 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6927 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6930 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6932 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6935 si_program_response_times(adev);
6936 si_program_ds_registers(adev);
6937 si_dpm_start_smc(adev);
6938 ret = si_notify_smc_display_change(adev, false);
6940 DRM_ERROR("si_notify_smc_display_change failed\n");
6943 si_enable_sclk_control(adev, true);
6946 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6947 si_thermal_start_thermal_controller(adev);
6948 ni_update_current_ps(adev, boot_ps);
6953 static int si_set_temperature_range(struct amdgpu_device *adev)
6957 ret = si_thermal_enable_alert(adev, false);
6960 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6963 ret = si_thermal_enable_alert(adev, true);
6970 static void si_dpm_disable(struct amdgpu_device *adev)
6972 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6973 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6975 if (!amdgpu_si_is_smc_running(adev))
6977 si_thermal_stop_thermal_controller(adev);
6978 si_disable_ulv(adev);
6980 if (pi->thermal_protection)
6981 si_enable_thermal_protection(adev, false);
6982 si_enable_power_containment(adev, boot_ps, false);
6983 si_enable_smc_cac(adev, boot_ps, false);
6984 si_enable_spread_spectrum(adev, false);
6985 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6987 si_reset_to_default(adev);
6988 si_dpm_stop_smc(adev);
6989 si_force_switch_to_arb_f0(adev);
6991 ni_update_current_ps(adev, boot_ps);
6994 static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6996 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6997 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6998 struct amdgpu_ps *new_ps = &requested_ps;
7000 ni_update_requested_ps(adev, new_ps);
7001 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
7006 static int si_power_control_set_level(struct amdgpu_device *adev)
7008 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
7011 ret = si_restrict_performance_levels_before_switch(adev);
7014 ret = si_halt_smc(adev);
7017 ret = si_populate_smc_tdp_limits(adev, new_ps);
7020 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7023 ret = si_resume_smc(adev);
7026 ret = si_set_sw_state(adev);
7032 static int si_dpm_set_power_state(struct amdgpu_device *adev)
7034 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7035 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7036 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7039 ret = si_disable_ulv(adev);
7041 DRM_ERROR("si_disable_ulv failed\n");
7044 ret = si_restrict_performance_levels_before_switch(adev);
7046 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7049 if (eg_pi->pcie_performance_request)
7050 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7051 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7052 ret = si_enable_power_containment(adev, new_ps, false);
7054 DRM_ERROR("si_enable_power_containment failed\n");
7057 ret = si_enable_smc_cac(adev, new_ps, false);
7059 DRM_ERROR("si_enable_smc_cac failed\n");
7062 ret = si_halt_smc(adev);
7064 DRM_ERROR("si_halt_smc failed\n");
7067 ret = si_upload_sw_state(adev, new_ps);
7069 DRM_ERROR("si_upload_sw_state failed\n");
7072 ret = si_upload_smc_data(adev);
7074 DRM_ERROR("si_upload_smc_data failed\n");
7077 ret = si_upload_ulv_state(adev);
7079 DRM_ERROR("si_upload_ulv_state failed\n");
7082 if (eg_pi->dynamic_ac_timing) {
7083 ret = si_upload_mc_reg_table(adev, new_ps);
7085 DRM_ERROR("si_upload_mc_reg_table failed\n");
7089 ret = si_program_memory_timing_parameters(adev, new_ps);
7091 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7094 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7096 ret = si_resume_smc(adev);
7098 DRM_ERROR("si_resume_smc failed\n");
7101 ret = si_set_sw_state(adev);
7103 DRM_ERROR("si_set_sw_state failed\n");
7106 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7107 if (eg_pi->pcie_performance_request)
7108 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7109 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7111 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7114 ret = si_enable_smc_cac(adev, new_ps, true);
7116 DRM_ERROR("si_enable_smc_cac failed\n");
7119 ret = si_enable_power_containment(adev, new_ps, true);
7121 DRM_ERROR("si_enable_power_containment failed\n");
7125 ret = si_power_control_set_level(adev);
7127 DRM_ERROR("si_power_control_set_level failed\n");
7134 static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7136 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7137 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7139 ni_update_current_ps(adev, new_ps);
7143 void si_dpm_reset_asic(struct amdgpu_device *adev)
7145 si_restrict_performance_levels_before_switch(adev);
7146 si_disable_ulv(adev);
7147 si_set_boot_state(adev);
7151 static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7153 si_program_display_gap(adev);
7157 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7158 struct amdgpu_ps *rps,
7159 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7162 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7163 rps->class = le16_to_cpu(non_clock_info->usClassification);
7164 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7166 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7167 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7168 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7169 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7170 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7171 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7177 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7178 adev->pm.dpm.boot_ps = rps;
7179 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7180 adev->pm.dpm.uvd_ps = rps;
7183 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7184 struct amdgpu_ps *rps, int index,
7185 union pplib_clock_info *clock_info)
7187 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7188 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7189 struct si_power_info *si_pi = si_get_pi(adev);
7190 struct si_ps *ps = si_get_ps(rps);
7191 u16 leakage_voltage;
7192 struct rv7xx_pl *pl = &ps->performance_levels[index];
7195 ps->performance_level_count = index + 1;
7197 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7198 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7199 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7200 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7202 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7203 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7204 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7205 pl->pcie_gen = r600_get_pcie_gen_support(adev,
7206 si_pi->sys_pcie_mask,
7207 si_pi->boot_pcie_gen,
7208 clock_info->si.ucPCIEGen);
7210 /* patch up vddc if necessary */
7211 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7214 pl->vddc = leakage_voltage;
7216 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7217 pi->acpi_vddc = pl->vddc;
7218 eg_pi->acpi_vddci = pl->vddci;
7219 si_pi->acpi_pcie_gen = pl->pcie_gen;
7222 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7224 /* XXX disable for A0 tahiti */
7225 si_pi->ulv.supported = false;
7226 si_pi->ulv.pl = *pl;
7227 si_pi->ulv.one_pcie_lane_in_ulv = false;
7228 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7229 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7230 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7233 if (pi->min_vddc_in_table > pl->vddc)
7234 pi->min_vddc_in_table = pl->vddc;
7236 if (pi->max_vddc_in_table < pl->vddc)
7237 pi->max_vddc_in_table = pl->vddc;
7239 /* patch up boot state */
7240 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7241 u16 vddc, vddci, mvdd;
7242 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7243 pl->mclk = adev->clock.default_mclk;
7244 pl->sclk = adev->clock.default_sclk;
7247 si_pi->mvdd_bootup_value = mvdd;
7250 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7251 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7252 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7253 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7254 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7255 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7259 union pplib_power_state {
7260 struct _ATOM_PPLIB_STATE v1;
7261 struct _ATOM_PPLIB_STATE_V2 v2;
7264 static int si_parse_power_table(struct amdgpu_device *adev)
7266 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7267 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7268 union pplib_power_state *power_state;
7269 int i, j, k, non_clock_array_index, clock_array_index;
7270 union pplib_clock_info *clock_info;
7271 struct _StateArray *state_array;
7272 struct _ClockInfoArray *clock_info_array;
7273 struct _NonClockInfoArray *non_clock_info_array;
7274 union power_info *power_info;
7275 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7278 u8 *power_state_offset;
7281 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7282 &frev, &crev, &data_offset))
7284 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7286 amdgpu_add_thermal_controller(adev);
7288 state_array = (struct _StateArray *)
7289 (mode_info->atom_context->bios + data_offset +
7290 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7291 clock_info_array = (struct _ClockInfoArray *)
7292 (mode_info->atom_context->bios + data_offset +
7293 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7294 non_clock_info_array = (struct _NonClockInfoArray *)
7295 (mode_info->atom_context->bios + data_offset +
7296 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7298 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7299 state_array->ucNumEntries, GFP_KERNEL);
7300 if (!adev->pm.dpm.ps)
7302 power_state_offset = (u8 *)state_array->states;
7303 for (i = 0; i < state_array->ucNumEntries; i++) {
7305 power_state = (union pplib_power_state *)power_state_offset;
7306 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7307 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7308 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7309 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7311 kfree(adev->pm.dpm.ps);
7314 adev->pm.dpm.ps[i].ps_priv = ps;
7315 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7317 non_clock_info_array->ucEntrySize);
7319 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7320 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7321 clock_array_index = idx[j];
7322 if (clock_array_index >= clock_info_array->ucNumEntries)
7324 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7326 clock_info = (union pplib_clock_info *)
7327 ((u8 *)&clock_info_array->clockInfo[0] +
7328 (clock_array_index * clock_info_array->ucEntrySize));
7329 si_parse_pplib_clock_info(adev,
7330 &adev->pm.dpm.ps[i], k,
7334 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7336 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7338 /* fill in the vce power states */
7339 for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
7341 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7342 clock_info = (union pplib_clock_info *)
7343 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7344 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7345 sclk |= clock_info->si.ucEngineClockHigh << 16;
7346 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7347 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7348 adev->pm.dpm.vce_states[i].sclk = sclk;
7349 adev->pm.dpm.vce_states[i].mclk = mclk;
7355 static int si_dpm_init(struct amdgpu_device *adev)
7357 struct rv7xx_power_info *pi;
7358 struct evergreen_power_info *eg_pi;
7359 struct ni_power_info *ni_pi;
7360 struct si_power_info *si_pi;
7361 struct atom_clock_dividers dividers;
7365 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7368 adev->pm.dpm.priv = si_pi;
7373 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7375 si_pi->sys_pcie_mask = 0;
7377 si_pi->sys_pcie_mask = mask;
7378 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7379 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7381 si_set_max_cu_value(adev);
7383 rv770_get_max_vddc(adev);
7384 si_get_leakage_vddc(adev);
7385 si_patch_dependency_tables_based_on_leakage(adev);
7388 eg_pi->acpi_vddci = 0;
7389 pi->min_vddc_in_table = 0;
7390 pi->max_vddc_in_table = 0;
7392 ret = amdgpu_get_platform_caps(adev);
7396 ret = amdgpu_parse_extended_power_table(adev);
7400 ret = si_parse_power_table(adev);
7404 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7405 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7406 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7407 amdgpu_free_extended_power_table(adev);
7410 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7411 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7412 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7413 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7414 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7415 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7416 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7417 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7418 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7420 if (adev->pm.dpm.voltage_response_time == 0)
7421 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7422 if (adev->pm.dpm.backbias_response_time == 0)
7423 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7425 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7426 0, false, ÷rs);
7428 pi->ref_div = dividers.ref_div + 1;
7430 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7432 eg_pi->smu_uvd_hs = false;
7434 pi->mclk_strobe_mode_threshold = 40000;
7435 if (si_is_special_1gb_platform(adev))
7436 pi->mclk_stutter_mode_threshold = 0;
7438 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7439 pi->mclk_edc_enable_threshold = 40000;
7440 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7442 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7444 pi->voltage_control =
7445 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7446 VOLTAGE_OBJ_GPIO_LUT);
7447 if (!pi->voltage_control) {
7448 si_pi->voltage_control_svi2 =
7449 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7451 if (si_pi->voltage_control_svi2)
7452 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7453 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7457 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7458 VOLTAGE_OBJ_GPIO_LUT);
7460 eg_pi->vddci_control =
7461 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7462 VOLTAGE_OBJ_GPIO_LUT);
7463 if (!eg_pi->vddci_control)
7464 si_pi->vddci_control_svi2 =
7465 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7468 si_pi->vddc_phase_shed_control =
7469 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7470 VOLTAGE_OBJ_PHASE_LUT);
7472 rv770_get_engine_memory_ss(adev);
7474 pi->asi = RV770_ASI_DFLT;
7475 pi->pasi = CYPRESS_HASI_DFLT;
7476 pi->vrc = SISLANDS_VRC_DFLT;
7478 pi->gfx_clock_gating = true;
7480 eg_pi->sclk_deep_sleep = true;
7481 si_pi->sclk_deep_sleep_above_low = false;
7483 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7484 pi->thermal_protection = true;
7486 pi->thermal_protection = false;
7488 eg_pi->dynamic_ac_timing = true;
7490 eg_pi->light_sleep = true;
7491 #if defined(CONFIG_ACPI)
7492 eg_pi->pcie_performance_request =
7493 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7495 eg_pi->pcie_performance_request = false;
7498 si_pi->sram_end = SMC_RAM_END;
7500 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7501 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7502 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7503 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7504 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7505 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7506 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7508 si_initialize_powertune_defaults(adev);
7510 /* make sure dc limits are valid */
7511 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7512 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7513 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7514 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7516 si_pi->fan_ctrl_is_in_default_mode = true;
7521 static void si_dpm_fini(struct amdgpu_device *adev)
7525 if (adev->pm.dpm.ps)
7526 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7527 kfree(adev->pm.dpm.ps[i].ps_priv);
7528 kfree(adev->pm.dpm.ps);
7529 kfree(adev->pm.dpm.priv);
7530 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7531 amdgpu_free_extended_power_table(adev);
7534 static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7537 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7538 struct amdgpu_ps *rps = &eg_pi->current_rps;
7539 struct si_ps *ps = si_get_ps(rps);
7540 struct rv7xx_pl *pl;
7542 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7543 CURRENT_STATE_INDEX_SHIFT;
7545 if (current_index >= ps->performance_level_count) {
7546 seq_printf(m, "invalid dpm profile %d\n", current_index);
7548 pl = &ps->performance_levels[current_index];
7549 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7550 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7551 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7555 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7556 struct amdgpu_irq_src *source,
7558 enum amdgpu_interrupt_state state)
7563 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7565 case AMDGPU_IRQ_STATE_DISABLE:
7566 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7567 cg_thermal_int |= THERM_INT_MASK_HIGH;
7568 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7570 case AMDGPU_IRQ_STATE_ENABLE:
7571 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7572 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7573 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7580 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7582 case AMDGPU_IRQ_STATE_DISABLE:
7583 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7584 cg_thermal_int |= THERM_INT_MASK_LOW;
7585 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7587 case AMDGPU_IRQ_STATE_ENABLE:
7588 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7589 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7590 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7603 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7604 struct amdgpu_irq_src *source,
7605 struct amdgpu_iv_entry *entry)
7607 bool queue_thermal = false;
7612 switch (entry->src_id) {
7613 case 230: /* thermal low to high */
7614 DRM_DEBUG("IH: thermal low to high\n");
7615 adev->pm.dpm.thermal.high_to_low = false;
7616 queue_thermal = true;
7618 case 231: /* thermal high to low */
7619 DRM_DEBUG("IH: thermal high to low\n");
7620 adev->pm.dpm.thermal.high_to_low = true;
7621 queue_thermal = true;
7628 schedule_work(&adev->pm.dpm.thermal.work);
7633 static int si_dpm_late_init(void *handle)
7636 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7641 /* init the sysfs and debugfs files late */
7642 ret = amdgpu_pm_sysfs_init(adev);
7646 ret = si_set_temperature_range(adev);
7650 si_dpm_powergate_uvd(adev, true);
7656 * si_dpm_init_microcode - load ucode images from disk
7658 * @adev: amdgpu_device pointer
7660 * Use the firmware interface to load the ucode images into
7661 * the driver (not loaded into hw).
7662 * Returns 0 on success, error on failure.
7664 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7666 const char *chip_name;
7671 switch (adev->asic_type) {
7673 chip_name = "tahiti";
7676 if ((adev->pdev->revision == 0x81) &&
7677 ((adev->pdev->device == 0x6810) ||
7678 (adev->pdev->device == 0x6811)))
7679 chip_name = "pitcairn_k";
7681 chip_name = "pitcairn";
7684 if (((adev->pdev->device == 0x6820) &&
7685 ((adev->pdev->revision == 0x81) ||
7686 (adev->pdev->revision == 0x83))) ||
7687 ((adev->pdev->device == 0x6821) &&
7688 ((adev->pdev->revision == 0x83) ||
7689 (adev->pdev->revision == 0x87))) ||
7690 ((adev->pdev->revision == 0x87) &&
7691 ((adev->pdev->device == 0x6823) ||
7692 (adev->pdev->device == 0x682b))))
7693 chip_name = "verde_k";
7695 chip_name = "verde";
7698 if (((adev->pdev->revision == 0x81) &&
7699 ((adev->pdev->device == 0x6600) ||
7700 (adev->pdev->device == 0x6604) ||
7701 (adev->pdev->device == 0x6605) ||
7702 (adev->pdev->device == 0x6610))) ||
7703 ((adev->pdev->revision == 0x83) &&
7704 (adev->pdev->device == 0x6610)))
7705 chip_name = "oland_k";
7707 chip_name = "oland";
7710 if (((adev->pdev->revision == 0x81) &&
7711 (adev->pdev->device == 0x6660)) ||
7712 ((adev->pdev->revision == 0x83) &&
7713 ((adev->pdev->device == 0x6660) ||
7714 (adev->pdev->device == 0x6663) ||
7715 (adev->pdev->device == 0x6665) ||
7716 (adev->pdev->device == 0x6667))))
7717 chip_name = "hainan_k";
7718 else if ((adev->pdev->revision == 0xc3) &&
7719 (adev->pdev->device == 0x6665))
7720 chip_name = "banks_k_2";
7722 chip_name = "hainan";
7727 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
7728 err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
7731 err = amdgpu_ucode_validate(adev->pm.fw);
7735 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7737 release_firmware(adev->pm.fw);
7744 static int si_dpm_sw_init(void *handle)
7747 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7749 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7753 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7757 /* default to balanced state */
7758 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7759 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7760 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7761 adev->pm.default_sclk = adev->clock.default_sclk;
7762 adev->pm.default_mclk = adev->clock.default_mclk;
7763 adev->pm.current_sclk = adev->clock.default_sclk;
7764 adev->pm.current_mclk = adev->clock.default_mclk;
7765 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7767 if (amdgpu_dpm == 0)
7770 ret = si_dpm_init_microcode(adev);
7774 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7775 mutex_lock(&adev->pm.mutex);
7776 ret = si_dpm_init(adev);
7779 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7780 if (amdgpu_dpm == 1)
7781 amdgpu_pm_print_power_states(adev);
7782 mutex_unlock(&adev->pm.mutex);
7783 DRM_INFO("amdgpu: dpm initialized\n");
7789 mutex_unlock(&adev->pm.mutex);
7790 DRM_ERROR("amdgpu: dpm initialization failed\n");
7794 static int si_dpm_sw_fini(void *handle)
7796 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7798 flush_work(&adev->pm.dpm.thermal.work);
7800 mutex_lock(&adev->pm.mutex);
7801 amdgpu_pm_sysfs_fini(adev);
7803 mutex_unlock(&adev->pm.mutex);
7808 static int si_dpm_hw_init(void *handle)
7812 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7817 mutex_lock(&adev->pm.mutex);
7818 si_dpm_setup_asic(adev);
7819 ret = si_dpm_enable(adev);
7821 adev->pm.dpm_enabled = false;
7823 adev->pm.dpm_enabled = true;
7824 mutex_unlock(&adev->pm.mutex);
7829 static int si_dpm_hw_fini(void *handle)
7831 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7833 if (adev->pm.dpm_enabled) {
7834 mutex_lock(&adev->pm.mutex);
7835 si_dpm_disable(adev);
7836 mutex_unlock(&adev->pm.mutex);
7842 static int si_dpm_suspend(void *handle)
7844 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7846 if (adev->pm.dpm_enabled) {
7847 mutex_lock(&adev->pm.mutex);
7849 si_dpm_disable(adev);
7850 /* reset the power state */
7851 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7852 mutex_unlock(&adev->pm.mutex);
7857 static int si_dpm_resume(void *handle)
7860 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7862 if (adev->pm.dpm_enabled) {
7863 /* asic init will reset to the boot state */
7864 mutex_lock(&adev->pm.mutex);
7865 si_dpm_setup_asic(adev);
7866 ret = si_dpm_enable(adev);
7868 adev->pm.dpm_enabled = false;
7870 adev->pm.dpm_enabled = true;
7871 mutex_unlock(&adev->pm.mutex);
7872 if (adev->pm.dpm_enabled)
7873 amdgpu_pm_compute_clocks(adev);
7878 static bool si_dpm_is_idle(void *handle)
7884 static int si_dpm_wait_for_idle(void *handle)
7890 static int si_dpm_soft_reset(void *handle)
7895 static int si_dpm_set_clockgating_state(void *handle,
7896 enum amd_clockgating_state state)
7901 static int si_dpm_set_powergating_state(void *handle,
7902 enum amd_powergating_state state)
7907 /* get temperature in millidegrees */
7908 static int si_dpm_get_temp(struct amdgpu_device *adev)
7911 int actual_temp = 0;
7913 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7919 actual_temp = temp & 0x1ff;
7921 actual_temp = (actual_temp * 1000);
7926 static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7928 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7929 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7932 return requested_state->performance_levels[0].sclk;
7934 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7937 static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7939 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7940 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7943 return requested_state->performance_levels[0].mclk;
7945 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7948 static void si_dpm_print_power_state(struct amdgpu_device *adev,
7949 struct amdgpu_ps *rps)
7951 struct si_ps *ps = si_get_ps(rps);
7952 struct rv7xx_pl *pl;
7955 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7956 amdgpu_dpm_print_cap_info(rps->caps);
7957 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7958 for (i = 0; i < ps->performance_level_count; i++) {
7959 pl = &ps->performance_levels[i];
7960 if (adev->asic_type >= CHIP_TAHITI)
7961 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7962 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7964 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
7965 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7967 amdgpu_dpm_print_ps_status(adev, rps);
7970 static int si_dpm_early_init(void *handle)
7973 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7975 si_dpm_set_dpm_funcs(adev);
7976 si_dpm_set_irq_funcs(adev);
7981 const struct amd_ip_funcs si_dpm_ip_funcs = {
7983 .early_init = si_dpm_early_init,
7984 .late_init = si_dpm_late_init,
7985 .sw_init = si_dpm_sw_init,
7986 .sw_fini = si_dpm_sw_fini,
7987 .hw_init = si_dpm_hw_init,
7988 .hw_fini = si_dpm_hw_fini,
7989 .suspend = si_dpm_suspend,
7990 .resume = si_dpm_resume,
7991 .is_idle = si_dpm_is_idle,
7992 .wait_for_idle = si_dpm_wait_for_idle,
7993 .soft_reset = si_dpm_soft_reset,
7994 .set_clockgating_state = si_dpm_set_clockgating_state,
7995 .set_powergating_state = si_dpm_set_powergating_state,
7998 static const struct amdgpu_dpm_funcs si_dpm_funcs = {
7999 .get_temperature = &si_dpm_get_temp,
8000 .pre_set_power_state = &si_dpm_pre_set_power_state,
8001 .set_power_state = &si_dpm_set_power_state,
8002 .post_set_power_state = &si_dpm_post_set_power_state,
8003 .display_configuration_changed = &si_dpm_display_configuration_changed,
8004 .get_sclk = &si_dpm_get_sclk,
8005 .get_mclk = &si_dpm_get_mclk,
8006 .print_power_state = &si_dpm_print_power_state,
8007 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8008 .force_performance_level = &si_dpm_force_performance_level,
8009 .vblank_too_short = &si_dpm_vblank_too_short,
8010 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8011 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8012 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8013 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8016 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8018 if (adev->pm.funcs == NULL)
8019 adev->pm.funcs = &si_dpm_funcs;
8022 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8023 .set = si_dpm_set_interrupt_state,
8024 .process = si_dpm_process_interrupt,
8027 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8029 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8030 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;