drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 /*(DEBLOBBED)*/
  53
  54 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  55 {
  56         SDMA0_REGISTER_OFFSET,
  57         SDMA1_REGISTER_OFFSET
  58 };
  59
  60 static const u32 golden_settings_iceland_a11[] =
  61 {
  62         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  63         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  64         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  65         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  66 };
  67
  68 static const u32 iceland_mgcg_cgcg_init[] =
  69 {
  70         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  71         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  72 };
  73
  74 /*
  75  * sDMA - System DMA
  76  * Starting with CIK, the GPU has new asynchronous
  77  * DMA engines.  These engines are used for compute
  78  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  79  * and each one supports 1 ring buffer used for gfx
  80  * and 2 queues used for compute.
  81  *
  82  * The programming model is very similar to the CP
  83  * (ring buffer, IBs, etc.), but sDMA has it's own
  84  * packet format that is different from the PM4 format
  85  * used by the CP. sDMA supports copying data, writing
  86  * embedded data, solid fills, and a number of other
  87  * things.  It also has support for tiling/detiling of
  88  * buffers.
  89  */
  90
  91 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  92 {
  93         switch (adev->asic_type) {
  94         case CHIP_TOPAZ:
  95                 amdgpu_program_register_sequence(adev,
  96                                                  iceland_mgcg_cgcg_init,
  97                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  98                 amdgpu_program_register_sequence(adev,
  99                                                  golden_settings_iceland_a11,
 100                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 101                 break;
 102         default:
 103                 break;
 104         }
 105 }
 106
 107 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 108 {
 109         int i;
 110         for (i = 0; i < adev->sdma.num_instances; i++) {
 111                 release_firmware(adev->sdma.instance[i].fw);
 112                 adev->sdma.instance[i].fw = NULL;
 113         }
 114 }
 115
 116 /**
 117  * sdma_v2_4_init_microcode - load ucode images from disk
 118  *
 119  * @adev: amdgpu_device pointer
 120  *
 121  * Use the firmware interface to load the ucode images into
 122  * the driver (not loaded into hw).
 123  * Returns 0 on success, error on failure.
 124  */
 125 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 126 {
 127         const char *chip_name;
 128         char fw_name[30];
 129         int err = 0, i;
 130         struct amdgpu_firmware_info *info = NULL;
 131         const struct common_firmware_header *header = NULL;
 132         const struct sdma_firmware_header_v1_0 *hdr;
 133
 134         DRM_DEBUG("\n");
 135
 136         switch (adev->asic_type) {
 137         case CHIP_TOPAZ:
 138                 chip_name = "topaz";
 139                 break;
 140         default: BUG();
 141         }
 142
 143         for (i = 0; i < adev->sdma.num_instances; i++) {
 144                 if (i == 0)
 145                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 146                 else
 147                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 148                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 149                 if (err)
 150                         goto out;
 151                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 152                 if (err)
 153                         goto out;
 154                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 155                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 156                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 157                 if (adev->sdma.instance[i].feature_version >= 20)
 158                         adev->sdma.instance[i].burst_nop = true;
 159
 160                 if (adev->firmware.smu_load) {
 161                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 162                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 163                         info->fw = adev->sdma.instance[i].fw;
 164                         header = (const struct common_firmware_header *)info->fw->data;
 165                         adev->firmware.fw_size +=
 166                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 167                 }
 168         }
 169
 170 out:
 171         if (err) {
 172                 printk(KERN_ERR
 173                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
 174                        fw_name);
 175                 for (i = 0; i < adev->sdma.num_instances; i++) {
 176                         release_firmware(adev->sdma.instance[i].fw);
 177                         adev->sdma.instance[i].fw = NULL;
 178                 }
 179         }
 180         return err;
 181 }
 182
 183 /**
 184  * sdma_v2_4_ring_get_rptr - get the current read pointer
 185  *
 186  * @ring: amdgpu ring pointer
 187  *
 188  * Get the current rptr from the hardware (VI+).
 189  */
 190 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 191 {
 192         u32 rptr;
 193
 194         /* XXX check if swapping is necessary on BE */
 195         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 196
 197         return rptr;
 198 }
 199
 200 /**
 201  * sdma_v2_4_ring_get_wptr - get the current write pointer
 202  *
 203  * @ring: amdgpu ring pointer
 204  *
 205  * Get the current wptr from the hardware (VI+).
 206  */
 207 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 208 {
 209         struct amdgpu_device *adev = ring->adev;
 210         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 211         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 212
 213         return wptr;
 214 }
 215
 216 /**
 217  * sdma_v2_4_ring_set_wptr - commit the write pointer
 218  *
 219  * @ring: amdgpu ring pointer
 220  *
 221  * Write the wptr back to the hardware (VI+).
 222  */
 223 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 224 {
 225         struct amdgpu_device *adev = ring->adev;
 226         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 227
 228         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 229 }
 230
 231 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 232 {
 233         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 234         int i;
 235
 236         for (i = 0; i < count; i++)
 237                 if (sdma && sdma->burst_nop && (i == 0))
 238                         amdgpu_ring_write(ring, ring->nop |
 239                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 240                 else
 241                         amdgpu_ring_write(ring, ring->nop);
 242 }
 243
 244 /**
 245  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 246  *
 247  * @ring: amdgpu ring pointer
 248  * @ib: IB object to schedule
 249  *
 250  * Schedule an IB in the DMA ring (VI).
 251  */
 252 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 253                                    struct amdgpu_ib *ib,
 254                                    unsigned vm_id, bool ctx_switch)
 255 {
 256         u32 vmid = vm_id & 0xf;
 257         u32 next_rptr = ring->wptr + 5;
 258
 259         while ((next_rptr & 7) != 2)
 260                 next_rptr++;
 261
 262         next_rptr += 6;
 263
 264         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 265                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 266         amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
 267         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
 268         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 269         amdgpu_ring_write(ring, next_rptr);
 270
 271         /* IB packet must end on a 8 DW boundary */
 272         sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 273
 274         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 275                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 276         /* base must be 32 byte aligned */
 277         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 278         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 279         amdgpu_ring_write(ring, ib->length_dw);
 280         amdgpu_ring_write(ring, 0);
 281         amdgpu_ring_write(ring, 0);
 282
 283 }
 284
 285 /**
 286  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 287  *
 288  * @ring: amdgpu ring pointer
 289  *
 290  * Emit an hdp flush packet on the requested DMA ring.
 291  */
 292 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 293 {
 294         u32 ref_and_mask = 0;
 295
 296         if (ring == &ring->adev->sdma.instance[0].ring)
 297                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 298         else
 299                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 300
 301         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 302                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 303                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 304         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 305         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 306         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 307         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 308         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 309                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 310 }
 311
 312 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 313 {
 314         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 315                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 316         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 317         amdgpu_ring_write(ring, 1);
 318 }
 319 /**
 320  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 321  *
 322  * @ring: amdgpu ring pointer
 323  * @fence: amdgpu fence object
 324  *
 325  * Add a DMA fence packet to the ring to write
 326  * the fence seq number and DMA trap packet to generate
 327  * an interrupt if needed (VI).
 328  */
 329 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 330                                       unsigned flags)
 331 {
 332         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 333         /* write the fence */
 334         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 335         amdgpu_ring_write(ring, lower_32_bits(addr));
 336         amdgpu_ring_write(ring, upper_32_bits(addr));
 337         amdgpu_ring_write(ring, lower_32_bits(seq));
 338
 339         /* optionally write high bits as well */
 340         if (write64bit) {
 341                 addr += 4;
 342                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 343                 amdgpu_ring_write(ring, lower_32_bits(addr));
 344                 amdgpu_ring_write(ring, upper_32_bits(addr));
 345                 amdgpu_ring_write(ring, upper_32_bits(seq));
 346         }
 347
 348         /* generate an interrupt */
 349         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 350         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 351 }
 352
 353 /**
 354  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 355  *
 356  * @adev: amdgpu_device pointer
 357  *
 358  * Stop the gfx async dma ring buffers (VI).
 359  */
 360 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 361 {
 362         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 363         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 364         u32 rb_cntl, ib_cntl;
 365         int i;
 366
 367         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 368             (adev->mman.buffer_funcs_ring == sdma1))
 369                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 370
 371         for (i = 0; i < adev->sdma.num_instances; i++) {
 372                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 373                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 374                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 375                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 376                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 377                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 378         }
 379         sdma0->ready = false;
 380         sdma1->ready = false;
 381 }
 382
 383 /**
 384  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 385  *
 386  * @adev: amdgpu_device pointer
 387  *
 388  * Stop the compute async dma queues (VI).
 389  */
 390 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 391 {
 392         /* XXX todo */
 393 }
 394
 395 /**
 396  * sdma_v2_4_enable - stop the async dma engines
 397  *
 398  * @adev: amdgpu_device pointer
 399  * @enable: enable/disable the DMA MEs.
 400  *
 401  * Halt or unhalt the async dma engines (VI).
 402  */
 403 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 404 {
 405         u32 f32_cntl;
 406         int i;
 407
 408         if (enable == false) {
 409                 sdma_v2_4_gfx_stop(adev);
 410                 sdma_v2_4_rlc_stop(adev);
 411         }
 412
 413         for (i = 0; i < adev->sdma.num_instances; i++) {
 414                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 415                 if (enable)
 416                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 417                 else
 418                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 419                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 420         }
 421 }
 422
 423 /**
 424  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 425  *
 426  * @adev: amdgpu_device pointer
 427  *
 428  * Set up the gfx DMA ring buffers and enable them (VI).
 429  * Returns 0 for success, error for failure.
 430  */
 431 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 432 {
 433         struct amdgpu_ring *ring;
 434         u32 rb_cntl, ib_cntl;
 435         u32 rb_bufsz;
 436         u32 wb_offset;
 437         int i, j, r;
 438
 439         for (i = 0; i < adev->sdma.num_instances; i++) {
 440                 ring = &adev->sdma.instance[i].ring;
 441                 wb_offset = (ring->rptr_offs * 4);
 442
 443                 mutex_lock(&adev->srbm_mutex);
 444                 for (j = 0; j < 16; j++) {
 445                         vi_srbm_select(adev, 0, 0, 0, j);
 446                         /* SDMA GFX */
 447                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 448                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 449                 }
 450                 vi_srbm_select(adev, 0, 0, 0, 0);
 451                 mutex_unlock(&adev->srbm_mutex);
 452
 453                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 454                        adev->gfx.config.gb_addr_config & 0x70);
 455
 456                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 457
 458                 /* Set ring buffer size in dwords */
 459                 rb_bufsz = order_base_2(ring->ring_size / 4);
 460                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 461                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 462 #ifdef __BIG_ENDIAN
 463                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 464                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 465                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 466 #endif
 467                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 468
 469                 /* Initialize the ring buffer's read and write pointers */
 470                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 471                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 472                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 473                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 474
 475                 /* set the wb address whether it's enabled or not */
 476                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 477                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 478                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 479                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 480
 481                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 482
 483                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 484                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 485
 486                 ring->wptr = 0;
 487                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 488
 489                 /* enable DMA RB */
 490                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 491                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 492
 493                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 494                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 495 #ifdef __BIG_ENDIAN
 496                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 497 #endif
 498                 /* enable DMA IBs */
 499                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 500
 501                 ring->ready = true;
 502         }
 503
 504         sdma_v2_4_enable(adev, true);
 505         for (i = 0; i < adev->sdma.num_instances; i++) {
 506                 ring = &adev->sdma.instance[i].ring;
 507                 r = amdgpu_ring_test_ring(ring);
 508                 if (r) {
 509                         ring->ready = false;
 510                         return r;
 511                 }
 512
 513                 if (adev->mman.buffer_funcs_ring == ring)
 514                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 515         }
 516
 517         return 0;
 518 }
 519
 520 /**
 521  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 522  *
 523  * @adev: amdgpu_device pointer
 524  *
 525  * Set up the compute DMA queues and enable them (VI).
 526  * Returns 0 for success, error for failure.
 527  */
 528 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 529 {
 530         /* XXX todo */
 531         return 0;
 532 }
 533
 534 /**
 535  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 536  *
 537  * @adev: amdgpu_device pointer
 538  *
 539  * Loads the sDMA0/1 ucode.
 540  * Returns 0 for success, -EINVAL if the ucode is not available.
 541  */
 542 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 543 {
 544         const struct sdma_firmware_header_v1_0 *hdr;
 545         const __le32 *fw_data;
 546         u32 fw_size;
 547         int i, j;
 548
 549         /* halt the MEs */
 550         sdma_v2_4_enable(adev, false);
 551
 552         for (i = 0; i < adev->sdma.num_instances; i++) {
 553                 if (!adev->sdma.instance[i].fw)
 554                         return -EINVAL;
 555                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 556                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 557                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 558                 fw_data = (const __le32 *)
 559                         (adev->sdma.instance[i].fw->data +
 560                          le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 561                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 562                 for (j = 0; j < fw_size; j++)
 563                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 564                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 565         }
 566
 567         return 0;
 568 }
 569
 570 /**
 571  * sdma_v2_4_start - setup and start the async dma engines
 572  *
 573  * @adev: amdgpu_device pointer
 574  *
 575  * Set up the DMA engines and enable them (VI).
 576  * Returns 0 for success, error for failure.
 577  */
 578 static int sdma_v2_4_start(struct amdgpu_device *adev)
 579 {
 580         int r;
 581
 582         if (!adev->firmware.smu_load) {
 583                 r = sdma_v2_4_load_microcode(adev);
 584                 if (r)
 585                         return r;
 586         } else {
 587                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 588                                                 AMDGPU_UCODE_ID_SDMA0);
 589                 if (r)
 590                         return -EINVAL;
 591                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 592                                                 AMDGPU_UCODE_ID_SDMA1);
 593                 if (r)
 594                         return -EINVAL;
 595         }
 596
 597         /* halt the engine before programing */
 598         sdma_v2_4_enable(adev, false);
 599
 600         /* start the gfx rings and rlc compute queues */
 601         r = sdma_v2_4_gfx_resume(adev);
 602         if (r)
 603                 return r;
 604         r = sdma_v2_4_rlc_resume(adev);
 605         if (r)
 606                 return r;
 607
 608         return 0;
 609 }
 610
 611 /**
 612  * sdma_v2_4_ring_test_ring - simple async dma engine test
 613  *
 614  * @ring: amdgpu_ring structure holding ring information
 615  *
 616  * Test the DMA engine by writing using it to write an
 617  * value to memory. (VI).
 618  * Returns 0 for success, error for failure.
 619  */
 620 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 621 {
 622         struct amdgpu_device *adev = ring->adev;
 623         unsigned i;
 624         unsigned index;
 625         int r;
 626         u32 tmp;
 627         u64 gpu_addr;
 628
 629         r = amdgpu_wb_get(adev, &index);
 630         if (r) {
 631                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 632                 return r;
 633         }
 634
 635         gpu_addr = adev->wb.gpu_addr + (index * 4);
 636         tmp = 0xCAFEDEAD;
 637         adev->wb.wb[index] = cpu_to_le32(tmp);
 638
 639         r = amdgpu_ring_alloc(ring, 5);
 640         if (r) {
 641                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 642                 amdgpu_wb_free(adev, index);
 643                 return r;
 644         }
 645
 646         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 647                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 648         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 649         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 650         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 651         amdgpu_ring_write(ring, 0xDEADBEEF);
 652         amdgpu_ring_commit(ring);
 653
 654         for (i = 0; i < adev->usec_timeout; i++) {
 655                 tmp = le32_to_cpu(adev->wb.wb[index]);
 656                 if (tmp == 0xDEADBEEF)
 657                         break;
 658                 DRM_UDELAY(1);
 659         }
 660
 661         if (i < adev->usec_timeout) {
 662                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 663         } else {
 664                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 665                           ring->idx, tmp);
 666                 r = -EINVAL;
 667         }
 668         amdgpu_wb_free(adev, index);
 669
 670         return r;
 671 }
 672
 673 /**
 674  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 675  *
 676  * @ring: amdgpu_ring structure holding ring information
 677  *
 678  * Test a simple IB in the DMA ring (VI).
 679  * Returns 0 on success, error on failure.
 680  */
 681 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
 682 {
 683         struct amdgpu_device *adev = ring->adev;
 684         struct amdgpu_ib ib;
 685         struct fence *f = NULL;
 686         unsigned i;
 687         unsigned index;
 688         int r;
 689         u32 tmp = 0;
 690         u64 gpu_addr;
 691
 692         r = amdgpu_wb_get(adev, &index);
 693         if (r) {
 694                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 695                 return r;
 696         }
 697
 698         gpu_addr = adev->wb.gpu_addr + (index * 4);
 699         tmp = 0xCAFEDEAD;
 700         adev->wb.wb[index] = cpu_to_le32(tmp);
 701         memset(&ib, 0, sizeof(ib));
 702         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 703         if (r) {
 704                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 705                 goto err0;
 706         }
 707
 708         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 709                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 710         ib.ptr[1] = lower_32_bits(gpu_addr);
 711         ib.ptr[2] = upper_32_bits(gpu_addr);
 712         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 713         ib.ptr[4] = 0xDEADBEEF;
 714         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 715         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 716         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 717         ib.length_dw = 8;
 718
 719         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 720         if (r)
 721                 goto err1;
 722
 723         r = fence_wait(f, false);
 724         if (r) {
 725                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 726                 goto err1;
 727         }
 728         for (i = 0; i < adev->usec_timeout; i++) {
 729                 tmp = le32_to_cpu(adev->wb.wb[index]);
 730                 if (tmp == 0xDEADBEEF)
 731                         break;
 732                 DRM_UDELAY(1);
 733         }
 734         if (i < adev->usec_timeout) {
 735                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 736                          ring->idx, i);
 737                 goto err1;
 738         } else {
 739                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 740                 r = -EINVAL;
 741         }
 742
 743 err1:
 744         fence_put(f);
 745         amdgpu_ib_free(adev, &ib, NULL);
 746         fence_put(f);
 747 err0:
 748         amdgpu_wb_free(adev, index);
 749         return r;
 750 }
 751
 752 /**
 753  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 754  *
 755  * @ib: indirect buffer to fill with commands
 756  * @pe: addr of the page entry
 757  * @src: src addr to copy from
 758  * @count: number of page entries to update
 759  *
 760  * Update PTEs by copying them from the GART using sDMA (CIK).
 761  */
 762 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 763                                   uint64_t pe, uint64_t src,
 764                                   unsigned count)
 765 {
 766         while (count) {
 767                 unsigned bytes = count * 8;
 768                 if (bytes > 0x1FFFF8)
 769                         bytes = 0x1FFFF8;
 770
 771                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 772                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 773                 ib->ptr[ib->length_dw++] = bytes;
 774                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 775                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 776                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 777                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 778                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 779
 780                 pe += bytes;
 781                 src += bytes;
 782                 count -= bytes / 8;
 783         }
 784 }
 785
 786 /**
 787  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 788  *
 789  * @ib: indirect buffer to fill with commands
 790  * @pe: addr of the page entry
 791  * @addr: dst addr to write into pe
 792  * @count: number of page entries to update
 793  * @incr: increase next addr by incr bytes
 794  * @flags: access flags
 795  *
 796  * Update PTEs by writing them manually using sDMA (CIK).
 797  */
 798 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
 799                                    const dma_addr_t *pages_addr, uint64_t pe,
 800                                    uint64_t addr, unsigned count,
 801                                    uint32_t incr, uint32_t flags)
 802 {
 803         uint64_t value;
 804         unsigned ndw;
 805
 806         while (count) {
 807                 ndw = count * 2;
 808                 if (ndw > 0xFFFFE)
 809                         ndw = 0xFFFFE;
 810
 811                 /* for non-physically contiguous pages (system) */
 812                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 813                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 814                 ib->ptr[ib->length_dw++] = pe;
 815                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 816                 ib->ptr[ib->length_dw++] = ndw;
 817                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 818                         value = amdgpu_vm_map_gart(pages_addr, addr);
 819                         addr += incr;
 820                         value |= flags;
 821                         ib->ptr[ib->length_dw++] = value;
 822                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 823                 }
 824         }
 825 }
 826
 827 /**
 828  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 829  *
 830  * @ib: indirect buffer to fill with commands
 831  * @pe: addr of the page entry
 832  * @addr: dst addr to write into pe
 833  * @count: number of page entries to update
 834  * @incr: increase next addr by incr bytes
 835  * @flags: access flags
 836  *
 837  * Update the page tables using sDMA (CIK).
 838  */
 839 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
 840                                      uint64_t pe,
 841                                      uint64_t addr, unsigned count,
 842                                      uint32_t incr, uint32_t flags)
 843 {
 844         uint64_t value;
 845         unsigned ndw;
 846
 847         while (count) {
 848                 ndw = count;
 849                 if (ndw > 0x7FFFF)
 850                         ndw = 0x7FFFF;
 851
 852                 if (flags & AMDGPU_PTE_VALID)
 853                         value = addr;
 854                 else
 855                         value = 0;
 856
 857                 /* for physically contiguous pages (vram) */
 858                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 859                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 860                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 861                 ib->ptr[ib->length_dw++] = flags; /* mask */
 862                 ib->ptr[ib->length_dw++] = 0;
 863                 ib->ptr[ib->length_dw++] = value; /* value */
 864                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 865                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 866                 ib->ptr[ib->length_dw++] = 0;
 867                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 868
 869                 pe += ndw * 8;
 870                 addr += ndw * incr;
 871                 count -= ndw;
 872         }
 873 }
 874
 875 /**
 876  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 877  *
 878  * @ib: indirect buffer to fill with padding
 879  *
 880  */
 881 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 882 {
 883         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 884         u32 pad_count;
 885         int i;
 886
 887         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 888         for (i = 0; i < pad_count; i++)
 889                 if (sdma && sdma->burst_nop && (i == 0))
 890                         ib->ptr[ib->length_dw++] =
 891                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 892                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 893                 else
 894                         ib->ptr[ib->length_dw++] =
 895                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 896 }
 897
 898 /**
 899  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 900  *
 901  * @ring: amdgpu_ring pointer
 902  *
 903  * Make sure all previous operations are completed (CIK).
 904  */
 905 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 906 {
 907         uint32_t seq = ring->fence_drv.sync_seq;
 908         uint64_t addr = ring->fence_drv.gpu_addr;
 909
 910         /* wait for idle */
 911         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 912                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 913                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 914                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 915         amdgpu_ring_write(ring, addr & 0xfffffffc);
 916         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 917         amdgpu_ring_write(ring, seq); /* reference */
 918         amdgpu_ring_write(ring, 0xfffffff); /* mask */
 919         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 920                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 921 }
 922
 923 /**
 924  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 925  *
 926  * @ring: amdgpu_ring pointer
 927  * @vm: amdgpu_vm pointer
 928  *
 929  * Update the page table base and flush the VM TLB
 930  * using sDMA (VI).
 931  */
 932 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 933                                          unsigned vm_id, uint64_t pd_addr)
 934 {
 935         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 936                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 937         if (vm_id < 8) {
 938                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 939         } else {
 940                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 941         }
 942         amdgpu_ring_write(ring, pd_addr >> 12);
 943
 944         /* flush TLB */
 945         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 946                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 947         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 948         amdgpu_ring_write(ring, 1 << vm_id);
 949
 950         /* wait for flush */
 951         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 952                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 953                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 954         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 955         amdgpu_ring_write(ring, 0);
 956         amdgpu_ring_write(ring, 0); /* reference */
 957         amdgpu_ring_write(ring, 0); /* mask */
 958         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 959                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 960 }
 961
 962 static int sdma_v2_4_early_init(void *handle)
 963 {
 964         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 965
 966         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 967
 968         sdma_v2_4_set_ring_funcs(adev);
 969         sdma_v2_4_set_buffer_funcs(adev);
 970         sdma_v2_4_set_vm_pte_funcs(adev);
 971         sdma_v2_4_set_irq_funcs(adev);
 972
 973         return 0;
 974 }
 975
 976 static int sdma_v2_4_sw_init(void *handle)
 977 {
 978         struct amdgpu_ring *ring;
 979         int r, i;
 980         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 981
 982         /* SDMA trap event */
 983         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 984         if (r)
 985                 return r;
 986
 987         /* SDMA Privileged inst */
 988         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 989         if (r)
 990                 return r;
 991
 992         /* SDMA Privileged inst */
 993         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 994         if (r)
 995                 return r;
 996
 997         r = sdma_v2_4_init_microcode(adev);
 998         if (r) {
 999                 DRM_ERROR("Failed to load sdma firmware!\n");
1000                 return r;
1001         }
1002
1003         for (i = 0; i < adev->sdma.num_instances; i++) {
1004                 ring = &adev->sdma.instance[i].ring;
1005                 ring->ring_obj = NULL;
1006                 ring->use_doorbell = false;
1007                 sprintf(ring->name, "sdma%d", i);
1008                 r = amdgpu_ring_init(adev, ring, 1024,
1009                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1010                                      &adev->sdma.trap_irq,
1011                                      (i == 0) ?
1012                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1013                                      AMDGPU_RING_TYPE_SDMA);
1014                 if (r)
1015                         return r;
1016         }
1017
1018         return r;
1019 }
1020
1021 static int sdma_v2_4_sw_fini(void *handle)
1022 {
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024         int i;
1025
1026         for (i = 0; i < adev->sdma.num_instances; i++)
1027                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1028
1029         sdma_v2_4_free_microcode(adev);
1030         return 0;
1031 }
1032
1033 static int sdma_v2_4_hw_init(void *handle)
1034 {
1035         int r;
1036         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1037
1038         sdma_v2_4_init_golden_registers(adev);
1039
1040         r = sdma_v2_4_start(adev);
1041         if (r)
1042                 return r;
1043
1044         return r;
1045 }
1046
1047 static int sdma_v2_4_hw_fini(void *handle)
1048 {
1049         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050
1051         sdma_v2_4_enable(adev, false);
1052
1053         return 0;
1054 }
1055
1056 static int sdma_v2_4_suspend(void *handle)
1057 {
1058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059
1060         return sdma_v2_4_hw_fini(adev);
1061 }
1062
1063 static int sdma_v2_4_resume(void *handle)
1064 {
1065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1066
1067         return sdma_v2_4_hw_init(adev);
1068 }
1069
1070 static bool sdma_v2_4_is_idle(void *handle)
1071 {
1072         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1073         u32 tmp = RREG32(mmSRBM_STATUS2);
1074
1075         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1076                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1077             return false;
1078
1079         return true;
1080 }
1081
1082 static int sdma_v2_4_wait_for_idle(void *handle)
1083 {
1084         unsigned i;
1085         u32 tmp;
1086         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1087
1088         for (i = 0; i < adev->usec_timeout; i++) {
1089                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1090                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1091
1092                 if (!tmp)
1093                         return 0;
1094                 udelay(1);
1095         }
1096         return -ETIMEDOUT;
1097 }
1098
1099 static int sdma_v2_4_soft_reset(void *handle)
1100 {
1101         u32 srbm_soft_reset = 0;
1102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1103         u32 tmp = RREG32(mmSRBM_STATUS2);
1104
1105         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1106                 /* sdma0 */
1107                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1108                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1109                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1110                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1111         }
1112         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1113                 /* sdma1 */
1114                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1115                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1116                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1117                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1118         }
1119
1120         if (srbm_soft_reset) {
1121                 tmp = RREG32(mmSRBM_SOFT_RESET);
1122                 tmp |= srbm_soft_reset;
1123                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1124                 WREG32(mmSRBM_SOFT_RESET, tmp);
1125                 tmp = RREG32(mmSRBM_SOFT_RESET);
1126
1127                 udelay(50);
1128
1129                 tmp &= ~srbm_soft_reset;
1130                 WREG32(mmSRBM_SOFT_RESET, tmp);
1131                 tmp = RREG32(mmSRBM_SOFT_RESET);
1132
1133                 /* Wait a little for things to settle down */
1134                 udelay(50);
1135         }
1136
1137         return 0;
1138 }
1139
1140 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1141                                         struct amdgpu_irq_src *src,
1142                                         unsigned type,
1143                                         enum amdgpu_interrupt_state state)
1144 {
1145         u32 sdma_cntl;
1146
1147         switch (type) {
1148         case AMDGPU_SDMA_IRQ_TRAP0:
1149                 switch (state) {
1150                 case AMDGPU_IRQ_STATE_DISABLE:
1151                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1152                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1153                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1154                         break;
1155                 case AMDGPU_IRQ_STATE_ENABLE:
1156                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1157                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1158                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1159                         break;
1160                 default:
1161                         break;
1162                 }
1163                 break;
1164         case AMDGPU_SDMA_IRQ_TRAP1:
1165                 switch (state) {
1166                 case AMDGPU_IRQ_STATE_DISABLE:
1167                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1168                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1169                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1170                         break;
1171                 case AMDGPU_IRQ_STATE_ENABLE:
1172                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1173                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1174                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1175                         break;
1176                 default:
1177                         break;
1178                 }
1179                 break;
1180         default:
1181                 break;
1182         }
1183         return 0;
1184 }
1185
1186 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1187                                       struct amdgpu_irq_src *source,
1188                                       struct amdgpu_iv_entry *entry)
1189 {
1190         u8 instance_id, queue_id;
1191
1192         instance_id = (entry->ring_id & 0x3) >> 0;
1193         queue_id = (entry->ring_id & 0xc) >> 2;
1194         DRM_DEBUG("IH: SDMA trap\n");
1195         switch (instance_id) {
1196         case 0:
1197                 switch (queue_id) {
1198                 case 0:
1199                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1200                         break;
1201                 case 1:
1202                         /* XXX compute */
1203                         break;
1204                 case 2:
1205                         /* XXX compute */
1206                         break;
1207                 }
1208                 break;
1209         case 1:
1210                 switch (queue_id) {
1211                 case 0:
1212                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1213                         break;
1214                 case 1:
1215                         /* XXX compute */
1216                         break;
1217                 case 2:
1218                         /* XXX compute */
1219                         break;
1220                 }
1221                 break;
1222         }
1223         return 0;
1224 }
1225
1226 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1227                                               struct amdgpu_irq_src *source,
1228                                               struct amdgpu_iv_entry *entry)
1229 {
1230         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1231         schedule_work(&adev->reset_work);
1232         return 0;
1233 }
1234
1235 static int sdma_v2_4_set_clockgating_state(void *handle,
1236                                           enum amd_clockgating_state state)
1237 {
1238         /* XXX handled via the smc on VI */
1239         return 0;
1240 }
1241
1242 static int sdma_v2_4_set_powergating_state(void *handle,
1243                                           enum amd_powergating_state state)
1244 {
1245         return 0;
1246 }
1247
1248 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1249         .name = "sdma_v2_4",
1250         .early_init = sdma_v2_4_early_init,
1251         .late_init = NULL,
1252         .sw_init = sdma_v2_4_sw_init,
1253         .sw_fini = sdma_v2_4_sw_fini,
1254         .hw_init = sdma_v2_4_hw_init,
1255         .hw_fini = sdma_v2_4_hw_fini,
1256         .suspend = sdma_v2_4_suspend,
1257         .resume = sdma_v2_4_resume,
1258         .is_idle = sdma_v2_4_is_idle,
1259         .wait_for_idle = sdma_v2_4_wait_for_idle,
1260         .soft_reset = sdma_v2_4_soft_reset,
1261         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1262         .set_powergating_state = sdma_v2_4_set_powergating_state,
1263 };
1264
1265 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1266         .get_rptr = sdma_v2_4_ring_get_rptr,
1267         .get_wptr = sdma_v2_4_ring_get_wptr,
1268         .set_wptr = sdma_v2_4_ring_set_wptr,
1269         .parse_cs = NULL,
1270         .emit_ib = sdma_v2_4_ring_emit_ib,
1271         .emit_fence = sdma_v2_4_ring_emit_fence,
1272         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1273         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1274         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1275         .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
1276         .test_ring = sdma_v2_4_ring_test_ring,
1277         .test_ib = sdma_v2_4_ring_test_ib,
1278         .insert_nop = sdma_v2_4_ring_insert_nop,
1279         .pad_ib = sdma_v2_4_ring_pad_ib,
1280 };
1281
1282 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1283 {
1284         int i;
1285
1286         for (i = 0; i < adev->sdma.num_instances; i++)
1287                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1288 }
1289
1290 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1291         .set = sdma_v2_4_set_trap_irq_state,
1292         .process = sdma_v2_4_process_trap_irq,
1293 };
1294
1295 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1296         .process = sdma_v2_4_process_illegal_inst_irq,
1297 };
1298
1299 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1300 {
1301         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1302         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1303         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1304 }
1305
1306 /**
1307  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1308  *
1309  * @ring: amdgpu_ring structure holding ring information
1310  * @src_offset: src GPU address
1311  * @dst_offset: dst GPU address
1312  * @byte_count: number of bytes to xfer
1313  *
1314  * Copy GPU buffers using the DMA engine (VI).
1315  * Used by the amdgpu ttm implementation to move pages if
1316  * registered as the asic copy callback.
1317  */
1318 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1319                                        uint64_t src_offset,
1320                                        uint64_t dst_offset,
1321                                        uint32_t byte_count)
1322 {
1323         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1324                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1325         ib->ptr[ib->length_dw++] = byte_count;
1326         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1327         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1328         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1329         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1330         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1331 }
1332
1333 /**
1334  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1335  *
1336  * @ring: amdgpu_ring structure holding ring information
1337  * @src_data: value to write to buffer
1338  * @dst_offset: dst GPU address
1339  * @byte_count: number of bytes to xfer
1340  *
1341  * Fill GPU buffers using the DMA engine (VI).
1342  */
1343 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1344                                        uint32_t src_data,
1345                                        uint64_t dst_offset,
1346                                        uint32_t byte_count)
1347 {
1348         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1349         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1350         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1351         ib->ptr[ib->length_dw++] = src_data;
1352         ib->ptr[ib->length_dw++] = byte_count;
1353 }
1354
1355 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1356         .copy_max_bytes = 0x1fffff,
1357         .copy_num_dw = 7,
1358         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1359
1360         .fill_max_bytes = 0x1fffff,
1361         .fill_num_dw = 7,
1362         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1363 };
1364
1365 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1366 {
1367         if (adev->mman.buffer_funcs == NULL) {
1368                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1369                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1370         }
1371 }
1372
1373 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1374         .copy_pte = sdma_v2_4_vm_copy_pte,
1375         .write_pte = sdma_v2_4_vm_write_pte,
1376         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1377 };
1378
1379 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1380 {
1381         unsigned i;
1382
1383         if (adev->vm_manager.vm_pte_funcs == NULL) {
1384                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1385                 for (i = 0; i < adev->sdma.num_instances; i++)
1386                         adev->vm_manager.vm_pte_rings[i] =
1387                                 &adev->sdma.instance[i].ring;
1388
1389                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1390         }
1391 }