drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "cikd.h"
  27 #include "cik.h"
  28 #include "gmc_v7_0.h"
  29 #include "amdgpu_ucode.h"
  30
  31 #include "bif/bif_4_1_d.h"
  32 #include "bif/bif_4_1_sh_mask.h"
  33
  34 #include "gmc/gmc_7_1_d.h"
  35 #include "gmc/gmc_7_1_sh_mask.h"
  36
  37 #include "oss/oss_2_0_d.h"
  38 #include "oss/oss_2_0_sh_mask.h"
  39
  40 #include "dce/dce_8_0_d.h"
  41 #include "dce/dce_8_0_sh_mask.h"
  42
  43 #include "amdgpu_atombios.h"
  44
  45 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
  46 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  47 static int gmc_v7_0_wait_for_idle(void *handle);
  48
  49 /*(DEBLOBBED)*/
  50
  51 static const u32 golden_settings_iceland_a11[] =
  52 {
  53         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  54         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  55         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  56         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  57 };
  58
  59 static const u32 iceland_mgcg_cgcg_init[] =
  60 {
  61         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  62 };
  63
  64 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  65 {
  66         switch (adev->asic_type) {
  67         case CHIP_TOPAZ:
  68                 amdgpu_program_register_sequence(adev,
  69                                                  iceland_mgcg_cgcg_init,
  70                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  71                 amdgpu_program_register_sequence(adev,
  72                                                  golden_settings_iceland_a11,
  73                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  74                 break;
  75         default:
  76                 break;
  77         }
  78 }
  79
  80 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
  81 {
  82         u32 blackout;
  83
  84         gmc_v7_0_wait_for_idle((void *)adev);
  85
  86         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  87         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  88                 /* Block CPU access */
  89                 WREG32(mmBIF_FB_EN, 0);
  90                 /* blackout the MC */
  91                 blackout = REG_SET_FIELD(blackout,
  92                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  93                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  94         }
  95         /* wait for the MC to settle */
  96         udelay(100);
  97 }
  98
  99 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
 100 {
 101         u32 tmp;
 102
 103         /* unblackout the MC */
 104         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 105         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 106         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 107         /* allow CPU access */
 108         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 109         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 110         WREG32(mmBIF_FB_EN, tmp);
 111 }
 112
 113 /**
 114  * gmc_v7_0_init_microcode - load ucode images from disk
 115  *
 116  * @adev: amdgpu_device pointer
 117  *
 118  * Use the firmware interface to load the ucode images into
 119  * the driver (not loaded into hw).
 120  * Returns 0 on success, error on failure.
 121  */
 122 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 123 {
 124         const char *chip_name;
 125         char fw_name[30];
 126         int err;
 127
 128         DRM_DEBUG("\n");
 129
 130         switch (adev->asic_type) {
 131         case CHIP_BONAIRE:
 132                 chip_name = "bonaire";
 133                 break;
 134         case CHIP_HAWAII:
 135                 chip_name = "hawaii";
 136                 break;
 137         case CHIP_TOPAZ:
 138                 chip_name = "topaz";
 139                 break;
 140         case CHIP_KAVERI:
 141         case CHIP_KABINI:
 142         case CHIP_MULLINS:
 143                 return 0;
 144         default: BUG();
 145         }
 146
 147         if (adev->asic_type == CHIP_TOPAZ)
 148                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 149         else
 150                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 151
 152         err = reject_firmware(&adev->mc.fw, fw_name, adev->dev);
 153         if (err)
 154                 goto out;
 155         err = amdgpu_ucode_validate(adev->mc.fw);
 156
 157 out:
 158         if (err) {
 159                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 160                 release_firmware(adev->mc.fw);
 161                 adev->mc.fw = NULL;
 162         }
 163         return err;
 164 }
 165
 166 /**
 167  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 168  *
 169  * @adev: amdgpu_device pointer
 170  *
 171  * Load the GDDR MC ucode into the hw (CIK).
 172  * Returns 0 on success, error on failure.
 173  */
 174 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 175 {
 176         const struct mc_firmware_header_v1_0 *hdr;
 177         const __le32 *fw_data = NULL;
 178         const __le32 *io_mc_regs = NULL;
 179         u32 running;
 180         int i, ucode_size, regs_size;
 181
 182         if (!adev->mc.fw)
 183                 return -EINVAL;
 184
 185         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 186         amdgpu_ucode_print_mc_hdr(&hdr->header);
 187
 188         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 189         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 190         io_mc_regs = (const __le32 *)
 191                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 192         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 193         fw_data = (const __le32 *)
 194                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 195
 196         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 197
 198         if (running == 0) {
 199                 /* reset the engine and set to writable */
 200                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 201                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 202
 203                 /* load mc io regs */
 204                 for (i = 0; i < regs_size; i++) {
 205                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 206                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 207                 }
 208                 /* load the MC ucode */
 209                 for (i = 0; i < ucode_size; i++)
 210                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 211
 212                 /* put the engine back into the active state */
 213                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 214                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 215                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 216
 217                 /* wait for training to complete */
 218                 for (i = 0; i < adev->usec_timeout; i++) {
 219                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 220                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 221                                 break;
 222                         udelay(1);
 223                 }
 224                 for (i = 0; i < adev->usec_timeout; i++) {
 225                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 226                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 227                                 break;
 228                         udelay(1);
 229                 }
 230         }
 231
 232         return 0;
 233 }
 234
 235 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 236                                        struct amdgpu_mc *mc)
 237 {
 238         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 239         base <<= 24;
 240
 241         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 242                 /* leave room for at least 1024M GTT */
 243                 dev_warn(adev->dev, "limiting VRAM\n");
 244                 mc->real_vram_size = 0xFFC0000000ULL;
 245                 mc->mc_vram_size = 0xFFC0000000ULL;
 246         }
 247         amdgpu_vram_location(adev, &adev->mc, base);
 248         amdgpu_gart_location(adev, mc);
 249 }
 250
 251 /**
 252  * gmc_v7_0_mc_program - program the GPU memory controller
 253  *
 254  * @adev: amdgpu_device pointer
 255  *
 256  * Set the location of vram, gart, and AGP in the GPU's
 257  * physical address space (CIK).
 258  */
 259 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 260 {
 261         u32 tmp;
 262         int i, j;
 263
 264         /* Initialize HDP */
 265         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 266                 WREG32((0xb05 + j), 0x00000000);
 267                 WREG32((0xb06 + j), 0x00000000);
 268                 WREG32((0xb07 + j), 0x00000000);
 269                 WREG32((0xb08 + j), 0x00000000);
 270                 WREG32((0xb09 + j), 0x00000000);
 271         }
 272         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 273
 274         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 275                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 276         }
 277         if (adev->mode_info.num_crtc) {
 278                 /* Lockout access through VGA aperture*/
 279                 tmp = RREG32(mmVGA_HDP_CONTROL);
 280                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 281                 WREG32(mmVGA_HDP_CONTROL, tmp);
 282
 283                 /* disable VGA render */
 284                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 285                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 286                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 287         }
 288         /* Update configuration */
 289         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 290                adev->mc.vram_start >> 12);
 291         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 292                adev->mc.vram_end >> 12);
 293         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 294                adev->vram_scratch.gpu_addr >> 12);
 295         WREG32(mmMC_VM_AGP_BASE, 0);
 296         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 297         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 298         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 299                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 300         }
 301
 302         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 303
 304         tmp = RREG32(mmHDP_MISC_CNTL);
 305         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 306         WREG32(mmHDP_MISC_CNTL, tmp);
 307
 308         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 309         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 310 }
 311
 312 /**
 313  * gmc_v7_0_mc_init - initialize the memory controller driver params
 314  *
 315  * @adev: amdgpu_device pointer
 316  *
 317  * Look up the amount of vram, vram width, and decide how to place
 318  * vram and gart within the GPU's physical address space (CIK).
 319  * Returns 0 for success.
 320  */
 321 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 322 {
 323         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 324         if (!adev->mc.vram_width) {
 325                 u32 tmp;
 326                 int chansize, numchan;
 327
 328                 /* Get VRAM informations */
 329                 tmp = RREG32(mmMC_ARB_RAMCFG);
 330                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 331                         chansize = 64;
 332                 } else {
 333                         chansize = 32;
 334                 }
 335                 tmp = RREG32(mmMC_SHARED_CHMAP);
 336                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 337                 case 0:
 338                 default:
 339                         numchan = 1;
 340                         break;
 341                 case 1:
 342                         numchan = 2;
 343                         break;
 344                 case 2:
 345                         numchan = 4;
 346                         break;
 347                 case 3:
 348                         numchan = 8;
 349                         break;
 350                 case 4:
 351                         numchan = 3;
 352                         break;
 353                 case 5:
 354                         numchan = 6;
 355                         break;
 356                 case 6:
 357                         numchan = 10;
 358                         break;
 359                 case 7:
 360                         numchan = 12;
 361                         break;
 362                 case 8:
 363                         numchan = 16;
 364                         break;
 365                 }
 366                 adev->mc.vram_width = numchan * chansize;
 367         }
 368         /* Could aper size report 0 ? */
 369         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 370         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 371         /* size in MB on si */
 372         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 373         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 374
 375 #ifdef CONFIG_X86_64
 376         if (adev->flags & AMD_IS_APU) {
 377                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 378                 adev->mc.aper_size = adev->mc.real_vram_size;
 379         }
 380 #endif
 381
 382         /* In case the PCI BAR is larger than the actual amount of vram */
 383         adev->mc.visible_vram_size = adev->mc.aper_size;
 384         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 385                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 386
 387         /* set the gart size */
 388         if (amdgpu_gart_size == -1) {
 389                 switch (adev->asic_type) {
 390                 case CHIP_TOPAZ:     /* no MM engines */
 391                 default:
 392                         adev->mc.gart_size = 256ULL << 20;
 393                         break;
 394 #ifdef CONFIG_DRM_AMDGPU_CIK
 395                 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
 396                 case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
 397                 case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
 398                 case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
 399                 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
 400                         adev->mc.gart_size = 1024ULL << 20;
 401                         break;
 402 #endif
 403                 }
 404         } else {
 405                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 406         }
 407
 408         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 409
 410         return 0;
 411 }
 412
 413 /*
 414  * GART
 415  * VMID 0 is the physical GPU addresses as used by the kernel.
 416  * VMIDs 1-15 are used for userspace clients and are handled
 417  * by the amdgpu vm/hsa code.
 418  */
 419
 420 /**
 421  * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
 422  *
 423  * @adev: amdgpu_device pointer
 424  * @vmid: vm instance to flush
 425  *
 426  * Flush the TLB for the requested page table (CIK).
 427  */
 428 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 429                                         uint32_t vmid)
 430 {
 431         /* flush hdp cache */
 432         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 433
 434         /* bits 0-15 are the VM contexts0-15 */
 435         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 436 }
 437
 438 /**
 439  * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
 440  *
 441  * @adev: amdgpu_device pointer
 442  * @cpu_pt_addr: cpu address of the page table
 443  * @gpu_page_idx: entry in the page table to update
 444  * @addr: dst addr to write into pte/pde
 445  * @flags: access flags
 446  *
 447  * Update the page tables using the CPU.
 448  */
 449 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 450                                      void *cpu_pt_addr,
 451                                      uint32_t gpu_page_idx,
 452                                      uint64_t addr,
 453                                      uint64_t flags)
 454 {
 455         void __iomem *ptr = (void *)cpu_pt_addr;
 456         uint64_t value;
 457
 458         value = addr & 0xFFFFFFFFFFFFF000ULL;
 459         value |= flags;
 460         writeq(value, ptr + (gpu_page_idx * 8));
 461
 462         return 0;
 463 }
 464
 465 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
 466                                           uint32_t flags)
 467 {
 468         uint64_t pte_flag = 0;
 469
 470         if (flags & AMDGPU_VM_PAGE_READABLE)
 471                 pte_flag |= AMDGPU_PTE_READABLE;
 472         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 473                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 474         if (flags & AMDGPU_VM_PAGE_PRT)
 475                 pte_flag |= AMDGPU_PTE_PRT;
 476
 477         return pte_flag;
 478 }
 479
 480 static uint64_t gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 481 {
 482         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 483         return addr;
 484 }
 485
 486 /**
 487  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 488  *
 489  * @adev: amdgpu_device pointer
 490  * @value: true redirects VM faults to the default page
 491  */
 492 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 493                                               bool value)
 494 {
 495         u32 tmp;
 496
 497         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 498         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 499                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 500         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 501                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 502         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 503                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 504         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 505                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 506         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 507                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 508         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 509                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 510         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 511 }
 512
 513 /**
 514  * gmc_v7_0_set_prt - set PRT VM fault
 515  *
 516  * @adev: amdgpu_device pointer
 517  * @enable: enable/disable VM fault handling for PRT
 518  */
 519 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 520 {
 521         uint32_t tmp;
 522
 523         if (enable && !adev->mc.prt_warning) {
 524                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 525                 adev->mc.prt_warning = true;
 526         }
 527
 528         tmp = RREG32(mmVM_PRT_CNTL);
 529         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 530                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 531         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 532                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 533         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 534                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 535         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 536                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 537         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 538                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 539         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 540                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 541         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 542                             MASK_PDE0_FAULT, enable);
 543         WREG32(mmVM_PRT_CNTL, tmp);
 544
 545         if (enable) {
 546                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 547                 uint32_t high = adev->vm_manager.max_pfn;
 548
 549                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 550                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 551                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 552                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 553                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 554                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 555                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 556                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 557         } else {
 558                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 559                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 560                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 561                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 562                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 563                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 564                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 565                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 566         }
 567 }
 568
 569 /**
 570  * gmc_v7_0_gart_enable - gart enable
 571  *
 572  * @adev: amdgpu_device pointer
 573  *
 574  * This sets up the TLBs, programs the page tables for VMID0,
 575  * sets up the hw for VMIDs 1-15 which are allocated on
 576  * demand, and sets up the global locations for the LDS, GDS,
 577  * and GPUVM for FSA64 clients (CIK).
 578  * Returns 0 for success, errors for failure.
 579  */
 580 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 581 {
 582         int r, i;
 583         u32 tmp, field;
 584
 585         if (adev->gart.robj == NULL) {
 586                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 587                 return -EINVAL;
 588         }
 589         r = amdgpu_gart_table_vram_pin(adev);
 590         if (r)
 591                 return r;
 592         /* Setup TLB control */
 593         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 594         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 595         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 596         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 597         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 598         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 599         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 600         /* Setup L2 cache */
 601         tmp = RREG32(mmVM_L2_CNTL);
 602         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 603         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 604         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 605         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 606         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 607         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 608         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 609         WREG32(mmVM_L2_CNTL, tmp);
 610         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 611         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 612         WREG32(mmVM_L2_CNTL2, tmp);
 613
 614         field = adev->vm_manager.fragment_size;
 615         tmp = RREG32(mmVM_L2_CNTL3);
 616         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 617         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 618         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 619         WREG32(mmVM_L2_CNTL3, tmp);
 620         /* setup context0 */
 621         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 622         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 623         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 624         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 625                         (u32)(adev->dummy_page.addr >> 12));
 626         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 627         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 628         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 629         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 630         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 631         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 632
 633         WREG32(0x575, 0);
 634         WREG32(0x576, 0);
 635         WREG32(0x577, 0);
 636
 637         /* empty context1-15 */
 638         /* FIXME start with 4G, once using 2 level pt switch to full
 639          * vm size space
 640          */
 641         /* set vm size, must be a multiple of 4 */
 642         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 643         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 644         for (i = 1; i < 16; i++) {
 645                 if (i < 8)
 646                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 647                                adev->gart.table_addr >> 12);
 648                 else
 649                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 650                                adev->gart.table_addr >> 12);
 651         }
 652
 653         /* enable context1-15 */
 654         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 655                (u32)(adev->dummy_page.addr >> 12));
 656         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 657         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 658         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 659         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 660         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 661                             adev->vm_manager.block_size - 9);
 662         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 663         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 664                 gmc_v7_0_set_fault_enable_default(adev, false);
 665         else
 666                 gmc_v7_0_set_fault_enable_default(adev, true);
 667
 668         if (adev->asic_type == CHIP_KAVERI) {
 669                 tmp = RREG32(mmCHUB_CONTROL);
 670                 tmp &= ~BYPASS_VM;
 671                 WREG32(mmCHUB_CONTROL, tmp);
 672         }
 673
 674         gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
 675         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 676                  (unsigned)(adev->mc.gart_size >> 20),
 677                  (unsigned long long)adev->gart.table_addr);
 678         adev->gart.ready = true;
 679         return 0;
 680 }
 681
 682 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 683 {
 684         int r;
 685
 686         if (adev->gart.robj) {
 687                 WARN(1, "R600 PCIE GART already initialized\n");
 688                 return 0;
 689         }
 690         /* Initialize common gart structure */
 691         r = amdgpu_gart_init(adev);
 692         if (r)
 693                 return r;
 694         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 695         adev->gart.gart_pte_flags = 0;
 696         return amdgpu_gart_table_vram_alloc(adev);
 697 }
 698
 699 /**
 700  * gmc_v7_0_gart_disable - gart disable
 701  *
 702  * @adev: amdgpu_device pointer
 703  *
 704  * This disables all VM page table (CIK).
 705  */
 706 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 707 {
 708         u32 tmp;
 709
 710         /* Disable all tables */
 711         WREG32(mmVM_CONTEXT0_CNTL, 0);
 712         WREG32(mmVM_CONTEXT1_CNTL, 0);
 713         /* Setup TLB control */
 714         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 715         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 716         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 717         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 718         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 719         /* Setup L2 cache */
 720         tmp = RREG32(mmVM_L2_CNTL);
 721         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 722         WREG32(mmVM_L2_CNTL, tmp);
 723         WREG32(mmVM_L2_CNTL2, 0);
 724         amdgpu_gart_table_vram_unpin(adev);
 725 }
 726
 727 /**
 728  * gmc_v7_0_gart_fini - vm fini callback
 729  *
 730  * @adev: amdgpu_device pointer
 731  *
 732  * Tears down the driver GART/VM setup (CIK).
 733  */
 734 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
 735 {
 736         amdgpu_gart_table_vram_free(adev);
 737         amdgpu_gart_fini(adev);
 738 }
 739
 740 /**
 741  * gmc_v7_0_vm_decode_fault - print human readable fault info
 742  *
 743  * @adev: amdgpu_device pointer
 744  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 745  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 746  *
 747  * Print human readable fault information (CIK).
 748  */
 749 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
 750                                      u32 status, u32 addr, u32 mc_client)
 751 {
 752         u32 mc_id;
 753         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 754         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 755                                         PROTECTIONS);
 756         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 757                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 758
 759         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 760                               MEMORY_CLIENT_ID);
 761
 762         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 763                protections, vmid, addr,
 764                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 765                              MEMORY_CLIENT_RW) ?
 766                "write" : "read", block, mc_client, mc_id);
 767 }
 768
 769
 770 static const u32 mc_cg_registers[] = {
 771         mmMC_HUB_MISC_HUB_CG,
 772         mmMC_HUB_MISC_SIP_CG,
 773         mmMC_HUB_MISC_VM_CG,
 774         mmMC_XPB_CLK_GAT,
 775         mmATC_MISC_CG,
 776         mmMC_CITF_MISC_WR_CG,
 777         mmMC_CITF_MISC_RD_CG,
 778         mmMC_CITF_MISC_VM_CG,
 779         mmVM_L2_CG,
 780 };
 781
 782 static const u32 mc_cg_ls_en[] = {
 783         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 784         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 785         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 786         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 787         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 788         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 789         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 790         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 791         VM_L2_CG__MEM_LS_ENABLE_MASK,
 792 };
 793
 794 static const u32 mc_cg_en[] = {
 795         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 796         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 797         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 798         MC_XPB_CLK_GAT__ENABLE_MASK,
 799         ATC_MISC_CG__ENABLE_MASK,
 800         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 801         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 802         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 803         VM_L2_CG__ENABLE_MASK,
 804 };
 805
 806 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 807                                   bool enable)
 808 {
 809         int i;
 810         u32 orig, data;
 811
 812         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 813                 orig = data = RREG32(mc_cg_registers[i]);
 814                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 815                         data |= mc_cg_ls_en[i];
 816                 else
 817                         data &= ~mc_cg_ls_en[i];
 818                 if (data != orig)
 819                         WREG32(mc_cg_registers[i], data);
 820         }
 821 }
 822
 823 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 824                                     bool enable)
 825 {
 826         int i;
 827         u32 orig, data;
 828
 829         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 830                 orig = data = RREG32(mc_cg_registers[i]);
 831                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 832                         data |= mc_cg_en[i];
 833                 else
 834                         data &= ~mc_cg_en[i];
 835                 if (data != orig)
 836                         WREG32(mc_cg_registers[i], data);
 837         }
 838 }
 839
 840 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 841                                      bool enable)
 842 {
 843         u32 orig, data;
 844
 845         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 846
 847         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 848                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 849                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 850                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 851                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 852         } else {
 853                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 854                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 855                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 856                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 857         }
 858
 859         if (orig != data)
 860                 WREG32_PCIE(ixPCIE_CNTL2, data);
 861 }
 862
 863 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 864                                      bool enable)
 865 {
 866         u32 orig, data;
 867
 868         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 869
 870         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 871                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 872         else
 873                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 874
 875         if (orig != data)
 876                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 877 }
 878
 879 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 880                                    bool enable)
 881 {
 882         u32 orig, data;
 883
 884         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 885
 886         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 887                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 888         else
 889                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 890
 891         if (orig != data)
 892                 WREG32(mmHDP_MEM_POWER_LS, data);
 893 }
 894
 895 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 896 {
 897         switch (mc_seq_vram_type) {
 898         case MC_SEQ_MISC0__MT__GDDR1:
 899                 return AMDGPU_VRAM_TYPE_GDDR1;
 900         case MC_SEQ_MISC0__MT__DDR2:
 901                 return AMDGPU_VRAM_TYPE_DDR2;
 902         case MC_SEQ_MISC0__MT__GDDR3:
 903                 return AMDGPU_VRAM_TYPE_GDDR3;
 904         case MC_SEQ_MISC0__MT__GDDR4:
 905                 return AMDGPU_VRAM_TYPE_GDDR4;
 906         case MC_SEQ_MISC0__MT__GDDR5:
 907                 return AMDGPU_VRAM_TYPE_GDDR5;
 908         case MC_SEQ_MISC0__MT__HBM:
 909                 return AMDGPU_VRAM_TYPE_HBM;
 910         case MC_SEQ_MISC0__MT__DDR3:
 911                 return AMDGPU_VRAM_TYPE_DDR3;
 912         default:
 913                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 914         }
 915 }
 916
 917 static int gmc_v7_0_early_init(void *handle)
 918 {
 919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 920
 921         gmc_v7_0_set_gart_funcs(adev);
 922         gmc_v7_0_set_irq_funcs(adev);
 923
 924         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 925         adev->mc.shared_aperture_end =
 926                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 927         adev->mc.private_aperture_start =
 928                 adev->mc.shared_aperture_end + 1;
 929         adev->mc.private_aperture_end =
 930                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 931
 932         return 0;
 933 }
 934
 935 static int gmc_v7_0_late_init(void *handle)
 936 {
 937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 938
 939         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 940                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 941         else
 942                 return 0;
 943 }
 944
 945 static int gmc_v7_0_sw_init(void *handle)
 946 {
 947         int r;
 948         int dma_bits;
 949         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 950
 951         if (adev->flags & AMD_IS_APU) {
 952                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 953         } else {
 954                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 955                 tmp &= MC_SEQ_MISC0__MT__MASK;
 956                 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 957         }
 958
 959         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
 960         if (r)
 961                 return r;
 962
 963         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
 964         if (r)
 965                 return r;
 966
 967         /* Adjust VM size here.
 968          * Currently set to 4GB ((1 << 20) 4k pages).
 969          * Max GPUVM size for cayman and SI is 40 bits.
 970          */
 971         amdgpu_vm_adjust_size(adev, 64, 4);
 972         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 973
 974         /* Set the internal MC address mask
 975          * This is the max address of the GPU's
 976          * internal address space.
 977          */
 978         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 979
 980         adev->mc.stolen_size = 256 * 1024;
 981
 982         /* set DMA mask + need_dma32 flags.
 983          * PCIE - can handle 40-bits.
 984          * IGP - can handle 40-bits
 985          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 986          */
 987         adev->need_dma32 = false;
 988         dma_bits = adev->need_dma32 ? 32 : 40;
 989         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 990         if (r) {
 991                 adev->need_dma32 = true;
 992                 dma_bits = 32;
 993                 pr_warn("amdgpu: No suitable DMA available\n");
 994         }
 995         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 996         if (r) {
 997                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 998                 pr_warn("amdgpu: No coherent DMA available\n");
 999         }
1000
1001         r = gmc_v7_0_init_microcode(adev);
1002         if (r) {
1003                 DRM_ERROR("Failed to load mc firmware!\n");
1004                 return r;
1005         }
1006
1007         r = gmc_v7_0_mc_init(adev);
1008         if (r)
1009                 return r;
1010
1011         /* Memory manager */
1012         r = amdgpu_bo_init(adev);
1013         if (r)
1014                 return r;
1015
1016         r = gmc_v7_0_gart_init(adev);
1017         if (r)
1018                 return r;
1019
1020         /*
1021          * number of VMs
1022          * VMID 0 is reserved for System
1023          * amdgpu graphics/compute will use VMIDs 1-7
1024          * amdkfd will use VMIDs 8-15
1025          */
1026         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1027         adev->vm_manager.num_level = 1;
1028         amdgpu_vm_manager_init(adev);
1029
1030         /* base offset of vram pages */
1031         if (adev->flags & AMD_IS_APU) {
1032                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1033
1034                 tmp <<= 22;
1035                 adev->vm_manager.vram_base_offset = tmp;
1036         } else {
1037                 adev->vm_manager.vram_base_offset = 0;
1038         }
1039
1040         return 0;
1041 }
1042
1043 static int gmc_v7_0_sw_fini(void *handle)
1044 {
1045         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1046
1047         amdgpu_vm_manager_fini(adev);
1048         gmc_v7_0_gart_fini(adev);
1049         amdgpu_gem_force_release(adev);
1050         amdgpu_bo_fini(adev);
1051
1052         return 0;
1053 }
1054
1055 static int gmc_v7_0_hw_init(void *handle)
1056 {
1057         int r;
1058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059
1060         gmc_v7_0_init_golden_registers(adev);
1061
1062         gmc_v7_0_mc_program(adev);
1063
1064         if (!(adev->flags & AMD_IS_APU)) {
1065                 r = gmc_v7_0_mc_load_microcode(adev);
1066                 if (r) {
1067                         DRM_ERROR("Failed to load MC firmware!\n");
1068                         return r;
1069                 }
1070         }
1071
1072         r = gmc_v7_0_gart_enable(adev);
1073         if (r)
1074                 return r;
1075
1076         return r;
1077 }
1078
1079 static int gmc_v7_0_hw_fini(void *handle)
1080 {
1081         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1082
1083         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1084         gmc_v7_0_gart_disable(adev);
1085
1086         return 0;
1087 }
1088
1089 static int gmc_v7_0_suspend(void *handle)
1090 {
1091         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1092
1093         gmc_v7_0_hw_fini(adev);
1094
1095         return 0;
1096 }
1097
1098 static int gmc_v7_0_resume(void *handle)
1099 {
1100         int r;
1101         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1102
1103         r = gmc_v7_0_hw_init(adev);
1104         if (r)
1105                 return r;
1106
1107         amdgpu_vm_reset_all_ids(adev);
1108
1109         return 0;
1110 }
1111
1112 static bool gmc_v7_0_is_idle(void *handle)
1113 {
1114         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1115         u32 tmp = RREG32(mmSRBM_STATUS);
1116
1117         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1118                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1119                 return false;
1120
1121         return true;
1122 }
1123
1124 static int gmc_v7_0_wait_for_idle(void *handle)
1125 {
1126         unsigned i;
1127         u32 tmp;
1128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1129
1130         for (i = 0; i < adev->usec_timeout; i++) {
1131                 /* read MC_STATUS */
1132                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1133                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1134                                                SRBM_STATUS__MCC_BUSY_MASK |
1135                                                SRBM_STATUS__MCD_BUSY_MASK |
1136                                                SRBM_STATUS__VMC_BUSY_MASK);
1137                 if (!tmp)
1138                         return 0;
1139                 udelay(1);
1140         }
1141         return -ETIMEDOUT;
1142
1143 }
1144
1145 static int gmc_v7_0_soft_reset(void *handle)
1146 {
1147         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1148         u32 srbm_soft_reset = 0;
1149         u32 tmp = RREG32(mmSRBM_STATUS);
1150
1151         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1152                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1153                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1154
1155         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1156                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1157                 if (!(adev->flags & AMD_IS_APU))
1158                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1159                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1160         }
1161
1162         if (srbm_soft_reset) {
1163                 gmc_v7_0_mc_stop(adev);
1164                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1165                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1166                 }
1167
1168
1169                 tmp = RREG32(mmSRBM_SOFT_RESET);
1170                 tmp |= srbm_soft_reset;
1171                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1172                 WREG32(mmSRBM_SOFT_RESET, tmp);
1173                 tmp = RREG32(mmSRBM_SOFT_RESET);
1174
1175                 udelay(50);
1176
1177                 tmp &= ~srbm_soft_reset;
1178                 WREG32(mmSRBM_SOFT_RESET, tmp);
1179                 tmp = RREG32(mmSRBM_SOFT_RESET);
1180
1181                 /* Wait a little for things to settle down */
1182                 udelay(50);
1183
1184                 gmc_v7_0_mc_resume(adev);
1185                 udelay(50);
1186         }
1187
1188         return 0;
1189 }
1190
1191 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1192                                              struct amdgpu_irq_src *src,
1193                                              unsigned type,
1194                                              enum amdgpu_interrupt_state state)
1195 {
1196         u32 tmp;
1197         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1198                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1199                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1200                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1201                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1202                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1203
1204         switch (state) {
1205         case AMDGPU_IRQ_STATE_DISABLE:
1206                 /* system context */
1207                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1208                 tmp &= ~bits;
1209                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1210                 /* VMs */
1211                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1212                 tmp &= ~bits;
1213                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1214                 break;
1215         case AMDGPU_IRQ_STATE_ENABLE:
1216                 /* system context */
1217                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1218                 tmp |= bits;
1219                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1220                 /* VMs */
1221                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1222                 tmp |= bits;
1223                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1224                 break;
1225         default:
1226                 break;
1227         }
1228
1229         return 0;
1230 }
1231
1232 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1233                                       struct amdgpu_irq_src *source,
1234                                       struct amdgpu_iv_entry *entry)
1235 {
1236         u32 addr, status, mc_client;
1237
1238         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1239         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1240         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1241         /* reset addr and status */
1242         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1243
1244         if (!addr && !status)
1245                 return 0;
1246
1247         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1248                 gmc_v7_0_set_fault_enable_default(adev, false);
1249
1250         if (printk_ratelimit()) {
1251                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1252                         entry->src_id, entry->src_data[0]);
1253                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1254                         addr);
1255                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1256                         status);
1257                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1258         }
1259
1260         return 0;
1261 }
1262
1263 static int gmc_v7_0_set_clockgating_state(void *handle,
1264                                           enum amd_clockgating_state state)
1265 {
1266         bool gate = false;
1267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1268
1269         if (state == AMD_CG_STATE_GATE)
1270                 gate = true;
1271
1272         if (!(adev->flags & AMD_IS_APU)) {
1273                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1274                 gmc_v7_0_enable_mc_ls(adev, gate);
1275         }
1276         gmc_v7_0_enable_bif_mgls(adev, gate);
1277         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1278         gmc_v7_0_enable_hdp_ls(adev, gate);
1279
1280         return 0;
1281 }
1282
1283 static int gmc_v7_0_set_powergating_state(void *handle,
1284                                           enum amd_powergating_state state)
1285 {
1286         return 0;
1287 }
1288
1289 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1290         .name = "gmc_v7_0",
1291         .early_init = gmc_v7_0_early_init,
1292         .late_init = gmc_v7_0_late_init,
1293         .sw_init = gmc_v7_0_sw_init,
1294         .sw_fini = gmc_v7_0_sw_fini,
1295         .hw_init = gmc_v7_0_hw_init,
1296         .hw_fini = gmc_v7_0_hw_fini,
1297         .suspend = gmc_v7_0_suspend,
1298         .resume = gmc_v7_0_resume,
1299         .is_idle = gmc_v7_0_is_idle,
1300         .wait_for_idle = gmc_v7_0_wait_for_idle,
1301         .soft_reset = gmc_v7_0_soft_reset,
1302         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1303         .set_powergating_state = gmc_v7_0_set_powergating_state,
1304 };
1305
1306 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1307         .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1308         .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1309         .set_prt = gmc_v7_0_set_prt,
1310         .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
1311         .get_vm_pde = gmc_v7_0_get_vm_pde
1312 };
1313
1314 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1315         .set = gmc_v7_0_vm_fault_interrupt_state,
1316         .process = gmc_v7_0_process_interrupt,
1317 };
1318
1319 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1320 {
1321         if (adev->gart.gart_funcs == NULL)
1322                 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1323 }
1324
1325 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1326 {
1327         adev->mc.vm_fault.num_types = 1;
1328         adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1329 }
1330
1331 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1332 {
1333         .type = AMD_IP_BLOCK_TYPE_GMC,
1334         .major = 7,
1335         .minor = 0,
1336         .rev = 0,
1337         .funcs = &gmc_v7_0_ip_funcs,
1338 };
1339
1340 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1341 {
1342         .type = AMD_IP_BLOCK_TYPE_GMC,
1343         .major = 7,
1344         .minor = 4,
1345         .rev = 0,
1346         .funcs = &gmc_v7_0_ip_funcs,
1347 };