2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/pci.h>
26 #include "amdgpu_atomfirmware.h"
27 #include "gmc_v10_0.h"
29 #include "hdp/hdp_5_0_0_offset.h"
30 #include "hdp/hdp_5_0_0_sh_mask.h"
31 #include "gc/gc_10_1_0_sh_mask.h"
32 #include "mmhub/mmhub_2_0_0_sh_mask.h"
33 #include "dcn/dcn_2_0_0_offset.h"
34 #include "dcn/dcn_2_0_0_sh_mask.h"
35 #include "oss/osssys_5_0_0_offset.h"
36 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
37 #include "navi10_enum.h"
40 #include "soc15_common.h"
42 #include "nbio_v2_3.h"
44 #include "gfxhub_v2_0.h"
45 #include "mmhub_v2_0.h"
46 #include "athub_v2_0.h"
47 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
48 #define AMDGPU_NUM_OF_VMIDS 8
51 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
53 /* TODO add golden setting for hdp */
58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
59 struct amdgpu_irq_src *src, unsigned type,
60 enum amdgpu_interrupt_state state)
62 struct amdgpu_vmhub *hub;
63 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
65 bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
66 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
67 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
68 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
69 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
70 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
71 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
73 bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
74 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
75 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
76 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
77 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
78 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
79 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
82 case AMDGPU_IRQ_STATE_DISABLE:
84 hub = &adev->vmhub[AMDGPU_MMHUB_0];
85 for (i = 0; i < 16; i++) {
86 reg = hub->vm_context0_cntl + i;
88 tmp &= ~bits[AMDGPU_MMHUB_0];
93 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
94 for (i = 0; i < 16; i++) {
95 reg = hub->vm_context0_cntl + i;
97 tmp &= ~bits[AMDGPU_GFXHUB_0];
101 case AMDGPU_IRQ_STATE_ENABLE:
103 hub = &adev->vmhub[AMDGPU_MMHUB_0];
104 for (i = 0; i < 16; i++) {
105 reg = hub->vm_context0_cntl + i;
107 tmp |= bits[AMDGPU_MMHUB_0];
112 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
113 for (i = 0; i < 16; i++) {
114 reg = hub->vm_context0_cntl + i;
116 tmp |= bits[AMDGPU_GFXHUB_0];
127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
128 struct amdgpu_irq_src *source,
129 struct amdgpu_iv_entry *entry)
131 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
135 addr = (u64)entry->src_data[0] << 12;
136 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
138 if (!amdgpu_sriov_vf(adev)) {
140 * Issue a dummy read to wait for the status register to
141 * be updated to avoid reading an incorrect value due to
142 * the new fast GRBM interface.
144 if (entry->vmid_src == AMDGPU_GFXHUB_0)
145 RREG32(hub->vm_l2_pro_fault_status);
147 status = RREG32(hub->vm_l2_pro_fault_status);
148 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
151 if (printk_ratelimit()) {
152 struct amdgpu_task_info task_info;
154 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
155 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
158 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
159 "for process %s pid %d thread %s pid %d)\n",
160 entry->vmid_src ? "mmhub" : "gfxhub",
161 entry->src_id, entry->ring_id, entry->vmid,
162 entry->pasid, task_info.process_name, task_info.tgid,
163 task_info.task_name, task_info.pid);
164 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
165 addr, entry->client_id);
166 if (!amdgpu_sriov_vf(adev)) {
168 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
170 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
171 REG_GET_FIELD(status,
172 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
173 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
174 REG_GET_FIELD(status,
175 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
176 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
177 REG_GET_FIELD(status,
178 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
179 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
180 REG_GET_FIELD(status,
181 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
182 dev_err(adev->dev, "\t RW: 0x%lx\n",
183 REG_GET_FIELD(status,
184 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
191 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
192 .set = gmc_v10_0_vm_fault_interrupt_state,
193 .process = gmc_v10_0_process_interrupt,
196 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
198 adev->gmc.vm_fault.num_types = 1;
199 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
202 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
207 /* invalidate using legacy mode on vmid*/
208 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
209 PER_VMID_INVALIDATE_REQ, 1 << vmid);
210 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
211 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
212 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
213 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
214 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
215 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
216 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
217 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
224 * VMID 0 is the physical GPU addresses as used by the kernel.
225 * VMIDs 1-15 are used for userspace clients and are handled
226 * by the amdgpu vm/hsa code.
229 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
230 unsigned int vmhub, uint32_t flush_type)
232 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
233 u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
235 /* Use register 17 for GART */
236 const unsigned eng = 17;
239 spin_lock(&adev->gmc.invalidate_lock);
241 * It may lose gpuvm invalidate acknowldege state across power-gating
242 * off cycle, add semaphore acquire before invalidation and semaphore
243 * release after invalidation to avoid entering power gated state
247 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
248 if (vmhub == AMDGPU_MMHUB_0 ||
249 vmhub == AMDGPU_MMHUB_1) {
250 for (i = 0; i < adev->usec_timeout; i++) {
251 /* a read return value of 1 means semaphore acuqire */
252 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
258 if (i >= adev->usec_timeout)
259 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
262 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
265 * Issue a dummy read to wait for the ACK register to be cleared
266 * to avoid a false ACK due to the new fast GRBM interface.
268 if (vmhub == AMDGPU_GFXHUB_0)
269 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
271 /* Wait for ACK with a delay.*/
272 for (i = 0; i < adev->usec_timeout; i++) {
273 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
281 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
282 if (vmhub == AMDGPU_MMHUB_0 ||
283 vmhub == AMDGPU_MMHUB_1)
285 * add semaphore release after invalidation,
286 * write with 0 means semaphore release
288 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
290 spin_unlock(&adev->gmc.invalidate_lock);
292 if (i < adev->usec_timeout)
295 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
299 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
301 * @adev: amdgpu_device pointer
302 * @vmid: vm instance to flush
304 * Flush the TLB for the requested page table.
306 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
307 uint32_t vmhub, uint32_t flush_type)
309 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
310 struct dma_fence *fence;
311 struct amdgpu_job *job;
315 /* flush hdp cache */
316 adev->nbio_funcs->hdp_flush(adev, NULL);
318 mutex_lock(&adev->mman.gtt_window_lock);
320 if (vmhub == AMDGPU_MMHUB_0) {
321 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
322 mutex_unlock(&adev->mman.gtt_window_lock);
326 BUG_ON(vmhub != AMDGPU_GFXHUB_0);
328 if (!adev->mman.buffer_funcs_enabled ||
329 !adev->ib_pool_ready ||
330 adev->in_gpu_reset) {
331 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
332 mutex_unlock(&adev->mman.gtt_window_lock);
336 /* The SDMA on Navi has a bug which can theoretically result in memory
337 * corruption if an invalidation happens at the same time as an VA
338 * translation. Avoid this by doing the invalidation from the SDMA
341 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job);
345 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
346 job->vm_needs_flush = true;
347 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
348 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
349 r = amdgpu_job_submit(job, &adev->mman.entity,
350 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
354 mutex_unlock(&adev->mman.gtt_window_lock);
356 dma_fence_wait(fence, false);
357 dma_fence_put(fence);
362 amdgpu_job_free(job);
365 mutex_unlock(&adev->mman.gtt_window_lock);
366 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
369 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
370 unsigned vmid, uint64_t pd_addr)
372 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
373 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
374 unsigned eng = ring->vm_inv_eng;
377 * It may lose gpuvm invalidate acknowldege state across power-gating
378 * off cycle, add semaphore acquire before invalidation and semaphore
379 * release after invalidation to avoid entering power gated state
383 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
384 if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
385 ring->funcs->vmhub == AMDGPU_MMHUB_1)
386 /* a read return value of 1 means semaphore acuqire */
387 amdgpu_ring_emit_reg_wait(ring,
388 hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
390 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
391 lower_32_bits(pd_addr));
393 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
394 upper_32_bits(pd_addr));
396 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
397 hub->vm_inv_eng0_ack + eng,
400 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
401 if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
402 ring->funcs->vmhub == AMDGPU_MMHUB_1)
404 * add semaphore release after invalidation,
405 * write with 0 means semaphore release
407 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
412 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
415 struct amdgpu_device *adev = ring->adev;
418 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
419 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
421 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
423 amdgpu_ring_emit_wreg(ring, reg, pasid);
427 * PTE format on NAVI 10:
436 * 47:12 4k physical page base address
446 * PDE format on NAVI 10:
447 * 63:59 block fragment size
451 * 47:6 physical base address of PD or PTE
457 static uint64_t gmc_v10_0_get_vm_pte_flags(struct amdgpu_device *adev,
460 uint64_t pte_flag = 0;
462 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
463 pte_flag |= AMDGPU_PTE_EXECUTABLE;
464 if (flags & AMDGPU_VM_PAGE_READABLE)
465 pte_flag |= AMDGPU_PTE_READABLE;
466 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
467 pte_flag |= AMDGPU_PTE_WRITEABLE;
469 switch (flags & AMDGPU_VM_MTYPE_MASK) {
470 case AMDGPU_VM_MTYPE_DEFAULT:
471 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
473 case AMDGPU_VM_MTYPE_NC:
474 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
476 case AMDGPU_VM_MTYPE_WC:
477 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
479 case AMDGPU_VM_MTYPE_CC:
480 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
482 case AMDGPU_VM_MTYPE_UC:
483 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
486 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
490 if (flags & AMDGPU_VM_PAGE_PRT)
491 pte_flag |= AMDGPU_PTE_PRT;
496 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
497 uint64_t *addr, uint64_t *flags)
499 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
500 *addr = adev->vm_manager.vram_base_offset + *addr -
501 adev->gmc.vram_start;
502 BUG_ON(*addr & 0xFFFF00000000003FULL);
504 if (!adev->gmc.translate_further)
507 if (level == AMDGPU_VM_PDB1) {
508 /* Set the block fragment size */
509 if (!(*flags & AMDGPU_PDE_PTE))
510 *flags |= AMDGPU_PDE_BFS(0x9);
512 } else if (level == AMDGPU_VM_PDB0) {
513 if (*flags & AMDGPU_PDE_PTE)
514 *flags &= ~AMDGPU_PDE_PTE;
516 *flags |= AMDGPU_PTE_TF;
520 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
521 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
522 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
523 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
524 .get_vm_pte_flags = gmc_v10_0_get_vm_pte_flags,
525 .get_vm_pde = gmc_v10_0_get_vm_pde
528 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
530 if (adev->gmc.gmc_funcs == NULL)
531 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
534 static int gmc_v10_0_early_init(void *handle)
536 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
538 gmc_v10_0_set_gmc_funcs(adev);
539 gmc_v10_0_set_irq_funcs(adev);
541 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
542 adev->gmc.shared_aperture_end =
543 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
544 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
545 adev->gmc.private_aperture_end =
546 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
551 static int gmc_v10_0_late_init(void *handle)
553 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
554 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
557 for(i = 0; i < adev->num_rings; ++i) {
558 struct amdgpu_ring *ring = adev->rings[i];
559 unsigned vmhub = ring->funcs->vmhub;
561 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
562 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
563 ring->idx, ring->name, ring->vm_inv_eng,
567 /* Engine 17 is used for GART flushes */
568 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
569 BUG_ON(vm_inv_eng[i] > 17);
571 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
574 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
575 struct amdgpu_gmc *mc)
579 if (!amdgpu_sriov_vf(adev))
580 base = gfxhub_v2_0_get_fb_location(adev);
582 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
583 amdgpu_gmc_gart_location(adev, mc);
585 /* base offset of vram pages */
586 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
590 * gmc_v10_0_mc_init - initialize the memory controller driver params
592 * @adev: amdgpu_device pointer
594 * Look up the amount of vram, vram width, and decide how to place
595 * vram and gart within the GPU's physical address space.
596 * Returns 0 for success.
598 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
600 int chansize, numchan;
602 if (!amdgpu_emu_mode)
603 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
605 /* hard code vram_width for emulation */
608 adev->gmc.vram_width = numchan * chansize;
611 /* Could aper size report 0 ? */
612 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
613 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
615 /* size in MB on si */
616 adev->gmc.mc_vram_size =
617 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
618 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
619 adev->gmc.visible_vram_size = adev->gmc.aper_size;
621 /* In case the PCI BAR is larger than the actual amount of vram */
622 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
623 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
625 /* set the gart size */
626 if (amdgpu_gart_size == -1) {
627 switch (adev->asic_type) {
632 adev->gmc.gart_size = 512ULL << 20;
636 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
638 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
643 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
648 WARN(1, "NAVI10 PCIE GART already initialized\n");
652 /* Initialize common gart structure */
653 r = amdgpu_gart_init(adev);
657 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
658 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
659 AMDGPU_PTE_EXECUTABLE;
661 return amdgpu_gart_table_vram_alloc(adev);
664 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
666 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
669 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
670 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
675 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
676 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
677 size = (REG_GET_FIELD(viewport,
678 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
679 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
682 /* return 0 if the pre-OS buffer uses up most of vram */
683 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
684 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
685 be aware of gart table overwrite\n");
694 static int gmc_v10_0_sw_init(void *handle)
697 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
699 gfxhub_v2_0_init(adev);
700 mmhub_v2_0_init(adev);
702 spin_lock_init(&adev->gmc.invalidate_lock);
704 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
705 switch (adev->asic_type) {
709 adev->num_vmhubs = 2;
711 * To fulfill 4-level page support,
712 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
713 * block size 512 (9bit)
715 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
721 /* This interrupt is VMC page fault.*/
722 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
723 VMC_1_0__SRCID__VM_FAULT,
724 &adev->gmc.vm_fault);
725 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
726 UTCL2_1_0__SRCID__FAULT,
727 &adev->gmc.vm_fault);
732 * Set the internal MC address mask This is the max address of the GPU's
733 * internal address space.
735 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
738 * Reserve 8M stolen memory for navi10 like vega10
739 * TODO: will check if it's really needed on asic.
741 if (amdgpu_emu_mode == 1)
742 adev->gmc.stolen_size = 0;
744 adev->gmc.stolen_size = 9 * 1024 *1024;
746 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
748 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
752 r = gmc_v10_0_mc_init(adev);
756 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev);
759 r = amdgpu_bo_init(adev);
763 r = gmc_v10_0_gart_init(adev);
769 * VMID 0 is reserved for System
770 * amdgpu graphics/compute will use VMIDs 1-7
771 * amdkfd will use VMIDs 8-15
773 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
774 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
776 amdgpu_vm_manager_init(adev);
782 * gmc_v8_0_gart_fini - vm fini callback
784 * @adev: amdgpu_device pointer
786 * Tears down the driver GART/VM setup (CIK).
788 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
790 amdgpu_gart_table_vram_free(adev);
791 amdgpu_gart_fini(adev);
794 static int gmc_v10_0_sw_fini(void *handle)
796 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
798 amdgpu_vm_manager_fini(adev);
799 gmc_v10_0_gart_fini(adev);
800 amdgpu_gem_force_release(adev);
801 amdgpu_bo_fini(adev);
806 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
808 switch (adev->asic_type) {
819 * gmc_v10_0_gart_enable - gart enable
821 * @adev: amdgpu_device pointer
823 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
829 if (adev->gart.bo == NULL) {
830 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
834 r = amdgpu_gart_table_vram_pin(adev);
838 r = gfxhub_v2_0_gart_enable(adev);
842 r = mmhub_v2_0_gart_enable(adev);
846 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
847 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
848 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
850 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
851 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
853 /* Flush HDP after it is initialized */
854 adev->nbio_funcs->hdp_flush(adev, NULL);
856 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
859 gfxhub_v2_0_set_fault_enable_default(adev, value);
860 mmhub_v2_0_set_fault_enable_default(adev, value);
861 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
862 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
864 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
865 (unsigned)(adev->gmc.gart_size >> 20),
866 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
868 adev->gart.ready = true;
873 static int gmc_v10_0_hw_init(void *handle)
876 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
878 /* The sequence of these two function calls matters.*/
879 gmc_v10_0_init_golden_registers(adev);
881 r = gmc_v10_0_gart_enable(adev);
889 * gmc_v10_0_gart_disable - gart disable
891 * @adev: amdgpu_device pointer
893 * This disables all VM page table.
895 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
897 gfxhub_v2_0_gart_disable(adev);
898 mmhub_v2_0_gart_disable(adev);
899 amdgpu_gart_table_vram_unpin(adev);
902 static int gmc_v10_0_hw_fini(void *handle)
904 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
906 if (amdgpu_sriov_vf(adev)) {
907 /* full access mode, so don't touch any GMC register */
908 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
912 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
913 gmc_v10_0_gart_disable(adev);
918 static int gmc_v10_0_suspend(void *handle)
920 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
922 gmc_v10_0_hw_fini(adev);
927 static int gmc_v10_0_resume(void *handle)
930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
932 r = gmc_v10_0_hw_init(adev);
936 amdgpu_vmid_reset_all(adev);
941 static bool gmc_v10_0_is_idle(void *handle)
943 /* MC is always ready in GMC v10.*/
947 static int gmc_v10_0_wait_for_idle(void *handle)
949 /* There is no need to wait for MC idle in GMC v10.*/
953 static int gmc_v10_0_soft_reset(void *handle)
958 static int gmc_v10_0_set_clockgating_state(void *handle,
959 enum amd_clockgating_state state)
962 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
964 r = mmhub_v2_0_set_clockgating(adev, state);
968 return athub_v2_0_set_clockgating(adev, state);
971 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
973 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
975 mmhub_v2_0_get_clockgating(adev, flags);
977 athub_v2_0_get_clockgating(adev, flags);
980 static int gmc_v10_0_set_powergating_state(void *handle,
981 enum amd_powergating_state state)
986 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
988 .early_init = gmc_v10_0_early_init,
989 .late_init = gmc_v10_0_late_init,
990 .sw_init = gmc_v10_0_sw_init,
991 .sw_fini = gmc_v10_0_sw_fini,
992 .hw_init = gmc_v10_0_hw_init,
993 .hw_fini = gmc_v10_0_hw_fini,
994 .suspend = gmc_v10_0_suspend,
995 .resume = gmc_v10_0_resume,
996 .is_idle = gmc_v10_0_is_idle,
997 .wait_for_idle = gmc_v10_0_wait_for_idle,
998 .soft_reset = gmc_v10_0_soft_reset,
999 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1000 .set_powergating_state = gmc_v10_0_set_powergating_state,
1001 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1004 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1006 .type = AMD_IP_BLOCK_TYPE_GMC,
1010 .funcs = &gmc_v10_0_ip_funcs,