drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_KABINI "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_KAVERI "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_HAWAII "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_MULLINS        "/*(DEBLOBBED)*/"
  48 #endif
  49 #define FIRMWARE_TONGA          "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_CARRIZO        "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_FIJI           "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_STONEY         "/*(DEBLOBBED)*/"
  53 #define FIRMWARE_POLARIS10      "/*(DEBLOBBED)*/"
  54 #define FIRMWARE_POLARIS11      "/*(DEBLOBBED)*/"
  55 #define FIRMWARE_POLARIS12      "/*(DEBLOBBED)*/"
  56 #define FIRMWARE_VEGAM          "/*(DEBLOBBED)*/"
  57
  58 #define FIRMWARE_VEGA10         "/*(DEBLOBBED)*/"
  59 #define FIRMWARE_VEGA12         "/*(DEBLOBBED)*/"
  60 #define FIRMWARE_VEGA20         "/*(DEBLOBBED)*/"
  61
  62 #ifdef CONFIG_DRM_AMDGPU_CIK
  63 /*(DEBLOBBED)*/
  64 #endif
  65 /*(DEBLOBBED)*/
  66
  67 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  68
  69 /**
  70  * amdgpu_vce_init - allocate memory, load vce firmware
  71  *
  72  * @adev: amdgpu_device pointer
  73  *
  74  * First step to get VCE online, allocate memory and load the firmware
  75  */
  76 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  77 {
  78         const char *fw_name;
  79         const struct common_firmware_header *hdr;
  80         unsigned ucode_version, version_major, version_minor, binary_id;
  81         int i, r;
  82
  83         switch (adev->asic_type) {
  84 #ifdef CONFIG_DRM_AMDGPU_CIK
  85         case CHIP_BONAIRE:
  86                 fw_name = FIRMWARE_BONAIRE;
  87                 break;
  88         case CHIP_KAVERI:
  89                 fw_name = FIRMWARE_KAVERI;
  90                 break;
  91         case CHIP_KABINI:
  92                 fw_name = FIRMWARE_KABINI;
  93                 break;
  94         case CHIP_HAWAII:
  95                 fw_name = FIRMWARE_HAWAII;
  96                 break;
  97         case CHIP_MULLINS:
  98                 fw_name = FIRMWARE_MULLINS;
  99                 break;
 100 #endif
 101         case CHIP_TONGA:
 102                 fw_name = FIRMWARE_TONGA;
 103                 break;
 104         case CHIP_CARRIZO:
 105                 fw_name = FIRMWARE_CARRIZO;
 106                 break;
 107         case CHIP_FIJI:
 108                 fw_name = FIRMWARE_FIJI;
 109                 break;
 110         case CHIP_STONEY:
 111                 fw_name = FIRMWARE_STONEY;
 112                 break;
 113         case CHIP_POLARIS10:
 114                 fw_name = FIRMWARE_POLARIS10;
 115                 break;
 116         case CHIP_POLARIS11:
 117                 fw_name = FIRMWARE_POLARIS11;
 118                 break;
 119         case CHIP_POLARIS12:
 120                 fw_name = FIRMWARE_POLARIS12;
 121                 break;
 122         case CHIP_VEGAM:
 123                 fw_name = FIRMWARE_VEGAM;
 124                 break;
 125         case CHIP_VEGA10:
 126                 fw_name = FIRMWARE_VEGA10;
 127                 break;
 128         case CHIP_VEGA12:
 129                 fw_name = FIRMWARE_VEGA12;
 130                 break;
 131         case CHIP_VEGA20:
 132                 fw_name = FIRMWARE_VEGA20;
 133                 break;
 134
 135         default:
 136                 return -EINVAL;
 137         }
 138
 139         r = reject_firmware(&adev->vce.fw, fw_name, adev->dev);
 140         if (r) {
 141                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 142                         fw_name);
 143                 return r;
 144         }
 145
 146         r = amdgpu_ucode_validate(adev->vce.fw);
 147         if (r) {
 148                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 149                         fw_name);
 150                 release_firmware(adev->vce.fw);
 151                 adev->vce.fw = NULL;
 152                 return r;
 153         }
 154
 155         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 156
 157         ucode_version = le32_to_cpu(hdr->ucode_version);
 158         version_major = (ucode_version >> 20) & 0xfff;
 159         version_minor = (ucode_version >> 8) & 0xfff;
 160         binary_id = ucode_version & 0xff;
 161         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 162                 version_major, version_minor, binary_id);
 163         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 164                                 (binary_id << 8));
 165
 166         r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
 167                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
 168                                     &adev->vce.gpu_addr, &adev->vce.cpu_addr);
 169         if (r) {
 170                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 171                 return r;
 172         }
 173
 174         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 175                 atomic_set(&adev->vce.handles[i], 0);
 176                 adev->vce.filp[i] = NULL;
 177         }
 178
 179         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
 180         mutex_init(&adev->vce.idle_mutex);
 181
 182         return 0;
 183 }
 184
 185 /**
 186  * amdgpu_vce_fini - free memory
 187  *
 188  * @adev: amdgpu_device pointer
 189  *
 190  * Last step on VCE teardown, free firmware memory
 191  */
 192 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 193 {
 194         unsigned i;
 195
 196         if (adev->vce.vcpu_bo == NULL)
 197                 return 0;
 198
 199         drm_sched_entity_destroy(&adev->vce.entity);
 200
 201         amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
 202                 (void **)&adev->vce.cpu_addr);
 203
 204         for (i = 0; i < adev->vce.num_rings; i++)
 205                 amdgpu_ring_fini(&adev->vce.ring[i]);
 206
 207         release_firmware(adev->vce.fw);
 208         mutex_destroy(&adev->vce.idle_mutex);
 209
 210         return 0;
 211 }
 212
 213 /**
 214  * amdgpu_vce_entity_init - init entity
 215  *
 216  * @adev: amdgpu_device pointer
 217  *
 218  */
 219 int amdgpu_vce_entity_init(struct amdgpu_device *adev)
 220 {
 221         struct amdgpu_ring *ring;
 222         struct drm_sched_rq *rq;
 223         int r;
 224
 225         ring = &adev->vce.ring[0];
 226         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 227         r = drm_sched_entity_init(&adev->vce.entity, &rq, 1, NULL);
 228         if (r != 0) {
 229                 DRM_ERROR("Failed setting up VCE run queue.\n");
 230                 return r;
 231         }
 232
 233         return 0;
 234 }
 235
 236 /**
 237  * amdgpu_vce_suspend - unpin VCE fw memory
 238  *
 239  * @adev: amdgpu_device pointer
 240  *
 241  */
 242 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 243 {
 244         int i;
 245
 246         cancel_delayed_work_sync(&adev->vce.idle_work);
 247
 248         if (adev->vce.vcpu_bo == NULL)
 249                 return 0;
 250
 251         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 252                 if (atomic_read(&adev->vce.handles[i]))
 253                         break;
 254
 255         if (i == AMDGPU_MAX_VCE_HANDLES)
 256                 return 0;
 257
 258         /* TODO: suspending running encoding sessions isn't supported */
 259         return -EINVAL;
 260 }
 261
 262 /**
 263  * amdgpu_vce_resume - pin VCE fw memory
 264  *
 265  * @adev: amdgpu_device pointer
 266  *
 267  */
 268 int amdgpu_vce_resume(struct amdgpu_device *adev)
 269 {
 270         void *cpu_addr;
 271         const struct common_firmware_header *hdr;
 272         unsigned offset;
 273         int r;
 274
 275         if (adev->vce.vcpu_bo == NULL)
 276                 return -EINVAL;
 277
 278         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 279         if (r) {
 280                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 281                 return r;
 282         }
 283
 284         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 285         if (r) {
 286                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 287                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 288                 return r;
 289         }
 290
 291         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 292         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 293         memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
 294                     adev->vce.fw->size - offset);
 295
 296         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 297
 298         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 299
 300         return 0;
 301 }
 302
 303 /**
 304  * amdgpu_vce_idle_work_handler - power off VCE
 305  *
 306  * @work: pointer to work structure
 307  *
 308  * power of VCE when it's not used any more
 309  */
 310 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 311 {
 312         struct amdgpu_device *adev =
 313                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 314         unsigned i, count = 0;
 315
 316         for (i = 0; i < adev->vce.num_rings; i++)
 317                 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 318
 319         if (count == 0) {
 320                 if (adev->pm.dpm_enabled) {
 321                         amdgpu_dpm_enable_vce(adev, false);
 322                 } else {
 323                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 324                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 325                                                                AMD_PG_STATE_GATE);
 326                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 327                                                                AMD_CG_STATE_GATE);
 328                 }
 329         } else {
 330                 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 331         }
 332 }
 333
 334 /**
 335  * amdgpu_vce_ring_begin_use - power up VCE
 336  *
 337  * @ring: amdgpu ring
 338  *
 339  * Make sure VCE is powerd up when we want to use it
 340  */
 341 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
 342 {
 343         struct amdgpu_device *adev = ring->adev;
 344         bool set_clocks;
 345
 346         if (amdgpu_sriov_vf(adev))
 347                 return;
 348
 349         mutex_lock(&adev->vce.idle_mutex);
 350         set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 351         if (set_clocks) {
 352                 if (adev->pm.dpm_enabled) {
 353                         amdgpu_dpm_enable_vce(adev, true);
 354                 } else {
 355                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 356                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 357                                                                AMD_CG_STATE_UNGATE);
 358                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 359                                                                AMD_PG_STATE_UNGATE);
 360
 361                 }
 362         }
 363         mutex_unlock(&adev->vce.idle_mutex);
 364 }
 365
 366 /**
 367  * amdgpu_vce_ring_end_use - power VCE down
 368  *
 369  * @ring: amdgpu ring
 370  *
 371  * Schedule work to power VCE down again
 372  */
 373 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
 374 {
 375         if (!amdgpu_sriov_vf(ring->adev))
 376                 schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 377 }
 378
 379 /**
 380  * amdgpu_vce_free_handles - free still open VCE handles
 381  *
 382  * @adev: amdgpu_device pointer
 383  * @filp: drm file pointer
 384  *
 385  * Close all VCE handles still open by this file pointer
 386  */
 387 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 388 {
 389         struct amdgpu_ring *ring = &adev->vce.ring[0];
 390         int i, r;
 391         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 392                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 393
 394                 if (!handle || adev->vce.filp[i] != filp)
 395                         continue;
 396
 397                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 398                 if (r)
 399                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 400
 401                 adev->vce.filp[i] = NULL;
 402                 atomic_set(&adev->vce.handles[i], 0);
 403         }
 404 }
 405
 406 /**
 407  * amdgpu_vce_get_create_msg - generate a VCE create msg
 408  *
 409  * @adev: amdgpu_device pointer
 410  * @ring: ring we should submit the msg to
 411  * @handle: VCE session handle to use
 412  * @fence: optional fence to return
 413  *
 414  * Open up a stream for HW test
 415  */
 416 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 417                               struct dma_fence **fence)
 418 {
 419         const unsigned ib_size_dw = 1024;
 420         struct amdgpu_job *job;
 421         struct amdgpu_ib *ib;
 422         struct dma_fence *f = NULL;
 423         uint64_t dummy;
 424         int i, r;
 425
 426         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 427         if (r)
 428                 return r;
 429
 430         ib = &job->ibs[0];
 431
 432         dummy = ib->gpu_addr + 1024;
 433
 434         /* stitch together an VCE create msg */
 435         ib->length_dw = 0;
 436         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 437         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 438         ib->ptr[ib->length_dw++] = handle;
 439
 440         if ((ring->adev->vce.fw_version >> 24) >= 52)
 441                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 442         else
 443                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 444         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 445         ib->ptr[ib->length_dw++] = 0x00000000;
 446         ib->ptr[ib->length_dw++] = 0x00000042;
 447         ib->ptr[ib->length_dw++] = 0x0000000a;
 448         ib->ptr[ib->length_dw++] = 0x00000001;
 449         ib->ptr[ib->length_dw++] = 0x00000080;
 450         ib->ptr[ib->length_dw++] = 0x00000060;
 451         ib->ptr[ib->length_dw++] = 0x00000100;
 452         ib->ptr[ib->length_dw++] = 0x00000100;
 453         ib->ptr[ib->length_dw++] = 0x0000000c;
 454         ib->ptr[ib->length_dw++] = 0x00000000;
 455         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 456                 ib->ptr[ib->length_dw++] = 0x00000000;
 457                 ib->ptr[ib->length_dw++] = 0x00000000;
 458                 ib->ptr[ib->length_dw++] = 0x00000000;
 459                 ib->ptr[ib->length_dw++] = 0x00000000;
 460         }
 461
 462         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 463         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 464         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 465         ib->ptr[ib->length_dw++] = dummy;
 466         ib->ptr[ib->length_dw++] = 0x00000001;
 467
 468         for (i = ib->length_dw; i < ib_size_dw; ++i)
 469                 ib->ptr[i] = 0x0;
 470
 471         r = amdgpu_job_submit_direct(job, ring, &f);
 472         if (r)
 473                 goto err;
 474
 475         if (fence)
 476                 *fence = dma_fence_get(f);
 477         dma_fence_put(f);
 478         return 0;
 479
 480 err:
 481         amdgpu_job_free(job);
 482         return r;
 483 }
 484
 485 /**
 486  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 487  *
 488  * @adev: amdgpu_device pointer
 489  * @ring: ring we should submit the msg to
 490  * @handle: VCE session handle to use
 491  * @fence: optional fence to return
 492  *
 493  * Close up a stream for HW test or if userspace failed to do so
 494  */
 495 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 496                                bool direct, struct dma_fence **fence)
 497 {
 498         const unsigned ib_size_dw = 1024;
 499         struct amdgpu_job *job;
 500         struct amdgpu_ib *ib;
 501         struct dma_fence *f = NULL;
 502         int i, r;
 503
 504         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 505         if (r)
 506                 return r;
 507
 508         ib = &job->ibs[0];
 509
 510         /* stitch together an VCE destroy msg */
 511         ib->length_dw = 0;
 512         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 513         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 514         ib->ptr[ib->length_dw++] = handle;
 515
 516         ib->ptr[ib->length_dw++] = 0x00000020; /* len */
 517         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 518         ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
 519         ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
 520         ib->ptr[ib->length_dw++] = 0x00000000;
 521         ib->ptr[ib->length_dw++] = 0x00000000;
 522         ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
 523         ib->ptr[ib->length_dw++] = 0x00000000;
 524
 525         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 526         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 527
 528         for (i = ib->length_dw; i < ib_size_dw; ++i)
 529                 ib->ptr[i] = 0x0;
 530
 531         if (direct)
 532                 r = amdgpu_job_submit_direct(job, ring, &f);
 533         else
 534                 r = amdgpu_job_submit(job, &ring->adev->vce.entity,
 535                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 536         if (r)
 537                 goto err;
 538
 539         if (fence)
 540                 *fence = dma_fence_get(f);
 541         dma_fence_put(f);
 542         return 0;
 543
 544 err:
 545         amdgpu_job_free(job);
 546         return r;
 547 }
 548
 549 /**
 550  * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
 551  *
 552  * @p: parser context
 553  * @lo: address of lower dword
 554  * @hi: address of higher dword
 555  * @size: minimum size
 556  * @index: bs/fb index
 557  *
 558  * Make sure that no BO cross a 4GB boundary.
 559  */
 560 static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 561                                   int lo, int hi, unsigned size, int32_t index)
 562 {
 563         int64_t offset = ((uint64_t)size) * ((int64_t)index);
 564         struct ttm_operation_ctx ctx = { false, false };
 565         struct amdgpu_bo_va_mapping *mapping;
 566         unsigned i, fpfn, lpfn;
 567         struct amdgpu_bo *bo;
 568         uint64_t addr;
 569         int r;
 570
 571         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 572                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 573         if (index >= 0) {
 574                 addr += offset;
 575                 fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
 576                 lpfn = 0x100000000ULL >> PAGE_SHIFT;
 577         } else {
 578                 fpfn = 0;
 579                 lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
 580         }
 581
 582         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 583         if (r) {
 584                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 585                           addr, lo, hi, size, index);
 586                 return r;
 587         }
 588
 589         for (i = 0; i < bo->placement.num_placement; ++i) {
 590                 bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
 591                 bo->placements[i].lpfn = bo->placements[i].lpfn ?
 592                         min(bo->placements[i].lpfn, lpfn) : lpfn;
 593         }
 594         return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 595 }
 596
 597
 598 /**
 599  * amdgpu_vce_cs_reloc - command submission relocation
 600  *
 601  * @p: parser context
 602  * @lo: address of lower dword
 603  * @hi: address of higher dword
 604  * @size: minimum size
 605  *
 606  * Patch relocation inside command stream with real buffer address
 607  */
 608 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 609                                int lo, int hi, unsigned size, uint32_t index)
 610 {
 611         struct amdgpu_bo_va_mapping *mapping;
 612         struct amdgpu_bo *bo;
 613         uint64_t addr;
 614         int r;
 615
 616         if (index == 0xffffffff)
 617                 index = 0;
 618
 619         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 620                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 621         addr += ((uint64_t)size) * ((uint64_t)index);
 622
 623         r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
 624         if (r) {
 625                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 626                           addr, lo, hi, size, index);
 627                 return r;
 628         }
 629
 630         if ((addr + (uint64_t)size) >
 631             (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 632                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 633                           addr, lo, hi);
 634                 return -EINVAL;
 635         }
 636
 637         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 638         addr += amdgpu_bo_gpu_offset(bo);
 639         addr -= ((uint64_t)size) * ((uint64_t)index);
 640
 641         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 642         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 643
 644         return 0;
 645 }
 646
 647 /**
 648  * amdgpu_vce_validate_handle - validate stream handle
 649  *
 650  * @p: parser context
 651  * @handle: handle to validate
 652  * @allocated: allocated a new handle?
 653  *
 654  * Validates the handle and return the found session index or -EINVAL
 655  * we we don't have another free session index.
 656  */
 657 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 658                                       uint32_t handle, uint32_t *allocated)
 659 {
 660         unsigned i;
 661
 662         /* validate the handle */
 663         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 664                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 665                         if (p->adev->vce.filp[i] != p->filp) {
 666                                 DRM_ERROR("VCE handle collision detected!\n");
 667                                 return -EINVAL;
 668                         }
 669                         return i;
 670                 }
 671         }
 672
 673         /* handle not found try to alloc a new one */
 674         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 675                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 676                         p->adev->vce.filp[i] = p->filp;
 677                         p->adev->vce.img_size[i] = 0;
 678                         *allocated |= 1 << i;
 679                         return i;
 680                 }
 681         }
 682
 683         DRM_ERROR("No more free VCE handles!\n");
 684         return -EINVAL;
 685 }
 686
 687 /**
 688  * amdgpu_vce_cs_parse - parse and validate the command stream
 689  *
 690  * @p: parser context
 691  *
 692  */
 693 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 694 {
 695         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 696         unsigned fb_idx = 0, bs_idx = 0;
 697         int session_idx = -1;
 698         uint32_t destroyed = 0;
 699         uint32_t created = 0;
 700         uint32_t allocated = 0;
 701         uint32_t tmp, handle = 0;
 702         uint32_t *size = &tmp;
 703         unsigned idx;
 704         int i, r = 0;
 705
 706         p->job->vm = NULL;
 707         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 708
 709         for (idx = 0; idx < ib->length_dw;) {
 710                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 711                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 712
 713                 if ((len < 8) || (len & 3)) {
 714                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 715                         r = -EINVAL;
 716                         goto out;
 717                 }
 718
 719                 switch (cmd) {
 720                 case 0x00000002: /* task info */
 721                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 722                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 723                         break;
 724
 725                 case 0x03000001: /* encode */
 726                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
 727                                                    idx + 9, 0, 0);
 728                         if (r)
 729                                 goto out;
 730
 731                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
 732                                                    idx + 11, 0, 0);
 733                         if (r)
 734                                 goto out;
 735                         break;
 736
 737                 case 0x05000001: /* context buffer */
 738                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
 739                                                    idx + 2, 0, 0);
 740                         if (r)
 741                                 goto out;
 742                         break;
 743
 744                 case 0x05000004: /* video bitstream buffer */
 745                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 746                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 747                                                    tmp, bs_idx);
 748                         if (r)
 749                                 goto out;
 750                         break;
 751
 752                 case 0x05000005: /* feedback buffer */
 753                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
 754                                                    4096, fb_idx);
 755                         if (r)
 756                                 goto out;
 757                         break;
 758
 759                 case 0x0500000d: /* MV buffer */
 760                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
 761                                                         idx + 2, 0, 0);
 762                         if (r)
 763                                 goto out;
 764
 765                         r = amdgpu_vce_validate_bo(p, ib_idx, idx + 8,
 766                                                         idx + 7, 0, 0);
 767                         if (r)
 768                                 goto out;
 769                         break;
 770                 }
 771
 772                 idx += len / 4;
 773         }
 774
 775         for (idx = 0; idx < ib->length_dw;) {
 776                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 777                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 778
 779                 switch (cmd) {
 780                 case 0x00000001: /* session */
 781                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 782                         session_idx = amdgpu_vce_validate_handle(p, handle,
 783                                                                  &allocated);
 784                         if (session_idx < 0) {
 785                                 r = session_idx;
 786                                 goto out;
 787                         }
 788                         size = &p->adev->vce.img_size[session_idx];
 789                         break;
 790
 791                 case 0x00000002: /* task info */
 792                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 793                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 794                         break;
 795
 796                 case 0x01000001: /* create */
 797                         created |= 1 << session_idx;
 798                         if (destroyed & (1 << session_idx)) {
 799                                 destroyed &= ~(1 << session_idx);
 800                                 allocated |= 1 << session_idx;
 801
 802                         } else if (!(allocated & (1 << session_idx))) {
 803                                 DRM_ERROR("Handle already in use!\n");
 804                                 r = -EINVAL;
 805                                 goto out;
 806                         }
 807
 808                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 809                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 810                                 8 * 3 / 2;
 811                         break;
 812
 813                 case 0x04000001: /* config extension */
 814                 case 0x04000002: /* pic control */
 815                 case 0x04000005: /* rate control */
 816                 case 0x04000007: /* motion estimation */
 817                 case 0x04000008: /* rdo */
 818                 case 0x04000009: /* vui */
 819                 case 0x05000002: /* auxiliary buffer */
 820                 case 0x05000009: /* clock table */
 821                         break;
 822
 823                 case 0x0500000c: /* hw config */
 824                         switch (p->adev->asic_type) {
 825 #ifdef CONFIG_DRM_AMDGPU_CIK
 826                         case CHIP_KAVERI:
 827                         case CHIP_MULLINS:
 828 #endif
 829                         case CHIP_CARRIZO:
 830                                 break;
 831                         default:
 832                                 r = -EINVAL;
 833                                 goto out;
 834                         }
 835                         break;
 836
 837                 case 0x03000001: /* encode */
 838                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 839                                                 *size, 0);
 840                         if (r)
 841                                 goto out;
 842
 843                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 844                                                 *size / 3, 0);
 845                         if (r)
 846                                 goto out;
 847                         break;
 848
 849                 case 0x02000001: /* destroy */
 850                         destroyed |= 1 << session_idx;
 851                         break;
 852
 853                 case 0x05000001: /* context buffer */
 854                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 855                                                 *size * 2, 0);
 856                         if (r)
 857                                 goto out;
 858                         break;
 859
 860                 case 0x05000004: /* video bitstream buffer */
 861                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 862                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 863                                                 tmp, bs_idx);
 864                         if (r)
 865                                 goto out;
 866                         break;
 867
 868                 case 0x05000005: /* feedback buffer */
 869                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 870                                                 4096, fb_idx);
 871                         if (r)
 872                                 goto out;
 873                         break;
 874
 875                 case 0x0500000d: /* MV buffer */
 876                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3,
 877                                                         idx + 2, *size, 0);
 878                         if (r)
 879                                 goto out;
 880
 881                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 8,
 882                                                         idx + 7, *size / 12, 0);
 883                         if (r)
 884                                 goto out;
 885                         break;
 886
 887                 default:
 888                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 889                         r = -EINVAL;
 890                         goto out;
 891                 }
 892
 893                 if (session_idx == -1) {
 894                         DRM_ERROR("no session command at start of IB\n");
 895                         r = -EINVAL;
 896                         goto out;
 897                 }
 898
 899                 idx += len / 4;
 900         }
 901
 902         if (allocated & ~created) {
 903                 DRM_ERROR("New session without create command!\n");
 904                 r = -ENOENT;
 905         }
 906
 907 out:
 908         if (!r) {
 909                 /* No error, free all destroyed handle slots */
 910                 tmp = destroyed;
 911         } else {
 912                 /* Error during parsing, free all allocated handle slots */
 913                 tmp = allocated;
 914         }
 915
 916         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 917                 if (tmp & (1 << i))
 918                         atomic_set(&p->adev->vce.handles[i], 0);
 919
 920         return r;
 921 }
 922
 923 /**
 924  * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
 925  *
 926  * @p: parser context
 927  *
 928  */
 929 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 930 {
 931         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 932         int session_idx = -1;
 933         uint32_t destroyed = 0;
 934         uint32_t created = 0;
 935         uint32_t allocated = 0;
 936         uint32_t tmp, handle = 0;
 937         int i, r = 0, idx = 0;
 938
 939         while (idx < ib->length_dw) {
 940                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 941                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 942
 943                 if ((len < 8) || (len & 3)) {
 944                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 945                         r = -EINVAL;
 946                         goto out;
 947                 }
 948
 949                 switch (cmd) {
 950                 case 0x00000001: /* session */
 951                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 952                         session_idx = amdgpu_vce_validate_handle(p, handle,
 953                                                                  &allocated);
 954                         if (session_idx < 0) {
 955                                 r = session_idx;
 956                                 goto out;
 957                         }
 958                         break;
 959
 960                 case 0x01000001: /* create */
 961                         created |= 1 << session_idx;
 962                         if (destroyed & (1 << session_idx)) {
 963                                 destroyed &= ~(1 << session_idx);
 964                                 allocated |= 1 << session_idx;
 965
 966                         } else if (!(allocated & (1 << session_idx))) {
 967                                 DRM_ERROR("Handle already in use!\n");
 968                                 r = -EINVAL;
 969                                 goto out;
 970                         }
 971
 972                         break;
 973
 974                 case 0x02000001: /* destroy */
 975                         destroyed |= 1 << session_idx;
 976                         break;
 977
 978                 default:
 979                         break;
 980                 }
 981
 982                 if (session_idx == -1) {
 983                         DRM_ERROR("no session command at start of IB\n");
 984                         r = -EINVAL;
 985                         goto out;
 986                 }
 987
 988                 idx += len / 4;
 989         }
 990
 991         if (allocated & ~created) {
 992                 DRM_ERROR("New session without create command!\n");
 993                 r = -ENOENT;
 994         }
 995
 996 out:
 997         if (!r) {
 998                 /* No error, free all destroyed handle slots */
 999                 tmp = destroyed;
1000                 amdgpu_ib_free(p->adev, ib, NULL);
1001         } else {
1002                 /* Error during parsing, free all allocated handle slots */
1003                 tmp = allocated;
1004         }
1005
1006         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
1007                 if (tmp & (1 << i))
1008                         atomic_set(&p->adev->vce.handles[i], 0);
1009
1010         return r;
1011 }
1012
1013 /**
1014  * amdgpu_vce_ring_emit_ib - execute indirect buffer
1015  *
1016  * @ring: engine to use
1017  * @ib: the IB to execute
1018  *
1019  */
1020 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring,
1021                                 struct amdgpu_job *job,
1022                                 struct amdgpu_ib *ib,
1023                                 bool ctx_switch)
1024 {
1025         amdgpu_ring_write(ring, VCE_CMD_IB);
1026         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1027         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1028         amdgpu_ring_write(ring, ib->length_dw);
1029 }
1030
1031 /**
1032  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
1033  *
1034  * @ring: engine to use
1035  * @fence: the fence
1036  *
1037  */
1038 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1039                                 unsigned flags)
1040 {
1041         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1042
1043         amdgpu_ring_write(ring, VCE_CMD_FENCE);
1044         amdgpu_ring_write(ring, addr);
1045         amdgpu_ring_write(ring, upper_32_bits(addr));
1046         amdgpu_ring_write(ring, seq);
1047         amdgpu_ring_write(ring, VCE_CMD_TRAP);
1048         amdgpu_ring_write(ring, VCE_CMD_END);
1049 }
1050
1051 /**
1052  * amdgpu_vce_ring_test_ring - test if VCE ring is working
1053  *
1054  * @ring: the engine to test on
1055  *
1056  */
1057 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
1058 {
1059         struct amdgpu_device *adev = ring->adev;
1060         uint32_t rptr = amdgpu_ring_get_rptr(ring);
1061         unsigned i;
1062         int r, timeout = adev->usec_timeout;
1063
1064         /* skip ring test for sriov*/
1065         if (amdgpu_sriov_vf(adev))
1066                 return 0;
1067
1068         r = amdgpu_ring_alloc(ring, 16);
1069         if (r)
1070                 return r;
1071
1072         amdgpu_ring_write(ring, VCE_CMD_END);
1073         amdgpu_ring_commit(ring);
1074
1075         for (i = 0; i < timeout; i++) {
1076                 if (amdgpu_ring_get_rptr(ring) != rptr)
1077                         break;
1078                 DRM_UDELAY(1);
1079         }
1080
1081         if (i >= timeout)
1082                 r = -ETIMEDOUT;
1083
1084         return r;
1085 }
1086
1087 /**
1088  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
1089  *
1090  * @ring: the engine to test on
1091  *
1092  */
1093 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1094 {
1095         struct dma_fence *fence = NULL;
1096         long r;
1097
1098         /* skip vce ring1/2 ib test for now, since it's not reliable */
1099         if (ring != &ring->adev->vce.ring[0])
1100                 return 0;
1101
1102         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
1103         if (r)
1104                 goto error;
1105
1106         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
1107         if (r)
1108                 goto error;
1109
1110         r = dma_fence_wait_timeout(fence, false, timeout);
1111         if (r == 0)
1112                 r = -ETIMEDOUT;
1113         else if (r > 0)
1114                 r = 0;
1115
1116 error:
1117         dma_fence_put(fence);
1118         return r;
1119 }