2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <linux/file.h>
29 #include <linux/pagemap.h>
30 #include <linux/sync_file.h>
32 #include <drm/amdgpu_drm.h>
33 #include <drm/drm_syncobj.h>
35 #include "amdgpu_trace.h"
36 #include "amdgpu_gmc.h"
37 #include "amdgpu_gem.h"
39 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
40 struct drm_amdgpu_cs_chunk_fence *data,
43 struct drm_gem_object *gobj;
48 gobj = drm_gem_object_lookup(p->filp, data->handle);
52 bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
53 p->uf_entry.priority = 0;
54 p->uf_entry.tv.bo = &bo->tbo;
55 /* One for TTM and one for the CS job */
56 p->uf_entry.tv.num_shared = 2;
58 drm_gem_object_put_unlocked(gobj);
60 size = amdgpu_bo_size(bo);
61 if (size != PAGE_SIZE || (data->offset + 8) > size) {
66 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
71 *offset = data->offset;
80 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
81 struct drm_amdgpu_bo_list_in *data)
84 struct drm_amdgpu_bo_list_entry *info = NULL;
86 r = amdgpu_bo_create_list_entry_array(data, &info);
90 r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
105 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
107 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
108 struct amdgpu_vm *vm = &fpriv->vm;
109 uint64_t *chunk_array_user;
110 uint64_t *chunk_array;
111 unsigned size, num_ibs = 0;
112 uint32_t uf_offset = 0;
116 if (cs->in.num_chunks == 0)
119 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
123 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
129 mutex_lock(&p->ctx->lock);
131 /* skip guilty context job */
132 if (atomic_read(&p->ctx->guilty) == 1) {
138 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
139 if (copy_from_user(chunk_array, chunk_array_user,
140 sizeof(uint64_t)*cs->in.num_chunks)) {
145 p->nchunks = cs->in.num_chunks;
146 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
153 for (i = 0; i < p->nchunks; i++) {
154 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
155 struct drm_amdgpu_cs_chunk user_chunk;
156 uint32_t __user *cdata;
158 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
159 if (copy_from_user(&user_chunk, chunk_ptr,
160 sizeof(struct drm_amdgpu_cs_chunk))) {
163 goto free_partial_kdata;
165 p->chunks[i].chunk_id = user_chunk.chunk_id;
166 p->chunks[i].length_dw = user_chunk.length_dw;
168 size = p->chunks[i].length_dw;
169 cdata = u64_to_user_ptr(user_chunk.chunk_data);
171 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
172 if (p->chunks[i].kdata == NULL) {
175 goto free_partial_kdata;
177 size *= sizeof(uint32_t);
178 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
180 goto free_partial_kdata;
183 switch (p->chunks[i].chunk_id) {
184 case AMDGPU_CHUNK_ID_IB:
188 case AMDGPU_CHUNK_ID_FENCE:
189 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
190 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
192 goto free_partial_kdata;
195 ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
198 goto free_partial_kdata;
202 case AMDGPU_CHUNK_ID_BO_HANDLES:
203 size = sizeof(struct drm_amdgpu_bo_list_in);
204 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
206 goto free_partial_kdata;
209 ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
211 goto free_partial_kdata;
215 case AMDGPU_CHUNK_ID_DEPENDENCIES:
216 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
217 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
218 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
219 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
220 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
225 goto free_partial_kdata;
229 ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
233 if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
238 if (p->uf_entry.tv.bo)
239 p->job->uf_addr = uf_offset;
242 /* Use this opportunity to fill in task info for the vm */
243 amdgpu_vm_set_task_info(vm);
251 kvfree(p->chunks[i].kdata);
261 /* Convert microseconds to bytes. */
262 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
264 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
267 /* Since accum_us is incremented by a million per second, just
268 * multiply it by the number of MB/s to get the number of bytes.
270 return us << adev->mm_stats.log2_max_MBps;
273 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
275 if (!adev->mm_stats.log2_max_MBps)
278 return bytes >> adev->mm_stats.log2_max_MBps;
281 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
282 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
283 * which means it can go over the threshold once. If that happens, the driver
284 * will be in debt and no other buffer migrations can be done until that debt
287 * This approach allows moving a buffer of any size (it's important to allow
290 * The currency is simply time in microseconds and it increases as the clock
291 * ticks. The accumulated microseconds (us) are converted to bytes and
294 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
298 s64 time_us, increment_us;
299 u64 free_vram, total_vram, used_vram;
301 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
304 * It means that in order to get full max MBps, at least 5 IBs per
305 * second must be submitted and not more than 200ms apart from each
308 const s64 us_upper_bound = 200000;
310 if (!adev->mm_stats.log2_max_MBps) {
316 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
317 used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
318 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
320 spin_lock(&adev->mm_stats.lock);
322 /* Increase the amount of accumulated us. */
323 time_us = ktime_to_us(ktime_get());
324 increment_us = time_us - adev->mm_stats.last_update_us;
325 adev->mm_stats.last_update_us = time_us;
326 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
329 /* This prevents the short period of low performance when the VRAM
330 * usage is low and the driver is in debt or doesn't have enough
331 * accumulated us to fill VRAM quickly.
333 * The situation can occur in these cases:
334 * - a lot of VRAM is freed by userspace
335 * - the presence of a big buffer causes a lot of evictions
336 * (solution: split buffers into smaller ones)
338 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
339 * accum_us to a positive number.
341 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
344 /* Be more aggresive on dGPUs. Try to fill a portion of free
347 if (!(adev->flags & AMD_IS_APU))
348 min_us = bytes_to_us(adev, free_vram / 4);
350 min_us = 0; /* Reset accum_us on APUs. */
352 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
355 /* This is set to 0 if the driver is in debt to disallow (optional)
358 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
360 /* Do the same for visible VRAM if half of it is free */
361 if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
362 u64 total_vis_vram = adev->gmc.visible_vram_size;
364 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
366 if (used_vis_vram < total_vis_vram) {
367 u64 free_vis_vram = total_vis_vram - used_vis_vram;
368 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
369 increment_us, us_upper_bound);
371 if (free_vis_vram >= total_vis_vram / 2)
372 adev->mm_stats.accum_us_vis =
373 max(bytes_to_us(adev, free_vis_vram / 2),
374 adev->mm_stats.accum_us_vis);
377 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
382 spin_unlock(&adev->mm_stats.lock);
385 /* Report how many bytes have really been moved for the last command
386 * submission. This can result in a debt that can stop buffer migrations
389 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
392 spin_lock(&adev->mm_stats.lock);
393 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
394 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
395 spin_unlock(&adev->mm_stats.lock);
398 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
399 struct amdgpu_bo *bo)
401 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
402 struct ttm_operation_ctx ctx = {
403 .interruptible = true,
404 .no_wait_gpu = false,
405 .resv = bo->tbo.base.resv,
414 /* Don't move this buffer if we have depleted our allowance
415 * to move it. Don't move anything if the threshold is zero.
417 if (p->bytes_moved < p->bytes_moved_threshold) {
418 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
419 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
420 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
421 * visible VRAM if we've depleted our allowance to do
424 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
425 domain = bo->preferred_domains;
427 domain = bo->allowed_domains;
429 domain = bo->preferred_domains;
432 domain = bo->allowed_domains;
436 amdgpu_bo_placement_from_domain(bo, domain);
437 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
439 p->bytes_moved += ctx.bytes_moved;
440 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
441 amdgpu_bo_in_cpu_visible_vram(bo))
442 p->bytes_moved_vis += ctx.bytes_moved;
444 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
445 domain = bo->allowed_domains;
452 /* Last resort, try to evict something from the current working set */
453 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
454 struct amdgpu_bo *validated)
456 uint32_t domain = validated->allowed_domains;
457 struct ttm_operation_ctx ctx = { true, false };
463 for (;&p->evictable->tv.head != &p->validated;
464 p->evictable = list_prev_entry(p->evictable, tv.head)) {
466 struct amdgpu_bo_list_entry *candidate = p->evictable;
467 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(candidate->tv.bo);
468 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
469 bool update_bytes_moved_vis;
472 /* If we reached our current BO we can forget it */
476 /* We can't move pinned BOs here */
480 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
482 /* Check if this BO is in one of the domains we need space for */
483 if (!(other & domain))
486 /* Check if we can move this BO somewhere else */
487 other = bo->allowed_domains & ~domain;
491 /* Good we can try to move this BO somewhere else */
492 update_bytes_moved_vis =
493 !amdgpu_gmc_vram_full_visible(&adev->gmc) &&
494 amdgpu_bo_in_cpu_visible_vram(bo);
495 amdgpu_bo_placement_from_domain(bo, other);
496 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
497 p->bytes_moved += ctx.bytes_moved;
498 if (update_bytes_moved_vis)
499 p->bytes_moved_vis += ctx.bytes_moved;
504 p->evictable = list_prev_entry(p->evictable, tv.head);
505 list_move(&candidate->tv.head, &p->validated);
513 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
515 struct amdgpu_cs_parser *p = param;
519 r = amdgpu_cs_bo_validate(p, bo);
520 } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
525 r = amdgpu_cs_bo_validate(p, bo->shadow);
530 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
531 struct list_head *validated)
533 struct ttm_operation_ctx ctx = { true, false };
534 struct amdgpu_bo_list_entry *lobj;
537 list_for_each_entry(lobj, validated, tv.head) {
538 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
539 struct mm_struct *usermm;
541 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
542 if (usermm && usermm != current->mm)
545 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
546 lobj->user_invalidated && lobj->user_pages) {
547 amdgpu_bo_placement_from_domain(bo,
548 AMDGPU_GEM_DOMAIN_CPU);
549 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
553 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
557 if (p->evictable == lobj)
560 r = amdgpu_cs_validate(p, bo);
564 kvfree(lobj->user_pages);
565 lobj->user_pages = NULL;
570 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
571 union drm_amdgpu_cs *cs)
573 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
574 struct amdgpu_vm *vm = &fpriv->vm;
575 struct amdgpu_bo_list_entry *e;
576 struct list_head duplicates;
577 struct amdgpu_bo *gds;
578 struct amdgpu_bo *gws;
579 struct amdgpu_bo *oa;
582 INIT_LIST_HEAD(&p->validated);
584 /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
585 if (cs->in.bo_list_handle) {
589 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
593 } else if (!p->bo_list) {
594 /* Create a empty bo_list when no handle is provided */
595 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
601 /* One for TTM and one for the CS job */
602 amdgpu_bo_list_for_each_entry(e, p->bo_list)
603 e->tv.num_shared = 2;
605 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
606 if (p->bo_list->first_userptr != p->bo_list->num_entries)
607 p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
609 INIT_LIST_HEAD(&duplicates);
610 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
612 if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
613 list_add(&p->uf_entry.tv.head, &p->validated);
615 /* Get userptr backing pages. If pages are updated after registered
616 * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
617 * amdgpu_ttm_backend_bind() to flush and invalidate new pages
619 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
620 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
621 bool userpage_invalidated = false;
624 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
625 sizeof(struct page *),
626 GFP_KERNEL | __GFP_ZERO);
627 if (!e->user_pages) {
628 DRM_ERROR("calloc failure\n");
632 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
634 kvfree(e->user_pages);
635 e->user_pages = NULL;
639 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
640 if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
641 userpage_invalidated = true;
645 e->user_invalidated = userpage_invalidated;
648 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
650 if (unlikely(r != 0)) {
651 if (r != -ERESTARTSYS)
652 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
656 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
657 &p->bytes_moved_vis_threshold);
659 p->bytes_moved_vis = 0;
660 p->evictable = list_last_entry(&p->validated,
661 struct amdgpu_bo_list_entry,
664 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
665 amdgpu_cs_validate, p);
667 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
671 r = amdgpu_cs_list_validate(p, &duplicates);
675 r = amdgpu_cs_list_validate(p, &p->validated);
679 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
682 gds = p->bo_list->gds_obj;
683 gws = p->bo_list->gws_obj;
684 oa = p->bo_list->oa_obj;
686 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
687 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
689 /* Make sure we use the exclusive slot for shared BOs */
690 if (bo->prime_shared_count)
691 e->tv.num_shared = 0;
692 e->bo_va = amdgpu_vm_bo_find(vm, bo);
696 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
697 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
700 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
701 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
704 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
705 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
708 if (!r && p->uf_entry.tv.bo) {
709 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
711 r = amdgpu_ttm_alloc_gart(&uf->tbo);
712 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
717 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
722 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
724 struct amdgpu_bo_list_entry *e;
727 list_for_each_entry(e, &p->validated, tv.head) {
728 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
729 struct dma_resv *resv = bo->tbo.base.resv;
731 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
732 amdgpu_bo_explicit_sync(bo));
741 * cs_parser_fini() - clean parser states
742 * @parser: parser structure holding parsing context.
743 * @error: error number
745 * If error is set than unvalidate buffer, otherwise just free memory
746 * used by parsing context.
748 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
753 if (error && backoff)
754 ttm_eu_backoff_reservation(&parser->ticket,
757 for (i = 0; i < parser->num_post_deps; i++) {
758 drm_syncobj_put(parser->post_deps[i].syncobj);
759 kfree(parser->post_deps[i].chain);
761 kfree(parser->post_deps);
763 dma_fence_put(parser->fence);
766 mutex_unlock(&parser->ctx->lock);
767 amdgpu_ctx_put(parser->ctx);
770 amdgpu_bo_list_put(parser->bo_list);
772 for (i = 0; i < parser->nchunks; i++)
773 kvfree(parser->chunks[i].kdata);
774 kfree(parser->chunks);
776 amdgpu_job_free(parser->job);
777 if (parser->uf_entry.tv.bo) {
778 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
780 amdgpu_bo_unref(&uf);
784 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
786 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
787 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
788 struct amdgpu_device *adev = p->adev;
789 struct amdgpu_vm *vm = &fpriv->vm;
790 struct amdgpu_bo_list_entry *e;
791 struct amdgpu_bo_va *bo_va;
792 struct amdgpu_bo *bo;
795 /* Only for UVD/VCE VM emulation */
796 if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
799 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
800 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
801 struct amdgpu_bo_va_mapping *m;
802 struct amdgpu_bo *aobj = NULL;
803 struct amdgpu_cs_chunk *chunk;
804 uint64_t offset, va_start;
805 struct amdgpu_ib *ib;
808 chunk = &p->chunks[i];
809 ib = &p->job->ibs[j];
810 chunk_ib = chunk->kdata;
812 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
815 va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
816 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
818 DRM_ERROR("IB va_start is invalid\n");
822 if ((va_start + chunk_ib->ib_bytes) >
823 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
824 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
828 /* the IB should be reserved at this point */
829 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
834 offset = m->start * AMDGPU_GPU_PAGE_SIZE;
835 kptr += va_start - offset;
837 if (ring->funcs->parse_cs) {
838 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
839 amdgpu_bo_kunmap(aobj);
841 r = amdgpu_ring_parse_cs(ring, p, j);
845 ib->ptr = (uint32_t *)kptr;
846 r = amdgpu_ring_patch_cs_in_place(ring, p, j);
847 amdgpu_bo_kunmap(aobj);
857 return amdgpu_cs_sync_rings(p);
860 r = amdgpu_vm_clear_freed(adev, vm, NULL);
864 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
868 r = amdgpu_sync_fence(adev, &p->job->sync,
869 fpriv->prt_va->last_pt_update, false);
873 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
876 bo_va = fpriv->csa_va;
878 r = amdgpu_vm_bo_update(adev, bo_va, false);
882 f = bo_va->last_pt_update;
883 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
888 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
891 /* ignore duplicates */
892 bo = ttm_to_amdgpu_bo(e->tv.bo);
900 r = amdgpu_vm_bo_update(adev, bo_va, false);
904 f = bo_va->last_pt_update;
905 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
910 r = amdgpu_vm_handle_moved(adev, vm);
914 r = amdgpu_vm_update_directories(adev, vm);
918 r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
922 p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
924 if (amdgpu_vm_debug) {
925 /* Invalidate all BOs to test for userspace bugs */
926 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
927 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
929 /* ignore duplicates */
933 amdgpu_vm_bo_invalidate(adev, bo, false);
937 return amdgpu_cs_sync_rings(p);
940 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
941 struct amdgpu_cs_parser *parser)
943 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
944 struct amdgpu_vm *vm = &fpriv->vm;
945 int r, ce_preempt = 0, de_preempt = 0;
946 struct amdgpu_ring *ring;
949 for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
950 struct amdgpu_cs_chunk *chunk;
951 struct amdgpu_ib *ib;
952 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
953 struct drm_sched_entity *entity;
955 chunk = &parser->chunks[i];
956 ib = &parser->job->ibs[j];
957 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
959 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
962 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
963 (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
964 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
965 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
971 /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
972 if (ce_preempt > 1 || de_preempt > 1)
976 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
977 chunk_ib->ip_instance, chunk_ib->ring,
982 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
983 parser->job->preamble_status |=
984 AMDGPU_PREAMBLE_IB_PRESENT;
986 if (parser->entity && parser->entity != entity)
989 parser->entity = entity;
991 ring = to_amdgpu_ring(entity->rq->sched);
992 r = amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
993 chunk_ib->ib_bytes : 0, ib);
995 DRM_ERROR("Failed to get ib !\n");
999 ib->gpu_addr = chunk_ib->va_start;
1000 ib->length_dw = chunk_ib->ib_bytes / 4;
1001 ib->flags = chunk_ib->flags;
1006 /* MM engine doesn't support user fences */
1007 ring = to_amdgpu_ring(parser->entity->rq->sched);
1008 if (parser->job->uf_addr && ring->funcs->no_user_fence)
1011 return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
1014 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1015 struct amdgpu_cs_chunk *chunk)
1017 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1020 struct drm_amdgpu_cs_chunk_dep *deps;
1022 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1023 num_deps = chunk->length_dw * 4 /
1024 sizeof(struct drm_amdgpu_cs_chunk_dep);
1026 for (i = 0; i < num_deps; ++i) {
1027 struct amdgpu_ctx *ctx;
1028 struct drm_sched_entity *entity;
1029 struct dma_fence *fence;
1031 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1035 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
1036 deps[i].ip_instance,
1037 deps[i].ring, &entity);
1039 amdgpu_ctx_put(ctx);
1043 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
1044 amdgpu_ctx_put(ctx);
1047 return PTR_ERR(fence);
1051 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
1052 struct drm_sched_fence *s_fence;
1053 struct dma_fence *old = fence;
1055 s_fence = to_drm_sched_fence(fence);
1056 fence = dma_fence_get(&s_fence->scheduled);
1060 r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1061 dma_fence_put(fence);
1068 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1069 uint32_t handle, u64 point,
1072 struct dma_fence *fence;
1075 r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
1077 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1082 r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1083 dma_fence_put(fence);
1088 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1089 struct amdgpu_cs_chunk *chunk)
1091 struct drm_amdgpu_cs_chunk_sem *deps;
1095 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1096 num_deps = chunk->length_dw * 4 /
1097 sizeof(struct drm_amdgpu_cs_chunk_sem);
1098 for (i = 0; i < num_deps; ++i) {
1099 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1109 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1110 struct amdgpu_cs_chunk *chunk)
1112 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1116 syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1117 num_deps = chunk->length_dw * 4 /
1118 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1119 for (i = 0; i < num_deps; ++i) {
1120 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1121 syncobj_deps[i].handle,
1122 syncobj_deps[i].point,
1123 syncobj_deps[i].flags);
1131 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1132 struct amdgpu_cs_chunk *chunk)
1134 struct drm_amdgpu_cs_chunk_sem *deps;
1138 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1139 num_deps = chunk->length_dw * 4 /
1140 sizeof(struct drm_amdgpu_cs_chunk_sem);
1145 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1147 p->num_post_deps = 0;
1153 for (i = 0; i < num_deps; ++i) {
1154 p->post_deps[i].syncobj =
1155 drm_syncobj_find(p->filp, deps[i].handle);
1156 if (!p->post_deps[i].syncobj)
1158 p->post_deps[i].chain = NULL;
1159 p->post_deps[i].point = 0;
1167 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1168 struct amdgpu_cs_chunk *chunk)
1170 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1174 syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1175 num_deps = chunk->length_dw * 4 /
1176 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1181 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1183 p->num_post_deps = 0;
1188 for (i = 0; i < num_deps; ++i) {
1189 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1192 if (syncobj_deps[i].point) {
1193 dep->chain = kmalloc(sizeof(*dep->chain), GFP_KERNEL);
1198 dep->syncobj = drm_syncobj_find(p->filp,
1199 syncobj_deps[i].handle);
1200 if (!dep->syncobj) {
1204 dep->point = syncobj_deps[i].point;
1211 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1212 struct amdgpu_cs_parser *p)
1216 for (i = 0; i < p->nchunks; ++i) {
1217 struct amdgpu_cs_chunk *chunk;
1219 chunk = &p->chunks[i];
1221 switch (chunk->chunk_id) {
1222 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1223 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1224 r = amdgpu_cs_process_fence_dep(p, chunk);
1228 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1229 r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1233 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1234 r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1238 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1239 r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1243 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1244 r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1254 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1258 for (i = 0; i < p->num_post_deps; ++i) {
1259 if (p->post_deps[i].chain && p->post_deps[i].point) {
1260 drm_syncobj_add_point(p->post_deps[i].syncobj,
1261 p->post_deps[i].chain,
1262 p->fence, p->post_deps[i].point);
1263 p->post_deps[i].chain = NULL;
1265 drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1271 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1272 union drm_amdgpu_cs *cs)
1274 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1275 struct drm_sched_entity *entity = p->entity;
1276 enum drm_sched_priority priority;
1277 struct amdgpu_ring *ring;
1278 struct amdgpu_bo_list_entry *e;
1279 struct amdgpu_job *job;
1286 r = drm_sched_job_init(&job->base, entity, p->filp);
1290 /* No memory allocation is allowed while holding the mn lock.
1291 * p->mn is hold until amdgpu_cs_submit is finished and fence is added
1294 amdgpu_mn_lock(p->mn);
1296 /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1297 * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1299 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1300 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1302 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1309 job->owner = p->filp;
1310 p->fence = dma_fence_get(&job->base.s_fence->finished);
1312 amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1313 amdgpu_cs_post_dependencies(p);
1315 if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1316 !p->ctx->preamble_presented) {
1317 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1318 p->ctx->preamble_presented = true;
1321 cs->out.handle = seq;
1322 job->uf_sequence = seq;
1324 amdgpu_job_free_resources(job);
1326 trace_amdgpu_cs_ioctl(job);
1327 amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1328 priority = job->base.s_priority;
1329 drm_sched_entity_push_job(&job->base, entity);
1331 ring = to_amdgpu_ring(entity->rq->sched);
1332 amdgpu_ring_priority_get(ring, priority);
1334 amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1336 ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1337 amdgpu_mn_unlock(p->mn);
1342 drm_sched_job_cleanup(&job->base);
1343 amdgpu_mn_unlock(p->mn);
1346 amdgpu_job_free(job);
1350 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1352 struct amdgpu_device *adev = dev->dev_private;
1353 union drm_amdgpu_cs *cs = data;
1354 struct amdgpu_cs_parser parser = {};
1355 bool reserved_buffers = false;
1358 if (!adev->accel_working)
1364 r = amdgpu_cs_parser_init(&parser, data);
1366 DRM_ERROR("Failed to initialize parser %d!\n", r);
1370 r = amdgpu_cs_ib_fill(adev, &parser);
1374 r = amdgpu_cs_dependencies(adev, &parser);
1376 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1380 r = amdgpu_cs_parser_bos(&parser, data);
1383 DRM_ERROR("Not enough memory for command submission!\n");
1384 else if (r != -ERESTARTSYS && r != -EAGAIN)
1385 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1389 reserved_buffers = true;
1391 for (i = 0; i < parser.job->num_ibs; i++)
1392 trace_amdgpu_cs(&parser, i);
1394 r = amdgpu_cs_vm_handling(&parser);
1398 r = amdgpu_cs_submit(&parser, cs);
1401 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1407 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1410 * @data: data from userspace
1411 * @filp: file private
1413 * Wait for the command submission identified by handle to finish.
1415 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1416 struct drm_file *filp)
1418 union drm_amdgpu_wait_cs *wait = data;
1419 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1420 struct drm_sched_entity *entity;
1421 struct amdgpu_ctx *ctx;
1422 struct dma_fence *fence;
1425 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1429 r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1430 wait->in.ring, &entity);
1432 amdgpu_ctx_put(ctx);
1436 fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1440 r = dma_fence_wait_timeout(fence, true, timeout);
1441 if (r > 0 && fence->error)
1443 dma_fence_put(fence);
1447 amdgpu_ctx_put(ctx);
1451 memset(wait, 0, sizeof(*wait));
1452 wait->out.status = (r == 0);
1458 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1460 * @adev: amdgpu device
1461 * @filp: file private
1462 * @user: drm_amdgpu_fence copied from user space
1464 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1465 struct drm_file *filp,
1466 struct drm_amdgpu_fence *user)
1468 struct drm_sched_entity *entity;
1469 struct amdgpu_ctx *ctx;
1470 struct dma_fence *fence;
1473 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1475 return ERR_PTR(-EINVAL);
1477 r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1478 user->ring, &entity);
1480 amdgpu_ctx_put(ctx);
1484 fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1485 amdgpu_ctx_put(ctx);
1490 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1491 struct drm_file *filp)
1493 struct amdgpu_device *adev = dev->dev_private;
1494 union drm_amdgpu_fence_to_handle *info = data;
1495 struct dma_fence *fence;
1496 struct drm_syncobj *syncobj;
1497 struct sync_file *sync_file;
1500 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1502 return PTR_ERR(fence);
1505 fence = dma_fence_get_stub();
1507 switch (info->in.what) {
1508 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1509 r = drm_syncobj_create(&syncobj, 0, fence);
1510 dma_fence_put(fence);
1513 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1514 drm_syncobj_put(syncobj);
1517 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1518 r = drm_syncobj_create(&syncobj, 0, fence);
1519 dma_fence_put(fence);
1522 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1523 drm_syncobj_put(syncobj);
1526 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1527 fd = get_unused_fd_flags(O_CLOEXEC);
1529 dma_fence_put(fence);
1533 sync_file = sync_file_create(fence);
1534 dma_fence_put(fence);
1540 fd_install(fd, sync_file->file);
1541 info->out.handle = fd;
1550 * amdgpu_cs_wait_all_fence - wait on all fences to signal
1552 * @adev: amdgpu device
1553 * @filp: file private
1554 * @wait: wait parameters
1555 * @fences: array of drm_amdgpu_fence
1557 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1558 struct drm_file *filp,
1559 union drm_amdgpu_wait_fences *wait,
1560 struct drm_amdgpu_fence *fences)
1562 uint32_t fence_count = wait->in.fence_count;
1566 for (i = 0; i < fence_count; i++) {
1567 struct dma_fence *fence;
1568 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1570 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1572 return PTR_ERR(fence);
1576 r = dma_fence_wait_timeout(fence, true, timeout);
1577 dma_fence_put(fence);
1585 return fence->error;
1588 memset(wait, 0, sizeof(*wait));
1589 wait->out.status = (r > 0);
1595 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1597 * @adev: amdgpu device
1598 * @filp: file private
1599 * @wait: wait parameters
1600 * @fences: array of drm_amdgpu_fence
1602 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1603 struct drm_file *filp,
1604 union drm_amdgpu_wait_fences *wait,
1605 struct drm_amdgpu_fence *fences)
1607 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1608 uint32_t fence_count = wait->in.fence_count;
1609 uint32_t first = ~0;
1610 struct dma_fence **array;
1614 /* Prepare the fence array */
1615 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1620 for (i = 0; i < fence_count; i++) {
1621 struct dma_fence *fence;
1623 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1624 if (IS_ERR(fence)) {
1626 goto err_free_fence_array;
1629 } else { /* NULL, the fence has been already signaled */
1636 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1639 goto err_free_fence_array;
1642 memset(wait, 0, sizeof(*wait));
1643 wait->out.status = (r > 0);
1644 wait->out.first_signaled = first;
1646 if (first < fence_count && array[first])
1647 r = array[first]->error;
1651 err_free_fence_array:
1652 for (i = 0; i < fence_count; i++)
1653 dma_fence_put(array[i]);
1660 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1663 * @data: data from userspace
1664 * @filp: file private
1666 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1667 struct drm_file *filp)
1669 struct amdgpu_device *adev = dev->dev_private;
1670 union drm_amdgpu_wait_fences *wait = data;
1671 uint32_t fence_count = wait->in.fence_count;
1672 struct drm_amdgpu_fence *fences_user;
1673 struct drm_amdgpu_fence *fences;
1676 /* Get the fences from userspace */
1677 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1682 fences_user = u64_to_user_ptr(wait->in.fences);
1683 if (copy_from_user(fences, fences_user,
1684 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1686 goto err_free_fences;
1689 if (wait->in.wait_all)
1690 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1692 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1701 * amdgpu_cs_find_bo_va - find bo_va for VM address
1703 * @parser: command submission parser context
1705 * @bo: resulting BO of the mapping found
1707 * Search the buffer objects in the command submission context for a certain
1708 * virtual memory address. Returns allocation structure when found, NULL
1711 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1712 uint64_t addr, struct amdgpu_bo **bo,
1713 struct amdgpu_bo_va_mapping **map)
1715 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1716 struct ttm_operation_ctx ctx = { false, false };
1717 struct amdgpu_vm *vm = &fpriv->vm;
1718 struct amdgpu_bo_va_mapping *mapping;
1721 addr /= AMDGPU_GPU_PAGE_SIZE;
1723 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1724 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1727 *bo = mapping->bo_va->base.bo;
1730 /* Double check that the BO is reserved by this CS */
1731 if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1734 if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1735 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1736 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1737 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1742 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);