2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/driver.h>
35 #include <linux/module.h>
40 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
41 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
42 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
43 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
44 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
45 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
46 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
47 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
49 #define GPIO_INT_FALL_EDGE 0x0
50 #define GPIO_INT_LOW_LEV 0x1
51 #define GPIO_INT_RISE_EDGE 0x2
52 #define GPIO_INT_HIGH_LEV 0x3
53 #define GPIO_INT_LEV_MASK (1 << 0)
54 #define GPIO_INT_POL_MASK (1 << 1)
61 struct mxs_gpio_port {
65 struct irq_domain *domain;
68 enum mxs_gpio_id devid;
72 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
74 return port->devid == IMX23_GPIO;
77 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
79 return port->devid == IMX28_GPIO;
82 /* Note: This driver assumes 32 GPIOs are handled in one register */
84 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
87 u32 pin_mask = 1 << d->hwirq;
88 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
89 struct irq_chip_type *ct = irq_data_get_chip_type(d);
90 struct mxs_gpio_port *port = gc->private;
91 void __iomem *pin_addr;
94 if (!(ct->type & type))
95 if (irq_setup_alt_chip(d, type))
98 port->both_edges &= ~pin_mask;
100 case IRQ_TYPE_EDGE_BOTH:
101 val = port->gc.get(&port->gc, d->hwirq);
103 edge = GPIO_INT_FALL_EDGE;
105 edge = GPIO_INT_RISE_EDGE;
106 port->both_edges |= pin_mask;
108 case IRQ_TYPE_EDGE_RISING:
109 edge = GPIO_INT_RISE_EDGE;
111 case IRQ_TYPE_EDGE_FALLING:
112 edge = GPIO_INT_FALL_EDGE;
114 case IRQ_TYPE_LEVEL_LOW:
115 edge = GPIO_INT_LOW_LEV;
117 case IRQ_TYPE_LEVEL_HIGH:
118 edge = GPIO_INT_HIGH_LEV;
124 /* set level or edge */
125 pin_addr = port->base + PINCTRL_IRQLEV(port);
126 if (edge & GPIO_INT_LEV_MASK) {
127 writel(pin_mask, pin_addr + MXS_SET);
128 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
130 writel(pin_mask, pin_addr + MXS_CLR);
131 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
135 pin_addr = port->base + PINCTRL_IRQPOL(port);
136 if (edge & GPIO_INT_POL_MASK)
137 writel(pin_mask, pin_addr + MXS_SET);
139 writel(pin_mask, pin_addr + MXS_CLR);
142 port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
147 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
150 void __iomem *pin_addr;
154 pin_addr = port->base + PINCTRL_IRQPOL(port);
155 val = readl(pin_addr);
159 writel(bit, pin_addr + MXS_CLR);
161 writel(bit, pin_addr + MXS_SET);
164 /* MXS has one interrupt *per* gpio port */
165 static void mxs_gpio_irq_handler(struct irq_desc *desc)
168 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
170 desc->irq_data.chip->irq_ack(&desc->irq_data);
172 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
173 readl(port->base + PINCTRL_IRQEN(port));
175 while (irq_stat != 0) {
176 int irqoffset = fls(irq_stat) - 1;
177 if (port->both_edges & (1 << irqoffset))
178 mxs_flip_edge(port, irqoffset);
180 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
181 irq_stat &= ~(1 << irqoffset);
186 * Set interrupt number "irq" in the GPIO as a wake-up source.
187 * While system is running, all registered GPIO interrupts need to have
188 * wake-up enabled. When system is suspended, only selected GPIO interrupts
189 * need to have wake-up enabled.
190 * @param irq interrupt source number
191 * @param enable enable as wake-up if equal to non-zero
192 * @return This function returns 0 on success.
194 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
196 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
197 struct mxs_gpio_port *port = gc->private;
200 enable_irq_wake(port->irq);
202 disable_irq_wake(port->irq);
207 static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
209 struct irq_chip_generic *gc;
210 struct irq_chip_type *ct;
213 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
214 port->base, handle_level_irq);
220 ct = &gc->chip_types[0];
221 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
222 ct->chip.irq_ack = irq_gc_ack_set_bit;
223 ct->chip.irq_mask = irq_gc_mask_disable_reg;
224 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
225 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
226 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
227 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
228 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
229 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
230 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
232 ct = &gc->chip_types[1];
233 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
234 ct->chip.irq_ack = irq_gc_ack_set_bit;
235 ct->chip.irq_mask = irq_gc_mask_disable_reg;
236 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
237 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
238 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
239 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
240 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
241 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
242 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
243 ct->handler = handle_level_irq;
245 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
246 IRQ_GC_INIT_NESTED_LOCK,
252 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
254 struct mxs_gpio_port *port = gpiochip_get_data(gc);
256 return irq_find_mapping(port->domain, offset);
259 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
261 struct mxs_gpio_port *port = gpiochip_get_data(gc);
262 u32 mask = 1 << offset;
265 dir = readl(port->base + PINCTRL_DOE(port));
266 return !(dir & mask);
269 static const struct platform_device_id mxs_gpio_ids[] = {
271 .name = "imx23-gpio",
272 .driver_data = IMX23_GPIO,
274 .name = "imx28-gpio",
275 .driver_data = IMX28_GPIO,
280 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
282 static const struct of_device_id mxs_gpio_dt_ids[] = {
283 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
284 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
287 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
289 static int mxs_gpio_probe(struct platform_device *pdev)
291 const struct of_device_id *of_id =
292 of_match_device(mxs_gpio_dt_ids, &pdev->dev);
293 struct device_node *np = pdev->dev.of_node;
294 struct device_node *parent;
295 static void __iomem *base;
296 struct mxs_gpio_port *port;
300 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
304 port->id = of_alias_get_id(np, "gpio");
307 port->devid = (enum mxs_gpio_id) of_id->data;
308 port->dev = &pdev->dev;
309 port->irq = platform_get_irq(pdev, 0);
314 * map memory region only once, as all the gpio ports
318 parent = of_get_parent(np);
319 base = of_iomap(parent, 0);
322 return -EADDRNOTAVAIL;
326 /* initially disable the interrupts */
327 writel(0, port->base + PINCTRL_PIN2IRQ(port));
328 writel(0, port->base + PINCTRL_IRQEN(port));
330 /* clear address has to be used to clear IRQSTAT bits */
331 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
333 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
339 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
340 &irq_domain_simple_ops, NULL);
346 /* gpio-mxs can be a generic irq chip */
347 err = mxs_gpio_init_gc(port, irq_base);
349 goto out_irqdomain_remove;
351 /* setup one handler for each entry */
352 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
355 err = bgpio_init(&port->gc, &pdev->dev, 4,
356 port->base + PINCTRL_DIN(port),
357 port->base + PINCTRL_DOUT(port) + MXS_SET,
358 port->base + PINCTRL_DOUT(port) + MXS_CLR,
359 port->base + PINCTRL_DOE(port), NULL, 0);
361 goto out_irqdomain_remove;
363 port->gc.to_irq = mxs_gpio_to_irq;
364 port->gc.get_direction = mxs_gpio_get_direction;
365 port->gc.base = port->id * 32;
367 err = gpiochip_add_data(&port->gc, port);
369 goto out_irqdomain_remove;
373 out_irqdomain_remove:
374 irq_domain_remove(port->domain);
380 static struct platform_driver mxs_gpio_driver = {
383 .of_match_table = mxs_gpio_dt_ids,
384 .suppress_bind_attrs = true,
386 .probe = mxs_gpio_probe,
387 .id_table = mxs_gpio_ids,
390 static int __init mxs_gpio_init(void)
392 return platform_driver_register(&mxs_gpio_driver);
394 postcore_initcall(mxs_gpio_init);
396 MODULE_AUTHOR("Freescale Semiconductor, "
397 "Daniel Mack <danielncaiaq.de>, "
398 "Juergen Beisert <kernel@pengutronix.de>");
399 MODULE_DESCRIPTION("Freescale MXS GPIO");
400 MODULE_LICENSE("GPL");