1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
13 #include <linux/genalloc.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/notifier.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/types.h>
25 #include <linux/uaccess.h>
27 #include "altera_edac.h"
28 #include "edac_module.h"
30 #define EDAC_MOD_STR "altera_edac"
31 #define EDAC_DEVICE "Altera"
33 #ifdef CONFIG_EDAC_ALTERA_SDRAM
34 static const struct altr_sdram_prv_data c5_data = {
35 .ecc_ctrl_offset = CV_CTLCFG_OFST,
36 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
37 .ecc_stat_offset = CV_DRAMSTS_OFST,
38 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
39 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
40 .ecc_saddr_offset = CV_ERRADDR_OFST,
41 .ecc_daddr_offset = CV_ERRADDR_OFST,
42 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
43 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
44 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
45 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
46 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
47 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
48 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
49 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
50 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
51 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
52 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
55 static const struct altr_sdram_prv_data a10_data = {
56 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
57 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
58 .ecc_stat_offset = A10_INTSTAT_OFST,
59 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
60 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
61 .ecc_saddr_offset = A10_SERRADDR_OFST,
62 .ecc_daddr_offset = A10_DERRADDR_OFST,
63 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
64 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
65 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
66 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
67 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
68 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
69 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
70 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
71 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
74 /*********************** EDAC Memory Controller Functions ****************/
76 /* The SDRAM controller uses the EDAC Memory Controller framework. */
78 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
80 struct mem_ctl_info *mci = dev_id;
81 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
82 const struct altr_sdram_prv_data *priv = drvdata->data;
83 u32 status, err_count = 1, err_addr;
85 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
87 if (status & priv->ecc_stat_ue_mask) {
88 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
90 if (priv->ecc_uecnt_offset)
91 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
93 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
96 if (status & priv->ecc_stat_ce_mask) {
97 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
99 if (priv->ecc_uecnt_offset)
100 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
102 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
103 err_addr >> PAGE_SHIFT,
104 err_addr & ~PAGE_MASK, 0,
105 0, 0, -1, mci->ctl_name, "");
106 /* Clear IRQ to resume */
107 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
108 priv->ecc_irq_clr_mask);
115 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
116 const char __user *data,
117 size_t count, loff_t *ppos)
119 struct mem_ctl_info *mci = file->private_data;
120 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
121 const struct altr_sdram_prv_data *priv = drvdata->data;
123 dma_addr_t dma_handle;
126 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
128 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
129 edac_printk(KERN_ERR, EDAC_MC,
130 "Inject: Buffer Allocation error\n");
134 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
136 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
138 /* Error are injected by writing a word while the SBE or DBE
139 * bit in the CTLCFG register is set. Reading the word will
140 * trigger the SBE or DBE error and the corresponding IRQ.
143 edac_printk(KERN_ALERT, EDAC_MC,
144 "Inject Double bit error\n");
146 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
147 (read_reg | priv->ue_set_mask));
150 edac_printk(KERN_ALERT, EDAC_MC,
151 "Inject Single bit error\n");
153 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
154 (read_reg | priv->ce_set_mask));
158 ptemp[0] = 0x5A5A5A5A;
159 ptemp[1] = 0xA5A5A5A5;
161 /* Clear the error injection bits */
162 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
163 /* Ensure it has been written out */
167 * To trigger the error, we need to read the data back
168 * (the data was written with errors above).
169 * The READ_ONCE macros and printk are used to prevent the
170 * the compiler optimizing these reads out.
172 reg = READ_ONCE(ptemp[0]);
173 read_reg = READ_ONCE(ptemp[1]);
177 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
180 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
185 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
187 .write = altr_sdr_mc_err_inject_write,
188 .llseek = generic_file_llseek,
191 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
193 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
199 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
200 &altr_sdr_mc_debug_inject_fops);
203 /* Get total memory size from Open Firmware DTB */
204 static unsigned long get_total_mem(void)
206 struct device_node *np = NULL;
209 unsigned long total_mem = 0;
211 for_each_node_by_type(np, "memory") {
212 ret = of_address_to_resource(np, 0, &res);
216 total_mem += resource_size(&res);
218 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
222 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
223 { .compatible = "altr,sdram-edac", .data = &c5_data},
224 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
227 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
229 static int a10_init(struct regmap *mc_vbase)
231 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
232 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
233 edac_printk(KERN_ERR, EDAC_MC,
234 "Error setting SB IRQ mode\n");
238 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
239 edac_printk(KERN_ERR, EDAC_MC,
240 "Error setting trigger count\n");
247 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
249 void __iomem *sm_base;
252 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
253 dev_name(&pdev->dev))) {
254 edac_printk(KERN_ERR, EDAC_MC,
255 "Unable to request mem region\n");
259 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
261 edac_printk(KERN_ERR, EDAC_MC,
262 "Unable to ioremap device\n");
268 iowrite32(mask, sm_base);
273 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
278 static int socfpga_is_a10(void);
279 static int altr_sdram_probe(struct platform_device *pdev)
281 const struct of_device_id *id;
282 struct edac_mc_layer layers[2];
283 struct mem_ctl_info *mci;
284 struct altr_sdram_mc_data *drvdata;
285 const struct altr_sdram_prv_data *priv;
286 struct regmap *mc_vbase;
287 struct dimm_info *dimm;
289 int irq, irq2, res = 0;
290 unsigned long mem_size, irqflags = 0;
292 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
296 /* Grab the register range from the sdr controller in device tree */
297 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
299 if (IS_ERR(mc_vbase)) {
300 edac_printk(KERN_ERR, EDAC_MC,
301 "regmap for altr,sdr-syscon lookup failed.\n");
305 /* Check specific dependencies for the module */
306 priv = of_match_node(altr_sdram_ctrl_of_match,
307 pdev->dev.of_node)->data;
309 /* Validate the SDRAM controller has ECC enabled */
310 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
311 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
312 edac_printk(KERN_ERR, EDAC_MC,
313 "No ECC/ECC disabled [0x%08X]\n", read_reg);
317 /* Grab memory size from device tree. */
318 mem_size = get_total_mem();
320 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
324 /* Ensure the SDRAM Interrupt is disabled */
325 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
326 priv->ecc_irq_en_mask, 0)) {
327 edac_printk(KERN_ERR, EDAC_MC,
328 "Error disabling SDRAM ECC IRQ\n");
332 /* Toggle to clear the SDRAM Error count */
333 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
334 priv->ecc_cnt_rst_mask,
335 priv->ecc_cnt_rst_mask)) {
336 edac_printk(KERN_ERR, EDAC_MC,
337 "Error clearing SDRAM ECC count\n");
341 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
342 priv->ecc_cnt_rst_mask, 0)) {
343 edac_printk(KERN_ERR, EDAC_MC,
344 "Error clearing SDRAM ECC count\n");
348 irq = platform_get_irq(pdev, 0);
350 edac_printk(KERN_ERR, EDAC_MC,
351 "No irq %d in DT\n", irq);
355 /* Arria10 has a 2nd IRQ */
356 irq2 = platform_get_irq(pdev, 1);
358 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
360 layers[0].is_virt_csrow = true;
361 layers[1].type = EDAC_MC_LAYER_CHANNEL;
363 layers[1].is_virt_csrow = false;
364 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
365 sizeof(struct altr_sdram_mc_data));
369 mci->pdev = &pdev->dev;
370 drvdata = mci->pvt_info;
371 drvdata->mc_vbase = mc_vbase;
372 drvdata->data = priv;
373 platform_set_drvdata(pdev, mci);
375 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
376 edac_printk(KERN_ERR, EDAC_MC,
377 "Unable to get managed device resource\n");
382 mci->mtype_cap = MEM_FLAG_DDR3;
383 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
384 mci->edac_cap = EDAC_FLAG_SECDED;
385 mci->mod_name = EDAC_MOD_STR;
386 mci->ctl_name = dev_name(&pdev->dev);
387 mci->scrub_mode = SCRUB_SW_SRC;
388 mci->dev_name = dev_name(&pdev->dev);
391 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
393 dimm->dtype = DEV_X8;
394 dimm->mtype = MEM_DDR3;
395 dimm->edac_mode = EDAC_SECDED;
397 res = edac_mc_add_mc(mci);
401 /* Only the Arria10 has separate IRQs */
402 if (socfpga_is_a10()) {
403 /* Arria10 specific initialization */
404 res = a10_init(mc_vbase);
408 res = devm_request_irq(&pdev->dev, irq2,
409 altr_sdram_mc_err_handler,
410 IRQF_SHARED, dev_name(&pdev->dev), mci);
412 edac_mc_printk(mci, KERN_ERR,
413 "Unable to request irq %d\n", irq2);
418 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
422 irqflags = IRQF_SHARED;
425 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
426 irqflags, dev_name(&pdev->dev), mci);
428 edac_mc_printk(mci, KERN_ERR,
429 "Unable to request irq %d\n", irq);
434 /* Infrastructure ready - enable the IRQ */
435 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
436 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
437 edac_mc_printk(mci, KERN_ERR,
438 "Error enabling SDRAM ECC IRQ\n");
443 altr_sdr_mc_create_debugfs_nodes(mci);
445 devres_close_group(&pdev->dev, NULL);
450 edac_mc_del_mc(&pdev->dev);
452 devres_release_group(&pdev->dev, NULL);
455 edac_printk(KERN_ERR, EDAC_MC,
456 "EDAC Probe Failed; Error %d\n", res);
461 static int altr_sdram_remove(struct platform_device *pdev)
463 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
465 edac_mc_del_mc(&pdev->dev);
467 platform_set_drvdata(pdev, NULL);
473 * If you want to suspend, need to disable EDAC by removing it
474 * from the device tree or defconfig.
477 static int altr_sdram_prepare(struct device *dev)
479 pr_err("Suspend not allowed when EDAC is enabled.\n");
484 static const struct dev_pm_ops altr_sdram_pm_ops = {
485 .prepare = altr_sdram_prepare,
489 static struct platform_driver altr_sdram_edac_driver = {
490 .probe = altr_sdram_probe,
491 .remove = altr_sdram_remove,
493 .name = "altr_sdram_edac",
495 .pm = &altr_sdram_pm_ops,
497 .of_match_table = altr_sdram_ctrl_of_match,
501 module_platform_driver(altr_sdram_edac_driver);
503 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
505 /**************** Stratix 10 EDAC Memory Controller Functions ************/
508 * s10_protected_reg_write
509 * Write to a protected SMC register.
510 * @context: Not used.
511 * @reg: Address of register
512 * @value: Value to write
513 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
514 * INTEL_SIP_SMC_REG_ERROR on error
515 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
517 static int s10_protected_reg_write(void *context, unsigned int reg,
520 struct arm_smccc_res result;
521 unsigned long offset = (unsigned long)context;
523 arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0,
526 return (int)result.a0;
530 * s10_protected_reg_read
531 * Read the status of a protected SMC register
532 * @context: Not used.
533 * @reg: Address of register
534 * @value: Value read.
535 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
536 * INTEL_SIP_SMC_REG_ERROR on error
537 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
539 static int s10_protected_reg_read(void *context, unsigned int reg,
542 struct arm_smccc_res result;
543 unsigned long offset = (unsigned long)context;
545 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0,
548 *val = (unsigned int)result.a1;
550 return (int)result.a0;
553 static const struct regmap_config s10_sdram_regmap_cfg = {
558 .max_register = 0xffd12228,
559 .reg_read = s10_protected_reg_read,
560 .reg_write = s10_protected_reg_write,
561 .use_single_read = true,
562 .use_single_write = true,
566 /************** </Stratix10 EDAC Memory Controller Functions> ***********/
568 /************************* EDAC Parent Probe *************************/
570 static const struct of_device_id altr_edac_device_of_match[];
572 static const struct of_device_id altr_edac_of_match[] = {
573 { .compatible = "altr,socfpga-ecc-manager" },
576 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
578 static int altr_edac_probe(struct platform_device *pdev)
580 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
585 static struct platform_driver altr_edac_driver = {
586 .probe = altr_edac_probe,
588 .name = "socfpga_ecc_manager",
589 .of_match_table = altr_edac_of_match,
592 module_platform_driver(altr_edac_driver);
594 /************************* EDAC Device Functions *************************/
597 * EDAC Device Functions (shared between various IPs).
598 * The discrete memories use the EDAC Device framework. The probe
599 * and error handling functions are very similar between memories
600 * so they are shared. The memory allocation and freeing for EDAC
601 * trigger testing are different for each memory.
604 static const struct edac_device_prv_data ocramecc_data;
605 static const struct edac_device_prv_data l2ecc_data;
606 static const struct edac_device_prv_data a10_ocramecc_data;
607 static const struct edac_device_prv_data a10_l2ecc_data;
609 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
611 irqreturn_t ret_value = IRQ_NONE;
612 struct edac_device_ctl_info *dci = dev_id;
613 struct altr_edac_device_dev *drvdata = dci->pvt_info;
614 const struct edac_device_prv_data *priv = drvdata->data;
616 if (irq == drvdata->sb_irq) {
617 if (priv->ce_clear_mask)
618 writel(priv->ce_clear_mask, drvdata->base);
619 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
620 ret_value = IRQ_HANDLED;
621 } else if (irq == drvdata->db_irq) {
622 if (priv->ue_clear_mask)
623 writel(priv->ue_clear_mask, drvdata->base);
624 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
625 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
626 ret_value = IRQ_HANDLED;
634 static ssize_t altr_edac_device_trig(struct file *file,
635 const char __user *user_buf,
636 size_t count, loff_t *ppos)
639 u32 *ptemp, i, error_mask;
643 struct edac_device_ctl_info *edac_dci = file->private_data;
644 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
645 const struct edac_device_prv_data *priv = drvdata->data;
646 void *generic_ptr = edac_dci->dev;
648 if (!user_buf || get_user(trig_type, user_buf))
651 if (!priv->alloc_mem)
655 * Note that generic_ptr is initialized to the device * but in
656 * some alloc_functions, this is overridden and returns data.
658 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
660 edac_printk(KERN_ERR, EDAC_DEVICE,
661 "Inject: Buffer Allocation error\n");
665 if (trig_type == ALTR_UE_TRIGGER_CHAR)
666 error_mask = priv->ue_set_mask;
668 error_mask = priv->ce_set_mask;
670 edac_printk(KERN_ALERT, EDAC_DEVICE,
671 "Trigger Error Mask (0x%X)\n", error_mask);
673 local_irq_save(flags);
674 /* write ECC corrupted data out. */
675 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
676 /* Read data so we're in the correct state */
678 if (READ_ONCE(ptemp[i]))
680 /* Toggle Error bit (it is latched), leave ECC enabled */
681 writel(error_mask, (drvdata->base + priv->set_err_ofst));
682 writel(priv->ecc_enable_mask, (drvdata->base +
683 priv->set_err_ofst));
686 /* Ensure it has been written out */
688 local_irq_restore(flags);
691 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
693 /* Read out written data. ECC error caused here */
694 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
695 if (READ_ONCE(ptemp[i]) != i)
696 edac_printk(KERN_ERR, EDAC_DEVICE,
697 "Read doesn't match written data\n");
700 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
705 static const struct file_operations altr_edac_device_inject_fops = {
707 .write = altr_edac_device_trig,
708 .llseek = generic_file_llseek,
711 static ssize_t altr_edac_a10_device_trig(struct file *file,
712 const char __user *user_buf,
713 size_t count, loff_t *ppos);
715 static const struct file_operations altr_edac_a10_device_inject_fops = {
717 .write = altr_edac_a10_device_trig,
718 .llseek = generic_file_llseek,
721 static ssize_t altr_edac_a10_device_trig2(struct file *file,
722 const char __user *user_buf,
723 size_t count, loff_t *ppos);
725 static const struct file_operations altr_edac_a10_device_inject2_fops = {
727 .write = altr_edac_a10_device_trig2,
728 .llseek = generic_file_llseek,
731 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
732 const struct edac_device_prv_data *priv)
734 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
736 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
739 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
740 if (!drvdata->debugfs_dir)
743 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
744 drvdata->debugfs_dir, edac_dci,
746 debugfs_remove_recursive(drvdata->debugfs_dir);
749 static const struct of_device_id altr_edac_device_of_match[] = {
750 #ifdef CONFIG_EDAC_ALTERA_L2C
751 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
753 #ifdef CONFIG_EDAC_ALTERA_OCRAM
754 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
758 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
761 * altr_edac_device_probe()
762 * This is a generic EDAC device driver that will support
763 * various Altera memory devices such as the L2 cache ECC and
764 * OCRAM ECC as well as the memories for other peripherals.
765 * Module specific initialization is done by passing the
766 * function index in the device tree.
768 static int altr_edac_device_probe(struct platform_device *pdev)
770 struct edac_device_ctl_info *dci;
771 struct altr_edac_device_dev *drvdata;
774 struct device_node *np = pdev->dev.of_node;
775 char *ecc_name = (char *)np->name;
776 static int dev_instance;
778 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
779 edac_printk(KERN_ERR, EDAC_DEVICE,
780 "Unable to open devm\n");
784 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
786 edac_printk(KERN_ERR, EDAC_DEVICE,
787 "Unable to get mem resource\n");
792 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
793 dev_name(&pdev->dev))) {
794 edac_printk(KERN_ERR, EDAC_DEVICE,
795 "%s:Error requesting mem region\n", ecc_name);
800 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
801 1, ecc_name, 1, 0, NULL, 0,
805 edac_printk(KERN_ERR, EDAC_DEVICE,
806 "%s: Unable to allocate EDAC device\n", ecc_name);
811 drvdata = dci->pvt_info;
812 dci->dev = &pdev->dev;
813 platform_set_drvdata(pdev, dci);
814 drvdata->edac_dev_name = ecc_name;
816 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
817 if (!drvdata->base) {
822 /* Get driver specific data for this EDAC device */
823 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
825 /* Check specific dependencies for the module */
826 if (drvdata->data->setup) {
827 res = drvdata->data->setup(drvdata);
832 drvdata->sb_irq = platform_get_irq(pdev, 0);
833 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
834 altr_edac_device_handler,
835 0, dev_name(&pdev->dev), dci);
839 drvdata->db_irq = platform_get_irq(pdev, 1);
840 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
841 altr_edac_device_handler,
842 0, dev_name(&pdev->dev), dci);
846 dci->mod_name = "Altera ECC Manager";
847 dci->dev_name = drvdata->edac_dev_name;
849 res = edac_device_add_device(dci);
853 altr_create_edacdev_dbgfs(dci, drvdata->data);
855 devres_close_group(&pdev->dev, NULL);
860 edac_device_free_ctl_info(dci);
862 devres_release_group(&pdev->dev, NULL);
863 edac_printk(KERN_ERR, EDAC_DEVICE,
864 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
869 static int altr_edac_device_remove(struct platform_device *pdev)
871 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
872 struct altr_edac_device_dev *drvdata = dci->pvt_info;
874 debugfs_remove_recursive(drvdata->debugfs_dir);
875 edac_device_del_device(&pdev->dev);
876 edac_device_free_ctl_info(dci);
881 static struct platform_driver altr_edac_device_driver = {
882 .probe = altr_edac_device_probe,
883 .remove = altr_edac_device_remove,
885 .name = "altr_edac_device",
886 .of_match_table = altr_edac_device_of_match,
889 module_platform_driver(altr_edac_device_driver);
891 /******************* Arria10 Device ECC Shared Functions *****************/
894 * Test for memory's ECC dependencies upon entry because platform specific
895 * startup should have initialized the memory and enabled the ECC.
896 * Can't turn on ECC here because accessing un-initialized memory will
897 * cause CE/UE errors possibly causing an ABORT.
899 static int __maybe_unused
900 altr_check_ecc_deps(struct altr_edac_device_dev *device)
902 void __iomem *base = device->base;
903 const struct edac_device_prv_data *prv = device->data;
905 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
908 edac_printk(KERN_ERR, EDAC_DEVICE,
909 "%s: No ECC present or ECC disabled.\n",
910 device->edac_dev_name);
914 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
916 struct altr_edac_device_dev *dci = dev_id;
917 void __iomem *base = dci->base;
919 if (irq == dci->sb_irq) {
920 writel(ALTR_A10_ECC_SERRPENA,
921 base + ALTR_A10_ECC_INTSTAT_OFST);
922 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
925 } else if (irq == dci->db_irq) {
926 writel(ALTR_A10_ECC_DERRPENA,
927 base + ALTR_A10_ECC_INTSTAT_OFST);
928 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
929 if (dci->data->panic)
930 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
940 /******************* Arria10 Memory Buffer Functions *********************/
942 static inline int a10_get_irq_mask(struct device_node *np)
945 const u32 *handle = of_get_property(np, "interrupts", NULL);
949 irq = be32_to_cpup(handle);
953 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
955 u32 value = readl(ioaddr);
958 writel(value, ioaddr);
961 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
963 u32 value = readl(ioaddr);
966 writel(value, ioaddr);
969 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
971 u32 value = readl(ioaddr);
973 return (value & bit_mask) ? 1 : 0;
977 * This function uses the memory initialization block in the Arria10 ECC
978 * controller to initialize/clear the entire memory data and ECC data.
980 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
982 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
983 u32 init_mask, stat_mask, clear_mask;
987 init_mask = ALTR_A10_ECC_INITB;
988 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
989 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
991 init_mask = ALTR_A10_ECC_INITA;
992 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
993 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
996 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
998 if (ecc_test_bits(stat_mask,
999 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
1006 /* Clear any pending ECC interrupts */
1007 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
1012 static int socfpga_is_a10(void)
1014 return of_machine_is_compatible("altr,socfpga-arria10");
1017 static int socfpga_is_s10(void)
1019 return of_machine_is_compatible("altr,socfpga-stratix10");
1022 static __init int __maybe_unused
1023 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
1024 u32 ecc_ctrl_en_mask, bool dual_port)
1027 void __iomem *ecc_block_base;
1028 struct regmap *ecc_mgr_map;
1030 struct device_node *np_eccmgr;
1032 ecc_name = (char *)np->name;
1034 /* Get the ECC Manager - parent of the device EDACs */
1035 np_eccmgr = of_get_parent(np);
1037 if (socfpga_is_a10()) {
1038 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1039 "altr,sysmgr-syscon");
1041 struct device_node *sysmgr_np;
1042 struct resource res;
1045 sysmgr_np = of_parse_phandle(np_eccmgr,
1046 "altr,sysmgr-syscon", 0);
1048 edac_printk(KERN_ERR, EDAC_DEVICE,
1049 "Unable to find altr,sysmgr-syscon\n");
1053 if (of_address_to_resource(sysmgr_np, 0, &res)) {
1054 of_node_put(sysmgr_np);
1058 /* Need physical address for SMCC call */
1061 ecc_mgr_map = regmap_init(NULL, NULL, (void *)base,
1062 &s10_sdram_regmap_cfg);
1063 of_node_put(sysmgr_np);
1065 of_node_put(np_eccmgr);
1066 if (IS_ERR(ecc_mgr_map)) {
1067 edac_printk(KERN_ERR, EDAC_DEVICE,
1068 "Unable to get syscon altr,sysmgr-syscon\n");
1072 /* Map the ECC Block */
1073 ecc_block_base = of_iomap(np, 0);
1074 if (!ecc_block_base) {
1075 edac_printk(KERN_ERR, EDAC_DEVICE,
1076 "Unable to map %s ECC block\n", ecc_name);
1081 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
1082 writel(ALTR_A10_ECC_SERRINTEN,
1083 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
1084 ecc_clear_bits(ecc_ctrl_en_mask,
1085 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
1086 /* Ensure all writes complete */
1088 /* Use HW initialization block to initialize memory for ECC */
1089 ret = altr_init_memory_port(ecc_block_base, 0);
1091 edac_printk(KERN_ERR, EDAC_DEVICE,
1092 "ECC: cannot init %s PORTA memory\n", ecc_name);
1097 ret = altr_init_memory_port(ecc_block_base, 1);
1099 edac_printk(KERN_ERR, EDAC_DEVICE,
1100 "ECC: cannot init %s PORTB memory\n",
1106 /* Interrupt mode set to every SBERR */
1107 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1108 ALTR_A10_ECC_INTMODE);
1110 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1111 ALTR_A10_ECC_CTRL_OFST));
1112 writel(ALTR_A10_ECC_SERRINTEN,
1113 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1114 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1115 /* Ensure all writes complete */
1118 iounmap(ecc_block_base);
1122 static int validate_parent_available(struct device_node *np);
1123 static const struct of_device_id altr_edac_a10_device_of_match[];
1124 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1127 struct device_node *child, *np;
1129 if (!socfpga_is_a10() && !socfpga_is_s10())
1132 np = of_find_compatible_node(NULL, NULL,
1133 "altr,socfpga-a10-ecc-manager");
1135 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1139 for_each_child_of_node(np, child) {
1140 const struct of_device_id *pdev_id;
1141 const struct edac_device_prv_data *prv;
1143 if (!of_device_is_available(child))
1145 if (!of_device_is_compatible(child, compat))
1148 if (validate_parent_available(child))
1151 irq = a10_get_irq_mask(child);
1155 /* Get matching node and check for valid result */
1156 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1157 if (IS_ERR_OR_NULL(pdev_id))
1160 /* Validate private data pointer before dereferencing */
1161 prv = pdev_id->data;
1165 altr_init_a10_ecc_block(child, BIT(irq),
1166 prv->ecc_enable_mask, 0);
1173 /*********************** SDRAM EDAC Device Functions *********************/
1175 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1177 static const struct edac_device_prv_data s10_sdramecc_data = {
1178 .setup = altr_check_ecc_deps,
1179 .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1180 .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1181 .ecc_enable_mask = ALTR_S10_ECC_EN,
1182 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1183 .ce_set_mask = ALTR_S10_ECC_TSERRA,
1184 .ue_set_mask = ALTR_S10_ECC_TDERRA,
1185 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1186 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1187 .inject_fops = &altr_edac_a10_device_inject_fops,
1189 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
1191 /*********************** OCRAM EDAC Device Functions *********************/
1193 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1195 static void *ocram_alloc_mem(size_t size, void **other)
1197 struct device_node *np;
1198 struct gen_pool *gp;
1201 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1205 gp = of_gen_pool_get(np, "iram", 0);
1210 sram_addr = (void *)gen_pool_alloc(gp, size);
1214 memset(sram_addr, 0, size);
1215 /* Ensure data is written out */
1218 /* Remember this handle for freeing later */
1224 static void ocram_free_mem(void *p, size_t size, void *other)
1226 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1229 static const struct edac_device_prv_data ocramecc_data = {
1230 .setup = altr_check_ecc_deps,
1231 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1232 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1233 .alloc_mem = ocram_alloc_mem,
1234 .free_mem = ocram_free_mem,
1235 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1236 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1237 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1238 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1239 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1240 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1241 .inject_fops = &altr_edac_device_inject_fops,
1244 static int __maybe_unused
1245 altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1247 void __iomem *base = device->base;
1250 ret = altr_check_ecc_deps(device);
1254 /* Verify OCRAM has been initialized */
1255 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1256 (base + ALTR_A10_ECC_INITSTAT_OFST)))
1259 /* Enable IRQ on Single Bit Error */
1260 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1261 /* Ensure all writes complete */
1267 static const struct edac_device_prv_data a10_ocramecc_data = {
1268 .setup = altr_check_ocram_deps_init,
1269 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1270 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1271 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1272 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1273 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1274 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1275 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1276 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1277 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1278 .inject_fops = &altr_edac_a10_device_inject2_fops,
1280 * OCRAM panic on uncorrectable error because sleep/resume
1281 * functions and FPGA contents are stored in OCRAM. Prefer
1282 * a kernel panic over executing/loading corrupted data.
1287 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1289 /********************* L2 Cache EDAC Device Functions ********************/
1291 #ifdef CONFIG_EDAC_ALTERA_L2C
1293 static void *l2_alloc_mem(size_t size, void **other)
1295 struct device *dev = *other;
1296 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1301 /* Make sure everything is written out */
1305 * Clean all cache levels up to LoC (includes L2)
1306 * This ensures the corrupted data is written into
1307 * L2 cache for readback test (which causes ECC error).
1314 static void l2_free_mem(void *p, size_t size, void *other)
1316 struct device *dev = other;
1323 * altr_l2_check_deps()
1324 * Test for L2 cache ECC dependencies upon entry because
1325 * platform specific startup should have initialized the L2
1326 * memory and enabled the ECC.
1327 * Bail if ECC is not enabled.
1328 * Note that L2 Cache Enable is forced at build time.
1330 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1332 void __iomem *base = device->base;
1333 const struct edac_device_prv_data *prv = device->data;
1335 if ((readl(base) & prv->ecc_enable_mask) ==
1336 prv->ecc_enable_mask)
1339 edac_printk(KERN_ERR, EDAC_DEVICE,
1340 "L2: No ECC present, or ECC disabled\n");
1344 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1346 struct altr_edac_device_dev *dci = dev_id;
1348 if (irq == dci->sb_irq) {
1349 regmap_write(dci->edac->ecc_mgr_map,
1350 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1351 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1352 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1355 } else if (irq == dci->db_irq) {
1356 regmap_write(dci->edac->ecc_mgr_map,
1357 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1358 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1359 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1360 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1370 static const struct edac_device_prv_data l2ecc_data = {
1371 .setup = altr_l2_check_deps,
1374 .alloc_mem = l2_alloc_mem,
1375 .free_mem = l2_free_mem,
1376 .ecc_enable_mask = ALTR_L2_ECC_EN,
1377 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1378 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1379 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1380 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1381 .inject_fops = &altr_edac_device_inject_fops,
1384 static const struct edac_device_prv_data a10_l2ecc_data = {
1385 .setup = altr_l2_check_deps,
1386 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1387 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1388 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1389 .alloc_mem = l2_alloc_mem,
1390 .free_mem = l2_free_mem,
1391 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1392 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1393 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1394 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1395 .ecc_irq_handler = altr_edac_a10_l2_irq,
1396 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1397 .inject_fops = &altr_edac_device_inject_fops,
1400 #endif /* CONFIG_EDAC_ALTERA_L2C */
1402 /********************* Ethernet Device Functions ********************/
1404 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1406 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1410 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1414 return altr_check_ecc_deps(dev);
1417 static const struct edac_device_prv_data a10_enetecc_data = {
1418 .setup = socfpga_init_ethernet_ecc,
1419 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1420 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1421 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1422 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1423 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1424 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1425 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1426 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1427 .inject_fops = &altr_edac_a10_device_inject2_fops,
1430 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1432 /********************** NAND Device Functions **********************/
1434 #ifdef CONFIG_EDAC_ALTERA_NAND
1436 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1440 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1444 return altr_check_ecc_deps(device);
1447 static const struct edac_device_prv_data a10_nandecc_data = {
1448 .setup = socfpga_init_nand_ecc,
1449 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1450 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1451 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1452 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1453 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1454 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1455 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1456 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1457 .inject_fops = &altr_edac_a10_device_inject_fops,
1460 #endif /* CONFIG_EDAC_ALTERA_NAND */
1462 /********************** DMA Device Functions **********************/
1464 #ifdef CONFIG_EDAC_ALTERA_DMA
1466 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1470 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1474 return altr_check_ecc_deps(device);
1477 static const struct edac_device_prv_data a10_dmaecc_data = {
1478 .setup = socfpga_init_dma_ecc,
1479 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1480 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1481 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1482 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1483 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1484 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1485 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1486 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1487 .inject_fops = &altr_edac_a10_device_inject_fops,
1490 #endif /* CONFIG_EDAC_ALTERA_DMA */
1492 /********************** USB Device Functions **********************/
1494 #ifdef CONFIG_EDAC_ALTERA_USB
1496 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1500 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1504 return altr_check_ecc_deps(device);
1507 static const struct edac_device_prv_data a10_usbecc_data = {
1508 .setup = socfpga_init_usb_ecc,
1509 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1510 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1511 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1512 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1513 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1514 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1515 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1516 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1517 .inject_fops = &altr_edac_a10_device_inject2_fops,
1520 #endif /* CONFIG_EDAC_ALTERA_USB */
1522 /********************** QSPI Device Functions **********************/
1524 #ifdef CONFIG_EDAC_ALTERA_QSPI
1526 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1530 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1534 return altr_check_ecc_deps(device);
1537 static const struct edac_device_prv_data a10_qspiecc_data = {
1538 .setup = socfpga_init_qspi_ecc,
1539 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1540 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1541 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1542 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1543 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1544 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1545 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1546 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1547 .inject_fops = &altr_edac_a10_device_inject_fops,
1550 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1552 /********************* SDMMC Device Functions **********************/
1554 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1556 static const struct edac_device_prv_data a10_sdmmceccb_data;
1557 static int altr_portb_setup(struct altr_edac_device_dev *device)
1559 struct edac_device_ctl_info *dci;
1560 struct altr_edac_device_dev *altdev;
1561 char *ecc_name = "sdmmcb-ecc";
1563 struct device_node *np;
1564 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1566 rc = altr_check_ecc_deps(device);
1570 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1572 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1576 /* Create the PortB EDAC device */
1577 edac_idx = edac_device_alloc_index();
1578 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1579 ecc_name, 1, 0, NULL, 0, edac_idx);
1581 edac_printk(KERN_ERR, EDAC_DEVICE,
1582 "%s: Unable to allocate PortB EDAC device\n",
1587 /* Initialize the PortB EDAC device structure from PortA structure */
1588 altdev = dci->pvt_info;
1591 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1594 /* Update PortB specific values */
1595 altdev->edac_dev_name = ecc_name;
1596 altdev->edac_idx = edac_idx;
1597 altdev->edac_dev = dci;
1599 dci->dev = &altdev->ddev;
1600 dci->ctl_name = "Altera ECC Manager";
1601 dci->mod_name = ecc_name;
1602 dci->dev_name = ecc_name;
1604 /* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */
1605 #ifdef CONFIG_ARCH_STRATIX10
1606 altdev->sb_irq = irq_of_parse_and_map(np, 1);
1608 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1610 if (!altdev->sb_irq) {
1611 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1613 goto err_release_group_1;
1615 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1616 prv->ecc_irq_handler,
1617 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1620 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1621 goto err_release_group_1;
1624 #ifdef CONFIG_ARCH_STRATIX10
1625 /* Use IRQ to determine SError origin instead of assigning IRQ */
1626 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1628 edac_printk(KERN_ERR, EDAC_DEVICE,
1629 "Error PortB DBIRQ alloc\n");
1630 goto err_release_group_1;
1633 altdev->db_irq = irq_of_parse_and_map(np, 3);
1634 if (!altdev->db_irq) {
1635 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1637 goto err_release_group_1;
1639 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1640 prv->ecc_irq_handler,
1641 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1644 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1645 goto err_release_group_1;
1649 rc = edac_device_add_device(dci);
1651 edac_printk(KERN_ERR, EDAC_DEVICE,
1652 "edac_device_add_device portB failed\n");
1654 goto err_release_group_1;
1656 altr_create_edacdev_dbgfs(dci, prv);
1658 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1660 devres_remove_group(&altdev->ddev, altr_portb_setup);
1664 err_release_group_1:
1665 edac_device_free_ctl_info(dci);
1666 devres_release_group(&altdev->ddev, altr_portb_setup);
1667 edac_printk(KERN_ERR, EDAC_DEVICE,
1668 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1672 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1675 struct device_node *child;
1677 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1681 if (!of_device_is_available(child))
1684 if (validate_parent_available(child))
1688 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1689 a10_sdmmceccb_data.ecc_enable_mask, 1);
1694 return altr_portb_setup(device);
1701 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1703 struct altr_edac_device_dev *ad = dev_id;
1704 void __iomem *base = ad->base;
1705 const struct edac_device_prv_data *priv = ad->data;
1707 if (irq == ad->sb_irq) {
1708 writel(priv->ce_clear_mask,
1709 base + ALTR_A10_ECC_INTSTAT_OFST);
1710 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1712 } else if (irq == ad->db_irq) {
1713 writel(priv->ue_clear_mask,
1714 base + ALTR_A10_ECC_INTSTAT_OFST);
1715 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1719 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1724 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1725 .setup = socfpga_init_sdmmc_ecc,
1726 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1727 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1728 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1729 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1730 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1731 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1732 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1733 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1734 .inject_fops = &altr_edac_a10_device_inject_fops,
1737 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1738 .setup = socfpga_init_sdmmc_ecc,
1739 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1740 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1741 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1742 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1743 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1744 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1745 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1746 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1747 .inject_fops = &altr_edac_a10_device_inject_fops,
1750 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1752 /********************* Arria10 EDAC Device Functions *************************/
1753 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1754 #ifdef CONFIG_EDAC_ALTERA_L2C
1755 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1757 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1758 { .compatible = "altr,socfpga-a10-ocram-ecc",
1759 .data = &a10_ocramecc_data },
1761 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1762 { .compatible = "altr,socfpga-eth-mac-ecc",
1763 .data = &a10_enetecc_data },
1765 #ifdef CONFIG_EDAC_ALTERA_NAND
1766 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1768 #ifdef CONFIG_EDAC_ALTERA_DMA
1769 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1771 #ifdef CONFIG_EDAC_ALTERA_USB
1772 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1774 #ifdef CONFIG_EDAC_ALTERA_QSPI
1775 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1777 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1778 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1780 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1781 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1785 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1788 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1789 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1790 * manager manages the IRQs and the children.
1791 * Based on xgene_edac.c peripheral code.
1794 static ssize_t altr_edac_a10_device_trig(struct file *file,
1795 const char __user *user_buf,
1796 size_t count, loff_t *ppos)
1798 struct edac_device_ctl_info *edac_dci = file->private_data;
1799 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1800 const struct edac_device_prv_data *priv = drvdata->data;
1801 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1802 unsigned long flags;
1805 if (!user_buf || get_user(trig_type, user_buf))
1808 local_irq_save(flags);
1809 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1810 writel(priv->ue_set_mask, set_addr);
1812 writel(priv->ce_set_mask, set_addr);
1814 /* Ensure the interrupt test bits are set */
1816 local_irq_restore(flags);
1822 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1823 * slightly. A few Arria10 peripherals can use this injection function.
1824 * Inject the error into the memory and then readback to trigger the IRQ.
1826 static ssize_t altr_edac_a10_device_trig2(struct file *file,
1827 const char __user *user_buf,
1828 size_t count, loff_t *ppos)
1830 struct edac_device_ctl_info *edac_dci = file->private_data;
1831 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1832 const struct edac_device_prv_data *priv = drvdata->data;
1833 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1834 unsigned long flags;
1837 if (!user_buf || get_user(trig_type, user_buf))
1840 local_irq_save(flags);
1841 if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1842 writel(priv->ue_set_mask, set_addr);
1844 /* Setup read/write of 4 bytes */
1845 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1846 /* Setup Address to 0 */
1847 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1848 /* Setup accctrl to read & ecc & data override */
1849 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1851 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1852 /* Setup write for single bit change */
1853 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1854 drvdata->base + ECC_BLK_WDATA0_OFST);
1855 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1856 drvdata->base + ECC_BLK_WDATA1_OFST);
1857 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1858 drvdata->base + ECC_BLK_WDATA2_OFST);
1859 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1860 drvdata->base + ECC_BLK_WDATA3_OFST);
1862 /* Copy Read ECC to Write ECC */
1863 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1864 drvdata->base + ECC_BLK_WECC0_OFST);
1865 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1866 drvdata->base + ECC_BLK_WECC1_OFST);
1867 /* Setup accctrl to write & ecc override & data override */
1868 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1870 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1871 /* Setup accctrl to read & ecc overwrite & data overwrite */
1872 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1874 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1877 /* Ensure the interrupt test bits are set */
1879 local_irq_restore(flags);
1884 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1886 int dberr, bit, sm_offset, irq_status;
1887 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1888 struct irq_chip *chip = irq_desc_get_chip(desc);
1889 int irq = irq_desc_get_irq(desc);
1892 dberr = (irq == edac->db_irq) ? 1 : 0;
1893 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1894 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1896 chained_irq_enter(chip, desc);
1898 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1901 for_each_set_bit(bit, &bits, 32) {
1902 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1904 generic_handle_irq(irq);
1907 chained_irq_exit(chip, desc);
1910 static int validate_parent_available(struct device_node *np)
1912 struct device_node *parent;
1915 /* SDRAM must be present for Linux (implied parent) */
1916 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1919 /* Ensure parent device is enabled if parent node exists */
1920 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1921 if (parent && !of_device_is_available(parent))
1924 of_node_put(parent);
1928 static int get_s10_sdram_edac_resource(struct device_node *np,
1929 struct resource *res)
1931 struct device_node *parent;
1934 parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1938 ret = of_address_to_resource(parent, 0, res);
1939 of_node_put(parent);
1944 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1945 struct device_node *np)
1947 struct edac_device_ctl_info *dci;
1948 struct altr_edac_device_dev *altdev;
1949 char *ecc_name = (char *)np->name;
1950 struct resource res;
1953 const struct edac_device_prv_data *prv;
1954 /* Get matching node and check for valid result */
1955 const struct of_device_id *pdev_id =
1956 of_match_node(altr_edac_a10_device_of_match, np);
1957 if (IS_ERR_OR_NULL(pdev_id))
1960 /* Get driver specific data for this EDAC device */
1961 prv = pdev_id->data;
1962 if (IS_ERR_OR_NULL(prv))
1965 if (validate_parent_available(np))
1968 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1971 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1972 rc = get_s10_sdram_edac_resource(np, &res);
1974 rc = of_address_to_resource(np, 0, &res);
1977 edac_printk(KERN_ERR, EDAC_DEVICE,
1978 "%s: no resource address\n", ecc_name);
1979 goto err_release_group;
1982 edac_idx = edac_device_alloc_index();
1983 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1984 1, ecc_name, 1, 0, NULL, 0,
1988 edac_printk(KERN_ERR, EDAC_DEVICE,
1989 "%s: Unable to allocate EDAC device\n", ecc_name);
1991 goto err_release_group;
1994 altdev = dci->pvt_info;
1995 dci->dev = edac->dev;
1996 altdev->edac_dev_name = ecc_name;
1997 altdev->edac_idx = edac_idx;
1998 altdev->edac = edac;
1999 altdev->edac_dev = dci;
2001 altdev->ddev = *edac->dev;
2002 dci->dev = &altdev->ddev;
2003 dci->ctl_name = "Altera ECC Manager";
2004 dci->mod_name = ecc_name;
2005 dci->dev_name = ecc_name;
2007 altdev->base = devm_ioremap_resource(edac->dev, &res);
2008 if (IS_ERR(altdev->base)) {
2009 rc = PTR_ERR(altdev->base);
2010 goto err_release_group1;
2013 /* Check specific dependencies for the module */
2014 if (altdev->data->setup) {
2015 rc = altdev->data->setup(altdev);
2017 goto err_release_group1;
2020 altdev->sb_irq = irq_of_parse_and_map(np, 0);
2021 if (!altdev->sb_irq) {
2022 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
2024 goto err_release_group1;
2026 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
2027 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
2030 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
2031 goto err_release_group1;
2034 #ifdef CONFIG_ARCH_STRATIX10
2035 /* Use IRQ to determine SError origin instead of assigning IRQ */
2036 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
2038 edac_printk(KERN_ERR, EDAC_DEVICE,
2039 "Unable to parse DB IRQ index\n");
2040 goto err_release_group1;
2043 altdev->db_irq = irq_of_parse_and_map(np, 1);
2044 if (!altdev->db_irq) {
2045 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
2047 goto err_release_group1;
2049 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
2050 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
2053 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
2054 goto err_release_group1;
2058 rc = edac_device_add_device(dci);
2060 dev_err(edac->dev, "edac_device_add_device failed\n");
2062 goto err_release_group1;
2065 altr_create_edacdev_dbgfs(dci, prv);
2067 list_add(&altdev->next, &edac->a10_ecc_devices);
2069 devres_remove_group(edac->dev, altr_edac_a10_device_add);
2074 edac_device_free_ctl_info(dci);
2076 devres_release_group(edac->dev, NULL);
2077 edac_printk(KERN_ERR, EDAC_DEVICE,
2078 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
2083 static void a10_eccmgr_irq_mask(struct irq_data *d)
2085 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2087 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2091 static void a10_eccmgr_irq_unmask(struct irq_data *d)
2093 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2095 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2099 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2100 irq_hw_number_t hwirq)
2102 struct altr_arria10_edac *edac = d->host_data;
2104 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2105 irq_set_chip_data(irq, edac);
2106 irq_set_noprobe(irq);
2111 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2112 .map = a10_eccmgr_irqdomain_map,
2113 .xlate = irq_domain_xlate_twocell,
2116 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2117 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2119 #ifdef CONFIG_ARCH_STRATIX10
2120 /* panic routine issues reboot on non-zero panic_timeout */
2121 extern int panic_timeout;
2124 * The double bit error is handled through SError which is fatal. This is
2125 * called as a panic notifier to printout ECC error info as part of the panic.
2127 static int s10_edac_dberr_handler(struct notifier_block *this,
2128 unsigned long event, void *ptr)
2130 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2131 int err_addr, dberror;
2133 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2135 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2136 if (dberror & S10_DBE_IRQ_MASK) {
2137 struct list_head *position;
2138 struct altr_edac_device_dev *ed;
2139 struct arm_smccc_res result;
2141 /* Find the matching DBE in the list of devices */
2142 list_for_each(position, &edac->a10_ecc_devices) {
2143 ed = list_entry(position, struct altr_edac_device_dev,
2145 if (!(BIT(ed->db_irq) & dberror))
2148 writel(ALTR_A10_ECC_DERRPENA,
2149 ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2150 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2151 regmap_write(edac->ecc_mgr_map,
2152 S10_SYSMGR_UE_ADDR_OFST, err_addr);
2153 edac_printk(KERN_ERR, EDAC_DEVICE,
2154 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2155 ed->edac_dev_name, err_addr);
2158 /* Notify the System through SMC. Reboot delay = 1 second */
2160 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2168 /****************** Arria 10 EDAC Probe Function *********************/
2169 static int altr_edac_a10_probe(struct platform_device *pdev)
2171 struct altr_arria10_edac *edac;
2172 struct device_node *child;
2174 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2178 edac->dev = &pdev->dev;
2179 platform_set_drvdata(pdev, edac);
2180 INIT_LIST_HEAD(&edac->a10_ecc_devices);
2182 if (socfpga_is_a10()) {
2184 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2185 "altr,sysmgr-syscon");
2187 struct device_node *sysmgr_np;
2188 struct resource res;
2191 sysmgr_np = of_parse_phandle(pdev->dev.of_node,
2192 "altr,sysmgr-syscon", 0);
2194 edac_printk(KERN_ERR, EDAC_DEVICE,
2195 "Unable to find altr,sysmgr-syscon\n");
2199 if (of_address_to_resource(sysmgr_np, 0, &res))
2202 /* Need physical address for SMCC call */
2205 edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL,
2207 &s10_sdram_regmap_cfg);
2210 if (IS_ERR(edac->ecc_mgr_map)) {
2211 edac_printk(KERN_ERR, EDAC_DEVICE,
2212 "Unable to get syscon altr,sysmgr-syscon\n");
2213 return PTR_ERR(edac->ecc_mgr_map);
2216 edac->irq_chip.name = pdev->dev.of_node->name;
2217 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2218 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2219 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2220 &a10_eccmgr_ic_ops, edac);
2221 if (!edac->domain) {
2222 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2226 edac->sb_irq = platform_get_irq(pdev, 0);
2227 if (edac->sb_irq < 0) {
2228 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2229 return edac->sb_irq;
2232 irq_set_chained_handler_and_data(edac->sb_irq,
2233 altr_edac_a10_irq_handler,
2236 #ifdef CONFIG_ARCH_STRATIX10
2238 int dberror, err_addr;
2240 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2241 atomic_notifier_chain_register(&panic_notifier_list,
2242 &edac->panic_notifier);
2244 /* Printout a message if uncorrectable error previously. */
2245 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2248 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2250 edac_printk(KERN_ERR, EDAC_DEVICE,
2251 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2253 /* Reset the sticky registers */
2254 regmap_write(edac->ecc_mgr_map,
2255 S10_SYSMGR_UE_VAL_OFST, 0);
2256 regmap_write(edac->ecc_mgr_map,
2257 S10_SYSMGR_UE_ADDR_OFST, 0);
2261 edac->db_irq = platform_get_irq(pdev, 1);
2262 if (edac->db_irq < 0) {
2263 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2264 return edac->db_irq;
2266 irq_set_chained_handler_and_data(edac->db_irq,
2267 altr_edac_a10_irq_handler, edac);
2270 for_each_child_of_node(pdev->dev.of_node, child) {
2271 if (!of_device_is_available(child))
2274 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
2275 of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
2276 of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
2277 of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
2278 of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
2279 of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
2280 of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
2281 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2282 of_device_is_compatible(child, "altr,sdram-edac-s10") ||
2284 of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
2286 altr_edac_a10_device_add(edac, child);
2288 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2289 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2290 of_platform_populate(pdev->dev.of_node,
2291 altr_sdram_ctrl_of_match,
2299 static const struct of_device_id altr_edac_a10_of_match[] = {
2300 { .compatible = "altr,socfpga-a10-ecc-manager" },
2301 { .compatible = "altr,socfpga-s10-ecc-manager" },
2304 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2306 static struct platform_driver altr_edac_a10_driver = {
2307 .probe = altr_edac_a10_probe,
2309 .name = "socfpga_a10_ecc_manager",
2310 .of_match_table = altr_edac_a10_of_match,
2313 module_platform_driver(altr_edac_a10_driver);
2315 MODULE_LICENSE("GPL v2");
2316 MODULE_AUTHOR("Thor Thayer");
2317 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");