drivers/dma/nbpfaxi.c

   1 /*
   2  * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
   3  * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/bitmap.h>
  11 #include <linux/bitops.h>
  12 #include <linux/clk.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/err.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/log2.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25
  26 #include <dt-bindings/dma/nbpfaxi.h>
  27
  28 #include "dmaengine.h"
  29
  30 #define NBPF_REG_CHAN_OFFSET    0
  31 #define NBPF_REG_CHAN_SIZE      0x40
  32
  33 /* Channel Current Transaction Byte register */
  34 #define NBPF_CHAN_CUR_TR_BYTE   0x20
  35
  36 /* Channel Status register */
  37 #define NBPF_CHAN_STAT  0x24
  38 #define NBPF_CHAN_STAT_EN       1
  39 #define NBPF_CHAN_STAT_TACT     4
  40 #define NBPF_CHAN_STAT_ERR      0x10
  41 #define NBPF_CHAN_STAT_END      0x20
  42 #define NBPF_CHAN_STAT_TC       0x40
  43 #define NBPF_CHAN_STAT_DER      0x400
  44
  45 /* Channel Control register */
  46 #define NBPF_CHAN_CTRL  0x28
  47 #define NBPF_CHAN_CTRL_SETEN    1
  48 #define NBPF_CHAN_CTRL_CLREN    2
  49 #define NBPF_CHAN_CTRL_STG      4
  50 #define NBPF_CHAN_CTRL_SWRST    8
  51 #define NBPF_CHAN_CTRL_CLRRQ    0x10
  52 #define NBPF_CHAN_CTRL_CLREND   0x20
  53 #define NBPF_CHAN_CTRL_CLRTC    0x40
  54 #define NBPF_CHAN_CTRL_SETSUS   0x100
  55 #define NBPF_CHAN_CTRL_CLRSUS   0x200
  56
  57 /* Channel Configuration register */
  58 #define NBPF_CHAN_CFG   0x2c
  59 #define NBPF_CHAN_CFG_SEL       7               /* terminal SELect: 0..7 */
  60 #define NBPF_CHAN_CFG_REQD      8               /* REQuest Direction: DMAREQ is 0: input, 1: output */
  61 #define NBPF_CHAN_CFG_LOEN      0x10            /* LOw ENable: low DMA request line is: 0: inactive, 1: active */
  62 #define NBPF_CHAN_CFG_HIEN      0x20            /* HIgh ENable: high DMA request line is: 0: inactive, 1: active */
  63 #define NBPF_CHAN_CFG_LVL       0x40            /* LeVeL: DMA request line is sensed as 0: edge, 1: level */
  64 #define NBPF_CHAN_CFG_AM        0x700           /* ACK Mode: 0: Pulse mode, 1: Level mode, b'1x: Bus Cycle */
  65 #define NBPF_CHAN_CFG_SDS       0xf000          /* Source Data Size: 0: 8 bits,... , 7: 1024 bits */
  66 #define NBPF_CHAN_CFG_DDS       0xf0000         /* Destination Data Size: as above */
  67 #define NBPF_CHAN_CFG_SAD       0x100000        /* Source ADdress counting: 0: increment, 1: fixed */
  68 #define NBPF_CHAN_CFG_DAD       0x200000        /* Destination ADdress counting: 0: increment, 1: fixed */
  69 #define NBPF_CHAN_CFG_TM        0x400000        /* Transfer Mode: 0: single, 1: block TM */
  70 #define NBPF_CHAN_CFG_DEM       0x1000000       /* DMAEND interrupt Mask */
  71 #define NBPF_CHAN_CFG_TCM       0x2000000       /* DMATCO interrupt Mask */
  72 #define NBPF_CHAN_CFG_SBE       0x8000000       /* Sweep Buffer Enable */
  73 #define NBPF_CHAN_CFG_RSEL      0x10000000      /* RM: Register Set sELect */
  74 #define NBPF_CHAN_CFG_RSW       0x20000000      /* RM: Register Select sWitch */
  75 #define NBPF_CHAN_CFG_REN       0x40000000      /* RM: Register Set Enable */
  76 #define NBPF_CHAN_CFG_DMS       0x80000000      /* 0: register mode (RM), 1: link mode (LM) */
  77
  78 #define NBPF_CHAN_NXLA  0x38
  79 #define NBPF_CHAN_CRLA  0x3c
  80
  81 /* Link Header field */
  82 #define NBPF_HEADER_LV  1
  83 #define NBPF_HEADER_LE  2
  84 #define NBPF_HEADER_WBD 4
  85 #define NBPF_HEADER_DIM 8
  86
  87 #define NBPF_CTRL       0x300
  88 #define NBPF_CTRL_PR    1               /* 0: fixed priority, 1: round robin */
  89 #define NBPF_CTRL_LVINT 2               /* DMAEND and DMAERR signalling: 0: pulse, 1: level */
  90
  91 #define NBPF_DSTAT_ER   0x314
  92 #define NBPF_DSTAT_END  0x318
  93
  94 #define NBPF_DMA_BUSWIDTHS \
  95         (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
  96          BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  97          BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  98          BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  99          BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
 100
 101 struct nbpf_config {
 102         int num_channels;
 103         int buffer_size;
 104 };
 105
 106 /*
 107  * We've got 3 types of objects, used to describe DMA transfers:
 108  * 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
 109  *      in it, used to communicate with the user
 110  * 2. hardware DMA link descriptors, that we pass to DMAC for DMA transfer
 111  *      queuing, these must be DMAable, using either the streaming DMA API or
 112  *      allocated from coherent memory - one per SG segment
 113  * 3. one per SG segment descriptors, used to manage HW link descriptors from
 114  *      (2). They do not have to be DMAable. They can either be (a) allocated
 115  *      together with link descriptors as mixed (DMA / CPU) objects, or (b)
 116  *      separately. Even if allocated separately it would be best to link them
 117  *      to link descriptors once during channel resource allocation and always
 118  *      use them as a single object.
 119  * Therefore for both cases (a) and (b) at run-time objects (2) and (3) shall be
 120  * treated as a single SG segment descriptor.
 121  */
 122
 123 struct nbpf_link_reg {
 124         u32     header;
 125         u32     src_addr;
 126         u32     dst_addr;
 127         u32     transaction_size;
 128         u32     config;
 129         u32     interval;
 130         u32     extension;
 131         u32     next;
 132 } __packed;
 133
 134 struct nbpf_device;
 135 struct nbpf_channel;
 136 struct nbpf_desc;
 137
 138 struct nbpf_link_desc {
 139         struct nbpf_link_reg *hwdesc;
 140         dma_addr_t hwdesc_dma_addr;
 141         struct nbpf_desc *desc;
 142         struct list_head node;
 143 };
 144
 145 /**
 146  * struct nbpf_desc - DMA transfer descriptor
 147  * @async_tx:   dmaengine object
 148  * @user_wait:  waiting for a user ack
 149  * @length:     total transfer length
 150  * @sg:         list of hardware descriptors, represented by struct nbpf_link_desc
 151  * @node:       member in channel descriptor lists
 152  */
 153 struct nbpf_desc {
 154         struct dma_async_tx_descriptor async_tx;
 155         bool user_wait;
 156         size_t length;
 157         struct nbpf_channel *chan;
 158         struct list_head sg;
 159         struct list_head node;
 160 };
 161
 162 /* Take a wild guess: allocate 4 segments per descriptor */
 163 #define NBPF_SEGMENTS_PER_DESC 4
 164 #define NBPF_DESCS_PER_PAGE ((PAGE_SIZE - sizeof(struct list_head)) /   \
 165         (sizeof(struct nbpf_desc) +                                     \
 166          NBPF_SEGMENTS_PER_DESC *                                       \
 167          (sizeof(struct nbpf_link_desc) + sizeof(struct nbpf_link_reg))))
 168 #define NBPF_SEGMENTS_PER_PAGE (NBPF_SEGMENTS_PER_DESC * NBPF_DESCS_PER_PAGE)
 169
 170 struct nbpf_desc_page {
 171         struct list_head node;
 172         struct nbpf_desc desc[NBPF_DESCS_PER_PAGE];
 173         struct nbpf_link_desc ldesc[NBPF_SEGMENTS_PER_PAGE];
 174         struct nbpf_link_reg hwdesc[NBPF_SEGMENTS_PER_PAGE];
 175 };
 176
 177 /**
 178  * struct nbpf_channel - one DMAC channel
 179  * @dma_chan:   standard dmaengine channel object
 180  * @base:       register address base
 181  * @nbpf:       DMAC
 182  * @name:       IRQ name
 183  * @irq:        IRQ number
 184  * @slave_addr: address for slave DMA
 185  * @slave_width:slave data size in bytes
 186  * @slave_burst:maximum slave burst size in bytes
 187  * @terminal:   DMA terminal, assigned to this channel
 188  * @dmarq_cfg:  DMA request line configuration - high / low, edge / level for NBPF_CHAN_CFG
 189  * @flags:      configuration flags from DT
 190  * @lock:       protect descriptor lists
 191  * @free_links: list of free link descriptors
 192  * @free:       list of free descriptors
 193  * @queued:     list of queued descriptors
 194  * @active:     list of descriptors, scheduled for processing
 195  * @done:       list of completed descriptors, waiting post-processing
 196  * @desc_page:  list of additionally allocated descriptor pages - if any
 197  */
 198 struct nbpf_channel {
 199         struct dma_chan dma_chan;
 200         struct tasklet_struct tasklet;
 201         void __iomem *base;
 202         struct nbpf_device *nbpf;
 203         char name[16];
 204         int irq;
 205         dma_addr_t slave_src_addr;
 206         size_t slave_src_width;
 207         size_t slave_src_burst;
 208         dma_addr_t slave_dst_addr;
 209         size_t slave_dst_width;
 210         size_t slave_dst_burst;
 211         unsigned int terminal;
 212         u32 dmarq_cfg;
 213         unsigned long flags;
 214         spinlock_t lock;
 215         struct list_head free_links;
 216         struct list_head free;
 217         struct list_head queued;
 218         struct list_head active;
 219         struct list_head done;
 220         struct list_head desc_page;
 221         struct nbpf_desc *running;
 222         bool paused;
 223 };
 224
 225 struct nbpf_device {
 226         struct dma_device dma_dev;
 227         void __iomem *base;
 228         u32 max_burst_mem_read;
 229         u32 max_burst_mem_write;
 230         struct clk *clk;
 231         const struct nbpf_config *config;
 232         unsigned int eirq;
 233         struct nbpf_channel chan[];
 234 };
 235
 236 enum nbpf_model {
 237         NBPF1B4,
 238         NBPF1B8,
 239         NBPF1B16,
 240         NBPF4B4,
 241         NBPF4B8,
 242         NBPF4B16,
 243         NBPF8B4,
 244         NBPF8B8,
 245         NBPF8B16,
 246 };
 247
 248 static struct nbpf_config nbpf_cfg[] = {
 249         [NBPF1B4] = {
 250                 .num_channels = 1,
 251                 .buffer_size = 4,
 252         },
 253         [NBPF1B8] = {
 254                 .num_channels = 1,
 255                 .buffer_size = 8,
 256         },
 257         [NBPF1B16] = {
 258                 .num_channels = 1,
 259                 .buffer_size = 16,
 260         },
 261         [NBPF4B4] = {
 262                 .num_channels = 4,
 263                 .buffer_size = 4,
 264         },
 265         [NBPF4B8] = {
 266                 .num_channels = 4,
 267                 .buffer_size = 8,
 268         },
 269         [NBPF4B16] = {
 270                 .num_channels = 4,
 271                 .buffer_size = 16,
 272         },
 273         [NBPF8B4] = {
 274                 .num_channels = 8,
 275                 .buffer_size = 4,
 276         },
 277         [NBPF8B8] = {
 278                 .num_channels = 8,
 279                 .buffer_size = 8,
 280         },
 281         [NBPF8B16] = {
 282                 .num_channels = 8,
 283                 .buffer_size = 16,
 284         },
 285 };
 286
 287 #define nbpf_to_chan(d) container_of(d, struct nbpf_channel, dma_chan)
 288
 289 /*
 290  * dmaengine drivers seem to have a lot in common and instead of sharing more
 291  * code, they reimplement those common algorithms independently. In this driver
 292  * we try to separate the hardware-specific part from the (largely) generic
 293  * part. This improves code readability and makes it possible in the future to
 294  * reuse the generic code in form of a helper library. That generic code should
 295  * be suitable for various DMA controllers, using transfer descriptors in RAM
 296  * and pushing one SG list at a time to the DMA controller.
 297  */
 298
 299 /*              Hardware-specific part          */
 300
 301 static inline u32 nbpf_chan_read(struct nbpf_channel *chan,
 302                                  unsigned int offset)
 303 {
 304         u32 data = ioread32(chan->base + offset);
 305         dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
 306                 __func__, chan->base, offset, data);
 307         return data;
 308 }
 309
 310 static inline void nbpf_chan_write(struct nbpf_channel *chan,
 311                                    unsigned int offset, u32 data)
 312 {
 313         iowrite32(data, chan->base + offset);
 314         dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
 315                 __func__, chan->base, offset, data);
 316 }
 317
 318 static inline u32 nbpf_read(struct nbpf_device *nbpf,
 319                             unsigned int offset)
 320 {
 321         u32 data = ioread32(nbpf->base + offset);
 322         dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
 323                 __func__, nbpf->base, offset, data);
 324         return data;
 325 }
 326
 327 static inline void nbpf_write(struct nbpf_device *nbpf,
 328                               unsigned int offset, u32 data)
 329 {
 330         iowrite32(data, nbpf->base + offset);
 331         dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
 332                 __func__, nbpf->base, offset, data);
 333 }
 334
 335 static void nbpf_chan_halt(struct nbpf_channel *chan)
 336 {
 337         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
 338 }
 339
 340 static bool nbpf_status_get(struct nbpf_channel *chan)
 341 {
 342         u32 status = nbpf_read(chan->nbpf, NBPF_DSTAT_END);
 343
 344         return status & BIT(chan - chan->nbpf->chan);
 345 }
 346
 347 static void nbpf_status_ack(struct nbpf_channel *chan)
 348 {
 349         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREND);
 350 }
 351
 352 static u32 nbpf_error_get(struct nbpf_device *nbpf)
 353 {
 354         return nbpf_read(nbpf, NBPF_DSTAT_ER);
 355 }
 356
 357 static struct nbpf_channel *nbpf_error_get_channel(struct nbpf_device *nbpf, u32 error)
 358 {
 359         return nbpf->chan + __ffs(error);
 360 }
 361
 362 static void nbpf_error_clear(struct nbpf_channel *chan)
 363 {
 364         u32 status;
 365         int i;
 366
 367         /* Stop the channel, make sure DMA has been aborted */
 368         nbpf_chan_halt(chan);
 369
 370         for (i = 1000; i; i--) {
 371                 status = nbpf_chan_read(chan, NBPF_CHAN_STAT);
 372                 if (!(status & NBPF_CHAN_STAT_TACT))
 373                         break;
 374                 cpu_relax();
 375         }
 376
 377         if (!i)
 378                 dev_err(chan->dma_chan.device->dev,
 379                         "%s(): abort timeout, channel status 0x%x\n", __func__, status);
 380
 381         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SWRST);
 382 }
 383
 384 static int nbpf_start(struct nbpf_desc *desc)
 385 {
 386         struct nbpf_channel *chan = desc->chan;
 387         struct nbpf_link_desc *ldesc = list_first_entry(&desc->sg, struct nbpf_link_desc, node);
 388
 389         nbpf_chan_write(chan, NBPF_CHAN_NXLA, (u32)ldesc->hwdesc_dma_addr);
 390         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETEN | NBPF_CHAN_CTRL_CLRSUS);
 391         chan->paused = false;
 392
 393         /* Software trigger MEMCPY - only MEMCPY uses the block mode */
 394         if (ldesc->hwdesc->config & NBPF_CHAN_CFG_TM)
 395                 nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_STG);
 396
 397         dev_dbg(chan->nbpf->dma_dev.dev, "%s(): next 0x%x, cur 0x%x\n", __func__,
 398                 nbpf_chan_read(chan, NBPF_CHAN_NXLA), nbpf_chan_read(chan, NBPF_CHAN_CRLA));
 399
 400         return 0;
 401 }
 402
 403 static void nbpf_chan_prepare(struct nbpf_channel *chan)
 404 {
 405         chan->dmarq_cfg = (chan->flags & NBPF_SLAVE_RQ_HIGH ? NBPF_CHAN_CFG_HIEN : 0) |
 406                 (chan->flags & NBPF_SLAVE_RQ_LOW ? NBPF_CHAN_CFG_LOEN : 0) |
 407                 (chan->flags & NBPF_SLAVE_RQ_LEVEL ?
 408                  NBPF_CHAN_CFG_LVL | (NBPF_CHAN_CFG_AM & 0x200) : 0) |
 409                 chan->terminal;
 410 }
 411
 412 static void nbpf_chan_prepare_default(struct nbpf_channel *chan)
 413 {
 414         /* Don't output DMAACK */
 415         chan->dmarq_cfg = NBPF_CHAN_CFG_AM & 0x400;
 416         chan->terminal = 0;
 417         chan->flags = 0;
 418 }
 419
 420 static void nbpf_chan_configure(struct nbpf_channel *chan)
 421 {
 422         /*
 423          * We assume, that only the link mode and DMA request line configuration
 424          * have to be set in the configuration register manually. Dynamic
 425          * per-transfer configuration will be loaded from transfer descriptors.
 426          */
 427         nbpf_chan_write(chan, NBPF_CHAN_CFG, NBPF_CHAN_CFG_DMS | chan->dmarq_cfg);
 428 }
 429
 430 static u32 nbpf_xfer_ds(struct nbpf_device *nbpf, size_t size,
 431                         enum dma_transfer_direction direction)
 432 {
 433         int max_burst = nbpf->config->buffer_size * 8;
 434
 435         if (nbpf->max_burst_mem_read || nbpf->max_burst_mem_write) {
 436                 switch (direction) {
 437                 case DMA_MEM_TO_MEM:
 438                         max_burst = min_not_zero(nbpf->max_burst_mem_read,
 439                                                  nbpf->max_burst_mem_write);
 440                         break;
 441                 case DMA_MEM_TO_DEV:
 442                         if (nbpf->max_burst_mem_read)
 443                                 max_burst = nbpf->max_burst_mem_read;
 444                         break;
 445                 case DMA_DEV_TO_MEM:
 446                         if (nbpf->max_burst_mem_write)
 447                                 max_burst = nbpf->max_burst_mem_write;
 448                         break;
 449                 case DMA_DEV_TO_DEV:
 450                 default:
 451                         break;
 452                 }
 453         }
 454
 455         /* Maximum supported bursts depend on the buffer size */
 456         return min_t(int, __ffs(size), ilog2(max_burst));
 457 }
 458
 459 static size_t nbpf_xfer_size(struct nbpf_device *nbpf,
 460                              enum dma_slave_buswidth width, u32 burst)
 461 {
 462         size_t size;
 463
 464         if (!burst)
 465                 burst = 1;
 466
 467         switch (width) {
 468         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 469                 size = 8 * burst;
 470                 break;
 471
 472         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 473                 size = 4 * burst;
 474                 break;
 475
 476         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 477                 size = 2 * burst;
 478                 break;
 479
 480         default:
 481                 pr_warn("%s(): invalid bus width %u\n", __func__, width);
 482                 /* fall through */
 483         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 484                 size = burst;
 485         }
 486
 487         return nbpf_xfer_ds(nbpf, size, DMA_TRANS_NONE);
 488 }
 489
 490 /*
 491  * We need a way to recognise slaves, whose data is sent "raw" over the bus,
 492  * i.e. it isn't known in advance how many bytes will be received. Therefore
 493  * the slave driver has to provide a "large enough" buffer and either read the
 494  * buffer, when it is full, or detect, that some data has arrived, then wait for
 495  * a timeout, if no more data arrives - receive what's already there. We want to
 496  * handle such slaves in a special way to allow an optimised mode for other
 497  * users, for whom the amount of data is known in advance. So far there's no way
 498  * to recognise such slaves. We use a data-width check to distinguish between
 499  * the SD host and the PL011 UART.
 500  */
 501
 502 static int nbpf_prep_one(struct nbpf_link_desc *ldesc,
 503                          enum dma_transfer_direction direction,
 504                          dma_addr_t src, dma_addr_t dst, size_t size, bool last)
 505 {
 506         struct nbpf_link_reg *hwdesc = ldesc->hwdesc;
 507         struct nbpf_desc *desc = ldesc->desc;
 508         struct nbpf_channel *chan = desc->chan;
 509         struct device *dev = chan->dma_chan.device->dev;
 510         size_t mem_xfer, slave_xfer;
 511         bool can_burst;
 512
 513         hwdesc->header = NBPF_HEADER_WBD | NBPF_HEADER_LV |
 514                 (last ? NBPF_HEADER_LE : 0);
 515
 516         hwdesc->src_addr = src;
 517         hwdesc->dst_addr = dst;
 518         hwdesc->transaction_size = size;
 519
 520         /*
 521          * set config: SAD, DAD, DDS, SDS, etc.
 522          * Note on transfer sizes: the DMAC can perform unaligned DMA transfers,
 523          * but it is important to have transaction size a multiple of both
 524          * receiver and transmitter transfer sizes. It is also possible to use
 525          * different RAM and device transfer sizes, and it does work well with
 526          * some devices, e.g. with V08R07S01E SD host controllers, which can use
 527          * 128 byte transfers. But this doesn't work with other devices,
 528          * especially when the transaction size is unknown. This is the case,
 529          * e.g. with serial drivers like amba-pl011.c. For reception it sets up
 530          * the transaction size of 4K and if fewer bytes are received, it
 531          * pauses DMA and reads out data received via DMA as well as those left
 532          * in the Rx FIFO. For this to work with the RAM side using burst
 533          * transfers we enable the SBE bit and terminate the transfer in our
 534          * .device_pause handler.
 535          */
 536         mem_xfer = nbpf_xfer_ds(chan->nbpf, size, direction);
 537
 538         switch (direction) {
 539         case DMA_DEV_TO_MEM:
 540                 can_burst = chan->slave_src_width >= 3;
 541                 slave_xfer = min(mem_xfer, can_burst ?
 542                                  chan->slave_src_burst : chan->slave_src_width);
 543                 /*
 544                  * Is the slave narrower than 64 bits, i.e. isn't using the full
 545                  * bus width and cannot use bursts?
 546                  */
 547                 if (mem_xfer > chan->slave_src_burst && !can_burst)
 548                         mem_xfer = chan->slave_src_burst;
 549                 /* Device-to-RAM DMA is unreliable without REQD set */
 550                 hwdesc->config = NBPF_CHAN_CFG_SAD | (NBPF_CHAN_CFG_DDS & (mem_xfer << 16)) |
 551                         (NBPF_CHAN_CFG_SDS & (slave_xfer << 12)) | NBPF_CHAN_CFG_REQD |
 552                         NBPF_CHAN_CFG_SBE;
 553                 break;
 554
 555         case DMA_MEM_TO_DEV:
 556                 slave_xfer = min(mem_xfer, chan->slave_dst_width >= 3 ?
 557                                  chan->slave_dst_burst : chan->slave_dst_width);
 558                 hwdesc->config = NBPF_CHAN_CFG_DAD | (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
 559                         (NBPF_CHAN_CFG_DDS & (slave_xfer << 16)) | NBPF_CHAN_CFG_REQD;
 560                 break;
 561
 562         case DMA_MEM_TO_MEM:
 563                 hwdesc->config = NBPF_CHAN_CFG_TCM | NBPF_CHAN_CFG_TM |
 564                         (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
 565                         (NBPF_CHAN_CFG_DDS & (mem_xfer << 16));
 566                 break;
 567
 568         default:
 569                 return -EINVAL;
 570         }
 571
 572         hwdesc->config |= chan->dmarq_cfg | (last ? 0 : NBPF_CHAN_CFG_DEM) |
 573                 NBPF_CHAN_CFG_DMS;
 574
 575         dev_dbg(dev, "%s(): desc @ %pad: hdr 0x%x, cfg 0x%x, %zu @ %pad -> %pad\n",
 576                 __func__, &ldesc->hwdesc_dma_addr, hwdesc->header,
 577                 hwdesc->config, size, &src, &dst);
 578
 579         dma_sync_single_for_device(dev, ldesc->hwdesc_dma_addr, sizeof(*hwdesc),
 580                                    DMA_TO_DEVICE);
 581
 582         return 0;
 583 }
 584
 585 static size_t nbpf_bytes_left(struct nbpf_channel *chan)
 586 {
 587         return nbpf_chan_read(chan, NBPF_CHAN_CUR_TR_BYTE);
 588 }
 589
 590 static void nbpf_configure(struct nbpf_device *nbpf)
 591 {
 592         nbpf_write(nbpf, NBPF_CTRL, NBPF_CTRL_LVINT);
 593 }
 594
 595 /*              Generic part                    */
 596
 597 /* DMA ENGINE functions */
 598 static void nbpf_issue_pending(struct dma_chan *dchan)
 599 {
 600         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 601         unsigned long flags;
 602
 603         dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
 604
 605         spin_lock_irqsave(&chan->lock, flags);
 606         if (list_empty(&chan->queued))
 607                 goto unlock;
 608
 609         list_splice_tail_init(&chan->queued, &chan->active);
 610
 611         if (!chan->running) {
 612                 struct nbpf_desc *desc = list_first_entry(&chan->active,
 613                                                 struct nbpf_desc, node);
 614                 if (!nbpf_start(desc))
 615                         chan->running = desc;
 616         }
 617
 618 unlock:
 619         spin_unlock_irqrestore(&chan->lock, flags);
 620 }
 621
 622 static enum dma_status nbpf_tx_status(struct dma_chan *dchan,
 623                 dma_cookie_t cookie, struct dma_tx_state *state)
 624 {
 625         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 626         enum dma_status status = dma_cookie_status(dchan, cookie, state);
 627
 628         if (state) {
 629                 dma_cookie_t running;
 630                 unsigned long flags;
 631
 632                 spin_lock_irqsave(&chan->lock, flags);
 633                 running = chan->running ? chan->running->async_tx.cookie : -EINVAL;
 634
 635                 if (cookie == running) {
 636                         state->residue = nbpf_bytes_left(chan);
 637                         dev_dbg(dchan->device->dev, "%s(): residue %u\n", __func__,
 638                                 state->residue);
 639                 } else if (status == DMA_IN_PROGRESS) {
 640                         struct nbpf_desc *desc;
 641                         bool found = false;
 642
 643                         list_for_each_entry(desc, &chan->active, node)
 644                                 if (desc->async_tx.cookie == cookie) {
 645                                         found = true;
 646                                         break;
 647                                 }
 648
 649                         if (!found)
 650                                 list_for_each_entry(desc, &chan->queued, node)
 651                                         if (desc->async_tx.cookie == cookie) {
 652                                                 found = true;
 653                                                 break;
 654
 655                                         }
 656
 657                         state->residue = found ? desc->length : 0;
 658                 }
 659
 660                 spin_unlock_irqrestore(&chan->lock, flags);
 661         }
 662
 663         if (chan->paused)
 664                 status = DMA_PAUSED;
 665
 666         return status;
 667 }
 668
 669 static dma_cookie_t nbpf_tx_submit(struct dma_async_tx_descriptor *tx)
 670 {
 671         struct nbpf_desc *desc = container_of(tx, struct nbpf_desc, async_tx);
 672         struct nbpf_channel *chan = desc->chan;
 673         unsigned long flags;
 674         dma_cookie_t cookie;
 675
 676         spin_lock_irqsave(&chan->lock, flags);
 677         cookie = dma_cookie_assign(tx);
 678         list_add_tail(&desc->node, &chan->queued);
 679         spin_unlock_irqrestore(&chan->lock, flags);
 680
 681         dev_dbg(chan->dma_chan.device->dev, "Entry %s(%d)\n", __func__, cookie);
 682
 683         return cookie;
 684 }
 685
 686 static int nbpf_desc_page_alloc(struct nbpf_channel *chan)
 687 {
 688         struct dma_chan *dchan = &chan->dma_chan;
 689         struct nbpf_desc_page *dpage = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA);
 690         struct nbpf_link_desc *ldesc;
 691         struct nbpf_link_reg *hwdesc;
 692         struct nbpf_desc *desc;
 693         LIST_HEAD(head);
 694         LIST_HEAD(lhead);
 695         int i;
 696         struct device *dev = dchan->device->dev;
 697
 698         if (!dpage)
 699                 return -ENOMEM;
 700
 701         dev_dbg(dev, "%s(): alloc %lu descriptors, %lu segments, total alloc %zu\n",
 702                 __func__, NBPF_DESCS_PER_PAGE, NBPF_SEGMENTS_PER_PAGE, sizeof(*dpage));
 703
 704         for (i = 0, ldesc = dpage->ldesc, hwdesc = dpage->hwdesc;
 705              i < ARRAY_SIZE(dpage->ldesc);
 706              i++, ldesc++, hwdesc++) {
 707                 ldesc->hwdesc = hwdesc;
 708                 list_add_tail(&ldesc->node, &lhead);
 709                 ldesc->hwdesc_dma_addr = dma_map_single(dchan->device->dev,
 710                                         hwdesc, sizeof(*hwdesc), DMA_TO_DEVICE);
 711
 712                 dev_dbg(dev, "%s(): mapped 0x%p to %pad\n", __func__,
 713                         hwdesc, &ldesc->hwdesc_dma_addr);
 714         }
 715
 716         for (i = 0, desc = dpage->desc;
 717              i < ARRAY_SIZE(dpage->desc);
 718              i++, desc++) {
 719                 dma_async_tx_descriptor_init(&desc->async_tx, dchan);
 720                 desc->async_tx.tx_submit = nbpf_tx_submit;
 721                 desc->chan = chan;
 722                 INIT_LIST_HEAD(&desc->sg);
 723                 list_add_tail(&desc->node, &head);
 724         }
 725
 726         /*
 727          * This function cannot be called from interrupt context, so, no need to
 728          * save flags
 729          */
 730         spin_lock_irq(&chan->lock);
 731         list_splice_tail(&lhead, &chan->free_links);
 732         list_splice_tail(&head, &chan->free);
 733         list_add(&dpage->node, &chan->desc_page);
 734         spin_unlock_irq(&chan->lock);
 735
 736         return ARRAY_SIZE(dpage->desc);
 737 }
 738
 739 static void nbpf_desc_put(struct nbpf_desc *desc)
 740 {
 741         struct nbpf_channel *chan = desc->chan;
 742         struct nbpf_link_desc *ldesc, *tmp;
 743         unsigned long flags;
 744
 745         spin_lock_irqsave(&chan->lock, flags);
 746         list_for_each_entry_safe(ldesc, tmp, &desc->sg, node)
 747                 list_move(&ldesc->node, &chan->free_links);
 748
 749         list_add(&desc->node, &chan->free);
 750         spin_unlock_irqrestore(&chan->lock, flags);
 751 }
 752
 753 static void nbpf_scan_acked(struct nbpf_channel *chan)
 754 {
 755         struct nbpf_desc *desc, *tmp;
 756         unsigned long flags;
 757         LIST_HEAD(head);
 758
 759         spin_lock_irqsave(&chan->lock, flags);
 760         list_for_each_entry_safe(desc, tmp, &chan->done, node)
 761                 if (async_tx_test_ack(&desc->async_tx) && desc->user_wait) {
 762                         list_move(&desc->node, &head);
 763                         desc->user_wait = false;
 764                 }
 765         spin_unlock_irqrestore(&chan->lock, flags);
 766
 767         list_for_each_entry_safe(desc, tmp, &head, node) {
 768                 list_del(&desc->node);
 769                 nbpf_desc_put(desc);
 770         }
 771 }
 772
 773 /*
 774  * We have to allocate descriptors with the channel lock dropped. This means,
 775  * before we re-acquire the lock buffers can be taken already, so we have to
 776  * re-check after re-acquiring the lock and possibly retry, if buffers are gone
 777  * again.
 778  */
 779 static struct nbpf_desc *nbpf_desc_get(struct nbpf_channel *chan, size_t len)
 780 {
 781         struct nbpf_desc *desc = NULL;
 782         struct nbpf_link_desc *ldesc, *prev = NULL;
 783
 784         nbpf_scan_acked(chan);
 785
 786         spin_lock_irq(&chan->lock);
 787
 788         do {
 789                 int i = 0, ret;
 790
 791                 if (list_empty(&chan->free)) {
 792                         /* No more free descriptors */
 793                         spin_unlock_irq(&chan->lock);
 794                         ret = nbpf_desc_page_alloc(chan);
 795                         if (ret < 0)
 796                                 return NULL;
 797                         spin_lock_irq(&chan->lock);
 798                         continue;
 799                 }
 800                 desc = list_first_entry(&chan->free, struct nbpf_desc, node);
 801                 list_del(&desc->node);
 802
 803                 do {
 804                         if (list_empty(&chan->free_links)) {
 805                                 /* No more free link descriptors */
 806                                 spin_unlock_irq(&chan->lock);
 807                                 ret = nbpf_desc_page_alloc(chan);
 808                                 if (ret < 0) {
 809                                         nbpf_desc_put(desc);
 810                                         return NULL;
 811                                 }
 812                                 spin_lock_irq(&chan->lock);
 813                                 continue;
 814                         }
 815
 816                         ldesc = list_first_entry(&chan->free_links,
 817                                                  struct nbpf_link_desc, node);
 818                         ldesc->desc = desc;
 819                         if (prev)
 820                                 prev->hwdesc->next = (u32)ldesc->hwdesc_dma_addr;
 821
 822                         prev = ldesc;
 823                         list_move_tail(&ldesc->node, &desc->sg);
 824
 825                         i++;
 826                 } while (i < len);
 827         } while (!desc);
 828
 829         prev->hwdesc->next = 0;
 830
 831         spin_unlock_irq(&chan->lock);
 832
 833         return desc;
 834 }
 835
 836 static void nbpf_chan_idle(struct nbpf_channel *chan)
 837 {
 838         struct nbpf_desc *desc, *tmp;
 839         unsigned long flags;
 840         LIST_HEAD(head);
 841
 842         spin_lock_irqsave(&chan->lock, flags);
 843
 844         list_splice_init(&chan->done, &head);
 845         list_splice_init(&chan->active, &head);
 846         list_splice_init(&chan->queued, &head);
 847
 848         chan->running = NULL;
 849
 850         spin_unlock_irqrestore(&chan->lock, flags);
 851
 852         list_for_each_entry_safe(desc, tmp, &head, node) {
 853                 dev_dbg(chan->nbpf->dma_dev.dev, "%s(): force-free desc %p cookie %d\n",
 854                         __func__, desc, desc->async_tx.cookie);
 855                 list_del(&desc->node);
 856                 nbpf_desc_put(desc);
 857         }
 858 }
 859
 860 static int nbpf_pause(struct dma_chan *dchan)
 861 {
 862         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 863
 864         dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
 865
 866         chan->paused = true;
 867         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETSUS);
 868         /* See comment in nbpf_prep_one() */
 869         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
 870
 871         return 0;
 872 }
 873
 874 static int nbpf_terminate_all(struct dma_chan *dchan)
 875 {
 876         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 877
 878         dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
 879         dev_dbg(dchan->device->dev, "Terminating\n");
 880
 881         nbpf_chan_halt(chan);
 882         nbpf_chan_idle(chan);
 883
 884         return 0;
 885 }
 886
 887 static int nbpf_config(struct dma_chan *dchan,
 888                        struct dma_slave_config *config)
 889 {
 890         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 891
 892         dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
 893
 894         /*
 895          * We could check config->slave_id to match chan->terminal here,
 896          * but with DT they would be coming from the same source, so
 897          * such a check would be superflous
 898          */
 899
 900         chan->slave_dst_addr = config->dst_addr;
 901         chan->slave_dst_width = nbpf_xfer_size(chan->nbpf,
 902                                                config->dst_addr_width, 1);
 903         chan->slave_dst_burst = nbpf_xfer_size(chan->nbpf,
 904                                                config->dst_addr_width,
 905                                                config->dst_maxburst);
 906         chan->slave_src_addr = config->src_addr;
 907         chan->slave_src_width = nbpf_xfer_size(chan->nbpf,
 908                                                config->src_addr_width, 1);
 909         chan->slave_src_burst = nbpf_xfer_size(chan->nbpf,
 910                                                config->src_addr_width,
 911                                                config->src_maxburst);
 912
 913         return 0;
 914 }
 915
 916 static struct dma_async_tx_descriptor *nbpf_prep_sg(struct nbpf_channel *chan,
 917                 struct scatterlist *src_sg, struct scatterlist *dst_sg,
 918                 size_t len, enum dma_transfer_direction direction,
 919                 unsigned long flags)
 920 {
 921         struct nbpf_link_desc *ldesc;
 922         struct scatterlist *mem_sg;
 923         struct nbpf_desc *desc;
 924         bool inc_src, inc_dst;
 925         size_t data_len = 0;
 926         int i = 0;
 927
 928         switch (direction) {
 929         case DMA_DEV_TO_MEM:
 930                 mem_sg = dst_sg;
 931                 inc_src = false;
 932                 inc_dst = true;
 933                 break;
 934
 935         case DMA_MEM_TO_DEV:
 936                 mem_sg = src_sg;
 937                 inc_src = true;
 938                 inc_dst = false;
 939                 break;
 940
 941         default:
 942         case DMA_MEM_TO_MEM:
 943                 mem_sg = src_sg;
 944                 inc_src = true;
 945                 inc_dst = true;
 946         }
 947
 948         desc = nbpf_desc_get(chan, len);
 949         if (!desc)
 950                 return NULL;
 951
 952         desc->async_tx.flags = flags;
 953         desc->async_tx.cookie = -EBUSY;
 954         desc->user_wait = false;
 955
 956         /*
 957          * This is a private descriptor list, and we own the descriptor. No need
 958          * to lock.
 959          */
 960         list_for_each_entry(ldesc, &desc->sg, node) {
 961                 int ret = nbpf_prep_one(ldesc, direction,
 962                                         sg_dma_address(src_sg),
 963                                         sg_dma_address(dst_sg),
 964                                         sg_dma_len(mem_sg),
 965                                         i == len - 1);
 966                 if (ret < 0) {
 967                         nbpf_desc_put(desc);
 968                         return NULL;
 969                 }
 970                 data_len += sg_dma_len(mem_sg);
 971                 if (inc_src)
 972                         src_sg = sg_next(src_sg);
 973                 if (inc_dst)
 974                         dst_sg = sg_next(dst_sg);
 975                 mem_sg = direction == DMA_DEV_TO_MEM ? dst_sg : src_sg;
 976                 i++;
 977         }
 978
 979         desc->length = data_len;
 980
 981         /* The user has to return the descriptor to us ASAP via .tx_submit() */
 982         return &desc->async_tx;
 983 }
 984
 985 static struct dma_async_tx_descriptor *nbpf_prep_memcpy(
 986         struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
 987         size_t len, unsigned long flags)
 988 {
 989         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 990         struct scatterlist dst_sg;
 991         struct scatterlist src_sg;
 992
 993         sg_init_table(&dst_sg, 1);
 994         sg_init_table(&src_sg, 1);
 995
 996         sg_dma_address(&dst_sg) = dst;
 997         sg_dma_address(&src_sg) = src;
 998
 999         sg_dma_len(&dst_sg) = len;
1000         sg_dma_len(&src_sg) = len;
1001
1002         dev_dbg(dchan->device->dev, "%s(): %zu @ %pad -> %pad\n",
1003                 __func__, len, &src, &dst);
1004
1005         return nbpf_prep_sg(chan, &src_sg, &dst_sg, 1,
1006                             DMA_MEM_TO_MEM, flags);
1007 }
1008
1009 static struct dma_async_tx_descriptor *nbpf_prep_slave_sg(
1010         struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
1011         enum dma_transfer_direction direction, unsigned long flags, void *context)
1012 {
1013         struct nbpf_channel *chan = nbpf_to_chan(dchan);
1014         struct scatterlist slave_sg;
1015
1016         dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
1017
1018         sg_init_table(&slave_sg, 1);
1019
1020         switch (direction) {
1021         case DMA_MEM_TO_DEV:
1022                 sg_dma_address(&slave_sg) = chan->slave_dst_addr;
1023                 return nbpf_prep_sg(chan, sgl, &slave_sg, sg_len,
1024                                     direction, flags);
1025
1026         case DMA_DEV_TO_MEM:
1027                 sg_dma_address(&slave_sg) = chan->slave_src_addr;
1028                 return nbpf_prep_sg(chan, &slave_sg, sgl, sg_len,
1029                                     direction, flags);
1030
1031         default:
1032                 return NULL;
1033         }
1034 }
1035
1036 static int nbpf_alloc_chan_resources(struct dma_chan *dchan)
1037 {
1038         struct nbpf_channel *chan = nbpf_to_chan(dchan);
1039         int ret;
1040
1041         INIT_LIST_HEAD(&chan->free);
1042         INIT_LIST_HEAD(&chan->free_links);
1043         INIT_LIST_HEAD(&chan->queued);
1044         INIT_LIST_HEAD(&chan->active);
1045         INIT_LIST_HEAD(&chan->done);
1046
1047         ret = nbpf_desc_page_alloc(chan);
1048         if (ret < 0)
1049                 return ret;
1050
1051         dev_dbg(dchan->device->dev, "Entry %s(): terminal %u\n", __func__,
1052                 chan->terminal);
1053
1054         nbpf_chan_configure(chan);
1055
1056         return ret;
1057 }
1058
1059 static void nbpf_free_chan_resources(struct dma_chan *dchan)
1060 {
1061         struct nbpf_channel *chan = nbpf_to_chan(dchan);
1062         struct nbpf_desc_page *dpage, *tmp;
1063
1064         dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
1065
1066         nbpf_chan_halt(chan);
1067         nbpf_chan_idle(chan);
1068         /* Clean up for if a channel is re-used for MEMCPY after slave DMA */
1069         nbpf_chan_prepare_default(chan);
1070
1071         list_for_each_entry_safe(dpage, tmp, &chan->desc_page, node) {
1072                 struct nbpf_link_desc *ldesc;
1073                 int i;
1074                 list_del(&dpage->node);
1075                 for (i = 0, ldesc = dpage->ldesc;
1076                      i < ARRAY_SIZE(dpage->ldesc);
1077                      i++, ldesc++)
1078                         dma_unmap_single(dchan->device->dev, ldesc->hwdesc_dma_addr,
1079                                          sizeof(*ldesc->hwdesc), DMA_TO_DEVICE);
1080                 free_page((unsigned long)dpage);
1081         }
1082 }
1083
1084 static struct dma_chan *nbpf_of_xlate(struct of_phandle_args *dma_spec,
1085                                       struct of_dma *ofdma)
1086 {
1087         struct nbpf_device *nbpf = ofdma->of_dma_data;
1088         struct dma_chan *dchan;
1089         struct nbpf_channel *chan;
1090
1091         if (dma_spec->args_count != 2)
1092                 return NULL;
1093
1094         dchan = dma_get_any_slave_channel(&nbpf->dma_dev);
1095         if (!dchan)
1096                 return NULL;
1097
1098         dev_dbg(dchan->device->dev, "Entry %s(%s)\n", __func__,
1099                 dma_spec->np->name);
1100
1101         chan = nbpf_to_chan(dchan);
1102
1103         chan->terminal = dma_spec->args[0];
1104         chan->flags = dma_spec->args[1];
1105
1106         nbpf_chan_prepare(chan);
1107         nbpf_chan_configure(chan);
1108
1109         return dchan;
1110 }
1111
1112 static void nbpf_chan_tasklet(unsigned long data)
1113 {
1114         struct nbpf_channel *chan = (struct nbpf_channel *)data;
1115         struct nbpf_desc *desc, *tmp;
1116         struct dmaengine_desc_callback cb;
1117
1118         while (!list_empty(&chan->done)) {
1119                 bool found = false, must_put, recycling = false;
1120
1121                 spin_lock_irq(&chan->lock);
1122
1123                 list_for_each_entry_safe(desc, tmp, &chan->done, node) {
1124                         if (!desc->user_wait) {
1125                                 /* Newly completed descriptor, have to process */
1126                                 found = true;
1127                                 break;
1128                         } else if (async_tx_test_ack(&desc->async_tx)) {
1129                                 /*
1130                                  * This descriptor was waiting for a user ACK,
1131                                  * it can be recycled now.
1132                                  */
1133                                 list_del(&desc->node);
1134                                 spin_unlock_irq(&chan->lock);
1135                                 nbpf_desc_put(desc);
1136                                 recycling = true;
1137                                 break;
1138                         }
1139                 }
1140
1141                 if (recycling)
1142                         continue;
1143
1144                 if (!found) {
1145                         /* This can happen if TERMINATE_ALL has been called */
1146                         spin_unlock_irq(&chan->lock);
1147                         break;
1148                 }
1149
1150                 dma_cookie_complete(&desc->async_tx);
1151
1152                 /*
1153                  * With released lock we cannot dereference desc, maybe it's
1154                  * still on the "done" list
1155                  */
1156                 if (async_tx_test_ack(&desc->async_tx)) {
1157                         list_del(&desc->node);
1158                         must_put = true;
1159                 } else {
1160                         desc->user_wait = true;
1161                         must_put = false;
1162                 }
1163
1164                 dmaengine_desc_get_callback(&desc->async_tx, &cb);
1165
1166                 /* ack and callback completed descriptor */
1167                 spin_unlock_irq(&chan->lock);
1168
1169                 dmaengine_desc_callback_invoke(&cb, NULL);
1170
1171                 if (must_put)
1172                         nbpf_desc_put(desc);
1173         }
1174 }
1175
1176 static irqreturn_t nbpf_chan_irq(int irq, void *dev)
1177 {
1178         struct nbpf_channel *chan = dev;
1179         bool done = nbpf_status_get(chan);
1180         struct nbpf_desc *desc;
1181         irqreturn_t ret;
1182         bool bh = false;
1183
1184         if (!done)
1185                 return IRQ_NONE;
1186
1187         nbpf_status_ack(chan);
1188
1189         dev_dbg(&chan->dma_chan.dev->device, "%s()\n", __func__);
1190
1191         spin_lock(&chan->lock);
1192         desc = chan->running;
1193         if (WARN_ON(!desc)) {
1194                 ret = IRQ_NONE;
1195                 goto unlock;
1196         } else {
1197                 ret = IRQ_HANDLED;
1198                 bh = true;
1199         }
1200
1201         list_move_tail(&desc->node, &chan->done);
1202         chan->running = NULL;
1203
1204         if (!list_empty(&chan->active)) {
1205                 desc = list_first_entry(&chan->active,
1206                                         struct nbpf_desc, node);
1207                 if (!nbpf_start(desc))
1208                         chan->running = desc;
1209         }
1210
1211 unlock:
1212         spin_unlock(&chan->lock);
1213
1214         if (bh)
1215                 tasklet_schedule(&chan->tasklet);
1216
1217         return ret;
1218 }
1219
1220 static irqreturn_t nbpf_err_irq(int irq, void *dev)
1221 {
1222         struct nbpf_device *nbpf = dev;
1223         u32 error = nbpf_error_get(nbpf);
1224
1225         dev_warn(nbpf->dma_dev.dev, "DMA error IRQ %u\n", irq);
1226
1227         if (!error)
1228                 return IRQ_NONE;
1229
1230         do {
1231                 struct nbpf_channel *chan = nbpf_error_get_channel(nbpf, error);
1232                 /* On error: abort all queued transfers, no callback */
1233                 nbpf_error_clear(chan);
1234                 nbpf_chan_idle(chan);
1235                 error = nbpf_error_get(nbpf);
1236         } while (error);
1237
1238         return IRQ_HANDLED;
1239 }
1240
1241 static int nbpf_chan_probe(struct nbpf_device *nbpf, int n)
1242 {
1243         struct dma_device *dma_dev = &nbpf->dma_dev;
1244         struct nbpf_channel *chan = nbpf->chan + n;
1245         int ret;
1246
1247         chan->nbpf = nbpf;
1248         chan->base = nbpf->base + NBPF_REG_CHAN_OFFSET + NBPF_REG_CHAN_SIZE * n;
1249         INIT_LIST_HEAD(&chan->desc_page);
1250         spin_lock_init(&chan->lock);
1251         chan->dma_chan.device = dma_dev;
1252         dma_cookie_init(&chan->dma_chan);
1253         nbpf_chan_prepare_default(chan);
1254
1255         dev_dbg(dma_dev->dev, "%s(): channel %d: -> %p\n", __func__, n, chan->base);
1256
1257         snprintf(chan->name, sizeof(chan->name), "nbpf %d", n);
1258
1259         tasklet_init(&chan->tasklet, nbpf_chan_tasklet, (unsigned long)chan);
1260         ret = devm_request_irq(dma_dev->dev, chan->irq,
1261                         nbpf_chan_irq, IRQF_SHARED,
1262                         chan->name, chan);
1263         if (ret < 0)
1264                 return ret;
1265
1266         /* Add the channel to DMA device channel list */
1267         list_add_tail(&chan->dma_chan.device_node,
1268                       &dma_dev->channels);
1269
1270         return 0;
1271 }
1272
1273 static const struct of_device_id nbpf_match[] = {
1274         {.compatible = "renesas,nbpfaxi64dmac1b4",      .data = &nbpf_cfg[NBPF1B4]},
1275         {.compatible = "renesas,nbpfaxi64dmac1b8",      .data = &nbpf_cfg[NBPF1B8]},
1276         {.compatible = "renesas,nbpfaxi64dmac1b16",     .data = &nbpf_cfg[NBPF1B16]},
1277         {.compatible = "renesas,nbpfaxi64dmac4b4",      .data = &nbpf_cfg[NBPF4B4]},
1278         {.compatible = "renesas,nbpfaxi64dmac4b8",      .data = &nbpf_cfg[NBPF4B8]},
1279         {.compatible = "renesas,nbpfaxi64dmac4b16",     .data = &nbpf_cfg[NBPF4B16]},
1280         {.compatible = "renesas,nbpfaxi64dmac8b4",      .data = &nbpf_cfg[NBPF8B4]},
1281         {.compatible = "renesas,nbpfaxi64dmac8b8",      .data = &nbpf_cfg[NBPF8B8]},
1282         {.compatible = "renesas,nbpfaxi64dmac8b16",     .data = &nbpf_cfg[NBPF8B16]},
1283         {}
1284 };
1285 MODULE_DEVICE_TABLE(of, nbpf_match);
1286
1287 static int nbpf_probe(struct platform_device *pdev)
1288 {
1289         struct device *dev = &pdev->dev;
1290         struct device_node *np = dev->of_node;
1291         struct nbpf_device *nbpf;
1292         struct dma_device *dma_dev;
1293         struct resource *iomem, *irq_res;
1294         const struct nbpf_config *cfg;
1295         int num_channels;
1296         int ret, irq, eirq, i;
1297         int irqbuf[9] /* maximum 8 channels + error IRQ */;
1298         unsigned int irqs = 0;
1299
1300         BUILD_BUG_ON(sizeof(struct nbpf_desc_page) > PAGE_SIZE);
1301
1302         /* DT only */
1303         if (!np)
1304                 return -ENODEV;
1305
1306         cfg = of_device_get_match_data(dev);
1307         num_channels = cfg->num_channels;
1308
1309         nbpf = devm_kzalloc(dev, struct_size(nbpf, chan, num_channels),
1310                             GFP_KERNEL);
1311         if (!nbpf)
1312                 return -ENOMEM;
1313
1314         dma_dev = &nbpf->dma_dev;
1315         dma_dev->dev = dev;
1316
1317         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1318         nbpf->base = devm_ioremap_resource(dev, iomem);
1319         if (IS_ERR(nbpf->base))
1320                 return PTR_ERR(nbpf->base);
1321
1322         nbpf->clk = devm_clk_get(dev, NULL);
1323         if (IS_ERR(nbpf->clk))
1324                 return PTR_ERR(nbpf->clk);
1325
1326         of_property_read_u32(np, "max-burst-mem-read",
1327                              &nbpf->max_burst_mem_read);
1328         of_property_read_u32(np, "max-burst-mem-write",
1329                              &nbpf->max_burst_mem_write);
1330
1331         nbpf->config = cfg;
1332
1333         for (i = 0; irqs < ARRAY_SIZE(irqbuf); i++) {
1334                 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1335                 if (!irq_res)
1336                         break;
1337
1338                 for (irq = irq_res->start; irq <= irq_res->end;
1339                      irq++, irqs++)
1340                         irqbuf[irqs] = irq;
1341         }
1342
1343         /*
1344          * 3 IRQ resource schemes are supported:
1345          * 1. 1 shared IRQ for error and all channels
1346          * 2. 2 IRQs: one for error and one shared for all channels
1347          * 3. 1 IRQ for error and an own IRQ for each channel
1348          */
1349         if (irqs != 1 && irqs != 2 && irqs != num_channels + 1)
1350                 return -ENXIO;
1351
1352         if (irqs == 1) {
1353                 eirq = irqbuf[0];
1354
1355                 for (i = 0; i <= num_channels; i++)
1356                         nbpf->chan[i].irq = irqbuf[0];
1357         } else {
1358                 eirq = platform_get_irq_byname(pdev, "error");
1359                 if (eirq < 0)
1360                         return eirq;
1361
1362                 if (irqs == num_channels + 1) {
1363                         struct nbpf_channel *chan;
1364
1365                         for (i = 0, chan = nbpf->chan; i <= num_channels;
1366                              i++, chan++) {
1367                                 /* Skip the error IRQ */
1368                                 if (irqbuf[i] == eirq)
1369                                         i++;
1370                                 chan->irq = irqbuf[i];
1371                         }
1372
1373                         if (chan != nbpf->chan + num_channels)
1374                                 return -EINVAL;
1375                 } else {
1376                         /* 2 IRQs and more than one channel */
1377                         if (irqbuf[0] == eirq)
1378                                 irq = irqbuf[1];
1379                         else
1380                                 irq = irqbuf[0];
1381
1382                         for (i = 0; i <= num_channels; i++)
1383                                 nbpf->chan[i].irq = irq;
1384                 }
1385         }
1386
1387         ret = devm_request_irq(dev, eirq, nbpf_err_irq,
1388                                IRQF_SHARED, "dma error", nbpf);
1389         if (ret < 0)
1390                 return ret;
1391         nbpf->eirq = eirq;
1392
1393         INIT_LIST_HEAD(&dma_dev->channels);
1394
1395         /* Create DMA Channel */
1396         for (i = 0; i < num_channels; i++) {
1397                 ret = nbpf_chan_probe(nbpf, i);
1398                 if (ret < 0)
1399                         return ret;
1400         }
1401
1402         dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1403         dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
1404         dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
1405
1406         /* Common and MEMCPY operations */
1407         dma_dev->device_alloc_chan_resources
1408                 = nbpf_alloc_chan_resources;
1409         dma_dev->device_free_chan_resources = nbpf_free_chan_resources;
1410         dma_dev->device_prep_dma_memcpy = nbpf_prep_memcpy;
1411         dma_dev->device_tx_status = nbpf_tx_status;
1412         dma_dev->device_issue_pending = nbpf_issue_pending;
1413
1414         /*
1415          * If we drop support for unaligned MEMCPY buffer addresses and / or
1416          * lengths by setting
1417          * dma_dev->copy_align = 4;
1418          * then we can set transfer length to 4 bytes in nbpf_prep_one() for
1419          * DMA_MEM_TO_MEM
1420          */
1421
1422         /* Compulsory for DMA_SLAVE fields */
1423         dma_dev->device_prep_slave_sg = nbpf_prep_slave_sg;
1424         dma_dev->device_config = nbpf_config;
1425         dma_dev->device_pause = nbpf_pause;
1426         dma_dev->device_terminate_all = nbpf_terminate_all;
1427
1428         dma_dev->src_addr_widths = NBPF_DMA_BUSWIDTHS;
1429         dma_dev->dst_addr_widths = NBPF_DMA_BUSWIDTHS;
1430         dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1431
1432         platform_set_drvdata(pdev, nbpf);
1433
1434         ret = clk_prepare_enable(nbpf->clk);
1435         if (ret < 0)
1436                 return ret;
1437
1438         nbpf_configure(nbpf);
1439
1440         ret = dma_async_device_register(dma_dev);
1441         if (ret < 0)
1442                 goto e_clk_off;
1443
1444         ret = of_dma_controller_register(np, nbpf_of_xlate, nbpf);
1445         if (ret < 0)
1446                 goto e_dma_dev_unreg;
1447
1448         return 0;
1449
1450 e_dma_dev_unreg:
1451         dma_async_device_unregister(dma_dev);
1452 e_clk_off:
1453         clk_disable_unprepare(nbpf->clk);
1454
1455         return ret;
1456 }
1457
1458 static int nbpf_remove(struct platform_device *pdev)
1459 {
1460         struct nbpf_device *nbpf = platform_get_drvdata(pdev);
1461         int i;
1462
1463         devm_free_irq(&pdev->dev, nbpf->eirq, nbpf);
1464
1465         for (i = 0; i < nbpf->config->num_channels; i++) {
1466                 struct nbpf_channel *chan = nbpf->chan + i;
1467
1468                 devm_free_irq(&pdev->dev, chan->irq, chan);
1469
1470                 tasklet_kill(&chan->tasklet);
1471         }
1472
1473         of_dma_controller_free(pdev->dev.of_node);
1474         dma_async_device_unregister(&nbpf->dma_dev);
1475         clk_disable_unprepare(nbpf->clk);
1476
1477         return 0;
1478 }
1479
1480 static const struct platform_device_id nbpf_ids[] = {
1481         {"nbpfaxi64dmac1b4",    (kernel_ulong_t)&nbpf_cfg[NBPF1B4]},
1482         {"nbpfaxi64dmac1b8",    (kernel_ulong_t)&nbpf_cfg[NBPF1B8]},
1483         {"nbpfaxi64dmac1b16",   (kernel_ulong_t)&nbpf_cfg[NBPF1B16]},
1484         {"nbpfaxi64dmac4b4",    (kernel_ulong_t)&nbpf_cfg[NBPF4B4]},
1485         {"nbpfaxi64dmac4b8",    (kernel_ulong_t)&nbpf_cfg[NBPF4B8]},
1486         {"nbpfaxi64dmac4b16",   (kernel_ulong_t)&nbpf_cfg[NBPF4B16]},
1487         {"nbpfaxi64dmac8b4",    (kernel_ulong_t)&nbpf_cfg[NBPF8B4]},
1488         {"nbpfaxi64dmac8b8",    (kernel_ulong_t)&nbpf_cfg[NBPF8B8]},
1489         {"nbpfaxi64dmac8b16",   (kernel_ulong_t)&nbpf_cfg[NBPF8B16]},
1490         {},
1491 };
1492 MODULE_DEVICE_TABLE(platform, nbpf_ids);
1493
1494 #ifdef CONFIG_PM
1495 static int nbpf_runtime_suspend(struct device *dev)
1496 {
1497         struct nbpf_device *nbpf = platform_get_drvdata(to_platform_device(dev));
1498         clk_disable_unprepare(nbpf->clk);
1499         return 0;
1500 }
1501
1502 static int nbpf_runtime_resume(struct device *dev)
1503 {
1504         struct nbpf_device *nbpf = platform_get_drvdata(to_platform_device(dev));
1505         return clk_prepare_enable(nbpf->clk);
1506 }
1507 #endif
1508
1509 static const struct dev_pm_ops nbpf_pm_ops = {
1510         SET_RUNTIME_PM_OPS(nbpf_runtime_suspend, nbpf_runtime_resume, NULL)
1511 };
1512
1513 static struct platform_driver nbpf_driver = {
1514         .driver = {
1515                 .name = "dma-nbpf",
1516                 .of_match_table = nbpf_match,
1517                 .pm = &nbpf_pm_ops,
1518         },
1519         .id_table = nbpf_ids,
1520         .probe = nbpf_probe,
1521         .remove = nbpf_remove,
1522 };
1523
1524 module_platform_driver(nbpf_driver);
1525
1526 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1527 MODULE_DESCRIPTION("dmaengine driver for NBPFAXI64* DMACs");
1528 MODULE_LICENSE("GPL v2");