drivers/dma/mv_xor.c

   1 /*
   2  * offload engine driver for the Marvell XOR engine
   3  * Copyright (C) 2007, 2008, Marvell International Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/memory.h>
  28 #include <linux/clk.h>
  29 #include <linux/of.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/irqdomain.h>
  32 #include <linux/platform_data/dma-mv_xor.h>
  33
  34 #include "dmaengine.h"
  35 #include "mv_xor.h"
  36
  37 static void mv_xor_issue_pending(struct dma_chan *chan);
  38
  39 #define to_mv_xor_chan(chan)            \
  40         container_of(chan, struct mv_xor_chan, dmachan)
  41
  42 #define to_mv_xor_slot(tx)              \
  43         container_of(tx, struct mv_xor_desc_slot, async_tx)
  44
  45 #define mv_chan_to_devp(chan)           \
  46         ((chan)->dmadev.dev)
  47
  48 static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
  49 {
  50         struct mv_xor_desc *hw_desc = desc->hw_desc;
  51
  52         hw_desc->status = (1 << 31);
  53         hw_desc->phy_next_desc = 0;
  54         hw_desc->desc_command = (1 << 31);
  55 }
  56
  57 static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
  58                                    u32 byte_count)
  59 {
  60         struct mv_xor_desc *hw_desc = desc->hw_desc;
  61         hw_desc->byte_count = byte_count;
  62 }
  63
  64 static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
  65                                   u32 next_desc_addr)
  66 {
  67         struct mv_xor_desc *hw_desc = desc->hw_desc;
  68         BUG_ON(hw_desc->phy_next_desc);
  69         hw_desc->phy_next_desc = next_desc_addr;
  70 }
  71
  72 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
  73 {
  74         struct mv_xor_desc *hw_desc = desc->hw_desc;
  75         hw_desc->phy_next_desc = 0;
  76 }
  77
  78 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
  79                                   dma_addr_t addr)
  80 {
  81         struct mv_xor_desc *hw_desc = desc->hw_desc;
  82         hw_desc->phy_dest_addr = addr;
  83 }
  84
  85 static int mv_chan_memset_slot_count(size_t len)
  86 {
  87         return 1;
  88 }
  89
  90 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
  91
  92 static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
  93                                  int index, dma_addr_t addr)
  94 {
  95         struct mv_xor_desc *hw_desc = desc->hw_desc;
  96         hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
  97         if (desc->type == DMA_XOR)
  98                 hw_desc->desc_command |= (1 << index);
  99 }
 100
 101 static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
 102 {
 103         return readl_relaxed(XOR_CURR_DESC(chan));
 104 }
 105
 106 static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
 107                                         u32 next_desc_addr)
 108 {
 109         writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
 110 }
 111
 112 static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
 113 {
 114         u32 val = readl_relaxed(XOR_INTR_MASK(chan));
 115         val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
 116         writel_relaxed(val, XOR_INTR_MASK(chan));
 117 }
 118
 119 static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
 120 {
 121         u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
 122         intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
 123         return intr_cause;
 124 }
 125
 126 static int mv_is_err_intr(u32 intr_cause)
 127 {
 128         if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
 129                 return 1;
 130
 131         return 0;
 132 }
 133
 134 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
 135 {
 136         u32 val = ~(1 << (chan->idx * 16));
 137         dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
 138         writel_relaxed(val, XOR_INTR_CAUSE(chan));
 139 }
 140
 141 static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
 142 {
 143         u32 val = 0xFFFF0000 >> (chan->idx * 16);
 144         writel_relaxed(val, XOR_INTR_CAUSE(chan));
 145 }
 146
 147 static int mv_can_chain(struct mv_xor_desc_slot *desc)
 148 {
 149         struct mv_xor_desc_slot *chain_old_tail = list_entry(
 150                 desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
 151
 152         if (chain_old_tail->type != desc->type)
 153                 return 0;
 154
 155         return 1;
 156 }
 157
 158 static void mv_set_mode(struct mv_xor_chan *chan,
 159                                enum dma_transaction_type type)
 160 {
 161         u32 op_mode;
 162         u32 config = readl_relaxed(XOR_CONFIG(chan));
 163
 164         switch (type) {
 165         case DMA_XOR:
 166                 op_mode = XOR_OPERATION_MODE_XOR;
 167                 break;
 168         case DMA_MEMCPY:
 169                 op_mode = XOR_OPERATION_MODE_MEMCPY;
 170                 break;
 171         default:
 172                 dev_err(mv_chan_to_devp(chan),
 173                         "error: unsupported operation %d\n",
 174                         type);
 175                 BUG();
 176                 return;
 177         }
 178
 179         config &= ~0x7;
 180         config |= op_mode;
 181
 182 #if defined(__BIG_ENDIAN)
 183         config |= XOR_DESCRIPTOR_SWAP;
 184 #else
 185         config &= ~XOR_DESCRIPTOR_SWAP;
 186 #endif
 187
 188         writel_relaxed(config, XOR_CONFIG(chan));
 189         chan->current_type = type;
 190 }
 191
 192 static void mv_chan_activate(struct mv_xor_chan *chan)
 193 {
 194         dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
 195
 196         /* writel ensures all descriptors are flushed before activation */
 197         writel(BIT(0), XOR_ACTIVATION(chan));
 198 }
 199
 200 static char mv_chan_is_busy(struct mv_xor_chan *chan)
 201 {
 202         u32 state = readl_relaxed(XOR_ACTIVATION(chan));
 203
 204         state = (state >> 4) & 0x3;
 205
 206         return (state == 1) ? 1 : 0;
 207 }
 208
 209 static int mv_chan_xor_slot_count(size_t len, int src_cnt)
 210 {
 211         return 1;
 212 }
 213
 214 /**
 215  * mv_xor_free_slots - flags descriptor slots for reuse
 216  * @slot: Slot to free
 217  * Caller must hold &mv_chan->lock while calling this function
 218  */
 219 static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
 220                               struct mv_xor_desc_slot *slot)
 221 {
 222         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n",
 223                 __func__, __LINE__, slot);
 224
 225         slot->slots_per_op = 0;
 226
 227 }
 228
 229 /*
 230  * mv_xor_start_new_chain - program the engine to operate on new chain headed by
 231  * sw_desc
 232  * Caller must hold &mv_chan->lock while calling this function
 233  */
 234 static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
 235                                    struct mv_xor_desc_slot *sw_desc)
 236 {
 237         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
 238                 __func__, __LINE__, sw_desc);
 239         if (sw_desc->type != mv_chan->current_type)
 240                 mv_set_mode(mv_chan, sw_desc->type);
 241
 242         /* set the hardware chain */
 243         mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
 244
 245         mv_chan->pending += sw_desc->slot_cnt;
 246         mv_xor_issue_pending(&mv_chan->dmachan);
 247 }
 248
 249 static dma_cookie_t
 250 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
 251         struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
 252 {
 253         BUG_ON(desc->async_tx.cookie < 0);
 254
 255         if (desc->async_tx.cookie > 0) {
 256                 cookie = desc->async_tx.cookie;
 257
 258                 /* call the callback (must not sleep or submit new
 259                  * operations to this channel)
 260                  */
 261                 if (desc->async_tx.callback)
 262                         desc->async_tx.callback(
 263                                 desc->async_tx.callback_param);
 264
 265                 dma_descriptor_unmap(&desc->async_tx);
 266                 if (desc->group_head)
 267                         desc->group_head = NULL;
 268         }
 269
 270         /* run dependent operations */
 271         dma_run_dependencies(&desc->async_tx);
 272
 273         return cookie;
 274 }
 275
 276 static int
 277 mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
 278 {
 279         struct mv_xor_desc_slot *iter, *_iter;
 280
 281         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
 282         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
 283                                  completed_node) {
 284
 285                 if (async_tx_test_ack(&iter->async_tx)) {
 286                         list_del(&iter->completed_node);
 287                         mv_xor_free_slots(mv_chan, iter);
 288                 }
 289         }
 290         return 0;
 291 }
 292
 293 static int
 294 mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
 295         struct mv_xor_chan *mv_chan)
 296 {
 297         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
 298                 __func__, __LINE__, desc, desc->async_tx.flags);
 299         list_del(&desc->chain_node);
 300         /* the client is allowed to attach dependent operations
 301          * until 'ack' is set
 302          */
 303         if (!async_tx_test_ack(&desc->async_tx)) {
 304                 /* move this slot to the completed_slots */
 305                 list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
 306                 return 0;
 307         }
 308
 309         mv_xor_free_slots(mv_chan, desc);
 310         return 0;
 311 }
 312
 313 static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 314 {
 315         struct mv_xor_desc_slot *iter, *_iter;
 316         dma_cookie_t cookie = 0;
 317         int busy = mv_chan_is_busy(mv_chan);
 318         u32 current_desc = mv_chan_get_current_desc(mv_chan);
 319         int current_cleaned = 0;
 320         struct mv_xor_desc *hw_desc;
 321
 322         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
 323         dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
 324         mv_xor_clean_completed_slots(mv_chan);
 325
 326         /* free completed slots from the chain starting with
 327          * the oldest descriptor
 328          */
 329
 330         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
 331                                         chain_node) {
 332
 333                 /* clean finished descriptors */
 334                 hw_desc = iter->hw_desc;
 335                 if (hw_desc->status & XOR_DESC_SUCCESS) {
 336                         cookie = mv_xor_run_tx_complete_actions(iter, mv_chan,
 337                                                                 cookie);
 338
 339                         /* done processing desc, clean slot */
 340                         mv_xor_clean_slot(iter, mv_chan);
 341
 342                         /* break if we did cleaned the current */
 343                         if (iter->async_tx.phys == current_desc) {
 344                                 current_cleaned = 1;
 345                                 break;
 346                         }
 347                 } else {
 348                         if (iter->async_tx.phys == current_desc) {
 349                                 current_cleaned = 0;
 350                                 break;
 351                         }
 352                 }
 353         }
 354
 355         if ((busy == 0) && !list_empty(&mv_chan->chain)) {
 356                 if (current_cleaned) {
 357                         /*
 358                          * current descriptor cleaned and removed, run
 359                          * from list head
 360                          */
 361                         iter = list_entry(mv_chan->chain.next,
 362                                           struct mv_xor_desc_slot,
 363                                           chain_node);
 364                         mv_xor_start_new_chain(mv_chan, iter);
 365                 } else {
 366                         if (!list_is_last(&iter->chain_node, &mv_chan->chain)) {
 367                                 /*
 368                                  * descriptors are still waiting after
 369                                  * current, trigger them
 370                                  */
 371                                 iter = list_entry(iter->chain_node.next,
 372                                                   struct mv_xor_desc_slot,
 373                                                   chain_node);
 374                                 mv_xor_start_new_chain(mv_chan, iter);
 375                         } else {
 376                                 /*
 377                                  * some descriptors are still waiting
 378                                  * to be cleaned
 379                                  */
 380                                 tasklet_schedule(&mv_chan->irq_tasklet);
 381                         }
 382                 }
 383         }
 384
 385         if (cookie > 0)
 386                 mv_chan->dmachan.completed_cookie = cookie;
 387 }
 388
 389 static void
 390 mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 391 {
 392         spin_lock_bh(&mv_chan->lock);
 393         __mv_xor_slot_cleanup(mv_chan);
 394         spin_unlock_bh(&mv_chan->lock);
 395 }
 396
 397 static void mv_xor_tasklet(unsigned long data)
 398 {
 399         struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
 400         mv_xor_slot_cleanup(chan);
 401 }
 402
 403 static struct mv_xor_desc_slot *
 404 mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
 405                     int slots_per_op)
 406 {
 407         struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
 408         LIST_HEAD(chain);
 409         int slots_found, retry = 0;
 410
 411         /* start search from the last allocated descrtiptor
 412          * if a contiguous allocation can not be found start searching
 413          * from the beginning of the list
 414          */
 415 retry:
 416         slots_found = 0;
 417         if (retry == 0)
 418                 iter = mv_chan->last_used;
 419         else
 420                 iter = list_entry(&mv_chan->all_slots,
 421                         struct mv_xor_desc_slot,
 422                         slot_node);
 423
 424         list_for_each_entry_safe_continue(
 425                 iter, _iter, &mv_chan->all_slots, slot_node) {
 426                 prefetch(_iter);
 427                 prefetch(&_iter->async_tx);
 428                 if (iter->slots_per_op) {
 429                         /* give up after finding the first busy slot
 430                          * on the second pass through the list
 431                          */
 432                         if (retry)
 433                                 break;
 434
 435                         slots_found = 0;
 436                         continue;
 437                 }
 438
 439                 /* start the allocation if the slot is correctly aligned */
 440                 if (!slots_found++)
 441                         alloc_start = iter;
 442
 443                 if (slots_found == num_slots) {
 444                         struct mv_xor_desc_slot *alloc_tail = NULL;
 445                         struct mv_xor_desc_slot *last_used = NULL;
 446                         iter = alloc_start;
 447                         while (num_slots) {
 448                                 int i;
 449
 450                                 /* pre-ack all but the last descriptor */
 451                                 async_tx_ack(&iter->async_tx);
 452
 453                                 list_add_tail(&iter->chain_node, &chain);
 454                                 alloc_tail = iter;
 455                                 iter->async_tx.cookie = 0;
 456                                 iter->slot_cnt = num_slots;
 457                                 iter->xor_check_result = NULL;
 458                                 for (i = 0; i < slots_per_op; i++) {
 459                                         iter->slots_per_op = slots_per_op - i;
 460                                         last_used = iter;
 461                                         iter = list_entry(iter->slot_node.next,
 462                                                 struct mv_xor_desc_slot,
 463                                                 slot_node);
 464                                 }
 465                                 num_slots -= slots_per_op;
 466                         }
 467                         alloc_tail->group_head = alloc_start;
 468                         alloc_tail->async_tx.cookie = -EBUSY;
 469                         list_splice(&chain, &alloc_tail->tx_list);
 470                         mv_chan->last_used = last_used;
 471                         mv_desc_clear_next_desc(alloc_start);
 472                         mv_desc_clear_next_desc(alloc_tail);
 473                         return alloc_tail;
 474                 }
 475         }
 476         if (!retry++)
 477                 goto retry;
 478
 479         /* try to free some slots if the allocation fails */
 480         tasklet_schedule(&mv_chan->irq_tasklet);
 481
 482         return NULL;
 483 }
 484
 485 /************************ DMA engine API functions ****************************/
 486 static dma_cookie_t
 487 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
 488 {
 489         struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
 490         struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
 491         struct mv_xor_desc_slot *grp_start, *old_chain_tail;
 492         dma_cookie_t cookie;
 493         int new_hw_chain = 1;
 494
 495         dev_dbg(mv_chan_to_devp(mv_chan),
 496                 "%s sw_desc %p: async_tx %p\n",
 497                 __func__, sw_desc, &sw_desc->async_tx);
 498
 499         grp_start = sw_desc->group_head;
 500
 501         spin_lock_bh(&mv_chan->lock);
 502         cookie = dma_cookie_assign(tx);
 503
 504         if (list_empty(&mv_chan->chain))
 505                 list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
 506         else {
 507                 new_hw_chain = 0;
 508
 509                 old_chain_tail = list_entry(mv_chan->chain.prev,
 510                                             struct mv_xor_desc_slot,
 511                                             chain_node);
 512                 list_splice_init(&grp_start->tx_list,
 513                                  &old_chain_tail->chain_node);
 514
 515                 if (!mv_can_chain(grp_start))
 516                         goto submit_done;
 517
 518                 dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
 519                         &old_chain_tail->async_tx.phys);
 520
 521                 /* fix up the hardware chain */
 522                 mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
 523
 524                 /* if the channel is not busy */
 525                 if (!mv_chan_is_busy(mv_chan)) {
 526                         u32 current_desc = mv_chan_get_current_desc(mv_chan);
 527                         /*
 528                          * and the curren desc is the end of the chain before
 529                          * the append, then we need to start the channel
 530                          */
 531                         if (current_desc == old_chain_tail->async_tx.phys)
 532                                 new_hw_chain = 1;
 533                 }
 534         }
 535
 536         if (new_hw_chain)
 537                 mv_xor_start_new_chain(mv_chan, grp_start);
 538
 539 submit_done:
 540         spin_unlock_bh(&mv_chan->lock);
 541
 542         return cookie;
 543 }
 544
 545 /* returns the number of allocated descriptors */
 546 static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
 547 {
 548         void *virt_desc;
 549         dma_addr_t dma_desc;
 550         int idx;
 551         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 552         struct mv_xor_desc_slot *slot = NULL;
 553         int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
 554
 555         /* Allocate descriptor slots */
 556         idx = mv_chan->slots_allocated;
 557         while (idx < num_descs_in_pool) {
 558                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 559                 if (!slot) {
 560                         printk(KERN_INFO "MV XOR Channel only initialized"
 561                                 " %d descriptor slots", idx);
 562                         break;
 563                 }
 564                 virt_desc = mv_chan->dma_desc_pool_virt;
 565                 slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE;
 566
 567                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
 568                 slot->async_tx.tx_submit = mv_xor_tx_submit;
 569                 INIT_LIST_HEAD(&slot->chain_node);
 570                 INIT_LIST_HEAD(&slot->slot_node);
 571                 INIT_LIST_HEAD(&slot->tx_list);
 572                 dma_desc = mv_chan->dma_desc_pool;
 573                 slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE;
 574                 slot->idx = idx++;
 575
 576                 spin_lock_bh(&mv_chan->lock);
 577                 mv_chan->slots_allocated = idx;
 578                 list_add_tail(&slot->slot_node, &mv_chan->all_slots);
 579                 spin_unlock_bh(&mv_chan->lock);
 580         }
 581
 582         if (mv_chan->slots_allocated && !mv_chan->last_used)
 583                 mv_chan->last_used = list_entry(mv_chan->all_slots.next,
 584                                         struct mv_xor_desc_slot,
 585                                         slot_node);
 586
 587         dev_dbg(mv_chan_to_devp(mv_chan),
 588                 "allocated %d descriptor slots last_used: %p\n",
 589                 mv_chan->slots_allocated, mv_chan->last_used);
 590
 591         return mv_chan->slots_allocated ? : -ENOMEM;
 592 }
 593
 594 static struct dma_async_tx_descriptor *
 595 mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 596                 size_t len, unsigned long flags)
 597 {
 598         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 599         struct mv_xor_desc_slot *sw_desc, *grp_start;
 600         int slot_cnt;
 601
 602         dev_dbg(mv_chan_to_devp(mv_chan),
 603                 "%s dest: %pad src %pad len: %u flags: %ld\n",
 604                 __func__, &dest, &src, len, flags);
 605         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 606                 return NULL;
 607
 608         BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
 609
 610         spin_lock_bh(&mv_chan->lock);
 611         slot_cnt = mv_chan_memcpy_slot_count(len);
 612         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 613         if (sw_desc) {
 614                 sw_desc->type = DMA_MEMCPY;
 615                 sw_desc->async_tx.flags = flags;
 616                 grp_start = sw_desc->group_head;
 617                 mv_desc_init(grp_start, flags);
 618                 mv_desc_set_byte_count(grp_start, len);
 619                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 620                 mv_desc_set_src_addr(grp_start, 0, src);
 621                 sw_desc->unmap_src_cnt = 1;
 622                 sw_desc->unmap_len = len;
 623         }
 624         spin_unlock_bh(&mv_chan->lock);
 625
 626         dev_dbg(mv_chan_to_devp(mv_chan),
 627                 "%s sw_desc %p async_tx %p\n",
 628                 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : NULL);
 629
 630         return sw_desc ? &sw_desc->async_tx : NULL;
 631 }
 632
 633 static struct dma_async_tx_descriptor *
 634 mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 635                     unsigned int src_cnt, size_t len, unsigned long flags)
 636 {
 637         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 638         struct mv_xor_desc_slot *sw_desc, *grp_start;
 639         int slot_cnt;
 640
 641         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 642                 return NULL;
 643
 644         BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
 645
 646         dev_dbg(mv_chan_to_devp(mv_chan),
 647                 "%s src_cnt: %d len: %u dest %pad flags: %ld\n",
 648                 __func__, src_cnt, len, &dest, flags);
 649
 650         spin_lock_bh(&mv_chan->lock);
 651         slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
 652         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 653         if (sw_desc) {
 654                 sw_desc->type = DMA_XOR;
 655                 sw_desc->async_tx.flags = flags;
 656                 grp_start = sw_desc->group_head;
 657                 mv_desc_init(grp_start, flags);
 658                 /* the byte count field is the same as in memcpy desc*/
 659                 mv_desc_set_byte_count(grp_start, len);
 660                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 661                 sw_desc->unmap_src_cnt = src_cnt;
 662                 sw_desc->unmap_len = len;
 663                 while (src_cnt--)
 664                         mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
 665         }
 666         spin_unlock_bh(&mv_chan->lock);
 667         dev_dbg(mv_chan_to_devp(mv_chan),
 668                 "%s sw_desc %p async_tx %p \n",
 669                 __func__, sw_desc, &sw_desc->async_tx);
 670         return sw_desc ? &sw_desc->async_tx : NULL;
 671 }
 672
 673 static void mv_xor_free_chan_resources(struct dma_chan *chan)
 674 {
 675         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 676         struct mv_xor_desc_slot *iter, *_iter;
 677         int in_use_descs = 0;
 678
 679         mv_xor_slot_cleanup(mv_chan);
 680
 681         spin_lock_bh(&mv_chan->lock);
 682         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
 683                                         chain_node) {
 684                 in_use_descs++;
 685                 list_del(&iter->chain_node);
 686         }
 687         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
 688                                  completed_node) {
 689                 in_use_descs++;
 690                 list_del(&iter->completed_node);
 691         }
 692         list_for_each_entry_safe_reverse(
 693                 iter, _iter, &mv_chan->all_slots, slot_node) {
 694                 list_del(&iter->slot_node);
 695                 kfree(iter);
 696                 mv_chan->slots_allocated--;
 697         }
 698         mv_chan->last_used = NULL;
 699
 700         dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
 701                 __func__, mv_chan->slots_allocated);
 702         spin_unlock_bh(&mv_chan->lock);
 703
 704         if (in_use_descs)
 705                 dev_err(mv_chan_to_devp(mv_chan),
 706                         "freeing %d in use descriptors!\n", in_use_descs);
 707 }
 708
 709 /**
 710  * mv_xor_status - poll the status of an XOR transaction
 711  * @chan: XOR channel handle
 712  * @cookie: XOR transaction identifier
 713  * @txstate: XOR transactions state holder (or NULL)
 714  */
 715 static enum dma_status mv_xor_status(struct dma_chan *chan,
 716                                           dma_cookie_t cookie,
 717                                           struct dma_tx_state *txstate)
 718 {
 719         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 720         enum dma_status ret;
 721
 722         ret = dma_cookie_status(chan, cookie, txstate);
 723         if (ret == DMA_COMPLETE) {
 724                 mv_xor_clean_completed_slots(mv_chan);
 725                 return ret;
 726         }
 727         mv_xor_slot_cleanup(mv_chan);
 728
 729         return dma_cookie_status(chan, cookie, txstate);
 730 }
 731
 732 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
 733 {
 734         u32 val;
 735
 736         val = readl_relaxed(XOR_CONFIG(chan));
 737         dev_err(mv_chan_to_devp(chan), "config       0x%08x\n", val);
 738
 739         val = readl_relaxed(XOR_ACTIVATION(chan));
 740         dev_err(mv_chan_to_devp(chan), "activation   0x%08x\n", val);
 741
 742         val = readl_relaxed(XOR_INTR_CAUSE(chan));
 743         dev_err(mv_chan_to_devp(chan), "intr cause   0x%08x\n", val);
 744
 745         val = readl_relaxed(XOR_INTR_MASK(chan));
 746         dev_err(mv_chan_to_devp(chan), "intr mask    0x%08x\n", val);
 747
 748         val = readl_relaxed(XOR_ERROR_CAUSE(chan));
 749         dev_err(mv_chan_to_devp(chan), "error cause  0x%08x\n", val);
 750
 751         val = readl_relaxed(XOR_ERROR_ADDR(chan));
 752         dev_err(mv_chan_to_devp(chan), "error addr   0x%08x\n", val);
 753 }
 754
 755 static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
 756                                          u32 intr_cause)
 757 {
 758         if (intr_cause & (1 << 4)) {
 759              dev_dbg(mv_chan_to_devp(chan),
 760                      "ignore this error\n");
 761              return;
 762         }
 763
 764         dev_err(mv_chan_to_devp(chan),
 765                 "error on chan %d. intr cause 0x%08x\n",
 766                 chan->idx, intr_cause);
 767
 768         mv_dump_xor_regs(chan);
 769         BUG();
 770 }
 771
 772 static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
 773 {
 774         struct mv_xor_chan *chan = data;
 775         u32 intr_cause = mv_chan_get_intr_cause(chan);
 776
 777         dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
 778
 779         if (mv_is_err_intr(intr_cause))
 780                 mv_xor_err_interrupt_handler(chan, intr_cause);
 781
 782         tasklet_schedule(&chan->irq_tasklet);
 783
 784         mv_xor_device_clear_eoc_cause(chan);
 785
 786         return IRQ_HANDLED;
 787 }
 788
 789 static void mv_xor_issue_pending(struct dma_chan *chan)
 790 {
 791         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 792
 793         if (mv_chan->pending >= MV_XOR_THRESHOLD) {
 794                 mv_chan->pending = 0;
 795                 mv_chan_activate(mv_chan);
 796         }
 797 }
 798
 799 /*
 800  * Perform a transaction to verify the HW works.
 801  */
 802
 803 static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
 804 {
 805         int i;
 806         void *src, *dest;
 807         dma_addr_t src_dma, dest_dma;
 808         struct dma_chan *dma_chan;
 809         dma_cookie_t cookie;
 810         struct dma_async_tx_descriptor *tx;
 811         struct dmaengine_unmap_data *unmap;
 812         int err = 0;
 813
 814         src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
 815         if (!src)
 816                 return -ENOMEM;
 817
 818         dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
 819         if (!dest) {
 820                 kfree(src);
 821                 return -ENOMEM;
 822         }
 823
 824         /* Fill in src buffer */
 825         for (i = 0; i < PAGE_SIZE; i++)
 826                 ((u8 *) src)[i] = (u8)i;
 827
 828         dma_chan = &mv_chan->dmachan;
 829         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
 830                 err = -ENODEV;
 831                 goto out;
 832         }
 833
 834         unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
 835         if (!unmap) {
 836                 err = -ENOMEM;
 837                 goto free_resources;
 838         }
 839
 840         src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0,
 841                                  PAGE_SIZE, DMA_TO_DEVICE);
 842         unmap->to_cnt = 1;
 843         unmap->addr[0] = src_dma;
 844
 845         dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0,
 846                                   PAGE_SIZE, DMA_FROM_DEVICE);
 847         unmap->from_cnt = 1;
 848         unmap->addr[1] = dest_dma;
 849
 850         unmap->len = PAGE_SIZE;
 851
 852         tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
 853                                     PAGE_SIZE, 0);
 854         cookie = mv_xor_tx_submit(tx);
 855         mv_xor_issue_pending(dma_chan);
 856         async_tx_ack(tx);
 857         msleep(1);
 858
 859         if (mv_xor_status(dma_chan, cookie, NULL) !=
 860             DMA_COMPLETE) {
 861                 dev_err(dma_chan->device->dev,
 862                         "Self-test copy timed out, disabling\n");
 863                 err = -ENODEV;
 864                 goto free_resources;
 865         }
 866
 867         dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
 868                                 PAGE_SIZE, DMA_FROM_DEVICE);
 869         if (memcmp(src, dest, PAGE_SIZE)) {
 870                 dev_err(dma_chan->device->dev,
 871                         "Self-test copy failed compare, disabling\n");
 872                 err = -ENODEV;
 873                 goto free_resources;
 874         }
 875
 876 free_resources:
 877         dmaengine_unmap_put(unmap);
 878         mv_xor_free_chan_resources(dma_chan);
 879 out:
 880         kfree(src);
 881         kfree(dest);
 882         return err;
 883 }
 884
 885 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
 886 static int
 887 mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
 888 {
 889         int i, src_idx;
 890         struct page *dest;
 891         struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
 892         dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
 893         dma_addr_t dest_dma;
 894         struct dma_async_tx_descriptor *tx;
 895         struct dmaengine_unmap_data *unmap;
 896         struct dma_chan *dma_chan;
 897         dma_cookie_t cookie;
 898         u8 cmp_byte = 0;
 899         u32 cmp_word;
 900         int err = 0;
 901         int src_count = MV_XOR_NUM_SRC_TEST;
 902
 903         for (src_idx = 0; src_idx < src_count; src_idx++) {
 904                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
 905                 if (!xor_srcs[src_idx]) {
 906                         while (src_idx--)
 907                                 __free_page(xor_srcs[src_idx]);
 908                         return -ENOMEM;
 909                 }
 910         }
 911
 912         dest = alloc_page(GFP_KERNEL);
 913         if (!dest) {
 914                 while (src_idx--)
 915                         __free_page(xor_srcs[src_idx]);
 916                 return -ENOMEM;
 917         }
 918
 919         /* Fill in src buffers */
 920         for (src_idx = 0; src_idx < src_count; src_idx++) {
 921                 u8 *ptr = page_address(xor_srcs[src_idx]);
 922                 for (i = 0; i < PAGE_SIZE; i++)
 923                         ptr[i] = (1 << src_idx);
 924         }
 925
 926         for (src_idx = 0; src_idx < src_count; src_idx++)
 927                 cmp_byte ^= (u8) (1 << src_idx);
 928
 929         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
 930                 (cmp_byte << 8) | cmp_byte;
 931
 932         memset(page_address(dest), 0, PAGE_SIZE);
 933
 934         dma_chan = &mv_chan->dmachan;
 935         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
 936                 err = -ENODEV;
 937                 goto out;
 938         }
 939
 940         unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
 941                                          GFP_KERNEL);
 942         if (!unmap) {
 943                 err = -ENOMEM;
 944                 goto free_resources;
 945         }
 946
 947         /* test xor */
 948         for (i = 0; i < src_count; i++) {
 949                 unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
 950                                               0, PAGE_SIZE, DMA_TO_DEVICE);
 951                 dma_srcs[i] = unmap->addr[i];
 952                 unmap->to_cnt++;
 953         }
 954
 955         unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
 956                                       DMA_FROM_DEVICE);
 957         dest_dma = unmap->addr[src_count];
 958         unmap->from_cnt = 1;
 959         unmap->len = PAGE_SIZE;
 960
 961         tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
 962                                  src_count, PAGE_SIZE, 0);
 963
 964         cookie = mv_xor_tx_submit(tx);
 965         mv_xor_issue_pending(dma_chan);
 966         async_tx_ack(tx);
 967         msleep(8);
 968
 969         if (mv_xor_status(dma_chan, cookie, NULL) !=
 970             DMA_COMPLETE) {
 971                 dev_err(dma_chan->device->dev,
 972                         "Self-test xor timed out, disabling\n");
 973                 err = -ENODEV;
 974                 goto free_resources;
 975         }
 976
 977         dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
 978                                 PAGE_SIZE, DMA_FROM_DEVICE);
 979         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
 980                 u32 *ptr = page_address(dest);
 981                 if (ptr[i] != cmp_word) {
 982                         dev_err(dma_chan->device->dev,
 983                                 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
 984                                 i, ptr[i], cmp_word);
 985                         err = -ENODEV;
 986                         goto free_resources;
 987                 }
 988         }
 989
 990 free_resources:
 991         dmaengine_unmap_put(unmap);
 992         mv_xor_free_chan_resources(dma_chan);
 993 out:
 994         src_idx = src_count;
 995         while (src_idx--)
 996                 __free_page(xor_srcs[src_idx]);
 997         __free_page(dest);
 998         return err;
 999 }
1000
1001 /* This driver does not implement any of the optional DMA operations. */
1002 static int
1003 mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1004                unsigned long arg)
1005 {
1006         return -ENOSYS;
1007 }
1008
1009 static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
1010 {
1011         struct dma_chan *chan, *_chan;
1012         struct device *dev = mv_chan->dmadev.dev;
1013
1014         dma_async_device_unregister(&mv_chan->dmadev);
1015
1016         dma_free_coherent(dev, MV_XOR_POOL_SIZE,
1017                           mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1018
1019         list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
1020                                  device_node) {
1021                 list_del(&chan->device_node);
1022         }
1023
1024         free_irq(mv_chan->irq, mv_chan);
1025
1026         return 0;
1027 }
1028
1029 static struct mv_xor_chan *
1030 mv_xor_channel_add(struct mv_xor_device *xordev,
1031                    struct platform_device *pdev,
1032                    int idx, dma_cap_mask_t cap_mask, int irq)
1033 {
1034         int ret = 0;
1035         struct mv_xor_chan *mv_chan;
1036         struct dma_device *dma_dev;
1037
1038         mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
1039         if (!mv_chan)
1040                 return ERR_PTR(-ENOMEM);
1041
1042         mv_chan->idx = idx;
1043         mv_chan->irq = irq;
1044
1045         dma_dev = &mv_chan->dmadev;
1046
1047         /* allocate coherent memory for hardware descriptors
1048          * note: writecombine gives slightly better performance, but
1049          * requires that we explicitly flush the writes
1050          */
1051         mv_chan->dma_desc_pool_virt =
1052           dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE,
1053                                  &mv_chan->dma_desc_pool, GFP_KERNEL);
1054         if (!mv_chan->dma_desc_pool_virt)
1055                 return ERR_PTR(-ENOMEM);
1056
1057         /* discover transaction capabilites from the platform data */
1058         dma_dev->cap_mask = cap_mask;
1059
1060         INIT_LIST_HEAD(&dma_dev->channels);
1061
1062         /* set base routines */
1063         dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1064         dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
1065         dma_dev->device_tx_status = mv_xor_status;
1066         dma_dev->device_issue_pending = mv_xor_issue_pending;
1067         dma_dev->device_control = mv_xor_control;
1068         dma_dev->dev = &pdev->dev;
1069
1070         /* set prep routines based on capability */
1071         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1072                 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1073         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1074                 dma_dev->max_xor = 8;
1075                 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1076         }
1077
1078         mv_chan->mmr_base = xordev->xor_base;
1079         mv_chan->mmr_high_base = xordev->xor_high_base;
1080         tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1081                      mv_chan);
1082
1083         /* clear errors before enabling interrupts */
1084         mv_xor_device_clear_err_status(mv_chan);
1085
1086         ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
1087                           0, dev_name(&pdev->dev), mv_chan);
1088         if (ret)
1089                 goto err_free_dma;
1090
1091         mv_chan_unmask_interrupts(mv_chan);
1092
1093         mv_set_mode(mv_chan, DMA_MEMCPY);
1094
1095         spin_lock_init(&mv_chan->lock);
1096         INIT_LIST_HEAD(&mv_chan->chain);
1097         INIT_LIST_HEAD(&mv_chan->completed_slots);
1098         INIT_LIST_HEAD(&mv_chan->all_slots);
1099         mv_chan->dmachan.device = dma_dev;
1100         dma_cookie_init(&mv_chan->dmachan);
1101
1102         list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
1103
1104         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1105                 ret = mv_xor_memcpy_self_test(mv_chan);
1106                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1107                 if (ret)
1108                         goto err_free_irq;
1109         }
1110
1111         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1112                 ret = mv_xor_xor_self_test(mv_chan);
1113                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1114                 if (ret)
1115                         goto err_free_irq;
1116         }
1117
1118         dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n",
1119                  dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1120                  dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1121                  dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1122
1123         dma_async_device_register(dma_dev);
1124         return mv_chan;
1125
1126 err_free_irq:
1127         free_irq(mv_chan->irq, mv_chan);
1128  err_free_dma:
1129         dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
1130                           mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1131         return ERR_PTR(ret);
1132 }
1133
1134 static void
1135 mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
1136                          const struct mbus_dram_target_info *dram)
1137 {
1138         void __iomem *base = xordev->xor_high_base;
1139         u32 win_enable = 0;
1140         int i;
1141
1142         for (i = 0; i < 8; i++) {
1143                 writel(0, base + WINDOW_BASE(i));
1144                 writel(0, base + WINDOW_SIZE(i));
1145                 if (i < 4)
1146                         writel(0, base + WINDOW_REMAP_HIGH(i));
1147         }
1148
1149         for (i = 0; i < dram->num_cs; i++) {
1150                 const struct mbus_dram_window *cs = dram->cs + i;
1151
1152                 writel((cs->base & 0xffff0000) |
1153                        (cs->mbus_attr << 8) |
1154                        dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1155                 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1156
1157                 win_enable |= (1 << i);
1158                 win_enable |= 3 << (16 + (2 * i));
1159         }
1160
1161         writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1162         writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1163         writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1164         writel(0, base + WINDOW_OVERRIDE_CTRL(1));
1165 }
1166
1167 static int mv_xor_probe(struct platform_device *pdev)
1168 {
1169         const struct mbus_dram_target_info *dram;
1170         struct mv_xor_device *xordev;
1171         struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
1172         struct resource *res;
1173         int i, ret;
1174
1175         dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
1176
1177         xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
1178         if (!xordev)
1179                 return -ENOMEM;
1180
1181         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1182         if (!res)
1183                 return -ENODEV;
1184
1185         xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
1186                                         resource_size(res));
1187         if (!xordev->xor_base)
1188                 return -EBUSY;
1189
1190         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1191         if (!res)
1192                 return -ENODEV;
1193
1194         xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1195                                              resource_size(res));
1196         if (!xordev->xor_high_base)
1197                 return -EBUSY;
1198
1199         platform_set_drvdata(pdev, xordev);
1200
1201         /*
1202          * (Re-)program MBUS remapping windows if we are asked to.
1203          */
1204         dram = mv_mbus_dram_info();
1205         if (dram)
1206                 mv_xor_conf_mbus_windows(xordev, dram);
1207
1208         /* Not all platforms can gate the clock, so it is not
1209          * an error if the clock does not exists.
1210          */
1211         xordev->clk = clk_get(&pdev->dev, NULL);
1212         if (!IS_ERR(xordev->clk))
1213                 clk_prepare_enable(xordev->clk);
1214
1215         if (pdev->dev.of_node) {
1216                 struct device_node *np;
1217                 int i = 0;
1218
1219                 for_each_child_of_node(pdev->dev.of_node, np) {
1220                         struct mv_xor_chan *chan;
1221                         dma_cap_mask_t cap_mask;
1222                         int irq;
1223
1224                         dma_cap_zero(cap_mask);
1225                         if (of_property_read_bool(np, "dmacap,memcpy"))
1226                                 dma_cap_set(DMA_MEMCPY, cap_mask);
1227                         if (of_property_read_bool(np, "dmacap,xor"))
1228                                 dma_cap_set(DMA_XOR, cap_mask);
1229                         if (of_property_read_bool(np, "dmacap,interrupt"))
1230                                 dma_cap_set(DMA_INTERRUPT, cap_mask);
1231
1232                         irq = irq_of_parse_and_map(np, 0);
1233                         if (!irq) {
1234                                 ret = -ENODEV;
1235                                 goto err_channel_add;
1236                         }
1237
1238                         chan = mv_xor_channel_add(xordev, pdev, i,
1239                                                   cap_mask, irq);
1240                         if (IS_ERR(chan)) {
1241                                 ret = PTR_ERR(chan);
1242                                 irq_dispose_mapping(irq);
1243                                 goto err_channel_add;
1244                         }
1245
1246                         xordev->channels[i] = chan;
1247                         i++;
1248                 }
1249         } else if (pdata && pdata->channels) {
1250                 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1251                         struct mv_xor_channel_data *cd;
1252                         struct mv_xor_chan *chan;
1253                         int irq;
1254
1255                         cd = &pdata->channels[i];
1256                         if (!cd) {
1257                                 ret = -ENODEV;
1258                                 goto err_channel_add;
1259                         }
1260
1261                         irq = platform_get_irq(pdev, i);
1262                         if (irq < 0) {
1263                                 ret = irq;
1264                                 goto err_channel_add;
1265                         }
1266
1267                         chan = mv_xor_channel_add(xordev, pdev, i,
1268                                                   cd->cap_mask, irq);
1269                         if (IS_ERR(chan)) {
1270                                 ret = PTR_ERR(chan);
1271                                 goto err_channel_add;
1272                         }
1273
1274                         xordev->channels[i] = chan;
1275                 }
1276         }
1277
1278         return 0;
1279
1280 err_channel_add:
1281         for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
1282                 if (xordev->channels[i]) {
1283                         mv_xor_channel_remove(xordev->channels[i]);
1284                         if (pdev->dev.of_node)
1285                                 irq_dispose_mapping(xordev->channels[i]->irq);
1286                 }
1287
1288         if (!IS_ERR(xordev->clk)) {
1289                 clk_disable_unprepare(xordev->clk);
1290                 clk_put(xordev->clk);
1291         }
1292
1293         return ret;
1294 }
1295
1296 static int mv_xor_remove(struct platform_device *pdev)
1297 {
1298         struct mv_xor_device *xordev = platform_get_drvdata(pdev);
1299         int i;
1300
1301         for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1302                 if (xordev->channels[i])
1303                         mv_xor_channel_remove(xordev->channels[i]);
1304         }
1305
1306         if (!IS_ERR(xordev->clk)) {
1307                 clk_disable_unprepare(xordev->clk);
1308                 clk_put(xordev->clk);
1309         }
1310
1311         return 0;
1312 }
1313
1314 #ifdef CONFIG_OF
1315 static struct of_device_id mv_xor_dt_ids[] = {
1316        { .compatible = "marvell,orion-xor", },
1317        {},
1318 };
1319 MODULE_DEVICE_TABLE(of, mv_xor_dt_ids);
1320 #endif
1321
1322 static struct platform_driver mv_xor_driver = {
1323         .probe          = mv_xor_probe,
1324         .remove         = mv_xor_remove,
1325         .driver         = {
1326                 .owner          = THIS_MODULE,
1327                 .name           = MV_XOR_NAME,
1328                 .of_match_table = of_match_ptr(mv_xor_dt_ids),
1329         },
1330 };
1331
1332
1333 static int __init mv_xor_init(void)
1334 {
1335         return platform_driver_register(&mv_xor_driver);
1336 }
1337 module_init(mv_xor_init);
1338
1339 /* it's currently unsafe to unload this module */
1340 #if 0
1341 static void __exit mv_xor_exit(void)
1342 {
1343         platform_driver_unregister(&mv_xor_driver);
1344         return;
1345 }
1346
1347 module_exit(mv_xor_exit);
1348 #endif
1349
1350 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1351 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1352 MODULE_LICENSE("GPL");