drivers/dma/ioat/hw.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called COPYING.
  16  */
  17 #ifndef _IOAT_HW_H_
  18 #define _IOAT_HW_H_
  19
  20 /* PCI Configuration Space Values */
  21 #define IOAT_MMIO_BAR           0
  22
  23 /* CB device ID's */
  24 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0   0x0e20
  25 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1   0x0e21
  26 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2   0x0e22
  27 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3   0x0e23
  28 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4   0x0e24
  29 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5   0x0e25
  30 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6   0x0e26
  31 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7   0x0e27
  32 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8   0x0e2e
  33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9   0x0e2f
  34
  35 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0   0x2f20
  36 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1   0x2f21
  37 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2   0x2f22
  38 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3   0x2f23
  39 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4   0x2f24
  40 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5   0x2f25
  41 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6   0x2f26
  42 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7   0x2f27
  43 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8   0x2f2e
  44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9   0x2f2f
  45
  46 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0   0x0C50
  47 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1   0x0C51
  48 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2   0x0C52
  49 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3   0x0C53
  50
  51 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
  52 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
  53 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
  54 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
  55
  56 #define PCI_DEVICE_ID_INTEL_IOAT_BDX0   0x6f20
  57 #define PCI_DEVICE_ID_INTEL_IOAT_BDX1   0x6f21
  58 #define PCI_DEVICE_ID_INTEL_IOAT_BDX2   0x6f22
  59 #define PCI_DEVICE_ID_INTEL_IOAT_BDX3   0x6f23
  60 #define PCI_DEVICE_ID_INTEL_IOAT_BDX4   0x6f24
  61 #define PCI_DEVICE_ID_INTEL_IOAT_BDX5   0x6f25
  62 #define PCI_DEVICE_ID_INTEL_IOAT_BDX6   0x6f26
  63 #define PCI_DEVICE_ID_INTEL_IOAT_BDX7   0x6f27
  64 #define PCI_DEVICE_ID_INTEL_IOAT_BDX8   0x6f2e
  65 #define PCI_DEVICE_ID_INTEL_IOAT_BDX9   0x6f2f
  66
  67 #define PCI_DEVICE_ID_INTEL_IOAT_SKX    0x2021
  68
  69 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
  70 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
  71 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
  72 #define IOAT_VER_3_2            0x32    /* Version 3.2 */
  73 #define IOAT_VER_3_3            0x33    /* Version 3.3 */
  74
  75
  76 int system_has_dca_enabled(struct pci_dev *pdev);
  77
  78 #define IOAT_DESC_SZ    64
  79
  80 struct ioat_dma_descriptor {
  81         uint32_t        size;
  82         union {
  83                 uint32_t ctl;
  84                 struct {
  85                         unsigned int int_en:1;
  86                         unsigned int src_snoop_dis:1;
  87                         unsigned int dest_snoop_dis:1;
  88                         unsigned int compl_write:1;
  89                         unsigned int fence:1;
  90                         unsigned int null:1;
  91                         unsigned int src_brk:1;
  92                         unsigned int dest_brk:1;
  93                         unsigned int bundle:1;
  94                         unsigned int dest_dca:1;
  95                         unsigned int hint:1;
  96                         unsigned int rsvd2:13;
  97                         #define IOAT_OP_COPY 0x00
  98                         unsigned int op:8;
  99                 } ctl_f;
 100         };
 101         uint64_t        src_addr;
 102         uint64_t        dst_addr;
 103         uint64_t        next;
 104         uint64_t        rsv1;
 105         uint64_t        rsv2;
 106         /* store some driver data in an unused portion of the descriptor */
 107         union {
 108                 uint64_t        user1;
 109                 uint64_t        tx_cnt;
 110         };
 111         uint64_t        user2;
 112 };
 113
 114 struct ioat_xor_descriptor {
 115         uint32_t        size;
 116         union {
 117                 uint32_t ctl;
 118                 struct {
 119                         unsigned int int_en:1;
 120                         unsigned int src_snoop_dis:1;
 121                         unsigned int dest_snoop_dis:1;
 122                         unsigned int compl_write:1;
 123                         unsigned int fence:1;
 124                         unsigned int src_cnt:3;
 125                         unsigned int bundle:1;
 126                         unsigned int dest_dca:1;
 127                         unsigned int hint:1;
 128                         unsigned int rsvd:13;
 129                         #define IOAT_OP_XOR 0x87
 130                         #define IOAT_OP_XOR_VAL 0x88
 131                         unsigned int op:8;
 132                 } ctl_f;
 133         };
 134         uint64_t        src_addr;
 135         uint64_t        dst_addr;
 136         uint64_t        next;
 137         uint64_t        src_addr2;
 138         uint64_t        src_addr3;
 139         uint64_t        src_addr4;
 140         uint64_t        src_addr5;
 141 };
 142
 143 struct ioat_xor_ext_descriptor {
 144         uint64_t        src_addr6;
 145         uint64_t        src_addr7;
 146         uint64_t        src_addr8;
 147         uint64_t        next;
 148         uint64_t        rsvd[4];
 149 };
 150
 151 struct ioat_pq_descriptor {
 152         union {
 153                 uint32_t        size;
 154                 uint32_t        dwbes;
 155                 struct {
 156                         unsigned int rsvd:25;
 157                         unsigned int p_val_err:1;
 158                         unsigned int q_val_err:1;
 159                         unsigned int rsvd1:4;
 160                         unsigned int wbes:1;
 161                 } dwbes_f;
 162         };
 163         union {
 164                 uint32_t ctl;
 165                 struct {
 166                         unsigned int int_en:1;
 167                         unsigned int src_snoop_dis:1;
 168                         unsigned int dest_snoop_dis:1;
 169                         unsigned int compl_write:1;
 170                         unsigned int fence:1;
 171                         unsigned int src_cnt:3;
 172                         unsigned int bundle:1;
 173                         unsigned int dest_dca:1;
 174                         unsigned int hint:1;
 175                         unsigned int p_disable:1;
 176                         unsigned int q_disable:1;
 177                         unsigned int rsvd2:2;
 178                         unsigned int wb_en:1;
 179                         unsigned int prl_en:1;
 180                         unsigned int rsvd3:7;
 181                         #define IOAT_OP_PQ 0x89
 182                         #define IOAT_OP_PQ_VAL 0x8a
 183                         #define IOAT_OP_PQ_16S 0xa0
 184                         #define IOAT_OP_PQ_VAL_16S 0xa1
 185                         unsigned int op:8;
 186                 } ctl_f;
 187         };
 188         uint64_t        src_addr;
 189         uint64_t        p_addr;
 190         uint64_t        next;
 191         uint64_t        src_addr2;
 192         union {
 193                 uint64_t        src_addr3;
 194                 uint64_t        sed_addr;
 195         };
 196         uint8_t         coef[8];
 197         uint64_t        q_addr;
 198 };
 199
 200 struct ioat_pq_ext_descriptor {
 201         uint64_t        src_addr4;
 202         uint64_t        src_addr5;
 203         uint64_t        src_addr6;
 204         uint64_t        next;
 205         uint64_t        src_addr7;
 206         uint64_t        src_addr8;
 207         uint64_t        rsvd[2];
 208 };
 209
 210 struct ioat_pq_update_descriptor {
 211         uint32_t        size;
 212         union {
 213                 uint32_t ctl;
 214                 struct {
 215                         unsigned int int_en:1;
 216                         unsigned int src_snoop_dis:1;
 217                         unsigned int dest_snoop_dis:1;
 218                         unsigned int compl_write:1;
 219                         unsigned int fence:1;
 220                         unsigned int src_cnt:3;
 221                         unsigned int bundle:1;
 222                         unsigned int dest_dca:1;
 223                         unsigned int hint:1;
 224                         unsigned int p_disable:1;
 225                         unsigned int q_disable:1;
 226                         unsigned int rsvd:3;
 227                         unsigned int coef:8;
 228                         #define IOAT_OP_PQ_UP 0x8b
 229                         unsigned int op:8;
 230                 } ctl_f;
 231         };
 232         uint64_t        src_addr;
 233         uint64_t        p_addr;
 234         uint64_t        next;
 235         uint64_t        src_addr2;
 236         uint64_t        p_src;
 237         uint64_t        q_src;
 238         uint64_t        q_addr;
 239 };
 240
 241 struct ioat_raw_descriptor {
 242         uint64_t        field[8];
 243 };
 244
 245 struct ioat_pq16a_descriptor {
 246         uint8_t coef[8];
 247         uint64_t src_addr3;
 248         uint64_t src_addr4;
 249         uint64_t src_addr5;
 250         uint64_t src_addr6;
 251         uint64_t src_addr7;
 252         uint64_t src_addr8;
 253         uint64_t src_addr9;
 254 };
 255
 256 struct ioat_pq16b_descriptor {
 257         uint64_t src_addr10;
 258         uint64_t src_addr11;
 259         uint64_t src_addr12;
 260         uint64_t src_addr13;
 261         uint64_t src_addr14;
 262         uint64_t src_addr15;
 263         uint64_t src_addr16;
 264         uint64_t rsvd;
 265 };
 266
 267 union ioat_sed_pq_descriptor {
 268         struct ioat_pq16a_descriptor a;
 269         struct ioat_pq16b_descriptor b;
 270 };
 271
 272 #define SED_SIZE        64
 273
 274 struct ioat_sed_raw_descriptor {
 275         uint64_t        a[8];
 276         uint64_t        b[8];
 277         uint64_t        c[8];
 278 };
 279
 280 #endif