drivers/crypto/ux500/hash/hash_core.c

   1 /*
   2  * Cryptographic API.
   3  * Support for Nomadik hardware crypto engine.
   4
   5  * Copyright (C) ST-Ericsson SA 2010
   6  * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson
   7  * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
   8  * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
   9  * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
  10  * Author: Andreas Westin <andreas.westin@stericsson.com> for ST-Ericsson.
  11  * License terms: GNU General Public License (GPL) version 2
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/err.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/klist.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/crypto.h>
  24
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/dmaengine.h>
  27 #include <linux/bitops.h>
  28
  29 #include <crypto/internal/hash.h>
  30 #include <crypto/sha.h>
  31 #include <crypto/scatterwalk.h>
  32 #include <crypto/algapi.h>
  33
  34 #include <linux/platform_data/crypto-ux500.h>
  35
  36 #include "hash_alg.h"
  37
  38 #define DEV_DBG_NAME "hashX hashX:"
  39
  40 static int hash_mode;
  41 module_param(hash_mode, int, 0);
  42 MODULE_PARM_DESC(hash_mode, "CPU or DMA mode. CPU = 0 (default), DMA = 1");
  43
  44 /**
  45  * Pre-calculated empty message digests.
  46  */
  47 static u8 zero_message_hash_sha1[SHA1_DIGEST_SIZE] = {
  48         0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d,
  49         0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90,
  50         0xaf, 0xd8, 0x07, 0x09
  51 };
  52
  53 static u8 zero_message_hash_sha256[SHA256_DIGEST_SIZE] = {
  54         0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14,
  55         0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24,
  56         0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c,
  57         0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55
  58 };
  59
  60 /* HMAC-SHA1, no key */
  61 static u8 zero_message_hmac_sha1[SHA1_DIGEST_SIZE] = {
  62         0xfb, 0xdb, 0x1d, 0x1b, 0x18, 0xaa, 0x6c, 0x08,
  63         0x32, 0x4b, 0x7d, 0x64, 0xb7, 0x1f, 0xb7, 0x63,
  64         0x70, 0x69, 0x0e, 0x1d
  65 };
  66
  67 /* HMAC-SHA256, no key */
  68 static u8 zero_message_hmac_sha256[SHA256_DIGEST_SIZE] = {
  69         0xb6, 0x13, 0x67, 0x9a, 0x08, 0x14, 0xd9, 0xec,
  70         0x77, 0x2f, 0x95, 0xd7, 0x78, 0xc3, 0x5f, 0xc5,
  71         0xff, 0x16, 0x97, 0xc4, 0x93, 0x71, 0x56, 0x53,
  72         0xc6, 0xc7, 0x12, 0x14, 0x42, 0x92, 0xc5, 0xad
  73 };
  74
  75 /**
  76  * struct hash_driver_data - data specific to the driver.
  77  *
  78  * @device_list:        A list of registered devices to choose from.
  79  * @device_allocation:  A semaphore initialized with number of devices.
  80  */
  81 struct hash_driver_data {
  82         struct klist            device_list;
  83         struct semaphore        device_allocation;
  84 };
  85
  86 static struct hash_driver_data  driver_data;
  87
  88 /* Declaration of functions */
  89 /**
  90  * hash_messagepad - Pads a message and write the nblw bits.
  91  * @device_data:        Structure for the hash device.
  92  * @message:            Last word of a message
  93  * @index_bytes:        The number of bytes in the last message
  94  *
  95  * This function manages the final part of the digest calculation, when less
  96  * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
  97  *
  98  */
  99 static void hash_messagepad(struct hash_device_data *device_data,
 100                 const u32 *message, u8 index_bytes);
 101
 102 /**
 103  * release_hash_device - Releases a previously allocated hash device.
 104  * @device_data:        Structure for the hash device.
 105  *
 106  */
 107 static void release_hash_device(struct hash_device_data *device_data)
 108 {
 109         spin_lock(&device_data->ctx_lock);
 110         device_data->current_ctx->device = NULL;
 111         device_data->current_ctx = NULL;
 112         spin_unlock(&device_data->ctx_lock);
 113
 114         /*
 115          * The down_interruptible part for this semaphore is called in
 116          * cryp_get_device_data.
 117          */
 118         up(&driver_data.device_allocation);
 119 }
 120
 121 static void hash_dma_setup_channel(struct hash_device_data *device_data,
 122                                 struct device *dev)
 123 {
 124         struct hash_platform_data *platform_data = dev->platform_data;
 125         struct dma_slave_config conf = {
 126                 .direction = DMA_MEM_TO_DEV,
 127                 .dst_addr = device_data->phybase + HASH_DMA_FIFO,
 128                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
 129                 .dst_maxburst = 16,
 130         };
 131
 132         dma_cap_zero(device_data->dma.mask);
 133         dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 134
 135         device_data->dma.cfg_mem2hash = platform_data->mem_to_engine;
 136         device_data->dma.chan_mem2hash =
 137                 dma_request_channel(device_data->dma.mask,
 138                                 platform_data->dma_filter,
 139                                 device_data->dma.cfg_mem2hash);
 140
 141         dmaengine_slave_config(device_data->dma.chan_mem2hash, &conf);
 142
 143         init_completion(&device_data->dma.complete);
 144 }
 145
 146 static void hash_dma_callback(void *data)
 147 {
 148         struct hash_ctx *ctx = (struct hash_ctx *) data;
 149
 150         complete(&ctx->device->dma.complete);
 151 }
 152
 153 static int hash_set_dma_transfer(struct hash_ctx *ctx, struct scatterlist *sg,
 154                 int len, enum dma_data_direction direction)
 155 {
 156         struct dma_async_tx_descriptor *desc = NULL;
 157         struct dma_chan *channel = NULL;
 158         dma_cookie_t cookie;
 159
 160         if (direction != DMA_TO_DEVICE) {
 161                 dev_err(ctx->device->dev, "[%s] Invalid DMA direction",
 162                                 __func__);
 163                 return -EFAULT;
 164         }
 165
 166         sg->length = ALIGN(sg->length, HASH_DMA_ALIGN_SIZE);
 167
 168         channel = ctx->device->dma.chan_mem2hash;
 169         ctx->device->dma.sg = sg;
 170         ctx->device->dma.sg_len = dma_map_sg(channel->device->dev,
 171                         ctx->device->dma.sg, ctx->device->dma.nents,
 172                         direction);
 173
 174         if (!ctx->device->dma.sg_len) {
 175                 dev_err(ctx->device->dev,
 176                                 "[%s]: Could not map the sg list (TO_DEVICE)",
 177                                 __func__);
 178                 return -EFAULT;
 179         }
 180
 181         dev_dbg(ctx->device->dev, "[%s]: Setting up DMA for buffer "
 182                         "(TO_DEVICE)", __func__);
 183         desc = dmaengine_prep_slave_sg(channel,
 184                         ctx->device->dma.sg, ctx->device->dma.sg_len,
 185                         direction, DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 186         if (!desc) {
 187                 dev_err(ctx->device->dev,
 188                         "[%s]: device_prep_slave_sg() failed!", __func__);
 189                 return -EFAULT;
 190         }
 191
 192         desc->callback = hash_dma_callback;
 193         desc->callback_param = ctx;
 194
 195         cookie = dmaengine_submit(desc);
 196         dma_async_issue_pending(channel);
 197
 198         return 0;
 199 }
 200
 201 static void hash_dma_done(struct hash_ctx *ctx)
 202 {
 203         struct dma_chan *chan;
 204
 205         chan = ctx->device->dma.chan_mem2hash;
 206         dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
 207         dma_unmap_sg(chan->device->dev, ctx->device->dma.sg,
 208                         ctx->device->dma.sg_len, DMA_TO_DEVICE);
 209
 210 }
 211
 212 static int hash_dma_write(struct hash_ctx *ctx,
 213                 struct scatterlist *sg, int len)
 214 {
 215         int error = hash_set_dma_transfer(ctx, sg, len, DMA_TO_DEVICE);
 216         if (error) {
 217                 dev_dbg(ctx->device->dev, "[%s]: hash_set_dma_transfer() "
 218                         "failed", __func__);
 219                 return error;
 220         }
 221
 222         return len;
 223 }
 224
 225 /**
 226  * get_empty_message_digest - Returns a pre-calculated digest for
 227  * the empty message.
 228  * @device_data:        Structure for the hash device.
 229  * @zero_hash:          Buffer to return the empty message digest.
 230  * @zero_hash_size:     Hash size of the empty message digest.
 231  * @zero_digest:        True if zero_digest returned.
 232  */
 233 static int get_empty_message_digest(
 234                 struct hash_device_data *device_data,
 235                 u8 *zero_hash, u32 *zero_hash_size, bool *zero_digest)
 236 {
 237         int ret = 0;
 238         struct hash_ctx *ctx = device_data->current_ctx;
 239         *zero_digest = false;
 240
 241         /**
 242          * Caller responsible for ctx != NULL.
 243          */
 244
 245         if (HASH_OPER_MODE_HASH == ctx->config.oper_mode) {
 246                 if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
 247                         memcpy(zero_hash, &zero_message_hash_sha1[0],
 248                                         SHA1_DIGEST_SIZE);
 249                         *zero_hash_size = SHA1_DIGEST_SIZE;
 250                         *zero_digest = true;
 251                 } else if (HASH_ALGO_SHA256 ==
 252                                 ctx->config.algorithm) {
 253                         memcpy(zero_hash, &zero_message_hash_sha256[0],
 254                                         SHA256_DIGEST_SIZE);
 255                         *zero_hash_size = SHA256_DIGEST_SIZE;
 256                         *zero_digest = true;
 257                 } else {
 258                         dev_err(device_data->dev, "[%s] "
 259                                         "Incorrect algorithm!"
 260                                         , __func__);
 261                         ret = -EINVAL;
 262                         goto out;
 263                 }
 264         } else if (HASH_OPER_MODE_HMAC == ctx->config.oper_mode) {
 265                 if (!ctx->keylen) {
 266                         if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
 267                                 memcpy(zero_hash, &zero_message_hmac_sha1[0],
 268                                                 SHA1_DIGEST_SIZE);
 269                                 *zero_hash_size = SHA1_DIGEST_SIZE;
 270                                 *zero_digest = true;
 271                         } else if (HASH_ALGO_SHA256 == ctx->config.algorithm) {
 272                                 memcpy(zero_hash, &zero_message_hmac_sha256[0],
 273                                                 SHA256_DIGEST_SIZE);
 274                                 *zero_hash_size = SHA256_DIGEST_SIZE;
 275                                 *zero_digest = true;
 276                         } else {
 277                                 dev_err(device_data->dev, "[%s] "
 278                                                 "Incorrect algorithm!"
 279                                                 , __func__);
 280                                 ret = -EINVAL;
 281                                 goto out;
 282                         }
 283                 } else {
 284                         dev_dbg(device_data->dev, "[%s] Continue hash "
 285                                         "calculation, since hmac key avalable",
 286                                         __func__);
 287                 }
 288         }
 289 out:
 290
 291         return ret;
 292 }
 293
 294 /**
 295  * hash_disable_power - Request to disable power and clock.
 296  * @device_data:        Structure for the hash device.
 297  * @save_device_state:  If true, saves the current hw state.
 298  *
 299  * This function request for disabling power (regulator) and clock,
 300  * and could also save current hw state.
 301  */
 302 static int hash_disable_power(
 303                 struct hash_device_data *device_data,
 304                 bool                    save_device_state)
 305 {
 306         int ret = 0;
 307         struct device *dev = device_data->dev;
 308
 309         spin_lock(&device_data->power_state_lock);
 310         if (!device_data->power_state)
 311                 goto out;
 312
 313         if (save_device_state) {
 314                 hash_save_state(device_data,
 315                                 &device_data->state);
 316                 device_data->restore_dev_state = true;
 317         }
 318
 319         clk_disable(device_data->clk);
 320         ret = regulator_disable(device_data->regulator);
 321         if (ret)
 322                 dev_err(dev, "[%s] regulator_disable() failed!", __func__);
 323
 324         device_data->power_state = false;
 325
 326 out:
 327         spin_unlock(&device_data->power_state_lock);
 328
 329         return ret;
 330 }
 331
 332 /**
 333  * hash_enable_power - Request to enable power and clock.
 334  * @device_data:                Structure for the hash device.
 335  * @restore_device_state:       If true, restores a previous saved hw state.
 336  *
 337  * This function request for enabling power (regulator) and clock,
 338  * and could also restore a previously saved hw state.
 339  */
 340 static int hash_enable_power(
 341                 struct hash_device_data *device_data,
 342                 bool                    restore_device_state)
 343 {
 344         int ret = 0;
 345         struct device *dev = device_data->dev;
 346
 347         spin_lock(&device_data->power_state_lock);
 348         if (!device_data->power_state) {
 349                 ret = regulator_enable(device_data->regulator);
 350                 if (ret) {
 351                         dev_err(dev, "[%s]: regulator_enable() failed!",
 352                                         __func__);
 353                         goto out;
 354                 }
 355                 ret = clk_enable(device_data->clk);
 356                 if (ret) {
 357                         dev_err(dev, "[%s]: clk_enable() failed!",
 358                                         __func__);
 359                         ret = regulator_disable(
 360                                         device_data->regulator);
 361                         goto out;
 362                 }
 363                 device_data->power_state = true;
 364         }
 365
 366         if (device_data->restore_dev_state) {
 367                 if (restore_device_state) {
 368                         device_data->restore_dev_state = false;
 369                         hash_resume_state(device_data,
 370                                 &device_data->state);
 371                 }
 372         }
 373 out:
 374         spin_unlock(&device_data->power_state_lock);
 375
 376         return ret;
 377 }
 378
 379 /**
 380  * hash_get_device_data - Checks for an available hash device and return it.
 381  * @hash_ctx:           Structure for the hash context.
 382  * @device_data:        Structure for the hash device.
 383  *
 384  * This function check for an available hash device and return it to
 385  * the caller.
 386  * Note! Caller need to release the device, calling up().
 387  */
 388 static int hash_get_device_data(struct hash_ctx *ctx,
 389                                 struct hash_device_data **device_data)
 390 {
 391         int                     ret;
 392         struct klist_iter       device_iterator;
 393         struct klist_node       *device_node;
 394         struct hash_device_data *local_device_data = NULL;
 395
 396         /* Wait until a device is available */
 397         ret = down_interruptible(&driver_data.device_allocation);
 398         if (ret)
 399                 return ret;  /* Interrupted */
 400
 401         /* Select a device */
 402         klist_iter_init(&driver_data.device_list, &device_iterator);
 403         device_node = klist_next(&device_iterator);
 404         while (device_node) {
 405                 local_device_data = container_of(device_node,
 406                                            struct hash_device_data, list_node);
 407                 spin_lock(&local_device_data->ctx_lock);
 408                 /* current_ctx allocates a device, NULL = unallocated */
 409                 if (local_device_data->current_ctx) {
 410                         device_node = klist_next(&device_iterator);
 411                 } else {
 412                         local_device_data->current_ctx = ctx;
 413                         ctx->device = local_device_data;
 414                         spin_unlock(&local_device_data->ctx_lock);
 415                         break;
 416                 }
 417                 spin_unlock(&local_device_data->ctx_lock);
 418         }
 419         klist_iter_exit(&device_iterator);
 420
 421         if (!device_node) {
 422                 /**
 423                  * No free device found.
 424                  * Since we allocated a device with down_interruptible, this
 425                  * should not be able to happen.
 426                  * Number of available devices, which are contained in
 427                  * device_allocation, is therefore decremented by not doing
 428                  * an up(device_allocation).
 429                  */
 430                 return -EBUSY;
 431         }
 432
 433         *device_data = local_device_data;
 434
 435         return 0;
 436 }
 437
 438 /**
 439  * hash_hw_write_key - Writes the key to the hardware registries.
 440  *
 441  * @device_data:        Structure for the hash device.
 442  * @key:                Key to be written.
 443  * @keylen:             The lengt of the key.
 444  *
 445  * Note! This function DOES NOT write to the NBLW registry, even though
 446  * specified in the the hw design spec. Either due to incorrect info in the
 447  * spec or due to a bug in the hw.
 448  */
 449 static void hash_hw_write_key(struct hash_device_data *device_data,
 450                 const u8 *key, unsigned int keylen)
 451 {
 452         u32 word = 0;
 453         int nwords = 1;
 454
 455         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 456
 457         while (keylen >= 4) {
 458                 u32 *key_word = (u32 *)key;
 459
 460                 HASH_SET_DIN(key_word, nwords);
 461                 keylen -= 4;
 462                 key += 4;
 463         }
 464
 465         /* Take care of the remaining bytes in the last word */
 466         if (keylen) {
 467                 word = 0;
 468                 while (keylen) {
 469                         word |= (key[keylen - 1] << (8 * (keylen - 1)));
 470                         keylen--;
 471                 }
 472
 473                 HASH_SET_DIN(&word, nwords);
 474         }
 475
 476         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 477                 cpu_relax();
 478
 479         HASH_SET_DCAL;
 480
 481         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 482                 cpu_relax();
 483 }
 484
 485 /**
 486  * init_hash_hw - Initialise the hash hardware for a new calculation.
 487  * @device_data:        Structure for the hash device.
 488  * @ctx:                The hash context.
 489  *
 490  * This function will enable the bits needed to clear and start a new
 491  * calculation.
 492  */
 493 static int init_hash_hw(struct hash_device_data *device_data,
 494                 struct hash_ctx *ctx)
 495 {
 496         int ret = 0;
 497
 498         ret = hash_setconfiguration(device_data, &ctx->config);
 499         if (ret) {
 500                 dev_err(device_data->dev, "[%s] hash_setconfiguration() "
 501                                 "failed!", __func__);
 502                 return ret;
 503         }
 504
 505         hash_begin(device_data, ctx);
 506
 507         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
 508                 hash_hw_write_key(device_data, ctx->key, ctx->keylen);
 509
 510         return ret;
 511 }
 512
 513 /**
 514  * hash_get_nents - Return number of entries (nents) in scatterlist (sg).
 515  *
 516  * @sg:         Scatterlist.
 517  * @size:       Size in bytes.
 518  * @aligned:    True if sg data aligned to work in DMA mode.
 519  *
 520  */
 521 static int hash_get_nents(struct scatterlist *sg, int size, bool *aligned)
 522 {
 523         int nents = 0;
 524         bool aligned_data = true;
 525
 526         while (size > 0 && sg) {
 527                 nents++;
 528                 size -= sg->length;
 529
 530                 /* hash_set_dma_transfer will align last nent */
 531                 if ((aligned && !IS_ALIGNED(sg->offset, HASH_DMA_ALIGN_SIZE))
 532                         || (!IS_ALIGNED(sg->length, HASH_DMA_ALIGN_SIZE) &&
 533                                 size > 0))
 534                         aligned_data = false;
 535
 536                 sg = sg_next(sg);
 537         }
 538
 539         if (aligned)
 540                 *aligned = aligned_data;
 541
 542         if (size != 0)
 543                 return -EFAULT;
 544
 545         return nents;
 546 }
 547
 548 /**
 549  * hash_dma_valid_data - checks for dma valid sg data.
 550  * @sg:         Scatterlist.
 551  * @datasize:   Datasize in bytes.
 552  *
 553  * NOTE! This function checks for dma valid sg data, since dma
 554  * only accept datasizes of even wordsize.
 555  */
 556 static bool hash_dma_valid_data(struct scatterlist *sg, int datasize)
 557 {
 558         bool aligned;
 559
 560         /* Need to include at least one nent, else error */
 561         if (hash_get_nents(sg, datasize, &aligned) < 1)
 562                 return false;
 563
 564         return aligned;
 565 }
 566
 567 /**
 568  * hash_init - Common hash init function for SHA1/SHA2 (SHA256).
 569  * @req: The hash request for the job.
 570  *
 571  * Initialize structures.
 572  */
 573 static int hash_init(struct ahash_request *req)
 574 {
 575         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 576         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 577         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 578
 579         if (!ctx->key)
 580                 ctx->keylen = 0;
 581
 582         memset(&req_ctx->state, 0, sizeof(struct hash_state));
 583         req_ctx->updated = 0;
 584         if (hash_mode == HASH_MODE_DMA) {
 585                 if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
 586                         req_ctx->dma_mode = false; /* Don't use DMA */
 587
 588                         pr_debug(DEV_DBG_NAME " [%s] DMA mode, but direct "
 589                                         "to CPU mode for data size < %d",
 590                                         __func__, HASH_DMA_ALIGN_SIZE);
 591                 } else {
 592                         if (req->nbytes >= HASH_DMA_PERFORMANCE_MIN_SIZE &&
 593                                         hash_dma_valid_data(req->src,
 594                                                 req->nbytes)) {
 595                                 req_ctx->dma_mode = true;
 596                         } else {
 597                                 req_ctx->dma_mode = false;
 598                                 pr_debug(DEV_DBG_NAME " [%s] DMA mode, but use"
 599                                                 " CPU mode for datalength < %d"
 600                                                 " or non-aligned data, except "
 601                                                 "in last nent", __func__,
 602                                                 HASH_DMA_PERFORMANCE_MIN_SIZE);
 603                         }
 604                 }
 605         }
 606         return 0;
 607 }
 608
 609 /**
 610  * hash_processblock - This function processes a single block of 512 bits (64
 611  *                     bytes), word aligned, starting at message.
 612  * @device_data:        Structure for the hash device.
 613  * @message:            Block (512 bits) of message to be written to
 614  *                      the HASH hardware.
 615  *
 616  */
 617 static void hash_processblock(
 618                 struct hash_device_data *device_data,
 619                 const u32 *message, int length)
 620 {
 621         int len = length / HASH_BYTES_PER_WORD;
 622         /*
 623          * NBLW bits. Reset the number of bits in last word (NBLW).
 624          */
 625         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 626
 627         /*
 628          * Write message data to the HASH_DIN register.
 629          */
 630         HASH_SET_DIN(message, len);
 631 }
 632
 633 /**
 634  * hash_messagepad - Pads a message and write the nblw bits.
 635  * @device_data:        Structure for the hash device.
 636  * @message:            Last word of a message.
 637  * @index_bytes:        The number of bytes in the last message.
 638  *
 639  * This function manages the final part of the digest calculation, when less
 640  * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
 641  *
 642  */
 643 static void hash_messagepad(struct hash_device_data *device_data,
 644                 const u32 *message, u8 index_bytes)
 645 {
 646         int nwords = 1;
 647
 648         /*
 649          * Clear hash str register, only clear NBLW
 650          * since DCAL will be reset by hardware.
 651          */
 652         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 653
 654         /* Main loop */
 655         while (index_bytes >= 4) {
 656                 HASH_SET_DIN(message, nwords);
 657                 index_bytes -= 4;
 658                 message++;
 659         }
 660
 661         if (index_bytes)
 662                 HASH_SET_DIN(message, nwords);
 663
 664         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 665                 cpu_relax();
 666
 667         /* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */
 668         HASH_SET_NBLW(index_bytes * 8);
 669         dev_dbg(device_data->dev, "[%s] DIN=0x%08x NBLW=%d", __func__,
 670                         readl_relaxed(&device_data->base->din),
 671                         (int)(readl_relaxed(&device_data->base->str) &
 672                                 HASH_STR_NBLW_MASK));
 673         HASH_SET_DCAL;
 674         dev_dbg(device_data->dev, "[%s] after dcal -> DIN=0x%08x NBLW=%d",
 675                         __func__, readl_relaxed(&device_data->base->din),
 676                         (int)(readl_relaxed(&device_data->base->str) &
 677                                 HASH_STR_NBLW_MASK));
 678
 679         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 680                 cpu_relax();
 681 }
 682
 683 /**
 684  * hash_incrementlength - Increments the length of the current message.
 685  * @ctx: Hash context
 686  * @incr: Length of message processed already
 687  *
 688  * Overflow cannot occur, because conditions for overflow are checked in
 689  * hash_hw_update.
 690  */
 691 static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
 692 {
 693         ctx->state.length.low_word += incr;
 694
 695         /* Check for wrap-around */
 696         if (ctx->state.length.low_word < incr)
 697                 ctx->state.length.high_word++;
 698 }
 699
 700 /**
 701  * hash_setconfiguration - Sets the required configuration for the hash
 702  *                         hardware.
 703  * @device_data:        Structure for the hash device.
 704  * @config:             Pointer to a configuration structure.
 705  */
 706 int hash_setconfiguration(struct hash_device_data *device_data,
 707                 struct hash_config *config)
 708 {
 709         int ret = 0;
 710
 711         if (config->algorithm != HASH_ALGO_SHA1 &&
 712             config->algorithm != HASH_ALGO_SHA256)
 713                 return -EPERM;
 714
 715         /*
 716          * DATAFORM bits. Set the DATAFORM bits to 0b11, which means the data
 717          * to be written to HASH_DIN is considered as 32 bits.
 718          */
 719         HASH_SET_DATA_FORMAT(config->data_format);
 720
 721         /*
 722          * ALGO bit. Set to 0b1 for SHA-1 and 0b0 for SHA-256
 723          */
 724         switch (config->algorithm) {
 725         case HASH_ALGO_SHA1:
 726                 HASH_SET_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
 727                 break;
 728
 729         case HASH_ALGO_SHA256:
 730                 HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
 731                 break;
 732
 733         default:
 734                 dev_err(device_data->dev, "[%s] Incorrect algorithm.",
 735                                 __func__);
 736                 return -EPERM;
 737         }
 738
 739         /*
 740          * MODE bit. This bit selects between HASH or HMAC mode for the
 741          * selected algorithm. 0b0 = HASH and 0b1 = HMAC.
 742          */
 743         if (HASH_OPER_MODE_HASH == config->oper_mode)
 744                 HASH_CLEAR_BITS(&device_data->base->cr,
 745                                 HASH_CR_MODE_MASK);
 746         else if (HASH_OPER_MODE_HMAC == config->oper_mode) {
 747                 HASH_SET_BITS(&device_data->base->cr,
 748                                 HASH_CR_MODE_MASK);
 749                 if (device_data->current_ctx->keylen > HASH_BLOCK_SIZE) {
 750                         /* Truncate key to blocksize */
 751                         dev_dbg(device_data->dev, "[%s] LKEY set", __func__);
 752                         HASH_SET_BITS(&device_data->base->cr,
 753                                         HASH_CR_LKEY_MASK);
 754                 } else {
 755                         dev_dbg(device_data->dev, "[%s] LKEY cleared",
 756                                         __func__);
 757                         HASH_CLEAR_BITS(&device_data->base->cr,
 758                                         HASH_CR_LKEY_MASK);
 759                 }
 760         } else {        /* Wrong hash mode */
 761                 ret = -EPERM;
 762                 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
 763                                 __func__);
 764         }
 765         return ret;
 766 }
 767
 768 /**
 769  * hash_begin - This routine resets some globals and initializes the hash
 770  *              hardware.
 771  * @device_data:        Structure for the hash device.
 772  * @ctx:                Hash context.
 773  */
 774 void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx)
 775 {
 776         /* HW and SW initializations */
 777         /* Note: there is no need to initialize buffer and digest members */
 778
 779         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 780                 cpu_relax();
 781
 782         /*
 783          * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
 784          * prepare the initialize the HASH accelerator to compute the message
 785          * digest of a new message.
 786          */
 787         HASH_INITIALIZE;
 788
 789         /*
 790          * NBLW bits. Reset the number of bits in last word (NBLW).
 791          */
 792         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 793 }
 794
 795 static int hash_process_data(struct hash_device_data *device_data,
 796                 struct hash_ctx *ctx, struct hash_req_ctx *req_ctx,
 797                 int msg_length, u8 *data_buffer, u8 *buffer, u8 *index)
 798 {
 799         int ret = 0;
 800         u32 count;
 801
 802         do {
 803                 if ((*index + msg_length) < HASH_BLOCK_SIZE) {
 804                         for (count = 0; count < msg_length; count++) {
 805                                 buffer[*index + count] =
 806                                         *(data_buffer + count);
 807                         }
 808                         *index += msg_length;
 809                         msg_length = 0;
 810                 } else {
 811                         if (req_ctx->updated) {
 812
 813                                 ret = hash_resume_state(device_data,
 814                                                 &device_data->state);
 815                                 memmove(req_ctx->state.buffer,
 816                                                 device_data->state.buffer,
 817                                                 HASH_BLOCK_SIZE / sizeof(u32));
 818                                 if (ret) {
 819                                         dev_err(device_data->dev, "[%s] "
 820                                                         "hash_resume_state()"
 821                                                         " failed!", __func__);
 822                                         goto out;
 823                                 }
 824                         } else {
 825                                 ret = init_hash_hw(device_data, ctx);
 826                                 if (ret) {
 827                                         dev_err(device_data->dev, "[%s] "
 828                                                         "init_hash_hw()"
 829                                                         " failed!", __func__);
 830                                         goto out;
 831                                 }
 832                                 req_ctx->updated = 1;
 833                         }
 834                         /*
 835                          * If 'data_buffer' is four byte aligned and
 836                          * local buffer does not have any data, we can
 837                          * write data directly from 'data_buffer' to
 838                          * HW peripheral, otherwise we first copy data
 839                          * to a local buffer
 840                          */
 841                         if ((0 == (((u32)data_buffer) % 4))
 842                                         && (0 == *index))
 843                                 hash_processblock(device_data,
 844                                                 (const u32 *)
 845                                                 data_buffer, HASH_BLOCK_SIZE);
 846                         else {
 847                                 for (count = 0; count <
 848                                                 (u32)(HASH_BLOCK_SIZE -
 849                                                         *index);
 850                                                 count++) {
 851                                         buffer[*index + count] =
 852                                                 *(data_buffer + count);
 853                                 }
 854                                 hash_processblock(device_data,
 855                                                 (const u32 *)buffer,
 856                                                 HASH_BLOCK_SIZE);
 857                         }
 858                         hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
 859                         data_buffer += (HASH_BLOCK_SIZE - *index);
 860
 861                         msg_length -= (HASH_BLOCK_SIZE - *index);
 862                         *index = 0;
 863
 864                         ret = hash_save_state(device_data,
 865                                         &device_data->state);
 866
 867                         memmove(device_data->state.buffer,
 868                                         req_ctx->state.buffer,
 869                                         HASH_BLOCK_SIZE / sizeof(u32));
 870                         if (ret) {
 871                                 dev_err(device_data->dev, "[%s] "
 872                                                 "hash_save_state()"
 873                                                 " failed!", __func__);
 874                                 goto out;
 875                         }
 876                 }
 877         } while (msg_length != 0);
 878 out:
 879
 880         return ret;
 881 }
 882
 883 /**
 884  * hash_dma_final - The hash dma final function for SHA1/SHA256.
 885  * @req:        The hash request for the job.
 886  */
 887 static int hash_dma_final(struct ahash_request *req)
 888 {
 889         int ret = 0;
 890         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 891         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 892         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 893         struct hash_device_data *device_data;
 894         u8 digest[SHA256_DIGEST_SIZE];
 895         int bytes_written = 0;
 896
 897         ret = hash_get_device_data(ctx, &device_data);
 898         if (ret)
 899                 return ret;
 900
 901         dev_dbg(device_data->dev, "[%s] (ctx=0x%x)!", __func__, (u32) ctx);
 902
 903         if (req_ctx->updated) {
 904                 ret = hash_resume_state(device_data, &device_data->state);
 905
 906                 if (ret) {
 907                         dev_err(device_data->dev, "[%s] hash_resume_state() "
 908                                         "failed!", __func__);
 909                         goto out;
 910                 }
 911
 912         }
 913
 914         if (!req_ctx->updated) {
 915                 ret = hash_setconfiguration(device_data, &ctx->config);
 916                 if (ret) {
 917                         dev_err(device_data->dev, "[%s] "
 918                                         "hash_setconfiguration() failed!",
 919                                         __func__);
 920                         goto out;
 921                 }
 922
 923                 /* Enable DMA input */
 924                 if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode) {
 925                         HASH_CLEAR_BITS(&device_data->base->cr,
 926                                         HASH_CR_DMAE_MASK);
 927                 } else {
 928                         HASH_SET_BITS(&device_data->base->cr,
 929                                         HASH_CR_DMAE_MASK);
 930                         HASH_SET_BITS(&device_data->base->cr,
 931                                         HASH_CR_PRIVN_MASK);
 932                 }
 933
 934                 HASH_INITIALIZE;
 935
 936                 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
 937                         hash_hw_write_key(device_data, ctx->key, ctx->keylen);
 938
 939                 /* Number of bits in last word = (nbytes * 8) % 32 */
 940                 HASH_SET_NBLW((req->nbytes * 8) % 32);
 941                 req_ctx->updated = 1;
 942         }
 943
 944         /* Store the nents in the dma struct. */
 945         ctx->device->dma.nents = hash_get_nents(req->src, req->nbytes, NULL);
 946         if (!ctx->device->dma.nents) {
 947                 dev_err(device_data->dev, "[%s] "
 948                                 "ctx->device->dma.nents = 0", __func__);
 949                 ret = ctx->device->dma.nents;
 950                 goto out;
 951         }
 952
 953         bytes_written = hash_dma_write(ctx, req->src, req->nbytes);
 954         if (bytes_written != req->nbytes) {
 955                 dev_err(device_data->dev, "[%s] "
 956                                 "hash_dma_write() failed!", __func__);
 957                 ret = bytes_written;
 958                 goto out;
 959         }
 960
 961         wait_for_completion(&ctx->device->dma.complete);
 962         hash_dma_done(ctx);
 963
 964         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 965                 cpu_relax();
 966
 967         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
 968                 unsigned int keylen = ctx->keylen;
 969                 u8 *key = ctx->key;
 970
 971                 dev_dbg(device_data->dev, "[%s] keylen: %d", __func__,
 972                                 ctx->keylen);
 973                 hash_hw_write_key(device_data, key, keylen);
 974         }
 975
 976         hash_get_digest(device_data, digest, ctx->config.algorithm);
 977         memcpy(req->result, digest, ctx->digestsize);
 978
 979 out:
 980         release_hash_device(device_data);
 981
 982         /**
 983          * Allocated in setkey, and only used in HMAC.
 984          */
 985         kfree(ctx->key);
 986
 987         return ret;
 988 }
 989
 990 /**
 991  * hash_hw_final - The final hash calculation function
 992  * @req:        The hash request for the job.
 993  */
 994 static int hash_hw_final(struct ahash_request *req)
 995 {
 996         int ret = 0;
 997         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 998         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 999         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1000         struct hash_device_data *device_data;
1001         u8 digest[SHA256_DIGEST_SIZE];
1002
1003         ret = hash_get_device_data(ctx, &device_data);
1004         if (ret)
1005                 return ret;
1006
1007         dev_dbg(device_data->dev, "[%s] (ctx=0x%x)!", __func__, (u32) ctx);
1008
1009         if (req_ctx->updated) {
1010                 ret = hash_resume_state(device_data, &device_data->state);
1011
1012                 if (ret) {
1013                         dev_err(device_data->dev, "[%s] hash_resume_state() "
1014                                         "failed!", __func__);
1015                         goto out;
1016                 }
1017         } else if (req->nbytes == 0 && ctx->keylen == 0) {
1018                 u8 zero_hash[SHA256_DIGEST_SIZE];
1019                 u32 zero_hash_size = 0;
1020                 bool zero_digest = false;
1021                 /**
1022                  * Use a pre-calculated empty message digest
1023                  * (workaround since hw return zeroes, hw bug!?)
1024                  */
1025                 ret = get_empty_message_digest(device_data, &zero_hash[0],
1026                                 &zero_hash_size, &zero_digest);
1027                 if (!ret && likely(zero_hash_size == ctx->digestsize) &&
1028                                 zero_digest) {
1029                         memcpy(req->result, &zero_hash[0], ctx->digestsize);
1030                         goto out;
1031                 } else if (!ret && !zero_digest) {
1032                         dev_dbg(device_data->dev, "[%s] HMAC zero msg with "
1033                                         "key, continue...", __func__);
1034                 } else {
1035                         dev_err(device_data->dev, "[%s] ret=%d, or wrong "
1036                                         "digest size? %s", __func__, ret,
1037                                         (zero_hash_size == ctx->digestsize) ?
1038                                         "true" : "false");
1039                         /* Return error */
1040                         goto out;
1041                 }
1042         } else if (req->nbytes == 0 && ctx->keylen > 0) {
1043                 dev_err(device_data->dev, "[%s] Empty message with "
1044                                 "keylength > 0, NOT supported.", __func__);
1045                 goto out;
1046         }
1047
1048         if (!req_ctx->updated) {
1049                 ret = init_hash_hw(device_data, ctx);
1050                 if (ret) {
1051                         dev_err(device_data->dev, "[%s] init_hash_hw() "
1052                                         "failed!", __func__);
1053                         goto out;
1054                 }
1055         }
1056
1057         if (req_ctx->state.index) {
1058                 hash_messagepad(device_data, req_ctx->state.buffer,
1059                                 req_ctx->state.index);
1060         } else {
1061                 HASH_SET_DCAL;
1062                 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
1063                         cpu_relax();
1064         }
1065
1066         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
1067                 unsigned int keylen = ctx->keylen;
1068                 u8 *key = ctx->key;
1069
1070                 dev_dbg(device_data->dev, "[%s] keylen: %d", __func__,
1071                                 ctx->keylen);
1072                 hash_hw_write_key(device_data, key, keylen);
1073         }
1074
1075         hash_get_digest(device_data, digest, ctx->config.algorithm);
1076         memcpy(req->result, digest, ctx->digestsize);
1077
1078 out:
1079         release_hash_device(device_data);
1080
1081         /**
1082          * Allocated in setkey, and only used in HMAC.
1083          */
1084         kfree(ctx->key);
1085
1086         return ret;
1087 }
1088
1089 /**
1090  * hash_hw_update - Updates current HASH computation hashing another part of
1091  *                  the message.
1092  * @req:        Byte array containing the message to be hashed (caller
1093  *              allocated).
1094  */
1095 int hash_hw_update(struct ahash_request *req)
1096 {
1097         int ret = 0;
1098         u8 index = 0;
1099         u8 *buffer;
1100         struct hash_device_data *device_data;
1101         u8 *data_buffer;
1102         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1103         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1104         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1105         struct crypto_hash_walk walk;
1106         int msg_length = crypto_hash_walk_first(req, &walk);
1107
1108         /* Empty message ("") is correct indata */
1109         if (msg_length == 0)
1110                 return ret;
1111
1112         index = req_ctx->state.index;
1113         buffer = (u8 *)req_ctx->state.buffer;
1114
1115         /* Check if ctx->state.length + msg_length
1116            overflows */
1117         if (msg_length > (req_ctx->state.length.low_word + msg_length) &&
1118                         HASH_HIGH_WORD_MAX_VAL ==
1119                         req_ctx->state.length.high_word) {
1120                 pr_err(DEV_DBG_NAME " [%s] HASH_MSG_LENGTH_OVERFLOW!",
1121                                 __func__);
1122                 return -EPERM;
1123         }
1124
1125         ret = hash_get_device_data(ctx, &device_data);
1126         if (ret)
1127                 return ret;
1128
1129         /* Main loop */
1130         while (0 != msg_length) {
1131                 data_buffer = walk.data;
1132                 ret = hash_process_data(device_data, ctx, req_ctx, msg_length,
1133                                 data_buffer, buffer, &index);
1134
1135                 if (ret) {
1136                         dev_err(device_data->dev, "[%s] hash_internal_hw_"
1137                                         "update() failed!", __func__);
1138                         goto out;
1139                 }
1140
1141                 msg_length = crypto_hash_walk_done(&walk, 0);
1142         }
1143
1144         req_ctx->state.index = index;
1145         dev_dbg(device_data->dev, "[%s] indata length=%d, bin=%d))",
1146                         __func__, req_ctx->state.index,
1147                         req_ctx->state.bit_index);
1148
1149 out:
1150         release_hash_device(device_data);
1151
1152         return ret;
1153 }
1154
1155 /**
1156  * hash_resume_state - Function that resumes the state of an calculation.
1157  * @device_data:        Pointer to the device structure.
1158  * @device_state:       The state to be restored in the hash hardware
1159  */
1160 int hash_resume_state(struct hash_device_data *device_data,
1161                 const struct hash_state *device_state)
1162 {
1163         u32 temp_cr;
1164         s32 count;
1165         int hash_mode = HASH_OPER_MODE_HASH;
1166
1167         if (NULL == device_state) {
1168                 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1169                                 __func__);
1170                 return -EPERM;
1171         }
1172
1173         /* Check correctness of index and length members */
1174         if (device_state->index > HASH_BLOCK_SIZE
1175             || (device_state->length.low_word % HASH_BLOCK_SIZE) != 0) {
1176                 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1177                                 __func__);
1178                 return -EPERM;
1179         }
1180
1181         /*
1182          * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
1183          * prepare the initialize the HASH accelerator to compute the message
1184          * digest of a new message.
1185          */
1186         HASH_INITIALIZE;
1187
1188         temp_cr = device_state->temp_cr;
1189         writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
1190
1191         if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
1192                 hash_mode = HASH_OPER_MODE_HMAC;
1193         else
1194                 hash_mode = HASH_OPER_MODE_HASH;
1195
1196         for (count = 0; count < HASH_CSR_COUNT; count++) {
1197                 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1198                         break;
1199
1200                 writel_relaxed(device_state->csr[count],
1201                                 &device_data->base->csrx[count]);
1202         }
1203
1204         writel_relaxed(device_state->csfull, &device_data->base->csfull);
1205         writel_relaxed(device_state->csdatain, &device_data->base->csdatain);
1206
1207         writel_relaxed(device_state->str_reg, &device_data->base->str);
1208         writel_relaxed(temp_cr, &device_data->base->cr);
1209
1210         return 0;
1211 }
1212
1213 /**
1214  * hash_save_state - Function that saves the state of hardware.
1215  * @device_data:        Pointer to the device structure.
1216  * @device_state:       The strucure where the hardware state should be saved.
1217  */
1218 int hash_save_state(struct hash_device_data *device_data,
1219                 struct hash_state *device_state)
1220 {
1221         u32 temp_cr;
1222         u32 count;
1223         int hash_mode = HASH_OPER_MODE_HASH;
1224
1225         if (NULL == device_state) {
1226                 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1227                                 __func__);
1228                 return -ENOTSUPP;
1229         }
1230
1231         /* Write dummy value to force digest intermediate calculation. This
1232          * actually makes sure that there isn't any ongoing calculation in the
1233          * hardware.
1234          */
1235         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
1236                 cpu_relax();
1237
1238         temp_cr = readl_relaxed(&device_data->base->cr);
1239
1240         device_state->str_reg = readl_relaxed(&device_data->base->str);
1241
1242         device_state->din_reg = readl_relaxed(&device_data->base->din);
1243
1244         if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
1245                 hash_mode = HASH_OPER_MODE_HMAC;
1246         else
1247                 hash_mode = HASH_OPER_MODE_HASH;
1248
1249         for (count = 0; count < HASH_CSR_COUNT; count++) {
1250                 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1251                         break;
1252
1253                 device_state->csr[count] =
1254                         readl_relaxed(&device_data->base->csrx[count]);
1255         }
1256
1257         device_state->csfull = readl_relaxed(&device_data->base->csfull);
1258         device_state->csdatain = readl_relaxed(&device_data->base->csdatain);
1259
1260         device_state->temp_cr = temp_cr;
1261
1262         return 0;
1263 }
1264
1265 /**
1266  * hash_check_hw - This routine checks for peripheral Ids and PCell Ids.
1267  * @device_data:
1268  *
1269  */
1270 int hash_check_hw(struct hash_device_data *device_data)
1271 {
1272         /* Checking Peripheral Ids  */
1273         if (HASH_P_ID0 == readl_relaxed(&device_data->base->periphid0)
1274                 && HASH_P_ID1 == readl_relaxed(&device_data->base->periphid1)
1275                 && HASH_P_ID2 == readl_relaxed(&device_data->base->periphid2)
1276                 && HASH_P_ID3 == readl_relaxed(&device_data->base->periphid3)
1277                 && HASH_CELL_ID0 == readl_relaxed(&device_data->base->cellid0)
1278                 && HASH_CELL_ID1 == readl_relaxed(&device_data->base->cellid1)
1279                 && HASH_CELL_ID2 == readl_relaxed(&device_data->base->cellid2)
1280                 && HASH_CELL_ID3 == readl_relaxed(&device_data->base->cellid3)
1281            ) {
1282                 return 0;
1283         }
1284
1285         dev_err(device_data->dev, "[%s] HASH_UNSUPPORTED_HW!",
1286                         __func__);
1287         return -ENOTSUPP;
1288 }
1289
1290 /**
1291  * hash_get_digest - Gets the digest.
1292  * @device_data:        Pointer to the device structure.
1293  * @digest:             User allocated byte array for the calculated digest.
1294  * @algorithm:          The algorithm in use.
1295  */
1296 void hash_get_digest(struct hash_device_data *device_data,
1297                 u8 *digest, int algorithm)
1298 {
1299         u32 temp_hx_val, count;
1300         int loop_ctr;
1301
1302         if (algorithm != HASH_ALGO_SHA1 && algorithm != HASH_ALGO_SHA256) {
1303                 dev_err(device_data->dev, "[%s] Incorrect algorithm %d",
1304                                 __func__, algorithm);
1305                 return;
1306         }
1307
1308         if (algorithm == HASH_ALGO_SHA1)
1309                 loop_ctr = SHA1_DIGEST_SIZE / sizeof(u32);
1310         else
1311                 loop_ctr = SHA256_DIGEST_SIZE / sizeof(u32);
1312
1313         dev_dbg(device_data->dev, "[%s] digest array:(0x%x)",
1314                         __func__, (u32) digest);
1315
1316         /* Copy result into digest array */
1317         for (count = 0; count < loop_ctr; count++) {
1318                 temp_hx_val = readl_relaxed(&device_data->base->hx[count]);
1319                 digest[count * 4] = (u8) ((temp_hx_val >> 24) & 0xFF);
1320                 digest[count * 4 + 1] = (u8) ((temp_hx_val >> 16) & 0xFF);
1321                 digest[count * 4 + 2] = (u8) ((temp_hx_val >> 8) & 0xFF);
1322                 digest[count * 4 + 3] = (u8) ((temp_hx_val >> 0) & 0xFF);
1323         }
1324 }
1325
1326 /**
1327  * hash_update - The hash update function for SHA1/SHA2 (SHA256).
1328  * @req: The hash request for the job.
1329  */
1330 static int ahash_update(struct ahash_request *req)
1331 {
1332         int ret = 0;
1333         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1334
1335         if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode)
1336                 ret = hash_hw_update(req);
1337         /* Skip update for DMA, all data will be passed to DMA in final */
1338
1339         if (ret) {
1340                 pr_err(DEV_DBG_NAME " [%s] hash_hw_update() failed!",
1341                                 __func__);
1342         }
1343
1344         return ret;
1345 }
1346
1347 /**
1348  * hash_final - The hash final function for SHA1/SHA2 (SHA256).
1349  * @req:        The hash request for the job.
1350  */
1351 static int ahash_final(struct ahash_request *req)
1352 {
1353         int ret = 0;
1354         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1355
1356         pr_debug(DEV_DBG_NAME " [%s] data size: %d", __func__, req->nbytes);
1357
1358         if ((hash_mode == HASH_MODE_DMA) && req_ctx->dma_mode)
1359                 ret = hash_dma_final(req);
1360         else
1361                 ret = hash_hw_final(req);
1362
1363         if (ret) {
1364                 pr_err(DEV_DBG_NAME " [%s] hash_hw/dma_final() failed",
1365                                 __func__);
1366         }
1367
1368         return ret;
1369 }
1370
1371 static int hash_setkey(struct crypto_ahash *tfm,
1372                 const u8 *key, unsigned int keylen, int alg)
1373 {
1374         int ret = 0;
1375         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1376
1377         /**
1378          * Freed in final.
1379          */
1380         ctx->key = kmemdup(key, keylen, GFP_KERNEL);
1381         if (!ctx->key) {
1382                 pr_err(DEV_DBG_NAME " [%s] Failed to allocate ctx->key "
1383                        "for %d\n", __func__, alg);
1384                 return -ENOMEM;
1385         }
1386         ctx->keylen = keylen;
1387
1388         return ret;
1389 }
1390
1391 static int ahash_sha1_init(struct ahash_request *req)
1392 {
1393         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1394         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1395
1396         ctx->config.data_format = HASH_DATA_8_BITS;
1397         ctx->config.algorithm = HASH_ALGO_SHA1;
1398         ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1399         ctx->digestsize = SHA1_DIGEST_SIZE;
1400
1401         return hash_init(req);
1402 }
1403
1404 static int ahash_sha256_init(struct ahash_request *req)
1405 {
1406         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1407         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1408
1409         ctx->config.data_format = HASH_DATA_8_BITS;
1410         ctx->config.algorithm = HASH_ALGO_SHA256;
1411         ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1412         ctx->digestsize = SHA256_DIGEST_SIZE;
1413
1414         return hash_init(req);
1415 }
1416
1417 static int ahash_sha1_digest(struct ahash_request *req)
1418 {
1419         int ret2, ret1;
1420
1421         ret1 = ahash_sha1_init(req);
1422         if (ret1)
1423                 goto out;
1424
1425         ret1 = ahash_update(req);
1426         ret2 = ahash_final(req);
1427
1428 out:
1429         return ret1 ? ret1 : ret2;
1430 }
1431
1432 static int ahash_sha256_digest(struct ahash_request *req)
1433 {
1434         int ret2, ret1;
1435
1436         ret1 = ahash_sha256_init(req);
1437         if (ret1)
1438                 goto out;
1439
1440         ret1 = ahash_update(req);
1441         ret2 = ahash_final(req);
1442
1443 out:
1444         return ret1 ? ret1 : ret2;
1445 }
1446
1447 static int hmac_sha1_init(struct ahash_request *req)
1448 {
1449         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1450         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1451
1452         ctx->config.data_format = HASH_DATA_8_BITS;
1453         ctx->config.algorithm   = HASH_ALGO_SHA1;
1454         ctx->config.oper_mode   = HASH_OPER_MODE_HMAC;
1455         ctx->digestsize         = SHA1_DIGEST_SIZE;
1456
1457         return hash_init(req);
1458 }
1459
1460 static int hmac_sha256_init(struct ahash_request *req)
1461 {
1462         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1463         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1464
1465         ctx->config.data_format = HASH_DATA_8_BITS;
1466         ctx->config.algorithm   = HASH_ALGO_SHA256;
1467         ctx->config.oper_mode   = HASH_OPER_MODE_HMAC;
1468         ctx->digestsize         = SHA256_DIGEST_SIZE;
1469
1470         return hash_init(req);
1471 }
1472
1473 static int hmac_sha1_digest(struct ahash_request *req)
1474 {
1475         int ret2, ret1;
1476
1477         ret1 = hmac_sha1_init(req);
1478         if (ret1)
1479                 goto out;
1480
1481         ret1 = ahash_update(req);
1482         ret2 = ahash_final(req);
1483
1484 out:
1485         return ret1 ? ret1 : ret2;
1486 }
1487
1488 static int hmac_sha256_digest(struct ahash_request *req)
1489 {
1490         int ret2, ret1;
1491
1492         ret1 = hmac_sha256_init(req);
1493         if (ret1)
1494                 goto out;
1495
1496         ret1 = ahash_update(req);
1497         ret2 = ahash_final(req);
1498
1499 out:
1500         return ret1 ? ret1 : ret2;
1501 }
1502
1503 static int hmac_sha1_setkey(struct crypto_ahash *tfm,
1504                 const u8 *key, unsigned int keylen)
1505 {
1506         return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA1);
1507 }
1508
1509 static int hmac_sha256_setkey(struct crypto_ahash *tfm,
1510                 const u8 *key, unsigned int keylen)
1511 {
1512         return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA256);
1513 }
1514
1515 struct hash_algo_template {
1516         struct hash_config conf;
1517         struct ahash_alg hash;
1518 };
1519
1520 static int hash_cra_init(struct crypto_tfm *tfm)
1521 {
1522         struct hash_ctx *ctx = crypto_tfm_ctx(tfm);
1523         struct crypto_alg *alg = tfm->__crt_alg;
1524         struct hash_algo_template *hash_alg;
1525
1526         hash_alg = container_of(__crypto_ahash_alg(alg),
1527                         struct hash_algo_template,
1528                         hash);
1529
1530         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1531                         sizeof(struct hash_req_ctx));
1532
1533         ctx->config.data_format = HASH_DATA_8_BITS;
1534         ctx->config.algorithm = hash_alg->conf.algorithm;
1535         ctx->config.oper_mode = hash_alg->conf.oper_mode;
1536
1537         ctx->digestsize = hash_alg->hash.halg.digestsize;
1538
1539         return 0;
1540 }
1541
1542 static struct hash_algo_template hash_algs[] = {
1543         {
1544                         .conf.algorithm = HASH_ALGO_SHA1,
1545                         .conf.oper_mode = HASH_OPER_MODE_HASH,
1546                         .hash = {
1547                                 .init = hash_init,
1548                                 .update = ahash_update,
1549                                 .final = ahash_final,
1550                                 .digest = ahash_sha1_digest,
1551                                 .halg.digestsize = SHA1_DIGEST_SIZE,
1552                                 .halg.statesize = sizeof(struct hash_ctx),
1553                                 .halg.base = {
1554                                         .cra_name = "sha1",
1555                                         .cra_driver_name = "sha1-ux500",
1556                                         .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1557                                                         CRYPTO_ALG_ASYNC,
1558                                         .cra_blocksize = SHA1_BLOCK_SIZE,
1559                                         .cra_ctxsize = sizeof(struct hash_ctx),
1560                                         .cra_init = hash_cra_init,
1561                                         .cra_module = THIS_MODULE,
1562                         }
1563                 }
1564         },
1565         {
1566                         .conf.algorithm         = HASH_ALGO_SHA256,
1567                         .conf.oper_mode         = HASH_OPER_MODE_HASH,
1568                         .hash = {
1569                                 .init = hash_init,
1570                                 .update = ahash_update,
1571                                 .final = ahash_final,
1572                                 .digest = ahash_sha256_digest,
1573                                 .halg.digestsize = SHA256_DIGEST_SIZE,
1574                                 .halg.statesize = sizeof(struct hash_ctx),
1575                                 .halg.base = {
1576                                         .cra_name = "sha256",
1577                                         .cra_driver_name = "sha256-ux500",
1578                                         .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1579                                                         CRYPTO_ALG_ASYNC,
1580                                         .cra_blocksize = SHA256_BLOCK_SIZE,
1581                                         .cra_ctxsize = sizeof(struct hash_ctx),
1582                                         .cra_type = &crypto_ahash_type,
1583                                         .cra_init = hash_cra_init,
1584                                         .cra_module = THIS_MODULE,
1585                                 }
1586                         }
1587
1588         },
1589         {
1590                         .conf.algorithm         = HASH_ALGO_SHA1,
1591                         .conf.oper_mode         = HASH_OPER_MODE_HMAC,
1592                         .hash = {
1593                                 .init = hash_init,
1594                                 .update = ahash_update,
1595                                 .final = ahash_final,
1596                                 .digest = hmac_sha1_digest,
1597                                 .setkey = hmac_sha1_setkey,
1598                                 .halg.digestsize = SHA1_DIGEST_SIZE,
1599                                 .halg.statesize = sizeof(struct hash_ctx),
1600                                 .halg.base = {
1601                                         .cra_name = "hmac(sha1)",
1602                                         .cra_driver_name = "hmac-sha1-ux500",
1603                                         .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1604                                                         CRYPTO_ALG_ASYNC,
1605                                         .cra_blocksize = SHA1_BLOCK_SIZE,
1606                                         .cra_ctxsize = sizeof(struct hash_ctx),
1607                                         .cra_type = &crypto_ahash_type,
1608                                         .cra_init = hash_cra_init,
1609                                         .cra_module = THIS_MODULE,
1610                                 }
1611                         }
1612         },
1613         {
1614                         .conf.algorithm         = HASH_ALGO_SHA256,
1615                         .conf.oper_mode         = HASH_OPER_MODE_HMAC,
1616                         .hash = {
1617                                 .init = hash_init,
1618                                 .update = ahash_update,
1619                                 .final = ahash_final,
1620                                 .digest = hmac_sha256_digest,
1621                                 .setkey = hmac_sha256_setkey,
1622                                 .halg.digestsize = SHA256_DIGEST_SIZE,
1623                                 .halg.statesize = sizeof(struct hash_ctx),
1624                                 .halg.base = {
1625                                         .cra_name = "hmac(sha256)",
1626                                         .cra_driver_name = "hmac-sha256-ux500",
1627                                         .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1628                                                         CRYPTO_ALG_ASYNC,
1629                                         .cra_blocksize = SHA256_BLOCK_SIZE,
1630                                         .cra_ctxsize = sizeof(struct hash_ctx),
1631                                         .cra_type = &crypto_ahash_type,
1632                                         .cra_init = hash_cra_init,
1633                                         .cra_module = THIS_MODULE,
1634                                 }
1635                         }
1636         }
1637 };
1638
1639 /**
1640  * hash_algs_register_all -
1641  */
1642 static int ahash_algs_register_all(struct hash_device_data *device_data)
1643 {
1644         int ret;
1645         int i;
1646         int count;
1647
1648         for (i = 0; i < ARRAY_SIZE(hash_algs); i++) {
1649                 ret = crypto_register_ahash(&hash_algs[i].hash);
1650                 if (ret) {
1651                         count = i;
1652                         dev_err(device_data->dev, "[%s] alg registration failed",
1653                                 hash_algs[i].hash.halg.base.cra_driver_name);
1654                         goto unreg;
1655                 }
1656         }
1657         return 0;
1658 unreg:
1659         for (i = 0; i < count; i++)
1660                 crypto_unregister_ahash(&hash_algs[i].hash);
1661         return ret;
1662 }
1663
1664 /**
1665  * hash_algs_unregister_all -
1666  */
1667 static void ahash_algs_unregister_all(struct hash_device_data *device_data)
1668 {
1669         int i;
1670
1671         for (i = 0; i < ARRAY_SIZE(hash_algs); i++)
1672                 crypto_unregister_ahash(&hash_algs[i].hash);
1673 }
1674
1675 /**
1676  * ux500_hash_probe - Function that probes the hash hardware.
1677  * @pdev: The platform device.
1678  */
1679 static int ux500_hash_probe(struct platform_device *pdev)
1680 {
1681         int                     ret = 0;
1682         struct resource         *res = NULL;
1683         struct hash_device_data *device_data;
1684         struct device           *dev = &pdev->dev;
1685
1686         device_data = kzalloc(sizeof(struct hash_device_data), GFP_ATOMIC);
1687         if (!device_data) {
1688                 dev_dbg(dev, "[%s] kzalloc() failed!", __func__);
1689                 ret = -ENOMEM;
1690                 goto out;
1691         }
1692
1693         device_data->dev = dev;
1694         device_data->current_ctx = NULL;
1695
1696         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1697         if (!res) {
1698                 dev_dbg(dev, "[%s] platform_get_resource() failed!", __func__);
1699                 ret = -ENODEV;
1700                 goto out_kfree;
1701         }
1702
1703         res = request_mem_region(res->start, resource_size(res), pdev->name);
1704         if (res == NULL) {
1705                 dev_dbg(dev, "[%s] request_mem_region() failed!", __func__);
1706                 ret = -EBUSY;
1707                 goto out_kfree;
1708         }
1709
1710         device_data->phybase = res->start;
1711         device_data->base = ioremap(res->start, resource_size(res));
1712         if (!device_data->base) {
1713                 dev_err(dev, "[%s] ioremap() failed!",
1714                                 __func__);
1715                 ret = -ENOMEM;
1716                 goto out_free_mem;
1717         }
1718         spin_lock_init(&device_data->ctx_lock);
1719         spin_lock_init(&device_data->power_state_lock);
1720
1721         /* Enable power for HASH1 hardware block */
1722         device_data->regulator = regulator_get(dev, "v-ape");
1723         if (IS_ERR(device_data->regulator)) {
1724                 dev_err(dev, "[%s] regulator_get() failed!", __func__);
1725                 ret = PTR_ERR(device_data->regulator);
1726                 device_data->regulator = NULL;
1727                 goto out_unmap;
1728         }
1729
1730         /* Enable the clock for HASH1 hardware block */
1731         device_data->clk = clk_get(dev, NULL);
1732         if (IS_ERR(device_data->clk)) {
1733                 dev_err(dev, "[%s] clk_get() failed!", __func__);
1734                 ret = PTR_ERR(device_data->clk);
1735                 goto out_regulator;
1736         }
1737
1738         ret = clk_prepare(device_data->clk);
1739         if (ret) {
1740                 dev_err(dev, "[%s] clk_prepare() failed!", __func__);
1741                 goto out_clk;
1742         }
1743
1744         /* Enable device power (and clock) */
1745         ret = hash_enable_power(device_data, false);
1746         if (ret) {
1747                 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1748                 goto out_clk_unprepare;
1749         }
1750
1751         ret = hash_check_hw(device_data);
1752         if (ret) {
1753                 dev_err(dev, "[%s] hash_check_hw() failed!", __func__);
1754                 goto out_power;
1755         }
1756
1757         if (hash_mode == HASH_MODE_DMA)
1758                 hash_dma_setup_channel(device_data, dev);
1759
1760         platform_set_drvdata(pdev, device_data);
1761
1762         /* Put the new device into the device list... */
1763         klist_add_tail(&device_data->list_node, &driver_data.device_list);
1764         /* ... and signal that a new device is available. */
1765         up(&driver_data.device_allocation);
1766
1767         ret = ahash_algs_register_all(device_data);
1768         if (ret) {
1769                 dev_err(dev, "[%s] ahash_algs_register_all() "
1770                                 "failed!", __func__);
1771                 goto out_power;
1772         }
1773
1774         dev_info(dev, "successfully registered\n");
1775         return 0;
1776
1777 out_power:
1778         hash_disable_power(device_data, false);
1779
1780 out_clk_unprepare:
1781         clk_unprepare(device_data->clk);
1782
1783 out_clk:
1784         clk_put(device_data->clk);
1785
1786 out_regulator:
1787         regulator_put(device_data->regulator);
1788
1789 out_unmap:
1790         iounmap(device_data->base);
1791
1792 out_free_mem:
1793         release_mem_region(res->start, resource_size(res));
1794
1795 out_kfree:
1796         kfree(device_data);
1797 out:
1798         return ret;
1799 }
1800
1801 /**
1802  * ux500_hash_remove - Function that removes the hash device from the platform.
1803  * @pdev: The platform device.
1804  */
1805 static int ux500_hash_remove(struct platform_device *pdev)
1806 {
1807         struct resource         *res;
1808         struct hash_device_data *device_data;
1809         struct device           *dev = &pdev->dev;
1810
1811         device_data = platform_get_drvdata(pdev);
1812         if (!device_data) {
1813                 dev_err(dev, "[%s]: platform_get_drvdata() failed!",
1814                         __func__);
1815                 return -ENOMEM;
1816         }
1817
1818         /* Try to decrease the number of available devices. */
1819         if (down_trylock(&driver_data.device_allocation))
1820                 return -EBUSY;
1821
1822         /* Check that the device is free */
1823         spin_lock(&device_data->ctx_lock);
1824         /* current_ctx allocates a device, NULL = unallocated */
1825         if (device_data->current_ctx) {
1826                 /* The device is busy */
1827                 spin_unlock(&device_data->ctx_lock);
1828                 /* Return the device to the pool. */
1829                 up(&driver_data.device_allocation);
1830                 return -EBUSY;
1831         }
1832
1833         spin_unlock(&device_data->ctx_lock);
1834
1835         /* Remove the device from the list */
1836         if (klist_node_attached(&device_data->list_node))
1837                 klist_remove(&device_data->list_node);
1838
1839         /* If this was the last device, remove the services */
1840         if (list_empty(&driver_data.device_list.k_list))
1841                 ahash_algs_unregister_all(device_data);
1842
1843         if (hash_disable_power(device_data, false))
1844                 dev_err(dev, "[%s]: hash_disable_power() failed",
1845                         __func__);
1846
1847         clk_unprepare(device_data->clk);
1848         clk_put(device_data->clk);
1849         regulator_put(device_data->regulator);
1850
1851         iounmap(device_data->base);
1852
1853         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1854         if (res)
1855                 release_mem_region(res->start, resource_size(res));
1856
1857         kfree(device_data);
1858
1859         return 0;
1860 }
1861
1862 /**
1863  * ux500_hash_shutdown - Function that shutdown the hash device.
1864  * @pdev: The platform device
1865  */
1866 static void ux500_hash_shutdown(struct platform_device *pdev)
1867 {
1868         struct resource *res = NULL;
1869         struct hash_device_data *device_data;
1870
1871         device_data = platform_get_drvdata(pdev);
1872         if (!device_data) {
1873                 dev_err(&pdev->dev, "[%s] platform_get_drvdata() failed!",
1874                                 __func__);
1875                 return;
1876         }
1877
1878         /* Check that the device is free */
1879         spin_lock(&device_data->ctx_lock);
1880         /* current_ctx allocates a device, NULL = unallocated */
1881         if (!device_data->current_ctx) {
1882                 if (down_trylock(&driver_data.device_allocation))
1883                         dev_dbg(&pdev->dev, "[%s]: Cryp still in use!"
1884                                 "Shutting down anyway...", __func__);
1885                 /**
1886                  * (Allocate the device)
1887                  * Need to set this to non-null (dummy) value,
1888                  * to avoid usage if context switching.
1889                  */
1890                 device_data->current_ctx++;
1891         }
1892         spin_unlock(&device_data->ctx_lock);
1893
1894         /* Remove the device from the list */
1895         if (klist_node_attached(&device_data->list_node))
1896                 klist_remove(&device_data->list_node);
1897
1898         /* If this was the last device, remove the services */
1899         if (list_empty(&driver_data.device_list.k_list))
1900                 ahash_algs_unregister_all(device_data);
1901
1902         iounmap(device_data->base);
1903
1904         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1905         if (res)
1906                 release_mem_region(res->start, resource_size(res));
1907
1908         if (hash_disable_power(device_data, false))
1909                 dev_err(&pdev->dev, "[%s] hash_disable_power() failed",
1910                                 __func__);
1911 }
1912
1913 /**
1914  * ux500_hash_suspend - Function that suspends the hash device.
1915  * @dev:        Device to suspend.
1916  */
1917 static int ux500_hash_suspend(struct device *dev)
1918 {
1919         int ret;
1920         struct hash_device_data *device_data;
1921         struct hash_ctx *temp_ctx = NULL;
1922
1923         device_data = dev_get_drvdata(dev);
1924         if (!device_data) {
1925                 dev_err(dev, "[%s] platform_get_drvdata() failed!", __func__);
1926                 return -ENOMEM;
1927         }
1928
1929         spin_lock(&device_data->ctx_lock);
1930         if (!device_data->current_ctx)
1931                 device_data->current_ctx++;
1932         spin_unlock(&device_data->ctx_lock);
1933
1934         if (device_data->current_ctx == ++temp_ctx) {
1935                 if (down_interruptible(&driver_data.device_allocation))
1936                         dev_dbg(dev, "[%s]: down_interruptible() failed",
1937                                 __func__);
1938                 ret = hash_disable_power(device_data, false);
1939
1940         } else
1941                 ret = hash_disable_power(device_data, true);
1942
1943         if (ret)
1944                 dev_err(dev, "[%s]: hash_disable_power()", __func__);
1945
1946         return ret;
1947 }
1948
1949 /**
1950  * ux500_hash_resume - Function that resume the hash device.
1951  * @dev:        Device to resume.
1952  */
1953 static int ux500_hash_resume(struct device *dev)
1954 {
1955         int ret = 0;
1956         struct hash_device_data *device_data;
1957         struct hash_ctx *temp_ctx = NULL;
1958
1959         device_data = dev_get_drvdata(dev);
1960         if (!device_data) {
1961                 dev_err(dev, "[%s] platform_get_drvdata() failed!", __func__);
1962                 return -ENOMEM;
1963         }
1964
1965         spin_lock(&device_data->ctx_lock);
1966         if (device_data->current_ctx == ++temp_ctx)
1967                 device_data->current_ctx = NULL;
1968         spin_unlock(&device_data->ctx_lock);
1969
1970         if (!device_data->current_ctx)
1971                 up(&driver_data.device_allocation);
1972         else
1973                 ret = hash_enable_power(device_data, true);
1974
1975         if (ret)
1976                 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1977
1978         return ret;
1979 }
1980
1981 static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume);
1982
1983 static const struct of_device_id ux500_hash_match[] = {
1984         { .compatible = "stericsson,ux500-hash" },
1985         { },
1986 };
1987
1988 static struct platform_driver hash_driver = {
1989         .probe  = ux500_hash_probe,
1990         .remove = ux500_hash_remove,
1991         .shutdown = ux500_hash_shutdown,
1992         .driver = {
1993                 .owner = THIS_MODULE,
1994                 .name  = "hash1",
1995                 .of_match_table = ux500_hash_match,
1996                 .pm    = &ux500_hash_pm,
1997         }
1998 };
1999
2000 /**
2001  * ux500_hash_mod_init - The kernel module init function.
2002  */
2003 static int __init ux500_hash_mod_init(void)
2004 {
2005         klist_init(&driver_data.device_list, NULL, NULL);
2006         /* Initialize the semaphore to 0 devices (locked state) */
2007         sema_init(&driver_data.device_allocation, 0);
2008
2009         return platform_driver_register(&hash_driver);
2010 }
2011
2012 /**
2013  * ux500_hash_mod_fini - The kernel module exit function.
2014  */
2015 static void __exit ux500_hash_mod_fini(void)
2016 {
2017         platform_driver_unregister(&hash_driver);
2018 }
2019
2020 module_init(ux500_hash_mod_init);
2021 module_exit(ux500_hash_mod_fini);
2022
2023 MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 HASH engine.");
2024 MODULE_LICENSE("GPL");
2025
2026 MODULE_ALIAS("sha1-all");
2027 MODULE_ALIAS("sha256-all");
2028 MODULE_ALIAS("hmac-sha1-all");
2029 MODULE_ALIAS("hmac-sha256-all");