drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/io.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/rtnetlink.h>
  40 #include <linux/slab.h>
  41
  42 #include <crypto/algapi.h>
  43 #include <crypto/aes.h>
  44 #include <crypto/des.h>
  45 #include <crypto/sha.h>
  46 #include <crypto/md5.h>
  47 #include <crypto/aead.h>
  48 #include <crypto/authenc.h>
  49 #include <crypto/skcipher.h>
  50 #include <crypto/hash.h>
  51 #include <crypto/internal/hash.h>
  52 #include <crypto/scatterwalk.h>
  53
  54 #include "talitos.h"
  55
  56 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
  57 {
  58         talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
  59         talitos_ptr->eptr = upper_32_bits(dma_addr);
  60 }
  61
  62 /*
  63  * map virtual single (contiguous) pointer to h/w descriptor pointer
  64  */
  65 static void map_single_talitos_ptr(struct device *dev,
  66                                    struct talitos_ptr *talitos_ptr,
  67                                    unsigned short len, void *data,
  68                                    unsigned char extent,
  69                                    enum dma_data_direction dir)
  70 {
  71         dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
  72
  73         talitos_ptr->len = cpu_to_be16(len);
  74         to_talitos_ptr(talitos_ptr, dma_addr);
  75         talitos_ptr->j_extent = extent;
  76 }
  77
  78 /*
  79  * unmap bus single (contiguous) h/w descriptor pointer
  80  */
  81 static void unmap_single_talitos_ptr(struct device *dev,
  82                                      struct talitos_ptr *talitos_ptr,
  83                                      enum dma_data_direction dir)
  84 {
  85         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
  86                          be16_to_cpu(talitos_ptr->len), dir);
  87 }
  88
  89 static int reset_channel(struct device *dev, int ch)
  90 {
  91         struct talitos_private *priv = dev_get_drvdata(dev);
  92         unsigned int timeout = TALITOS_TIMEOUT;
  93
  94         setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
  95
  96         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
  97                && --timeout)
  98                 cpu_relax();
  99
 100         if (timeout == 0) {
 101                 dev_err(dev, "failed to reset channel %d\n", ch);
 102                 return -EIO;
 103         }
 104
 105         /* set 36-bit addressing, done writeback enable and done IRQ enable */
 106         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
 107                   TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
 108
 109         /* and ICCR writeback, if available */
 110         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 111                 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
 112                           TALITOS_CCCR_LO_IWSE);
 113
 114         return 0;
 115 }
 116
 117 static int reset_device(struct device *dev)
 118 {
 119         struct talitos_private *priv = dev_get_drvdata(dev);
 120         unsigned int timeout = TALITOS_TIMEOUT;
 121         u32 mcr = TALITOS_MCR_SWR;
 122
 123         setbits32(priv->reg + TALITOS_MCR, mcr);
 124
 125         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 126                && --timeout)
 127                 cpu_relax();
 128
 129         if (priv->irq[1]) {
 130                 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
 131                 setbits32(priv->reg + TALITOS_MCR, mcr);
 132         }
 133
 134         if (timeout == 0) {
 135                 dev_err(dev, "failed to reset device\n");
 136                 return -EIO;
 137         }
 138
 139         return 0;
 140 }
 141
 142 /*
 143  * Reset and initialize the device
 144  */
 145 static int init_device(struct device *dev)
 146 {
 147         struct talitos_private *priv = dev_get_drvdata(dev);
 148         int ch, err;
 149
 150         /*
 151          * Master reset
 152          * errata documentation: warning: certain SEC interrupts
 153          * are not fully cleared by writing the MCR:SWR bit,
 154          * set bit twice to completely reset
 155          */
 156         err = reset_device(dev);
 157         if (err)
 158                 return err;
 159
 160         err = reset_device(dev);
 161         if (err)
 162                 return err;
 163
 164         /* reset channels */
 165         for (ch = 0; ch < priv->num_channels; ch++) {
 166                 err = reset_channel(dev, ch);
 167                 if (err)
 168                         return err;
 169         }
 170
 171         /* enable channel done and error interrupts */
 172         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 173         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 174
 175         /* disable integrity check error interrupts (use writeback instead) */
 176         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 177                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
 178                           TALITOS_MDEUICR_LO_ICE);
 179
 180         return 0;
 181 }
 182
 183 /**
 184  * talitos_submit - submits a descriptor to the device for processing
 185  * @dev:        the SEC device to be used
 186  * @ch:         the SEC device channel to be used
 187  * @desc:       the descriptor to be processed by the device
 188  * @callback:   whom to call when processing is complete
 189  * @context:    a handle for use by caller (optional)
 190  *
 191  * desc must contain valid dma-mapped (bus physical) address pointers.
 192  * callback must check err and feedback in descriptor header
 193  * for device processing status.
 194  */
 195 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
 196                    void (*callback)(struct device *dev,
 197                                     struct talitos_desc *desc,
 198                                     void *context, int error),
 199                    void *context)
 200 {
 201         struct talitos_private *priv = dev_get_drvdata(dev);
 202         struct talitos_request *request;
 203         unsigned long flags;
 204         int head;
 205
 206         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
 207
 208         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
 209                 /* h/w fifo is full */
 210                 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 211                 return -EAGAIN;
 212         }
 213
 214         head = priv->chan[ch].head;
 215         request = &priv->chan[ch].fifo[head];
 216
 217         /* map descriptor and save caller data */
 218         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 219                                            DMA_BIDIRECTIONAL);
 220         request->callback = callback;
 221         request->context = context;
 222
 223         /* increment fifo head */
 224         priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
 225
 226         smp_wmb();
 227         request->desc = desc;
 228
 229         /* GO! */
 230         wmb();
 231         out_be32(priv->chan[ch].reg + TALITOS_FF,
 232                  upper_32_bits(request->dma_desc));
 233         out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
 234                  lower_32_bits(request->dma_desc));
 235
 236         spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 237
 238         return -EINPROGRESS;
 239 }
 240 EXPORT_SYMBOL(talitos_submit);
 241
 242 /*
 243  * process what was done, notify callback of error if not
 244  */
 245 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 246 {
 247         struct talitos_private *priv = dev_get_drvdata(dev);
 248         struct talitos_request *request, saved_req;
 249         unsigned long flags;
 250         int tail, status;
 251
 252         spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 253
 254         tail = priv->chan[ch].tail;
 255         while (priv->chan[ch].fifo[tail].desc) {
 256                 request = &priv->chan[ch].fifo[tail];
 257
 258                 /* descriptors with their done bits set don't get the error */
 259                 rmb();
 260                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
 261                         status = 0;
 262                 else
 263                         if (!error)
 264                                 break;
 265                         else
 266                                 status = error;
 267
 268                 dma_unmap_single(dev, request->dma_desc,
 269                                  sizeof(struct talitos_desc),
 270                                  DMA_BIDIRECTIONAL);
 271
 272                 /* copy entries so we can call callback outside lock */
 273                 saved_req.desc = request->desc;
 274                 saved_req.callback = request->callback;
 275                 saved_req.context = request->context;
 276
 277                 /* release request entry in fifo */
 278                 smp_wmb();
 279                 request->desc = NULL;
 280
 281                 /* increment fifo tail */
 282                 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
 283
 284                 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 285
 286                 atomic_dec(&priv->chan[ch].submit_count);
 287
 288                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 289                                    status);
 290                 /* channel may resume processing in single desc error case */
 291                 if (error && !reset_ch && status == error)
 292                         return;
 293                 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 294                 tail = priv->chan[ch].tail;
 295         }
 296
 297         spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 298 }
 299
 300 /*
 301  * process completed requests for channels that have done status
 302  */
 303 #define DEF_TALITOS_DONE(name, ch_done_mask)                            \
 304 static void talitos_done_##name(unsigned long data)                     \
 305 {                                                                       \
 306         struct device *dev = (struct device *)data;                     \
 307         struct talitos_private *priv = dev_get_drvdata(dev);            \
 308         unsigned long flags;                                            \
 309                                                                         \
 310         if (ch_done_mask & 1)                                           \
 311                 flush_channel(dev, 0, 0, 0);                            \
 312         if (priv->num_channels == 1)                                    \
 313                 goto out;                                               \
 314         if (ch_done_mask & (1 << 2))                                    \
 315                 flush_channel(dev, 1, 0, 0);                            \
 316         if (ch_done_mask & (1 << 4))                                    \
 317                 flush_channel(dev, 2, 0, 0);                            \
 318         if (ch_done_mask & (1 << 6))                                    \
 319                 flush_channel(dev, 3, 0, 0);                            \
 320                                                                         \
 321 out:                                                                    \
 322         /* At this point, all completed channels have been processed */ \
 323         /* Unmask done interrupts for channels completed later on. */   \
 324         spin_lock_irqsave(&priv->reg_lock, flags);                      \
 325         setbits32(priv->reg + TALITOS_IMR, ch_done_mask);               \
 326         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);     \
 327         spin_unlock_irqrestore(&priv->reg_lock, flags);                 \
 328 }
 329 DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
 330 DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
 331 DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
 332
 333 /*
 334  * locate current (offending) descriptor
 335  */
 336 static u32 current_desc_hdr(struct device *dev, int ch)
 337 {
 338         struct talitos_private *priv = dev_get_drvdata(dev);
 339         int tail = priv->chan[ch].tail;
 340         dma_addr_t cur_desc;
 341
 342         cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
 343
 344         while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
 345                 tail = (tail + 1) & (priv->fifo_len - 1);
 346                 if (tail == priv->chan[ch].tail) {
 347                         dev_err(dev, "couldn't locate current descriptor\n");
 348                         return 0;
 349                 }
 350         }
 351
 352         return priv->chan[ch].fifo[tail].desc->hdr;
 353 }
 354
 355 /*
 356  * user diagnostics; report root cause of error based on execution unit status
 357  */
 358 static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
 359 {
 360         struct talitos_private *priv = dev_get_drvdata(dev);
 361         int i;
 362
 363         if (!desc_hdr)
 364                 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
 365
 366         switch (desc_hdr & DESC_HDR_SEL0_MASK) {
 367         case DESC_HDR_SEL0_AFEU:
 368                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 369                         in_be32(priv->reg + TALITOS_AFEUISR),
 370                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 371                 break;
 372         case DESC_HDR_SEL0_DEU:
 373                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 374                         in_be32(priv->reg + TALITOS_DEUISR),
 375                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 376                 break;
 377         case DESC_HDR_SEL0_MDEUA:
 378         case DESC_HDR_SEL0_MDEUB:
 379                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 380                         in_be32(priv->reg + TALITOS_MDEUISR),
 381                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 382                 break;
 383         case DESC_HDR_SEL0_RNG:
 384                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 385                         in_be32(priv->reg + TALITOS_RNGUISR),
 386                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 387                 break;
 388         case DESC_HDR_SEL0_PKEU:
 389                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 390                         in_be32(priv->reg + TALITOS_PKEUISR),
 391                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 392                 break;
 393         case DESC_HDR_SEL0_AESU:
 394                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 395                         in_be32(priv->reg + TALITOS_AESUISR),
 396                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 397                 break;
 398         case DESC_HDR_SEL0_CRCU:
 399                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 400                         in_be32(priv->reg + TALITOS_CRCUISR),
 401                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 402                 break;
 403         case DESC_HDR_SEL0_KEU:
 404                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 405                         in_be32(priv->reg + TALITOS_KEUISR),
 406                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 407                 break;
 408         }
 409
 410         switch (desc_hdr & DESC_HDR_SEL1_MASK) {
 411         case DESC_HDR_SEL1_MDEUA:
 412         case DESC_HDR_SEL1_MDEUB:
 413                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 414                         in_be32(priv->reg + TALITOS_MDEUISR),
 415                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 416                 break;
 417         case DESC_HDR_SEL1_CRCU:
 418                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 419                         in_be32(priv->reg + TALITOS_CRCUISR),
 420                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 421                 break;
 422         }
 423
 424         for (i = 0; i < 8; i++)
 425                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 426                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
 427                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
 428 }
 429
 430 /*
 431  * recover from error interrupts
 432  */
 433 static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
 434 {
 435         struct talitos_private *priv = dev_get_drvdata(dev);
 436         unsigned int timeout = TALITOS_TIMEOUT;
 437         int ch, error, reset_dev = 0, reset_ch = 0;
 438         u32 v, v_lo;
 439
 440         for (ch = 0; ch < priv->num_channels; ch++) {
 441                 /* skip channels without errors */
 442                 if (!(isr & (1 << (ch * 2 + 1))))
 443                         continue;
 444
 445                 error = -EINVAL;
 446
 447                 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
 448                 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
 449
 450                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 451                         dev_err(dev, "double fetch fifo overflow error\n");
 452                         error = -EAGAIN;
 453                         reset_ch = 1;
 454                 }
 455                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 456                         /* h/w dropped descriptor */
 457                         dev_err(dev, "single fetch fifo overflow error\n");
 458                         error = -EAGAIN;
 459                 }
 460                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 461                         dev_err(dev, "master data transfer error\n");
 462                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 463                         dev_err(dev, "s/g data length zero error\n");
 464                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 465                         dev_err(dev, "fetch pointer zero error\n");
 466                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 467                         dev_err(dev, "illegal descriptor header error\n");
 468                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 469                         dev_err(dev, "invalid execution unit error\n");
 470                 if (v_lo & TALITOS_CCPSR_LO_EU)
 471                         report_eu_error(dev, ch, current_desc_hdr(dev, ch));
 472                 if (v_lo & TALITOS_CCPSR_LO_GB)
 473                         dev_err(dev, "gather boundary error\n");
 474                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 475                         dev_err(dev, "gather return/length error\n");
 476                 if (v_lo & TALITOS_CCPSR_LO_SB)
 477                         dev_err(dev, "scatter boundary error\n");
 478                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 479                         dev_err(dev, "scatter return/length error\n");
 480
 481                 flush_channel(dev, ch, error, reset_ch);
 482
 483                 if (reset_ch) {
 484                         reset_channel(dev, ch);
 485                 } else {
 486                         setbits32(priv->chan[ch].reg + TALITOS_CCCR,
 487                                   TALITOS_CCCR_CONT);
 488                         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
 489                         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
 490                                TALITOS_CCCR_CONT) && --timeout)
 491                                 cpu_relax();
 492                         if (timeout == 0) {
 493                                 dev_err(dev, "failed to restart channel %d\n",
 494                                         ch);
 495                                 reset_dev = 1;
 496                         }
 497                 }
 498         }
 499         if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
 500                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 501                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 502
 503                 /* purge request queues */
 504                 for (ch = 0; ch < priv->num_channels; ch++)
 505                         flush_channel(dev, ch, -EIO, 1);
 506
 507                 /* reset and reinitialize the device */
 508                 init_device(dev);
 509         }
 510 }
 511
 512 #define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)           \
 513 static irqreturn_t talitos_interrupt_##name(int irq, void *data)               \
 514 {                                                                              \
 515         struct device *dev = data;                                             \
 516         struct talitos_private *priv = dev_get_drvdata(dev);                   \
 517         u32 isr, isr_lo;                                                       \
 518         unsigned long flags;                                                   \
 519                                                                                \
 520         spin_lock_irqsave(&priv->reg_lock, flags);                             \
 521         isr = in_be32(priv->reg + TALITOS_ISR);                                \
 522         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);                          \
 523         /* Acknowledge interrupt */                                            \
 524         out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
 525         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);                          \
 526                                                                                \
 527         if (unlikely(isr & ch_err_mask || isr_lo)) {                           \
 528                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 529                 talitos_error(dev, isr & ch_err_mask, isr_lo);                 \
 530         }                                                                      \
 531         else {                                                                 \
 532                 if (likely(isr & ch_done_mask)) {                              \
 533                         /* mask further done interrupts. */                    \
 534                         clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
 535                         /* done_task will unmask done interrupts at exit */    \
 536                         tasklet_schedule(&priv->done_task[tlet]);              \
 537                 }                                                              \
 538                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 539         }                                                                      \
 540                                                                                \
 541         return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED :  \
 542                                                                 IRQ_NONE;      \
 543 }
 544 DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
 545 DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
 546 DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
 547
 548 /*
 549  * hwrng
 550  */
 551 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 552 {
 553         struct device *dev = (struct device *)rng->priv;
 554         struct talitos_private *priv = dev_get_drvdata(dev);
 555         u32 ofl;
 556         int i;
 557
 558         for (i = 0; i < 20; i++) {
 559                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 560                       TALITOS_RNGUSR_LO_OFL;
 561                 if (ofl || !wait)
 562                         break;
 563                 udelay(10);
 564         }
 565
 566         return !!ofl;
 567 }
 568
 569 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 570 {
 571         struct device *dev = (struct device *)rng->priv;
 572         struct talitos_private *priv = dev_get_drvdata(dev);
 573
 574         /* rng fifo requires 64-bit accesses */
 575         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 576         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 577
 578         return sizeof(u32);
 579 }
 580
 581 static int talitos_rng_init(struct hwrng *rng)
 582 {
 583         struct device *dev = (struct device *)rng->priv;
 584         struct talitos_private *priv = dev_get_drvdata(dev);
 585         unsigned int timeout = TALITOS_TIMEOUT;
 586
 587         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 588         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 589                && --timeout)
 590                 cpu_relax();
 591         if (timeout == 0) {
 592                 dev_err(dev, "failed to reset rng hw\n");
 593                 return -ENODEV;
 594         }
 595
 596         /* start generating */
 597         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 598
 599         return 0;
 600 }
 601
 602 static int talitos_register_rng(struct device *dev)
 603 {
 604         struct talitos_private *priv = dev_get_drvdata(dev);
 605
 606         priv->rng.name          = dev_driver_string(dev),
 607         priv->rng.init          = talitos_rng_init,
 608         priv->rng.data_present  = talitos_rng_data_present,
 609         priv->rng.data_read     = talitos_rng_data_read,
 610         priv->rng.priv          = (unsigned long)dev;
 611
 612         return hwrng_register(&priv->rng);
 613 }
 614
 615 static void talitos_unregister_rng(struct device *dev)
 616 {
 617         struct talitos_private *priv = dev_get_drvdata(dev);
 618
 619         hwrng_unregister(&priv->rng);
 620 }
 621
 622 /*
 623  * crypto alg
 624  */
 625 #define TALITOS_CRA_PRIORITY            3000
 626 #define TALITOS_MAX_KEY_SIZE            96
 627 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 628
 629 #define MD5_BLOCK_SIZE    64
 630
 631 struct talitos_ctx {
 632         struct device *dev;
 633         int ch;
 634         __be32 desc_hdr_template;
 635         u8 key[TALITOS_MAX_KEY_SIZE];
 636         u8 iv[TALITOS_MAX_IV_LENGTH];
 637         unsigned int keylen;
 638         unsigned int enckeylen;
 639         unsigned int authkeylen;
 640         unsigned int authsize;
 641 };
 642
 643 #define HASH_MAX_BLOCK_SIZE             SHA512_BLOCK_SIZE
 644 #define TALITOS_MDEU_MAX_CONTEXT_SIZE   TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
 645
 646 struct talitos_ahash_req_ctx {
 647         u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
 648         unsigned int hw_context_size;
 649         u8 buf[HASH_MAX_BLOCK_SIZE];
 650         u8 bufnext[HASH_MAX_BLOCK_SIZE];
 651         unsigned int swinit;
 652         unsigned int first;
 653         unsigned int last;
 654         unsigned int to_hash_later;
 655         u64 nbuf;
 656         struct scatterlist bufsl[2];
 657         struct scatterlist *psrc;
 658 };
 659
 660 static int aead_setauthsize(struct crypto_aead *authenc,
 661                             unsigned int authsize)
 662 {
 663         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 664
 665         ctx->authsize = authsize;
 666
 667         return 0;
 668 }
 669
 670 static int aead_setkey(struct crypto_aead *authenc,
 671                        const u8 *key, unsigned int keylen)
 672 {
 673         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 674         struct rtattr *rta = (void *)key;
 675         struct crypto_authenc_key_param *param;
 676         unsigned int authkeylen;
 677         unsigned int enckeylen;
 678
 679         if (!RTA_OK(rta, keylen))
 680                 goto badkey;
 681
 682         if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
 683                 goto badkey;
 684
 685         if (RTA_PAYLOAD(rta) < sizeof(*param))
 686                 goto badkey;
 687
 688         param = RTA_DATA(rta);
 689         enckeylen = be32_to_cpu(param->enckeylen);
 690
 691         key += RTA_ALIGN(rta->rta_len);
 692         keylen -= RTA_ALIGN(rta->rta_len);
 693
 694         if (keylen < enckeylen)
 695                 goto badkey;
 696
 697         authkeylen = keylen - enckeylen;
 698
 699         if (keylen > TALITOS_MAX_KEY_SIZE)
 700                 goto badkey;
 701
 702         memcpy(&ctx->key, key, keylen);
 703
 704         ctx->keylen = keylen;
 705         ctx->enckeylen = enckeylen;
 706         ctx->authkeylen = authkeylen;
 707
 708         return 0;
 709
 710 badkey:
 711         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 712         return -EINVAL;
 713 }
 714
 715 /*
 716  * talitos_edesc - s/w-extended descriptor
 717  * @assoc_nents: number of segments in associated data scatterlist
 718  * @src_nents: number of segments in input scatterlist
 719  * @dst_nents: number of segments in output scatterlist
 720  * @assoc_chained: whether assoc is chained or not
 721  * @src_chained: whether src is chained or not
 722  * @dst_chained: whether dst is chained or not
 723  * @iv_dma: dma address of iv for checking continuity and link table
 724  * @dma_len: length of dma mapped link_tbl space
 725  * @dma_link_tbl: bus physical address of link_tbl
 726  * @desc: h/w descriptor
 727  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 728  *
 729  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 730  * is greater than 1, an integrity check value is concatenated to the end
 731  * of link_tbl data
 732  */
 733 struct talitos_edesc {
 734         int assoc_nents;
 735         int src_nents;
 736         int dst_nents;
 737         bool assoc_chained;
 738         bool src_chained;
 739         bool dst_chained;
 740         dma_addr_t iv_dma;
 741         int dma_len;
 742         dma_addr_t dma_link_tbl;
 743         struct talitos_desc desc;
 744         struct talitos_ptr link_tbl[0];
 745 };
 746
 747 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
 748                           unsigned int nents, enum dma_data_direction dir,
 749                           bool chained)
 750 {
 751         if (unlikely(chained))
 752                 while (sg) {
 753                         dma_map_sg(dev, sg, 1, dir);
 754                         sg = scatterwalk_sg_next(sg);
 755                 }
 756         else
 757                 dma_map_sg(dev, sg, nents, dir);
 758         return nents;
 759 }
 760
 761 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
 762                                    enum dma_data_direction dir)
 763 {
 764         while (sg) {
 765                 dma_unmap_sg(dev, sg, 1, dir);
 766                 sg = scatterwalk_sg_next(sg);
 767         }
 768 }
 769
 770 static void talitos_sg_unmap(struct device *dev,
 771                              struct talitos_edesc *edesc,
 772                              struct scatterlist *src,
 773                              struct scatterlist *dst)
 774 {
 775         unsigned int src_nents = edesc->src_nents ? : 1;
 776         unsigned int dst_nents = edesc->dst_nents ? : 1;
 777
 778         if (src != dst) {
 779                 if (edesc->src_chained)
 780                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
 781                 else
 782                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
 783
 784                 if (dst) {
 785                         if (edesc->dst_chained)
 786                                 talitos_unmap_sg_chain(dev, dst,
 787                                                        DMA_FROM_DEVICE);
 788                         else
 789                                 dma_unmap_sg(dev, dst, dst_nents,
 790                                              DMA_FROM_DEVICE);
 791                 }
 792         } else
 793                 if (edesc->src_chained)
 794                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
 795                 else
 796                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
 797 }
 798
 799 static void ipsec_esp_unmap(struct device *dev,
 800                             struct talitos_edesc *edesc,
 801                             struct aead_request *areq)
 802 {
 803         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 804         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 805         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 806         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 807
 808         if (edesc->assoc_chained)
 809                 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
 810         else
 811                 /* assoc_nents counts also for IV in non-contiguous cases */
 812                 dma_unmap_sg(dev, areq->assoc,
 813                              edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
 814                              DMA_TO_DEVICE);
 815
 816         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
 817
 818         if (edesc->dma_len)
 819                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 820                                  DMA_BIDIRECTIONAL);
 821 }
 822
 823 /*
 824  * ipsec_esp descriptor callbacks
 825  */
 826 static void ipsec_esp_encrypt_done(struct device *dev,
 827                                    struct talitos_desc *desc, void *context,
 828                                    int err)
 829 {
 830         struct aead_request *areq = context;
 831         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 832         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 833         struct talitos_edesc *edesc;
 834         struct scatterlist *sg;
 835         void *icvdata;
 836
 837         edesc = container_of(desc, struct talitos_edesc, desc);
 838
 839         ipsec_esp_unmap(dev, edesc, areq);
 840
 841         /* copy the generated ICV to dst */
 842         if (edesc->dst_nents) {
 843                 icvdata = &edesc->link_tbl[edesc->src_nents +
 844                                            edesc->dst_nents + 2 +
 845                                            edesc->assoc_nents];
 846                 sg = sg_last(areq->dst, edesc->dst_nents);
 847                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 848                        icvdata, ctx->authsize);
 849         }
 850
 851         kfree(edesc);
 852
 853         aead_request_complete(areq, err);
 854 }
 855
 856 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
 857                                           struct talitos_desc *desc,
 858                                           void *context, int err)
 859 {
 860         struct aead_request *req = context;
 861         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 862         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 863         struct talitos_edesc *edesc;
 864         struct scatterlist *sg;
 865         void *icvdata;
 866
 867         edesc = container_of(desc, struct talitos_edesc, desc);
 868
 869         ipsec_esp_unmap(dev, edesc, req);
 870
 871         if (!err) {
 872                 /* auth check */
 873                 if (edesc->dma_len)
 874                         icvdata = &edesc->link_tbl[edesc->src_nents +
 875                                                    edesc->dst_nents + 2 +
 876                                                    edesc->assoc_nents];
 877                 else
 878                         icvdata = &edesc->link_tbl[0];
 879
 880                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 881                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 882                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 883         }
 884
 885         kfree(edesc);
 886
 887         aead_request_complete(req, err);
 888 }
 889
 890 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
 891                                           struct talitos_desc *desc,
 892                                           void *context, int err)
 893 {
 894         struct aead_request *req = context;
 895         struct talitos_edesc *edesc;
 896
 897         edesc = container_of(desc, struct talitos_edesc, desc);
 898
 899         ipsec_esp_unmap(dev, edesc, req);
 900
 901         /* check ICV auth status */
 902         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
 903                      DESC_HDR_LO_ICCR1_PASS))
 904                 err = -EBADMSG;
 905
 906         kfree(edesc);
 907
 908         aead_request_complete(req, err);
 909 }
 910
 911 /*
 912  * convert scatterlist to SEC h/w link table format
 913  * stop at cryptlen bytes
 914  */
 915 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 916                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 917 {
 918         int n_sg = sg_count;
 919
 920         while (n_sg--) {
 921                 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
 922                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 923                 link_tbl_ptr->j_extent = 0;
 924                 link_tbl_ptr++;
 925                 cryptlen -= sg_dma_len(sg);
 926                 sg = scatterwalk_sg_next(sg);
 927         }
 928
 929         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 930         link_tbl_ptr--;
 931         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 932                 /* Empty this entry, and move to previous one */
 933                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 934                 link_tbl_ptr->len = 0;
 935                 sg_count--;
 936                 link_tbl_ptr--;
 937         }
 938         link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
 939                                         + cryptlen);
 940
 941         /* tag end of link table */
 942         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 943
 944         return sg_count;
 945 }
 946
 947 /*
 948  * fill in and submit ipsec_esp descriptor
 949  */
 950 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
 951                      u64 seq, void (*callback) (struct device *dev,
 952                                                 struct talitos_desc *desc,
 953                                                 void *context, int error))
 954 {
 955         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
 956         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
 957         struct device *dev = ctx->dev;
 958         struct talitos_desc *desc = &edesc->desc;
 959         unsigned int cryptlen = areq->cryptlen;
 960         unsigned int authsize = ctx->authsize;
 961         unsigned int ivsize = crypto_aead_ivsize(aead);
 962         int sg_count, ret;
 963         int sg_link_tbl_len;
 964
 965         /* hmac key */
 966         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
 967                                0, DMA_TO_DEVICE);
 968
 969         /* hmac data */
 970         desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
 971         if (edesc->assoc_nents) {
 972                 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
 973                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
 974
 975                 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
 976                                sizeof(struct talitos_ptr));
 977                 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
 978
 979                 /* assoc_nents - 1 entries for assoc, 1 for IV */
 980                 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
 981                                           areq->assoclen, tbl_ptr);
 982
 983                 /* add IV to link table */
 984                 tbl_ptr += sg_count - 1;
 985                 tbl_ptr->j_extent = 0;
 986                 tbl_ptr++;
 987                 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
 988                 tbl_ptr->len = cpu_to_be16(ivsize);
 989                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 990
 991                 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
 992                                            edesc->dma_len, DMA_BIDIRECTIONAL);
 993         } else {
 994                 to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->assoc));
 995                 desc->ptr[1].j_extent = 0;
 996         }
 997
 998         /* cipher iv */
 999         to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
1000         desc->ptr[2].len = cpu_to_be16(ivsize);
1001         desc->ptr[2].j_extent = 0;
1002         /* Sync needed for the aead_givencrypt case */
1003         dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
1004
1005         /* cipher key */
1006         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1007                                (char *)&ctx->key + ctx->authkeylen, 0,
1008                                DMA_TO_DEVICE);
1009
1010         /*
1011          * cipher in
1012          * map and adjust cipher len to aead request cryptlen.
1013          * extent is bytes of HMAC postpended to ciphertext,
1014          * typically 12 for ipsec
1015          */
1016         desc->ptr[4].len = cpu_to_be16(cryptlen);
1017         desc->ptr[4].j_extent = authsize;
1018
1019         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1020                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1021                                                            : DMA_TO_DEVICE,
1022                                   edesc->src_chained);
1023
1024         if (sg_count == 1) {
1025                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1026         } else {
1027                 sg_link_tbl_len = cryptlen;
1028
1029                 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1030                         sg_link_tbl_len = cryptlen + authsize;
1031
1032                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1033                                           &edesc->link_tbl[0]);
1034                 if (sg_count > 1) {
1035                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1036                         to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1037                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1038                                                    edesc->dma_len,
1039                                                    DMA_BIDIRECTIONAL);
1040                 } else {
1041                         /* Only one segment now, so no link tbl needed */
1042                         to_talitos_ptr(&desc->ptr[4],
1043                                        sg_dma_address(areq->src));
1044                 }
1045         }
1046
1047         /* cipher out */
1048         desc->ptr[5].len = cpu_to_be16(cryptlen);
1049         desc->ptr[5].j_extent = authsize;
1050
1051         if (areq->src != areq->dst)
1052                 sg_count = talitos_map_sg(dev, areq->dst,
1053                                           edesc->dst_nents ? : 1,
1054                                           DMA_FROM_DEVICE, edesc->dst_chained);
1055
1056         if (sg_count == 1) {
1057                 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1058         } else {
1059                 int tbl_off = edesc->src_nents + 1;
1060                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1061
1062                 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1063                                tbl_off * sizeof(struct talitos_ptr));
1064                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1065                                           tbl_ptr);
1066
1067                 /* Add an entry to the link table for ICV data */
1068                 tbl_ptr += sg_count - 1;
1069                 tbl_ptr->j_extent = 0;
1070                 tbl_ptr++;
1071                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1072                 tbl_ptr->len = cpu_to_be16(authsize);
1073
1074                 /* icv data follows link tables */
1075                 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1076                                (tbl_off + edesc->dst_nents + 1 +
1077                                 edesc->assoc_nents) *
1078                                sizeof(struct talitos_ptr));
1079                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1080                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1081                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1082         }
1083
1084         /* iv out */
1085         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1086                                DMA_FROM_DEVICE);
1087
1088         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1089         if (ret != -EINPROGRESS) {
1090                 ipsec_esp_unmap(dev, edesc, areq);
1091                 kfree(edesc);
1092         }
1093         return ret;
1094 }
1095
1096 /*
1097  * derive number of elements in scatterlist
1098  */
1099 static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
1100 {
1101         struct scatterlist *sg = sg_list;
1102         int sg_nents = 0;
1103
1104         *chained = false;
1105         while (nbytes > 0) {
1106                 sg_nents++;
1107                 nbytes -= sg->length;
1108                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1109                         *chained = true;
1110                 sg = scatterwalk_sg_next(sg);
1111         }
1112
1113         return sg_nents;
1114 }
1115
1116 /**
1117  * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1118  * @sgl:                 The SG list
1119  * @nents:               Number of SG entries
1120  * @buf:                 Where to copy to
1121  * @buflen:              The number of bytes to copy
1122  * @skip:                The number of bytes to skip before copying.
1123  *                       Note: skip + buflen should equal SG total size.
1124  *
1125  * Returns the number of copied bytes.
1126  *
1127  **/
1128 static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1129                                     void *buf, size_t buflen, unsigned int skip)
1130 {
1131         unsigned int offset = 0;
1132         unsigned int boffset = 0;
1133         struct sg_mapping_iter miter;
1134         unsigned long flags;
1135         unsigned int sg_flags = SG_MITER_ATOMIC;
1136         size_t total_buffer = buflen + skip;
1137
1138         sg_flags |= SG_MITER_FROM_SG;
1139
1140         sg_miter_start(&miter, sgl, nents, sg_flags);
1141
1142         local_irq_save(flags);
1143
1144         while (sg_miter_next(&miter) && offset < total_buffer) {
1145                 unsigned int len;
1146                 unsigned int ignore;
1147
1148                 if ((offset + miter.length) > skip) {
1149                         if (offset < skip) {
1150                                 /* Copy part of this segment */
1151                                 ignore = skip - offset;
1152                                 len = miter.length - ignore;
1153                                 if (boffset + len > buflen)
1154                                         len = buflen - boffset;
1155                                 memcpy(buf + boffset, miter.addr + ignore, len);
1156                         } else {
1157                                 /* Copy all of this segment (up to buflen) */
1158                                 len = miter.length;
1159                                 if (boffset + len > buflen)
1160                                         len = buflen - boffset;
1161                                 memcpy(buf + boffset, miter.addr, len);
1162                         }
1163                         boffset += len;
1164                 }
1165                 offset += miter.length;
1166         }
1167
1168         sg_miter_stop(&miter);
1169
1170         local_irq_restore(flags);
1171         return boffset;
1172 }
1173
1174 /*
1175  * allocate and map the extended descriptor
1176  */
1177 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1178                                                  struct scatterlist *assoc,
1179                                                  struct scatterlist *src,
1180                                                  struct scatterlist *dst,
1181                                                  u8 *iv,
1182                                                  unsigned int assoclen,
1183                                                  unsigned int cryptlen,
1184                                                  unsigned int authsize,
1185                                                  unsigned int ivsize,
1186                                                  int icv_stashing,
1187                                                  u32 cryptoflags)
1188 {
1189         struct talitos_edesc *edesc;
1190         int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1191         bool assoc_chained = false, src_chained = false, dst_chained = false;
1192         dma_addr_t iv_dma = 0;
1193         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1194                       GFP_ATOMIC;
1195
1196         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1197                 dev_err(dev, "length exceeds h/w max limit\n");
1198                 return ERR_PTR(-EINVAL);
1199         }
1200
1201         if (iv)
1202                 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1203
1204         if (assoc) {
1205                 /*
1206                  * Currently it is assumed that iv is provided whenever assoc
1207                  * is.
1208                  */
1209                 BUG_ON(!iv);
1210
1211                 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1212                 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1213                                assoc_chained);
1214                 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1215
1216                 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1217                         assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1218         }
1219
1220         src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1221         src_nents = (src_nents == 1) ? 0 : src_nents;
1222
1223         if (!dst) {
1224                 dst_nents = 0;
1225         } else {
1226                 if (dst == src) {
1227                         dst_nents = src_nents;
1228                 } else {
1229                         dst_nents = sg_count(dst, cryptlen + authsize,
1230                                              &dst_chained);
1231                         dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1232                 }
1233         }
1234
1235         /*
1236          * allocate space for base edesc plus the link tables,
1237          * allowing for two separate entries for ICV and generated ICV (+ 2),
1238          * and the ICV data itself
1239          */
1240         alloc_len = sizeof(struct talitos_edesc);
1241         if (assoc_nents || src_nents || dst_nents) {
1242                 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1243                           sizeof(struct talitos_ptr) + authsize;
1244                 alloc_len += dma_len;
1245         } else {
1246                 dma_len = 0;
1247                 alloc_len += icv_stashing ? authsize : 0;
1248         }
1249
1250         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1251         if (!edesc) {
1252                 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1253                 if (iv_dma)
1254                         dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1255                 dev_err(dev, "could not allocate edescriptor\n");
1256                 return ERR_PTR(-ENOMEM);
1257         }
1258
1259         edesc->assoc_nents = assoc_nents;
1260         edesc->src_nents = src_nents;
1261         edesc->dst_nents = dst_nents;
1262         edesc->assoc_chained = assoc_chained;
1263         edesc->src_chained = src_chained;
1264         edesc->dst_chained = dst_chained;
1265         edesc->iv_dma = iv_dma;
1266         edesc->dma_len = dma_len;
1267         if (dma_len)
1268                 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1269                                                      edesc->dma_len,
1270                                                      DMA_BIDIRECTIONAL);
1271
1272         return edesc;
1273 }
1274
1275 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1276                                               int icv_stashing)
1277 {
1278         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1279         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1280         unsigned int ivsize = crypto_aead_ivsize(authenc);
1281
1282         return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1283                                    iv, areq->assoclen, areq->cryptlen,
1284                                    ctx->authsize, ivsize, icv_stashing,
1285                                    areq->base.flags);
1286 }
1287
1288 static int aead_encrypt(struct aead_request *req)
1289 {
1290         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1291         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1292         struct talitos_edesc *edesc;
1293
1294         /* allocate extended descriptor */
1295         edesc = aead_edesc_alloc(req, req->iv, 0);
1296         if (IS_ERR(edesc))
1297                 return PTR_ERR(edesc);
1298
1299         /* set encrypt */
1300         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1301
1302         return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
1303 }
1304
1305 static int aead_decrypt(struct aead_request *req)
1306 {
1307         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1308         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1309         unsigned int authsize = ctx->authsize;
1310         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1311         struct talitos_edesc *edesc;
1312         struct scatterlist *sg;
1313         void *icvdata;
1314
1315         req->cryptlen -= authsize;
1316
1317         /* allocate extended descriptor */
1318         edesc = aead_edesc_alloc(req, req->iv, 1);
1319         if (IS_ERR(edesc))
1320                 return PTR_ERR(edesc);
1321
1322         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1323             ((!edesc->src_nents && !edesc->dst_nents) ||
1324              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1325
1326                 /* decrypt and check the ICV */
1327                 edesc->desc.hdr = ctx->desc_hdr_template |
1328                                   DESC_HDR_DIR_INBOUND |
1329                                   DESC_HDR_MODE1_MDEU_CICV;
1330
1331                 /* reset integrity check result bits */
1332                 edesc->desc.hdr_lo = 0;
1333
1334                 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
1335         }
1336
1337         /* Have to check the ICV with software */
1338         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1339
1340         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1341         if (edesc->dma_len)
1342                 icvdata = &edesc->link_tbl[edesc->src_nents +
1343                                            edesc->dst_nents + 2 +
1344                                            edesc->assoc_nents];
1345         else
1346                 icvdata = &edesc->link_tbl[0];
1347
1348         sg = sg_last(req->src, edesc->src_nents ? : 1);
1349
1350         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1351                ctx->authsize);
1352
1353         return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
1354 }
1355
1356 static int aead_givencrypt(struct aead_givcrypt_request *req)
1357 {
1358         struct aead_request *areq = &req->areq;
1359         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1360         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1361         struct talitos_edesc *edesc;
1362
1363         /* allocate extended descriptor */
1364         edesc = aead_edesc_alloc(areq, req->giv, 0);
1365         if (IS_ERR(edesc))
1366                 return PTR_ERR(edesc);
1367
1368         /* set encrypt */
1369         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1370
1371         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1372         /* avoid consecutive packets going out with same IV */
1373         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1374
1375         return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
1376 }
1377
1378 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1379                              const u8 *key, unsigned int keylen)
1380 {
1381         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1382
1383         memcpy(&ctx->key, key, keylen);
1384         ctx->keylen = keylen;
1385
1386         return 0;
1387 }
1388
1389 static void common_nonsnoop_unmap(struct device *dev,
1390                                   struct talitos_edesc *edesc,
1391                                   struct ablkcipher_request *areq)
1392 {
1393         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1394         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1395         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1396
1397         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1398
1399         if (edesc->dma_len)
1400                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1401                                  DMA_BIDIRECTIONAL);
1402 }
1403
1404 static void ablkcipher_done(struct device *dev,
1405                             struct talitos_desc *desc, void *context,
1406                             int err)
1407 {
1408         struct ablkcipher_request *areq = context;
1409         struct talitos_edesc *edesc;
1410
1411         edesc = container_of(desc, struct talitos_edesc, desc);
1412
1413         common_nonsnoop_unmap(dev, edesc, areq);
1414
1415         kfree(edesc);
1416
1417         areq->base.complete(&areq->base, err);
1418 }
1419
1420 static int common_nonsnoop(struct talitos_edesc *edesc,
1421                            struct ablkcipher_request *areq,
1422                            void (*callback) (struct device *dev,
1423                                              struct talitos_desc *desc,
1424                                              void *context, int error))
1425 {
1426         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1427         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1428         struct device *dev = ctx->dev;
1429         struct talitos_desc *desc = &edesc->desc;
1430         unsigned int cryptlen = areq->nbytes;
1431         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1432         int sg_count, ret;
1433
1434         /* first DWORD empty */
1435         desc->ptr[0].len = 0;
1436         to_talitos_ptr(&desc->ptr[0], 0);
1437         desc->ptr[0].j_extent = 0;
1438
1439         /* cipher iv */
1440         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1441         desc->ptr[1].len = cpu_to_be16(ivsize);
1442         desc->ptr[1].j_extent = 0;
1443
1444         /* cipher key */
1445         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1446                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1447
1448         /*
1449          * cipher in
1450          */
1451         desc->ptr[3].len = cpu_to_be16(cryptlen);
1452         desc->ptr[3].j_extent = 0;
1453
1454         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1455                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1456                                                            : DMA_TO_DEVICE,
1457                                   edesc->src_chained);
1458
1459         if (sg_count == 1) {
1460                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1461         } else {
1462                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1463                                           &edesc->link_tbl[0]);
1464                 if (sg_count > 1) {
1465                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1466                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1467                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1468                                                    edesc->dma_len,
1469                                                    DMA_BIDIRECTIONAL);
1470                 } else {
1471                         /* Only one segment now, so no link tbl needed */
1472                         to_talitos_ptr(&desc->ptr[3],
1473                                        sg_dma_address(areq->src));
1474                 }
1475         }
1476
1477         /* cipher out */
1478         desc->ptr[4].len = cpu_to_be16(cryptlen);
1479         desc->ptr[4].j_extent = 0;
1480
1481         if (areq->src != areq->dst)
1482                 sg_count = talitos_map_sg(dev, areq->dst,
1483                                           edesc->dst_nents ? : 1,
1484                                           DMA_FROM_DEVICE, edesc->dst_chained);
1485
1486         if (sg_count == 1) {
1487                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1488         } else {
1489                 struct talitos_ptr *link_tbl_ptr =
1490                         &edesc->link_tbl[edesc->src_nents + 1];
1491
1492                 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1493                                               (edesc->src_nents + 1) *
1494                                               sizeof(struct talitos_ptr));
1495                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1496                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1497                                           link_tbl_ptr);
1498                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1499                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1500         }
1501
1502         /* iv out */
1503         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1504                                DMA_FROM_DEVICE);
1505
1506         /* last DWORD empty */
1507         desc->ptr[6].len = 0;
1508         to_talitos_ptr(&desc->ptr[6], 0);
1509         desc->ptr[6].j_extent = 0;
1510
1511         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1512         if (ret != -EINPROGRESS) {
1513                 common_nonsnoop_unmap(dev, edesc, areq);
1514                 kfree(edesc);
1515         }
1516         return ret;
1517 }
1518
1519 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1520                                                     areq)
1521 {
1522         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1523         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1524         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1525
1526         return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1527                                    areq->info, 0, areq->nbytes, 0, ivsize, 0,
1528                                    areq->base.flags);
1529 }
1530
1531 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1532 {
1533         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1534         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1535         struct talitos_edesc *edesc;
1536
1537         /* allocate extended descriptor */
1538         edesc = ablkcipher_edesc_alloc(areq);
1539         if (IS_ERR(edesc))
1540                 return PTR_ERR(edesc);
1541
1542         /* set encrypt */
1543         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1544
1545         return common_nonsnoop(edesc, areq, ablkcipher_done);
1546 }
1547
1548 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1549 {
1550         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1551         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1552         struct talitos_edesc *edesc;
1553
1554         /* allocate extended descriptor */
1555         edesc = ablkcipher_edesc_alloc(areq);
1556         if (IS_ERR(edesc))
1557                 return PTR_ERR(edesc);
1558
1559         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1560
1561         return common_nonsnoop(edesc, areq, ablkcipher_done);
1562 }
1563
1564 static void common_nonsnoop_hash_unmap(struct device *dev,
1565                                        struct talitos_edesc *edesc,
1566                                        struct ahash_request *areq)
1567 {
1568         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1569
1570         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1571
1572         /* When using hashctx-in, must unmap it. */
1573         if (edesc->desc.ptr[1].len)
1574                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1575                                          DMA_TO_DEVICE);
1576
1577         if (edesc->desc.ptr[2].len)
1578                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1579                                          DMA_TO_DEVICE);
1580
1581         talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1582
1583         if (edesc->dma_len)
1584                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1585                                  DMA_BIDIRECTIONAL);
1586
1587 }
1588
1589 static void ahash_done(struct device *dev,
1590                        struct talitos_desc *desc, void *context,
1591                        int err)
1592 {
1593         struct ahash_request *areq = context;
1594         struct talitos_edesc *edesc =
1595                  container_of(desc, struct talitos_edesc, desc);
1596         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1597
1598         if (!req_ctx->last && req_ctx->to_hash_later) {
1599                 /* Position any partial block for next update/final/finup */
1600                 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1601                 req_ctx->nbuf = req_ctx->to_hash_later;
1602         }
1603         common_nonsnoop_hash_unmap(dev, edesc, areq);
1604
1605         kfree(edesc);
1606
1607         areq->base.complete(&areq->base, err);
1608 }
1609
1610 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1611                                 struct ahash_request *areq, unsigned int length,
1612                                 void (*callback) (struct device *dev,
1613                                                   struct talitos_desc *desc,
1614                                                   void *context, int error))
1615 {
1616         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1617         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1618         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1619         struct device *dev = ctx->dev;
1620         struct talitos_desc *desc = &edesc->desc;
1621         int sg_count, ret;
1622
1623         /* first DWORD empty */
1624         desc->ptr[0] = zero_entry;
1625
1626         /* hash context in */
1627         if (!req_ctx->first || req_ctx->swinit) {
1628                 map_single_talitos_ptr(dev, &desc->ptr[1],
1629                                        req_ctx->hw_context_size,
1630                                        (char *)req_ctx->hw_context, 0,
1631                                        DMA_TO_DEVICE);
1632                 req_ctx->swinit = 0;
1633         } else {
1634                 desc->ptr[1] = zero_entry;
1635                 /* Indicate next op is not the first. */
1636                 req_ctx->first = 0;
1637         }
1638
1639         /* HMAC key */
1640         if (ctx->keylen)
1641                 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1642                                        (char *)&ctx->key, 0, DMA_TO_DEVICE);
1643         else
1644                 desc->ptr[2] = zero_entry;
1645
1646         /*
1647          * data in
1648          */
1649         desc->ptr[3].len = cpu_to_be16(length);
1650         desc->ptr[3].j_extent = 0;
1651
1652         sg_count = talitos_map_sg(dev, req_ctx->psrc,
1653                                   edesc->src_nents ? : 1,
1654                                   DMA_TO_DEVICE, edesc->src_chained);
1655
1656         if (sg_count == 1) {
1657                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1658         } else {
1659                 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1660                                           &edesc->link_tbl[0]);
1661                 if (sg_count > 1) {
1662                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1663                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1664                         dma_sync_single_for_device(ctx->dev,
1665                                                    edesc->dma_link_tbl,
1666                                                    edesc->dma_len,
1667                                                    DMA_BIDIRECTIONAL);
1668                 } else {
1669                         /* Only one segment now, so no link tbl needed */
1670                         to_talitos_ptr(&desc->ptr[3],
1671                                        sg_dma_address(req_ctx->psrc));
1672                 }
1673         }
1674
1675         /* fifth DWORD empty */
1676         desc->ptr[4] = zero_entry;
1677
1678         /* hash/HMAC out -or- hash context out */
1679         if (req_ctx->last)
1680                 map_single_talitos_ptr(dev, &desc->ptr[5],
1681                                        crypto_ahash_digestsize(tfm),
1682                                        areq->result, 0, DMA_FROM_DEVICE);
1683         else
1684                 map_single_talitos_ptr(dev, &desc->ptr[5],
1685                                        req_ctx->hw_context_size,
1686                                        req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1687
1688         /* last DWORD empty */
1689         desc->ptr[6] = zero_entry;
1690
1691         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1692         if (ret != -EINPROGRESS) {
1693                 common_nonsnoop_hash_unmap(dev, edesc, areq);
1694                 kfree(edesc);
1695         }
1696         return ret;
1697 }
1698
1699 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1700                                                unsigned int nbytes)
1701 {
1702         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1703         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1704         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1705
1706         return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1707                                    nbytes, 0, 0, 0, areq->base.flags);
1708 }
1709
1710 static int ahash_init(struct ahash_request *areq)
1711 {
1712         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1713         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1714
1715         /* Initialize the context */
1716         req_ctx->nbuf = 0;
1717         req_ctx->first = 1; /* first indicates h/w must init its context */
1718         req_ctx->swinit = 0; /* assume h/w init of context */
1719         req_ctx->hw_context_size =
1720                 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1721                         ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1722                         : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1723
1724         return 0;
1725 }
1726
1727 /*
1728  * on h/w without explicit sha224 support, we initialize h/w context
1729  * manually with sha224 constants, and tell it to run sha256.
1730  */
1731 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1732 {
1733         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1734
1735         ahash_init(areq);
1736         req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1737
1738         req_ctx->hw_context[0] = SHA224_H0;
1739         req_ctx->hw_context[1] = SHA224_H1;
1740         req_ctx->hw_context[2] = SHA224_H2;
1741         req_ctx->hw_context[3] = SHA224_H3;
1742         req_ctx->hw_context[4] = SHA224_H4;
1743         req_ctx->hw_context[5] = SHA224_H5;
1744         req_ctx->hw_context[6] = SHA224_H6;
1745         req_ctx->hw_context[7] = SHA224_H7;
1746
1747         /* init 64-bit count */
1748         req_ctx->hw_context[8] = 0;
1749         req_ctx->hw_context[9] = 0;
1750
1751         return 0;
1752 }
1753
1754 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1755 {
1756         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1757         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1758         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1759         struct talitos_edesc *edesc;
1760         unsigned int blocksize =
1761                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1762         unsigned int nbytes_to_hash;
1763         unsigned int to_hash_later;
1764         unsigned int nsg;
1765         bool chained;
1766
1767         if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1768                 /* Buffer up to one whole block */
1769                 sg_copy_to_buffer(areq->src,
1770                                   sg_count(areq->src, nbytes, &chained),
1771                                   req_ctx->buf + req_ctx->nbuf, nbytes);
1772                 req_ctx->nbuf += nbytes;
1773                 return 0;
1774         }
1775
1776         /* At least (blocksize + 1) bytes are available to hash */
1777         nbytes_to_hash = nbytes + req_ctx->nbuf;
1778         to_hash_later = nbytes_to_hash & (blocksize - 1);
1779
1780         if (req_ctx->last)
1781                 to_hash_later = 0;
1782         else if (to_hash_later)
1783                 /* There is a partial block. Hash the full block(s) now */
1784                 nbytes_to_hash -= to_hash_later;
1785         else {
1786                 /* Keep one block buffered */
1787                 nbytes_to_hash -= blocksize;
1788                 to_hash_later = blocksize;
1789         }
1790
1791         /* Chain in any previously buffered data */
1792         if (req_ctx->nbuf) {
1793                 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1794                 sg_init_table(req_ctx->bufsl, nsg);
1795                 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1796                 if (nsg > 1)
1797                         scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1798                 req_ctx->psrc = req_ctx->bufsl;
1799         } else
1800                 req_ctx->psrc = areq->src;
1801
1802         if (to_hash_later) {
1803                 int nents = sg_count(areq->src, nbytes, &chained);
1804                 sg_copy_end_to_buffer(areq->src, nents,
1805                                       req_ctx->bufnext,
1806                                       to_hash_later,
1807                                       nbytes - to_hash_later);
1808         }
1809         req_ctx->to_hash_later = to_hash_later;
1810
1811         /* Allocate extended descriptor */
1812         edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1813         if (IS_ERR(edesc))
1814                 return PTR_ERR(edesc);
1815
1816         edesc->desc.hdr = ctx->desc_hdr_template;
1817
1818         /* On last one, request SEC to pad; otherwise continue */
1819         if (req_ctx->last)
1820                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1821         else
1822                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1823
1824         /* request SEC to INIT hash. */
1825         if (req_ctx->first && !req_ctx->swinit)
1826                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1827
1828         /* When the tfm context has a keylen, it's an HMAC.
1829          * A first or last (ie. not middle) descriptor must request HMAC.
1830          */
1831         if (ctx->keylen && (req_ctx->first || req_ctx->last))
1832                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1833
1834         return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1835                                     ahash_done);
1836 }
1837
1838 static int ahash_update(struct ahash_request *areq)
1839 {
1840         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1841
1842         req_ctx->last = 0;
1843
1844         return ahash_process_req(areq, areq->nbytes);
1845 }
1846
1847 static int ahash_final(struct ahash_request *areq)
1848 {
1849         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1850
1851         req_ctx->last = 1;
1852
1853         return ahash_process_req(areq, 0);
1854 }
1855
1856 static int ahash_finup(struct ahash_request *areq)
1857 {
1858         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1859
1860         req_ctx->last = 1;
1861
1862         return ahash_process_req(areq, areq->nbytes);
1863 }
1864
1865 static int ahash_digest(struct ahash_request *areq)
1866 {
1867         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1868         struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1869
1870         ahash->init(areq);
1871         req_ctx->last = 1;
1872
1873         return ahash_process_req(areq, areq->nbytes);
1874 }
1875
1876 struct keyhash_result {
1877         struct completion completion;
1878         int err;
1879 };
1880
1881 static void keyhash_complete(struct crypto_async_request *req, int err)
1882 {
1883         struct keyhash_result *res = req->data;
1884
1885         if (err == -EINPROGRESS)
1886                 return;
1887
1888         res->err = err;
1889         complete(&res->completion);
1890 }
1891
1892 static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1893                    u8 *hash)
1894 {
1895         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1896
1897         struct scatterlist sg[1];
1898         struct ahash_request *req;
1899         struct keyhash_result hresult;
1900         int ret;
1901
1902         init_completion(&hresult.completion);
1903
1904         req = ahash_request_alloc(tfm, GFP_KERNEL);
1905         if (!req)
1906                 return -ENOMEM;
1907
1908         /* Keep tfm keylen == 0 during hash of the long key */
1909         ctx->keylen = 0;
1910         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1911                                    keyhash_complete, &hresult);
1912
1913         sg_init_one(&sg[0], key, keylen);
1914
1915         ahash_request_set_crypt(req, sg, hash, keylen);
1916         ret = crypto_ahash_digest(req);
1917         switch (ret) {
1918         case 0:
1919                 break;
1920         case -EINPROGRESS:
1921         case -EBUSY:
1922                 ret = wait_for_completion_interruptible(
1923                         &hresult.completion);
1924                 if (!ret)
1925                         ret = hresult.err;
1926                 break;
1927         default:
1928                 break;
1929         }
1930         ahash_request_free(req);
1931
1932         return ret;
1933 }
1934
1935 static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1936                         unsigned int keylen)
1937 {
1938         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1939         unsigned int blocksize =
1940                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1941         unsigned int digestsize = crypto_ahash_digestsize(tfm);
1942         unsigned int keysize = keylen;
1943         u8 hash[SHA512_DIGEST_SIZE];
1944         int ret;
1945
1946         if (keylen <= blocksize)
1947                 memcpy(ctx->key, key, keysize);
1948         else {
1949                 /* Must get the hash of the long key */
1950                 ret = keyhash(tfm, key, keylen, hash);
1951
1952                 if (ret) {
1953                         crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1954                         return -EINVAL;
1955                 }
1956
1957                 keysize = digestsize;
1958                 memcpy(ctx->key, hash, digestsize);
1959         }
1960
1961         ctx->keylen = keysize;
1962
1963         return 0;
1964 }
1965
1966
1967 struct talitos_alg_template {
1968         u32 type;
1969         union {
1970                 struct crypto_alg crypto;
1971                 struct ahash_alg hash;
1972         } alg;
1973         __be32 desc_hdr_template;
1974 };
1975
1976 static struct talitos_alg_template driver_algs[] = {
1977         /* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
1978         {       .type = CRYPTO_ALG_TYPE_AEAD,
1979                 .alg.crypto = {
1980                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1981                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1982                         .cra_blocksize = AES_BLOCK_SIZE,
1983                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1984                         .cra_aead = {
1985                                 .ivsize = AES_BLOCK_SIZE,
1986                                 .maxauthsize = SHA1_DIGEST_SIZE,
1987                         }
1988                 },
1989                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1990                                      DESC_HDR_SEL0_AESU |
1991                                      DESC_HDR_MODE0_AESU_CBC |
1992                                      DESC_HDR_SEL1_MDEUA |
1993                                      DESC_HDR_MODE1_MDEU_INIT |
1994                                      DESC_HDR_MODE1_MDEU_PAD |
1995                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1996         },
1997         {       .type = CRYPTO_ALG_TYPE_AEAD,
1998                 .alg.crypto = {
1999                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
2000                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
2001                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2002                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2003                         .cra_aead = {
2004                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2005                                 .maxauthsize = SHA1_DIGEST_SIZE,
2006                         }
2007                 },
2008                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2009                                      DESC_HDR_SEL0_DEU |
2010                                      DESC_HDR_MODE0_DEU_CBC |
2011                                      DESC_HDR_MODE0_DEU_3DES |
2012                                      DESC_HDR_SEL1_MDEUA |
2013                                      DESC_HDR_MODE1_MDEU_INIT |
2014                                      DESC_HDR_MODE1_MDEU_PAD |
2015                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
2016         },
2017         {       .type = CRYPTO_ALG_TYPE_AEAD,
2018                 .alg.crypto = {
2019                         .cra_name = "authenc(hmac(sha224),cbc(aes))",
2020                         .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
2021                         .cra_blocksize = AES_BLOCK_SIZE,
2022                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2023                         .cra_aead = {
2024                                 .ivsize = AES_BLOCK_SIZE,
2025                                 .maxauthsize = SHA224_DIGEST_SIZE,
2026                         }
2027                 },
2028                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2029                                      DESC_HDR_SEL0_AESU |
2030                                      DESC_HDR_MODE0_AESU_CBC |
2031                                      DESC_HDR_SEL1_MDEUA |
2032                                      DESC_HDR_MODE1_MDEU_INIT |
2033                                      DESC_HDR_MODE1_MDEU_PAD |
2034                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2035         },
2036         {       .type = CRYPTO_ALG_TYPE_AEAD,
2037                 .alg.crypto = {
2038                         .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
2039                         .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
2040                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2041                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2042                         .cra_aead = {
2043                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2044                                 .maxauthsize = SHA224_DIGEST_SIZE,
2045                         }
2046                 },
2047                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2048                                      DESC_HDR_SEL0_DEU |
2049                                      DESC_HDR_MODE0_DEU_CBC |
2050                                      DESC_HDR_MODE0_DEU_3DES |
2051                                      DESC_HDR_SEL1_MDEUA |
2052                                      DESC_HDR_MODE1_MDEU_INIT |
2053                                      DESC_HDR_MODE1_MDEU_PAD |
2054                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2055         },
2056         {       .type = CRYPTO_ALG_TYPE_AEAD,
2057                 .alg.crypto = {
2058                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
2059                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
2060                         .cra_blocksize = AES_BLOCK_SIZE,
2061                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2062                         .cra_aead = {
2063                                 .ivsize = AES_BLOCK_SIZE,
2064                                 .maxauthsize = SHA256_DIGEST_SIZE,
2065                         }
2066                 },
2067                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2068                                      DESC_HDR_SEL0_AESU |
2069                                      DESC_HDR_MODE0_AESU_CBC |
2070                                      DESC_HDR_SEL1_MDEUA |
2071                                      DESC_HDR_MODE1_MDEU_INIT |
2072                                      DESC_HDR_MODE1_MDEU_PAD |
2073                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2074         },
2075         {       .type = CRYPTO_ALG_TYPE_AEAD,
2076                 .alg.crypto = {
2077                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2078                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2079                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2080                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2081                         .cra_aead = {
2082                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2083                                 .maxauthsize = SHA256_DIGEST_SIZE,
2084                         }
2085                 },
2086                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2087                                      DESC_HDR_SEL0_DEU |
2088                                      DESC_HDR_MODE0_DEU_CBC |
2089                                      DESC_HDR_MODE0_DEU_3DES |
2090                                      DESC_HDR_SEL1_MDEUA |
2091                                      DESC_HDR_MODE1_MDEU_INIT |
2092                                      DESC_HDR_MODE1_MDEU_PAD |
2093                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2094         },
2095         {       .type = CRYPTO_ALG_TYPE_AEAD,
2096                 .alg.crypto = {
2097                         .cra_name = "authenc(hmac(sha384),cbc(aes))",
2098                         .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2099                         .cra_blocksize = AES_BLOCK_SIZE,
2100                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2101                         .cra_aead = {
2102                                 .ivsize = AES_BLOCK_SIZE,
2103                                 .maxauthsize = SHA384_DIGEST_SIZE,
2104                         }
2105                 },
2106                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2107                                      DESC_HDR_SEL0_AESU |
2108                                      DESC_HDR_MODE0_AESU_CBC |
2109                                      DESC_HDR_SEL1_MDEUB |
2110                                      DESC_HDR_MODE1_MDEU_INIT |
2111                                      DESC_HDR_MODE1_MDEU_PAD |
2112                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2113         },
2114         {       .type = CRYPTO_ALG_TYPE_AEAD,
2115                 .alg.crypto = {
2116                         .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2117                         .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2118                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2119                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2120                         .cra_aead = {
2121                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2122                                 .maxauthsize = SHA384_DIGEST_SIZE,
2123                         }
2124                 },
2125                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2126                                      DESC_HDR_SEL0_DEU |
2127                                      DESC_HDR_MODE0_DEU_CBC |
2128                                      DESC_HDR_MODE0_DEU_3DES |
2129                                      DESC_HDR_SEL1_MDEUB |
2130                                      DESC_HDR_MODE1_MDEU_INIT |
2131                                      DESC_HDR_MODE1_MDEU_PAD |
2132                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2133         },
2134         {       .type = CRYPTO_ALG_TYPE_AEAD,
2135                 .alg.crypto = {
2136                         .cra_name = "authenc(hmac(sha512),cbc(aes))",
2137                         .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2138                         .cra_blocksize = AES_BLOCK_SIZE,
2139                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2140                         .cra_aead = {
2141                                 .ivsize = AES_BLOCK_SIZE,
2142                                 .maxauthsize = SHA512_DIGEST_SIZE,
2143                         }
2144                 },
2145                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2146                                      DESC_HDR_SEL0_AESU |
2147                                      DESC_HDR_MODE0_AESU_CBC |
2148                                      DESC_HDR_SEL1_MDEUB |
2149                                      DESC_HDR_MODE1_MDEU_INIT |
2150                                      DESC_HDR_MODE1_MDEU_PAD |
2151                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2152         },
2153         {       .type = CRYPTO_ALG_TYPE_AEAD,
2154                 .alg.crypto = {
2155                         .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2156                         .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2157                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2158                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2159                         .cra_aead = {
2160                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2161                                 .maxauthsize = SHA512_DIGEST_SIZE,
2162                         }
2163                 },
2164                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2165                                      DESC_HDR_SEL0_DEU |
2166                                      DESC_HDR_MODE0_DEU_CBC |
2167                                      DESC_HDR_MODE0_DEU_3DES |
2168                                      DESC_HDR_SEL1_MDEUB |
2169                                      DESC_HDR_MODE1_MDEU_INIT |
2170                                      DESC_HDR_MODE1_MDEU_PAD |
2171                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2172         },
2173         {       .type = CRYPTO_ALG_TYPE_AEAD,
2174                 .alg.crypto = {
2175                         .cra_name = "authenc(hmac(md5),cbc(aes))",
2176                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2177                         .cra_blocksize = AES_BLOCK_SIZE,
2178                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2179                         .cra_aead = {
2180                                 .ivsize = AES_BLOCK_SIZE,
2181                                 .maxauthsize = MD5_DIGEST_SIZE,
2182                         }
2183                 },
2184                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2185                                      DESC_HDR_SEL0_AESU |
2186                                      DESC_HDR_MODE0_AESU_CBC |
2187                                      DESC_HDR_SEL1_MDEUA |
2188                                      DESC_HDR_MODE1_MDEU_INIT |
2189                                      DESC_HDR_MODE1_MDEU_PAD |
2190                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2191         },
2192         {       .type = CRYPTO_ALG_TYPE_AEAD,
2193                 .alg.crypto = {
2194                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2195                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2196                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2197                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2198                         .cra_aead = {
2199                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2200                                 .maxauthsize = MD5_DIGEST_SIZE,
2201                         }
2202                 },
2203                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2204                                      DESC_HDR_SEL0_DEU |
2205                                      DESC_HDR_MODE0_DEU_CBC |
2206                                      DESC_HDR_MODE0_DEU_3DES |
2207                                      DESC_HDR_SEL1_MDEUA |
2208                                      DESC_HDR_MODE1_MDEU_INIT |
2209                                      DESC_HDR_MODE1_MDEU_PAD |
2210                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2211         },
2212         /* ABLKCIPHER algorithms. */
2213         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2214                 .alg.crypto = {
2215                         .cra_name = "cbc(aes)",
2216                         .cra_driver_name = "cbc-aes-talitos",
2217                         .cra_blocksize = AES_BLOCK_SIZE,
2218                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2219                                      CRYPTO_ALG_ASYNC,
2220                         .cra_ablkcipher = {
2221                                 .min_keysize = AES_MIN_KEY_SIZE,
2222                                 .max_keysize = AES_MAX_KEY_SIZE,
2223                                 .ivsize = AES_BLOCK_SIZE,
2224                         }
2225                 },
2226                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2227                                      DESC_HDR_SEL0_AESU |
2228                                      DESC_HDR_MODE0_AESU_CBC,
2229         },
2230         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2231                 .alg.crypto = {
2232                         .cra_name = "cbc(des3_ede)",
2233                         .cra_driver_name = "cbc-3des-talitos",
2234                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2235                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2236                                      CRYPTO_ALG_ASYNC,
2237                         .cra_ablkcipher = {
2238                                 .min_keysize = DES3_EDE_KEY_SIZE,
2239                                 .max_keysize = DES3_EDE_KEY_SIZE,
2240                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2241                         }
2242                 },
2243                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2244                                      DESC_HDR_SEL0_DEU |
2245                                      DESC_HDR_MODE0_DEU_CBC |
2246                                      DESC_HDR_MODE0_DEU_3DES,
2247         },
2248         /* AHASH algorithms. */
2249         {       .type = CRYPTO_ALG_TYPE_AHASH,
2250                 .alg.hash = {
2251                         .halg.digestsize = MD5_DIGEST_SIZE,
2252                         .halg.base = {
2253                                 .cra_name = "md5",
2254                                 .cra_driver_name = "md5-talitos",
2255                                 .cra_blocksize = MD5_BLOCK_SIZE,
2256                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2257                                              CRYPTO_ALG_ASYNC,
2258                         }
2259                 },
2260                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2261                                      DESC_HDR_SEL0_MDEUA |
2262                                      DESC_HDR_MODE0_MDEU_MD5,
2263         },
2264         {       .type = CRYPTO_ALG_TYPE_AHASH,
2265                 .alg.hash = {
2266                         .halg.digestsize = SHA1_DIGEST_SIZE,
2267                         .halg.base = {
2268                                 .cra_name = "sha1",
2269                                 .cra_driver_name = "sha1-talitos",
2270                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2271                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2272                                              CRYPTO_ALG_ASYNC,
2273                         }
2274                 },
2275                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2276                                      DESC_HDR_SEL0_MDEUA |
2277                                      DESC_HDR_MODE0_MDEU_SHA1,
2278         },
2279         {       .type = CRYPTO_ALG_TYPE_AHASH,
2280                 .alg.hash = {
2281                         .halg.digestsize = SHA224_DIGEST_SIZE,
2282                         .halg.base = {
2283                                 .cra_name = "sha224",
2284                                 .cra_driver_name = "sha224-talitos",
2285                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2286                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2287                                              CRYPTO_ALG_ASYNC,
2288                         }
2289                 },
2290                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2291                                      DESC_HDR_SEL0_MDEUA |
2292                                      DESC_HDR_MODE0_MDEU_SHA224,
2293         },
2294         {       .type = CRYPTO_ALG_TYPE_AHASH,
2295                 .alg.hash = {
2296                         .halg.digestsize = SHA256_DIGEST_SIZE,
2297                         .halg.base = {
2298                                 .cra_name = "sha256",
2299                                 .cra_driver_name = "sha256-talitos",
2300                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2301                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2302                                              CRYPTO_ALG_ASYNC,
2303                         }
2304                 },
2305                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2306                                      DESC_HDR_SEL0_MDEUA |
2307                                      DESC_HDR_MODE0_MDEU_SHA256,
2308         },
2309         {       .type = CRYPTO_ALG_TYPE_AHASH,
2310                 .alg.hash = {
2311                         .halg.digestsize = SHA384_DIGEST_SIZE,
2312                         .halg.base = {
2313                                 .cra_name = "sha384",
2314                                 .cra_driver_name = "sha384-talitos",
2315                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2316                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2317                                              CRYPTO_ALG_ASYNC,
2318                         }
2319                 },
2320                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2321                                      DESC_HDR_SEL0_MDEUB |
2322                                      DESC_HDR_MODE0_MDEUB_SHA384,
2323         },
2324         {       .type = CRYPTO_ALG_TYPE_AHASH,
2325                 .alg.hash = {
2326                         .halg.digestsize = SHA512_DIGEST_SIZE,
2327                         .halg.base = {
2328                                 .cra_name = "sha512",
2329                                 .cra_driver_name = "sha512-talitos",
2330                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2331                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2332                                              CRYPTO_ALG_ASYNC,
2333                         }
2334                 },
2335                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2336                                      DESC_HDR_SEL0_MDEUB |
2337                                      DESC_HDR_MODE0_MDEUB_SHA512,
2338         },
2339         {       .type = CRYPTO_ALG_TYPE_AHASH,
2340                 .alg.hash = {
2341                         .halg.digestsize = MD5_DIGEST_SIZE,
2342                         .halg.base = {
2343                                 .cra_name = "hmac(md5)",
2344                                 .cra_driver_name = "hmac-md5-talitos",
2345                                 .cra_blocksize = MD5_BLOCK_SIZE,
2346                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2347                                              CRYPTO_ALG_ASYNC,
2348                         }
2349                 },
2350                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2351                                      DESC_HDR_SEL0_MDEUA |
2352                                      DESC_HDR_MODE0_MDEU_MD5,
2353         },
2354         {       .type = CRYPTO_ALG_TYPE_AHASH,
2355                 .alg.hash = {
2356                         .halg.digestsize = SHA1_DIGEST_SIZE,
2357                         .halg.base = {
2358                                 .cra_name = "hmac(sha1)",
2359                                 .cra_driver_name = "hmac-sha1-talitos",
2360                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2361                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2362                                              CRYPTO_ALG_ASYNC,
2363                         }
2364                 },
2365                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2366                                      DESC_HDR_SEL0_MDEUA |
2367                                      DESC_HDR_MODE0_MDEU_SHA1,
2368         },
2369         {       .type = CRYPTO_ALG_TYPE_AHASH,
2370                 .alg.hash = {
2371                         .halg.digestsize = SHA224_DIGEST_SIZE,
2372                         .halg.base = {
2373                                 .cra_name = "hmac(sha224)",
2374                                 .cra_driver_name = "hmac-sha224-talitos",
2375                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2376                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2377                                              CRYPTO_ALG_ASYNC,
2378                         }
2379                 },
2380                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2381                                      DESC_HDR_SEL0_MDEUA |
2382                                      DESC_HDR_MODE0_MDEU_SHA224,
2383         },
2384         {       .type = CRYPTO_ALG_TYPE_AHASH,
2385                 .alg.hash = {
2386                         .halg.digestsize = SHA256_DIGEST_SIZE,
2387                         .halg.base = {
2388                                 .cra_name = "hmac(sha256)",
2389                                 .cra_driver_name = "hmac-sha256-talitos",
2390                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2391                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2392                                              CRYPTO_ALG_ASYNC,
2393                         }
2394                 },
2395                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2396                                      DESC_HDR_SEL0_MDEUA |
2397                                      DESC_HDR_MODE0_MDEU_SHA256,
2398         },
2399         {       .type = CRYPTO_ALG_TYPE_AHASH,
2400                 .alg.hash = {
2401                         .halg.digestsize = SHA384_DIGEST_SIZE,
2402                         .halg.base = {
2403                                 .cra_name = "hmac(sha384)",
2404                                 .cra_driver_name = "hmac-sha384-talitos",
2405                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2406                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2407                                              CRYPTO_ALG_ASYNC,
2408                         }
2409                 },
2410                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2411                                      DESC_HDR_SEL0_MDEUB |
2412                                      DESC_HDR_MODE0_MDEUB_SHA384,
2413         },
2414         {       .type = CRYPTO_ALG_TYPE_AHASH,
2415                 .alg.hash = {
2416                         .halg.digestsize = SHA512_DIGEST_SIZE,
2417                         .halg.base = {
2418                                 .cra_name = "hmac(sha512)",
2419                                 .cra_driver_name = "hmac-sha512-talitos",
2420                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2421                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2422                                              CRYPTO_ALG_ASYNC,
2423                         }
2424                 },
2425                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2426                                      DESC_HDR_SEL0_MDEUB |
2427                                      DESC_HDR_MODE0_MDEUB_SHA512,
2428         }
2429 };
2430
2431 struct talitos_crypto_alg {
2432         struct list_head entry;
2433         struct device *dev;
2434         struct talitos_alg_template algt;
2435 };
2436
2437 static int talitos_cra_init(struct crypto_tfm *tfm)
2438 {
2439         struct crypto_alg *alg = tfm->__crt_alg;
2440         struct talitos_crypto_alg *talitos_alg;
2441         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2442         struct talitos_private *priv;
2443
2444         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2445                 talitos_alg = container_of(__crypto_ahash_alg(alg),
2446                                            struct talitos_crypto_alg,
2447                                            algt.alg.hash);
2448         else
2449                 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2450                                            algt.alg.crypto);
2451
2452         /* update context with ptr to dev */
2453         ctx->dev = talitos_alg->dev;
2454
2455         /* assign SEC channel to tfm in round-robin fashion */
2456         priv = dev_get_drvdata(ctx->dev);
2457         ctx->ch = atomic_inc_return(&priv->last_chan) &
2458                   (priv->num_channels - 1);
2459
2460         /* copy descriptor header template value */
2461         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2462
2463         /* select done notification */
2464         ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2465
2466         return 0;
2467 }
2468
2469 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2470 {
2471         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2472
2473         talitos_cra_init(tfm);
2474
2475         /* random first IV */
2476         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2477
2478         return 0;
2479 }
2480
2481 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2482 {
2483         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2484
2485         talitos_cra_init(tfm);
2486
2487         ctx->keylen = 0;
2488         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2489                                  sizeof(struct talitos_ahash_req_ctx));
2490
2491         return 0;
2492 }
2493
2494 /*
2495  * given the alg's descriptor header template, determine whether descriptor
2496  * type and primary/secondary execution units required match the hw
2497  * capabilities description provided in the device tree node.
2498  */
2499 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2500 {
2501         struct talitos_private *priv = dev_get_drvdata(dev);
2502         int ret;
2503
2504         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2505               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2506
2507         if (SECONDARY_EU(desc_hdr_template))
2508                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2509                               & priv->exec_units);
2510
2511         return ret;
2512 }
2513
2514 static int talitos_remove(struct platform_device *ofdev)
2515 {
2516         struct device *dev = &ofdev->dev;
2517         struct talitos_private *priv = dev_get_drvdata(dev);
2518         struct talitos_crypto_alg *t_alg, *n;
2519         int i;
2520
2521         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2522                 switch (t_alg->algt.type) {
2523                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2524                 case CRYPTO_ALG_TYPE_AEAD:
2525                         crypto_unregister_alg(&t_alg->algt.alg.crypto);
2526                         break;
2527                 case CRYPTO_ALG_TYPE_AHASH:
2528                         crypto_unregister_ahash(&t_alg->algt.alg.hash);
2529                         break;
2530                 }
2531                 list_del(&t_alg->entry);
2532                 kfree(t_alg);
2533         }
2534
2535         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2536                 talitos_unregister_rng(dev);
2537
2538         for (i = 0; i < priv->num_channels; i++)
2539                 kfree(priv->chan[i].fifo);
2540
2541         kfree(priv->chan);
2542
2543         for (i = 0; i < 2; i++)
2544                 if (priv->irq[i]) {
2545                         free_irq(priv->irq[i], dev);
2546                         irq_dispose_mapping(priv->irq[i]);
2547                 }
2548
2549         tasklet_kill(&priv->done_task[0]);
2550         if (priv->irq[1])
2551                 tasklet_kill(&priv->done_task[1]);
2552
2553         iounmap(priv->reg);
2554
2555         dev_set_drvdata(dev, NULL);
2556
2557         kfree(priv);
2558
2559         return 0;
2560 }
2561
2562 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2563                                                     struct talitos_alg_template
2564                                                            *template)
2565 {
2566         struct talitos_private *priv = dev_get_drvdata(dev);
2567         struct talitos_crypto_alg *t_alg;
2568         struct crypto_alg *alg;
2569
2570         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2571         if (!t_alg)
2572                 return ERR_PTR(-ENOMEM);
2573
2574         t_alg->algt = *template;
2575
2576         switch (t_alg->algt.type) {
2577         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2578                 alg = &t_alg->algt.alg.crypto;
2579                 alg->cra_init = talitos_cra_init;
2580                 alg->cra_type = &crypto_ablkcipher_type;
2581                 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2582                 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2583                 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2584                 alg->cra_ablkcipher.geniv = "eseqiv";
2585                 break;
2586         case CRYPTO_ALG_TYPE_AEAD:
2587                 alg = &t_alg->algt.alg.crypto;
2588                 alg->cra_init = talitos_cra_init_aead;
2589                 alg->cra_type = &crypto_aead_type;
2590                 alg->cra_aead.setkey = aead_setkey;
2591                 alg->cra_aead.setauthsize = aead_setauthsize;
2592                 alg->cra_aead.encrypt = aead_encrypt;
2593                 alg->cra_aead.decrypt = aead_decrypt;
2594                 alg->cra_aead.givencrypt = aead_givencrypt;
2595                 alg->cra_aead.geniv = "<built-in>";
2596                 break;
2597         case CRYPTO_ALG_TYPE_AHASH:
2598                 alg = &t_alg->algt.alg.hash.halg.base;
2599                 alg->cra_init = talitos_cra_init_ahash;
2600                 alg->cra_type = &crypto_ahash_type;
2601                 t_alg->algt.alg.hash.init = ahash_init;
2602                 t_alg->algt.alg.hash.update = ahash_update;
2603                 t_alg->algt.alg.hash.final = ahash_final;
2604                 t_alg->algt.alg.hash.finup = ahash_finup;
2605                 t_alg->algt.alg.hash.digest = ahash_digest;
2606                 t_alg->algt.alg.hash.setkey = ahash_setkey;
2607
2608                 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
2609                     !strncmp(alg->cra_name, "hmac", 4)) {
2610                         kfree(t_alg);
2611                         return ERR_PTR(-ENOTSUPP);
2612                 }
2613                 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2614                     (!strcmp(alg->cra_name, "sha224") ||
2615                      !strcmp(alg->cra_name, "hmac(sha224)"))) {
2616                         t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2617                         t_alg->algt.desc_hdr_template =
2618                                         DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2619                                         DESC_HDR_SEL0_MDEUA |
2620                                         DESC_HDR_MODE0_MDEU_SHA256;
2621                 }
2622                 break;
2623         default:
2624                 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2625                 kfree(t_alg);
2626                 return ERR_PTR(-EINVAL);
2627         }
2628
2629         alg->cra_module = THIS_MODULE;
2630         alg->cra_priority = TALITOS_CRA_PRIORITY;
2631         alg->cra_alignmask = 0;
2632         alg->cra_ctxsize = sizeof(struct talitos_ctx);
2633         alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2634
2635         t_alg->dev = dev;
2636
2637         return t_alg;
2638 }
2639
2640 static int talitos_probe_irq(struct platform_device *ofdev)
2641 {
2642         struct device *dev = &ofdev->dev;
2643         struct device_node *np = ofdev->dev.of_node;
2644         struct talitos_private *priv = dev_get_drvdata(dev);
2645         int err;
2646
2647         priv->irq[0] = irq_of_parse_and_map(np, 0);
2648         if (!priv->irq[0]) {
2649                 dev_err(dev, "failed to map irq\n");
2650                 return -EINVAL;
2651         }
2652
2653         priv->irq[1] = irq_of_parse_and_map(np, 1);
2654
2655         /* get the primary irq line */
2656         if (!priv->irq[1]) {
2657                 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2658                                   dev_driver_string(dev), dev);
2659                 goto primary_out;
2660         }
2661
2662         err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2663                           dev_driver_string(dev), dev);
2664         if (err)
2665                 goto primary_out;
2666
2667         /* get the secondary irq line */
2668         err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2669                           dev_driver_string(dev), dev);
2670         if (err) {
2671                 dev_err(dev, "failed to request secondary irq\n");
2672                 irq_dispose_mapping(priv->irq[1]);
2673                 priv->irq[1] = 0;
2674         }
2675
2676         return err;
2677
2678 primary_out:
2679         if (err) {
2680                 dev_err(dev, "failed to request primary irq\n");
2681                 irq_dispose_mapping(priv->irq[0]);
2682                 priv->irq[0] = 0;
2683         }
2684
2685         return err;
2686 }
2687
2688 static int talitos_probe(struct platform_device *ofdev)
2689 {
2690         struct device *dev = &ofdev->dev;
2691         struct device_node *np = ofdev->dev.of_node;
2692         struct talitos_private *priv;
2693         const unsigned int *prop;
2694         int i, err;
2695
2696         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2697         if (!priv)
2698                 return -ENOMEM;
2699
2700         dev_set_drvdata(dev, priv);
2701
2702         priv->ofdev = ofdev;
2703
2704         spin_lock_init(&priv->reg_lock);
2705
2706         err = talitos_probe_irq(ofdev);
2707         if (err)
2708                 goto err_out;
2709
2710         if (!priv->irq[1]) {
2711                 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2712                              (unsigned long)dev);
2713         } else {
2714                 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2715                              (unsigned long)dev);
2716                 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2717                              (unsigned long)dev);
2718         }
2719
2720         INIT_LIST_HEAD(&priv->alg_list);
2721
2722         priv->reg = of_iomap(np, 0);
2723         if (!priv->reg) {
2724                 dev_err(dev, "failed to of_iomap\n");
2725                 err = -ENOMEM;
2726                 goto err_out;
2727         }
2728
2729         /* get SEC version capabilities from device tree */
2730         prop = of_get_property(np, "fsl,num-channels", NULL);
2731         if (prop)
2732                 priv->num_channels = *prop;
2733
2734         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2735         if (prop)
2736                 priv->chfifo_len = *prop;
2737
2738         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2739         if (prop)
2740                 priv->exec_units = *prop;
2741
2742         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2743         if (prop)
2744                 priv->desc_types = *prop;
2745
2746         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2747             !priv->exec_units || !priv->desc_types) {
2748                 dev_err(dev, "invalid property data in device tree node\n");
2749                 err = -EINVAL;
2750                 goto err_out;
2751         }
2752
2753         if (of_device_is_compatible(np, "fsl,sec3.0"))
2754                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2755
2756         if (of_device_is_compatible(np, "fsl,sec2.1"))
2757                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2758                                   TALITOS_FTR_SHA224_HWINIT |
2759                                   TALITOS_FTR_HMAC_OK;
2760
2761         priv->chan = kzalloc(sizeof(struct talitos_channel) *
2762                              priv->num_channels, GFP_KERNEL);
2763         if (!priv->chan) {
2764                 dev_err(dev, "failed to allocate channel management space\n");
2765                 err = -ENOMEM;
2766                 goto err_out;
2767         }
2768
2769         for (i = 0; i < priv->num_channels; i++) {
2770                 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2771                 if (!priv->irq[1] || !(i & 1))
2772                         priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2773         }
2774
2775         for (i = 0; i < priv->num_channels; i++) {
2776                 spin_lock_init(&priv->chan[i].head_lock);
2777                 spin_lock_init(&priv->chan[i].tail_lock);
2778         }
2779
2780         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2781
2782         for (i = 0; i < priv->num_channels; i++) {
2783                 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2784                                              priv->fifo_len, GFP_KERNEL);
2785                 if (!priv->chan[i].fifo) {
2786                         dev_err(dev, "failed to allocate request fifo %d\n", i);
2787                         err = -ENOMEM;
2788                         goto err_out;
2789                 }
2790         }
2791
2792         for (i = 0; i < priv->num_channels; i++)
2793                 atomic_set(&priv->chan[i].submit_count,
2794                            -(priv->chfifo_len - 1));
2795
2796         dma_set_mask(dev, DMA_BIT_MASK(36));
2797
2798         /* reset and initialize the h/w */
2799         err = init_device(dev);
2800         if (err) {
2801                 dev_err(dev, "failed to initialize device\n");
2802                 goto err_out;
2803         }
2804
2805         /* register the RNG, if available */
2806         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2807                 err = talitos_register_rng(dev);
2808                 if (err) {
2809                         dev_err(dev, "failed to register hwrng: %d\n", err);
2810                         goto err_out;
2811                 } else
2812                         dev_info(dev, "hwrng\n");
2813         }
2814
2815         /* register crypto algorithms the device supports */
2816         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2817                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2818                         struct talitos_crypto_alg *t_alg;
2819                         char *name = NULL;
2820
2821                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2822                         if (IS_ERR(t_alg)) {
2823                                 err = PTR_ERR(t_alg);
2824                                 if (err == -ENOTSUPP)
2825                                         continue;
2826                                 goto err_out;
2827                         }
2828
2829                         switch (t_alg->algt.type) {
2830                         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2831                         case CRYPTO_ALG_TYPE_AEAD:
2832                                 err = crypto_register_alg(
2833                                                 &t_alg->algt.alg.crypto);
2834                                 name = t_alg->algt.alg.crypto.cra_driver_name;
2835                                 break;
2836                         case CRYPTO_ALG_TYPE_AHASH:
2837                                 err = crypto_register_ahash(
2838                                                 &t_alg->algt.alg.hash);
2839                                 name =
2840                                  t_alg->algt.alg.hash.halg.base.cra_driver_name;
2841                                 break;
2842                         }
2843                         if (err) {
2844                                 dev_err(dev, "%s alg registration failed\n",
2845                                         name);
2846                                 kfree(t_alg);
2847                         } else
2848                                 list_add_tail(&t_alg->entry, &priv->alg_list);
2849                 }
2850         }
2851         if (!list_empty(&priv->alg_list))
2852                 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2853                          (char *)of_get_property(np, "compatible", NULL));
2854
2855         return 0;
2856
2857 err_out:
2858         talitos_remove(ofdev);
2859
2860         return err;
2861 }
2862
2863 static const struct of_device_id talitos_match[] = {
2864         {
2865                 .compatible = "fsl,sec2.0",
2866         },
2867         {},
2868 };
2869 MODULE_DEVICE_TABLE(of, talitos_match);
2870
2871 static struct platform_driver talitos_driver = {
2872         .driver = {
2873                 .name = "talitos",
2874                 .owner = THIS_MODULE,
2875                 .of_match_table = talitos_match,
2876         },
2877         .probe = talitos_probe,
2878         .remove = talitos_remove,
2879 };
2880
2881 module_platform_driver(talitos_driver);
2882
2883 MODULE_LICENSE("GPL");
2884 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2885 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");