drivers/crypto/chelsio/chcr_core.c

   1 /**
   2  * This file is part of the Chelsio T4/T5/T6 Ethernet driver for Linux.
   3  *
   4  * Copyright (C) 2011-2016 Chelsio Communications.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  *
  10  * Written and Maintained by:
  11  * Manoj Malviya (manojmalviya@chelsio.com)
  12  * Atul Gupta (atul.gupta@chelsio.com)
  13  * Jitendra Lulla (jlulla@chelsio.com)
  14  * Yeshaswi M R Gowda (yeshaswi@chelsio.com)
  15  * Harsh Jain (harsh@chelsio.com)
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/skbuff.h>
  21
  22 #include <crypto/aes.h>
  23 #include <crypto/hash.h>
  24
  25 #include "t4_msg.h"
  26 #include "chcr_core.h"
  27 #include "cxgb4_uld.h"
  28
  29 static struct chcr_driver_data drv_data;
  30
  31 typedef int (*chcr_handler_func)(struct chcr_dev *dev, unsigned char *input);
  32 static int cpl_fw6_pld_handler(struct chcr_dev *dev, unsigned char *input);
  33 static void *chcr_uld_add(const struct cxgb4_lld_info *lld);
  34 static int chcr_uld_state_change(void *handle, enum cxgb4_state state);
  35
  36 static chcr_handler_func work_handlers[NUM_CPL_CMDS] = {
  37         [CPL_FW6_PLD] = cpl_fw6_pld_handler,
  38 };
  39
  40 static struct cxgb4_uld_info chcr_uld_info = {
  41         .name = DRV_MODULE_NAME,
  42         .nrxq = MAX_ULD_QSETS,
  43         /* Max ntxq will be derived from fw config file*/
  44         .rxq_size = 1024,
  45         .add = chcr_uld_add,
  46         .state_change = chcr_uld_state_change,
  47         .rx_handler = chcr_uld_rx_handler,
  48 #ifdef CONFIG_CHELSIO_IPSEC_INLINE
  49         .tx_handler = chcr_uld_tx_handler,
  50 #endif /* CONFIG_CHELSIO_IPSEC_INLINE */
  51 };
  52
  53 static void detach_work_fn(struct work_struct *work)
  54 {
  55         struct chcr_dev *dev;
  56
  57         dev = container_of(work, struct chcr_dev, detach_work.work);
  58
  59         if (atomic_read(&dev->inflight)) {
  60                 dev->wqretry--;
  61                 if (dev->wqretry) {
  62                         pr_debug("Request Inflight Count %d\n",
  63                                 atomic_read(&dev->inflight));
  64
  65                         schedule_delayed_work(&dev->detach_work, WQ_DETACH_TM);
  66                 } else {
  67                         WARN(1, "CHCR:%d request Still Pending\n",
  68                                 atomic_read(&dev->inflight));
  69                         complete(&dev->detach_comp);
  70                 }
  71         } else {
  72                 complete(&dev->detach_comp);
  73         }
  74 }
  75
  76 struct uld_ctx *assign_chcr_device(void)
  77 {
  78         struct uld_ctx *u_ctx = NULL;
  79
  80         /*
  81          * When multiple devices are present in system select
  82          * device in round-robin fashion for crypto operations
  83          * Although One session must use the same device to
  84          * maintain request-response ordering.
  85          */
  86         mutex_lock(&drv_data.drv_mutex);
  87         if (!list_empty(&drv_data.act_dev)) {
  88                 u_ctx = drv_data.last_dev;
  89                 if (list_is_last(&drv_data.last_dev->entry, &drv_data.act_dev))
  90                         drv_data.last_dev = list_first_entry(&drv_data.act_dev,
  91                                                   struct uld_ctx, entry);
  92                 else
  93                         drv_data.last_dev =
  94                                 list_next_entry(drv_data.last_dev, entry);
  95         }
  96         mutex_unlock(&drv_data.drv_mutex);
  97         return u_ctx;
  98 }
  99
 100 static void chcr_dev_add(struct uld_ctx *u_ctx)
 101 {
 102         struct chcr_dev *dev;
 103
 104         dev = &u_ctx->dev;
 105         dev->state = CHCR_ATTACH;
 106         atomic_set(&dev->inflight, 0);
 107         mutex_lock(&drv_data.drv_mutex);
 108         list_move(&u_ctx->entry, &drv_data.act_dev);
 109         if (!drv_data.last_dev)
 110                 drv_data.last_dev = u_ctx;
 111         mutex_unlock(&drv_data.drv_mutex);
 112 }
 113
 114 static void chcr_dev_init(struct uld_ctx *u_ctx)
 115 {
 116         struct chcr_dev *dev;
 117
 118         dev = &u_ctx->dev;
 119         spin_lock_init(&dev->lock_chcr_dev);
 120         INIT_DELAYED_WORK(&dev->detach_work, detach_work_fn);
 121         init_completion(&dev->detach_comp);
 122         dev->state = CHCR_INIT;
 123         dev->wqretry = WQ_RETRY;
 124         atomic_inc(&drv_data.dev_count);
 125         atomic_set(&dev->inflight, 0);
 126         mutex_lock(&drv_data.drv_mutex);
 127         list_add_tail(&u_ctx->entry, &drv_data.inact_dev);
 128         mutex_unlock(&drv_data.drv_mutex);
 129 }
 130
 131 static int chcr_dev_move(struct uld_ctx *u_ctx)
 132 {
 133         struct adapter *adap;
 134
 135          mutex_lock(&drv_data.drv_mutex);
 136         if (drv_data.last_dev == u_ctx) {
 137                 if (list_is_last(&drv_data.last_dev->entry, &drv_data.act_dev))
 138                         drv_data.last_dev = list_first_entry(&drv_data.act_dev,
 139                                                   struct uld_ctx, entry);
 140                 else
 141                         drv_data.last_dev =
 142                                 list_next_entry(drv_data.last_dev, entry);
 143         }
 144         list_move(&u_ctx->entry, &drv_data.inact_dev);
 145         if (list_empty(&drv_data.act_dev))
 146                 drv_data.last_dev = NULL;
 147         adap = padap(&u_ctx->dev);
 148         memset(&adap->chcr_stats, 0, sizeof(adap->chcr_stats));
 149         atomic_dec(&drv_data.dev_count);
 150         mutex_unlock(&drv_data.drv_mutex);
 151
 152         return 0;
 153 }
 154
 155 static int cpl_fw6_pld_handler(struct chcr_dev *dev,
 156                                unsigned char *input)
 157 {
 158         struct crypto_async_request *req;
 159         struct cpl_fw6_pld *fw6_pld;
 160         u32 ack_err_status = 0;
 161         int error_status = 0;
 162         struct adapter *adap = padap(dev);
 163
 164         fw6_pld = (struct cpl_fw6_pld *)input;
 165         req = (struct crypto_async_request *)(uintptr_t)be64_to_cpu(
 166                                                     fw6_pld->data[1]);
 167
 168         ack_err_status =
 169                 ntohl(*(__be32 *)((unsigned char *)&fw6_pld->data[0] + 4));
 170         if (CHK_MAC_ERR_BIT(ack_err_status) || CHK_PAD_ERR_BIT(ack_err_status))
 171                 error_status = -EBADMSG;
 172         /* call completion callback with failure status */
 173         if (req) {
 174                 error_status = chcr_handle_resp(req, input, error_status);
 175         } else {
 176                 pr_err("Incorrect request address from the firmware\n");
 177                 return -EFAULT;
 178         }
 179         if (error_status)
 180                 atomic_inc(&adap->chcr_stats.error);
 181
 182         return 0;
 183 }
 184
 185 int chcr_send_wr(struct sk_buff *skb)
 186 {
 187         return cxgb4_crypto_send(skb->dev, skb);
 188 }
 189
 190 static void *chcr_uld_add(const struct cxgb4_lld_info *lld)
 191 {
 192         struct uld_ctx *u_ctx;
 193
 194         /* Create the device and add it in the device list */
 195         if (!(lld->ulp_crypto & ULP_CRYPTO_LOOKASIDE))
 196                 return ERR_PTR(-EOPNOTSUPP);
 197
 198         /* Create the device and add it in the device list */
 199         u_ctx = kzalloc(sizeof(*u_ctx), GFP_KERNEL);
 200         if (!u_ctx) {
 201                 u_ctx = ERR_PTR(-ENOMEM);
 202                 goto out;
 203         }
 204         u_ctx->lldi = *lld;
 205         chcr_dev_init(u_ctx);
 206 #ifdef CONFIG_CHELSIO_IPSEC_INLINE
 207         if (lld->crypto & ULP_CRYPTO_IPSEC_INLINE)
 208                 chcr_add_xfrmops(lld);
 209 #endif /* CONFIG_CHELSIO_IPSEC_INLINE */
 210 out:
 211         return u_ctx;
 212 }
 213
 214 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
 215                         const struct pkt_gl *pgl)
 216 {
 217         struct uld_ctx *u_ctx = (struct uld_ctx *)handle;
 218         struct chcr_dev *dev = &u_ctx->dev;
 219         const struct cpl_fw6_pld *rpl = (struct cpl_fw6_pld *)rsp;
 220
 221         if (rpl->opcode != CPL_FW6_PLD) {
 222                 pr_err("Unsupported opcode\n");
 223                 return 0;
 224         }
 225
 226         if (!pgl)
 227                 work_handlers[rpl->opcode](dev, (unsigned char *)&rsp[1]);
 228         else
 229                 work_handlers[rpl->opcode](dev, pgl->va);
 230         return 0;
 231 }
 232
 233 #ifdef CONFIG_CHELSIO_IPSEC_INLINE
 234 int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev)
 235 {
 236         return chcr_ipsec_xmit(skb, dev);
 237 }
 238 #endif /* CONFIG_CHELSIO_IPSEC_INLINE */
 239
 240 static void chcr_detach_device(struct uld_ctx *u_ctx)
 241 {
 242         struct chcr_dev *dev = &u_ctx->dev;
 243
 244         if (dev->state == CHCR_DETACH) {
 245                 pr_debug("Detached Event received for already detach device\n");
 246                 return;
 247         }
 248         dev->state = CHCR_DETACH;
 249         if (atomic_read(&dev->inflight) != 0) {
 250                 schedule_delayed_work(&dev->detach_work, WQ_DETACH_TM);
 251                 wait_for_completion(&dev->detach_comp);
 252         }
 253
 254         // Move u_ctx to inactive_dev list
 255         chcr_dev_move(u_ctx);
 256 }
 257
 258 static int chcr_uld_state_change(void *handle, enum cxgb4_state state)
 259 {
 260         struct uld_ctx *u_ctx = handle;
 261         int ret = 0;
 262
 263         switch (state) {
 264         case CXGB4_STATE_UP:
 265                 if (u_ctx->dev.state != CHCR_INIT) {
 266                         // ALready Initialised.
 267                         return 0;
 268                 }
 269                 chcr_dev_add(u_ctx);
 270                 ret = start_crypto();
 271                 break;
 272
 273         case CXGB4_STATE_DETACH:
 274                 chcr_detach_device(u_ctx);
 275                 break;
 276
 277         case CXGB4_STATE_START_RECOVERY:
 278         case CXGB4_STATE_DOWN:
 279         default:
 280                 break;
 281         }
 282         return ret;
 283 }
 284
 285 static int __init chcr_crypto_init(void)
 286 {
 287         INIT_LIST_HEAD(&drv_data.act_dev);
 288         INIT_LIST_HEAD(&drv_data.inact_dev);
 289         atomic_set(&drv_data.dev_count, 0);
 290         mutex_init(&drv_data.drv_mutex);
 291         drv_data.last_dev = NULL;
 292         cxgb4_register_uld(CXGB4_ULD_CRYPTO, &chcr_uld_info);
 293
 294         return 0;
 295 }
 296
 297 static void __exit chcr_crypto_exit(void)
 298 {
 299         struct uld_ctx *u_ctx, *tmp;
 300
 301         stop_crypto();
 302
 303         cxgb4_unregister_uld(CXGB4_ULD_CRYPTO);
 304         /* Remove all devices from list */
 305         mutex_lock(&drv_data.drv_mutex);
 306         list_for_each_entry_safe(u_ctx, tmp, &drv_data.act_dev, entry) {
 307                 list_del(&u_ctx->entry);
 308                 kfree(u_ctx);
 309         }
 310         list_for_each_entry_safe(u_ctx, tmp, &drv_data.inact_dev, entry) {
 311                 list_del(&u_ctx->entry);
 312                 kfree(u_ctx);
 313         }
 314         mutex_unlock(&drv_data.drv_mutex);
 315 }
 316
 317 module_init(chcr_crypto_init);
 318 module_exit(chcr_crypto_exit);
 319
 320 MODULE_DESCRIPTION("Crypto Co-processor for Chelsio Terminator cards.");
 321 MODULE_LICENSE("GPL");
 322 MODULE_AUTHOR("Chelsio Communications");
 323 MODULE_VERSION(DRV_VERSION);