drivers/clk/zte/clk-zx296718.c

   1 /*
   2  * Copyright (C) 2015 - 2016 ZTE Corporation.
   3  * Copyright (C) 2016 Linaro Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk-provider.h>
  10 #include <linux/device.h>
  11 #include <linux/kernel.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <dt-bindings/clock/zx296718-clock.h>
  17 #include "clk.h"
  18
  19 /* TOP CRM */
  20 #define TOP_CLK_MUX0    0x04
  21 #define TOP_CLK_MUX1    0x08
  22 #define TOP_CLK_MUX2    0x0c
  23 #define TOP_CLK_MUX3    0x10
  24 #define TOP_CLK_MUX4    0x14
  25 #define TOP_CLK_MUX5    0x18
  26 #define TOP_CLK_MUX6    0x1c
  27 #define TOP_CLK_MUX7    0x20
  28 #define TOP_CLK_MUX9    0x28
  29
  30
  31 #define TOP_CLK_GATE0   0x34
  32 #define TOP_CLK_GATE1   0x38
  33 #define TOP_CLK_GATE2   0x3c
  34 #define TOP_CLK_GATE3   0x40
  35 #define TOP_CLK_GATE4   0x44
  36 #define TOP_CLK_GATE5   0x48
  37 #define TOP_CLK_GATE6   0x4c
  38
  39 #define TOP_CLK_DIV0    0x58
  40
  41 #define PLL_CPU_REG     0x80
  42 #define PLL_VGA_REG     0xb0
  43 #define PLL_DDR_REG     0xa0
  44
  45 /* LSP0 CRM */
  46 #define LSP0_TIMER3_CLK 0x4
  47 #define LSP0_TIMER4_CLK 0x8
  48 #define LSP0_TIMER5_CLK 0xc
  49 #define LSP0_UART3_CLK  0x10
  50 #define LSP0_UART1_CLK  0x14
  51 #define LSP0_UART2_CLK  0x18
  52 #define LSP0_SPIFC0_CLK 0x1c
  53 #define LSP0_I2C4_CLK   0x20
  54 #define LSP0_I2C5_CLK   0x24
  55 #define LSP0_SSP0_CLK   0x28
  56 #define LSP0_SSP1_CLK   0x2c
  57 #define LSP0_USIM0_CLK  0x30
  58 #define LSP0_GPIO_CLK   0x34
  59 #define LSP0_I2C3_CLK   0x38
  60
  61 /* LSP1 CRM */
  62 #define LSP1_UART4_CLK  0x08
  63 #define LSP1_UART5_CLK  0x0c
  64 #define LSP1_PWM_CLK    0x10
  65 #define LSP1_I2C2_CLK   0x14
  66 #define LSP1_SSP2_CLK   0x1c
  67 #define LSP1_SSP3_CLK   0x20
  68 #define LSP1_SSP4_CLK   0x24
  69 #define LSP1_USIM1_CLK  0x28
  70
  71 /* audio lsp */
  72 #define AUDIO_I2S0_DIV_CFG1     0x10
  73 #define AUDIO_I2S0_DIV_CFG2     0x14
  74 #define AUDIO_I2S0_CLK          0x18
  75 #define AUDIO_I2S1_DIV_CFG1     0x20
  76 #define AUDIO_I2S1_DIV_CFG2     0x24
  77 #define AUDIO_I2S1_CLK          0x28
  78 #define AUDIO_I2S2_DIV_CFG1     0x30
  79 #define AUDIO_I2S2_DIV_CFG2     0x34
  80 #define AUDIO_I2S2_CLK          0x38
  81 #define AUDIO_I2S3_DIV_CFG1     0x40
  82 #define AUDIO_I2S3_DIV_CFG2     0x44
  83 #define AUDIO_I2S3_CLK          0x48
  84 #define AUDIO_I2C0_CLK          0x50
  85 #define AUDIO_SPDIF0_DIV_CFG1   0x60
  86 #define AUDIO_SPDIF0_DIV_CFG2   0x64
  87 #define AUDIO_SPDIF0_CLK        0x68
  88 #define AUDIO_SPDIF1_DIV_CFG1   0x70
  89 #define AUDIO_SPDIF1_DIV_CFG2   0x74
  90 #define AUDIO_SPDIF1_CLK        0x78
  91 #define AUDIO_TIMER_CLK         0x80
  92 #define AUDIO_TDM_CLK           0x90
  93 #define AUDIO_TS_CLK            0xa0
  94
  95 static DEFINE_SPINLOCK(clk_lock);
  96
  97 static const struct zx_pll_config pll_cpu_table[] = {
  98         PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa),
  99         PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa),
 100         PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa),
 101         PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
 102 };
 103
 104 static const struct zx_pll_config pll_vga_table[] = {
 105         PLL_RATE(36000000,  0x00102464, 0x04000000), /* 800x600@56 */
 106         PLL_RATE(40000000,  0x00102864, 0x04000000), /* 800x600@60 */
 107         PLL_RATE(49500000,  0x00103164, 0x04800000), /* 800x600@75 */
 108         PLL_RATE(50000000,  0x00103264, 0x04000000), /* 800x600@72 */
 109         PLL_RATE(56250000,  0x00103864, 0x04400000), /* 800x600@85 */
 110         PLL_RATE(65000000,  0x00104164, 0x04000000), /* 1024x768@60 */
 111         PLL_RATE(74375000,  0x00104a64, 0x04600000), /* 1280x720@60 */
 112         PLL_RATE(75000000,  0x00104b64, 0x04800000), /* 1024x768@70 */
 113         PLL_RATE(78750000,  0x00104e64, 0x04c00000), /* 1024x768@75 */
 114         PLL_RATE(85500000,  0x00105564, 0x04800000), /* 1360x768@60 */
 115         PLL_RATE(106500000, 0x00106a64, 0x04800000), /* 1440x900@60 */
 116         PLL_RATE(108000000, 0x00106c64, 0x04000000), /* 1280x1024@60 */
 117         PLL_RATE(110000000, 0x00106e64, 0x04000000), /* 1024x768@85 */
 118         PLL_RATE(135000000, 0x00105a44, 0x04000000), /* 1280x1024@75 */
 119         PLL_RATE(136750000, 0x00104462, 0x04600000), /* 1440x900@75 */
 120         PLL_RATE(148500000, 0x00104a62, 0x04400000), /* 1920x1080@60 */
 121         PLL_RATE(157000000, 0x00104e62, 0x04800000), /* 1440x900@85 */
 122         PLL_RATE(157500000, 0x00104e62, 0x04c00000), /* 1280x1024@85 */
 123         PLL_RATE(162000000, 0x00105162, 0x04000000), /* 1600x1200@60 */
 124         PLL_RATE(193250000, 0x00106062, 0x04a00000), /* 1920x1200@60 */
 125 };
 126
 127 PNAME(osc) = {
 128         "osc24m",
 129         "osc32k",
 130 };
 131
 132 PNAME(dbg_wclk_p) = {
 133         "clk334m",
 134         "clk466m",
 135         "clk396m",
 136         "clk250m",
 137 };
 138
 139 PNAME(a72_coreclk_p) = {
 140         "osc24m",
 141         "pll_mm0_1188m",
 142         "pll_mm1_1296m",
 143         "clk1000m",
 144         "clk648m",
 145         "clk1600m",
 146         "pll_audio_1800m",
 147         "pll_vga_1800m",
 148 };
 149
 150 PNAME(cpu_periclk_p) = {
 151         "osc24m",
 152         "clk500m",
 153         "clk594m",
 154         "clk466m",
 155         "clk294m",
 156         "clk334m",
 157         "clk250m",
 158         "clk125m",
 159 };
 160
 161 PNAME(a53_coreclk_p) = {
 162         "osc24m",
 163         "clk1000m",
 164         "pll_mm0_1188m",
 165         "clk648m",
 166         "clk500m",
 167         "clk800m",
 168         "clk1600m",
 169         "pll_audio_1800m",
 170 };
 171
 172 PNAME(sec_wclk_p) = {
 173         "osc24m",
 174         "clk396m",
 175         "clk334m",
 176         "clk297m",
 177         "clk250m",
 178         "clk198m",
 179         "clk148m5",
 180         "clk99m",
 181 };
 182
 183 PNAME(sd_nand_wclk_p) = {
 184         "osc24m",
 185         "clk49m5",
 186         "clk99m",
 187         "clk198m",
 188         "clk167m",
 189         "clk148m5",
 190         "clk125m",
 191         "clk216m",
 192 };
 193
 194 PNAME(emmc_wclk_p) = {
 195         "osc24m",
 196         "clk198m",
 197         "clk99m",
 198         "clk396m",
 199         "clk334m",
 200         "clk297m",
 201         "clk250m",
 202         "clk148m5",
 203 };
 204
 205 PNAME(clk32_p) = {
 206         "osc32k",
 207         "clk32k768",
 208 };
 209
 210 PNAME(usb_ref24m_p) = {
 211         "osc32k",
 212         "clk32k768",
 213 };
 214
 215 PNAME(sys_noc_alck_p) = {
 216         "osc24m",
 217         "clk250m",
 218         "clk198m",
 219         "clk148m5",
 220         "clk108m",
 221         "clk54m",
 222         "clk216m",
 223         "clk240m",
 224 };
 225
 226 PNAME(vde_aclk_p) = {
 227         "clk334m",
 228         "clk594m",
 229         "clk500m",
 230         "clk432m",
 231         "clk480m",
 232         "clk297m",
 233         "clk_vga",  /*600MHz*/
 234         "clk294m",
 235 };
 236
 237 PNAME(vce_aclk_p) = {
 238         "clk334m",
 239         "clk594m",
 240         "clk500m",
 241         "clk432m",
 242         "clk396m",
 243         "clk297m",
 244         "clk_vga",  /*600MHz*/
 245         "clk294m",
 246 };
 247
 248 PNAME(hde_aclk_p) = {
 249         "clk334m",
 250         "clk594m",
 251         "clk500m",
 252         "clk432m",
 253         "clk396m",
 254         "clk297m",
 255         "clk_vga",  /*600MHz*/
 256         "clk294m",
 257 };
 258
 259 PNAME(gpu_aclk_p) = {
 260         "clk334m",
 261         "clk648m",
 262         "clk594m",
 263         "clk500m",
 264         "clk396m",
 265         "clk297m",
 266         "clk_vga",  /*600MHz*/
 267         "clk294m",
 268 };
 269
 270 PNAME(sappu_aclk_p) = {
 271         "clk396m",
 272         "clk500m",
 273         "clk250m",
 274         "clk148m5",
 275 };
 276
 277 PNAME(sappu_wclk_p) = {
 278         "clk198m",
 279         "clk396m",
 280         "clk334m",
 281         "clk297m",
 282         "clk250m",
 283         "clk148m5",
 284         "clk125m",
 285         "clk99m",
 286 };
 287
 288 PNAME(vou_aclk_p) = {
 289         "clk334m",
 290         "clk594m",
 291         "clk500m",
 292         "clk432m",
 293         "clk396m",
 294         "clk297m",
 295         "clk_vga",  /*600MHz*/
 296         "clk294m",
 297 };
 298
 299 PNAME(vou_main_wclk_p) = {
 300         "clk108m",
 301         "clk594m",
 302         "clk297m",
 303         "clk148m5",
 304         "clk74m25",
 305         "clk54m",
 306         "clk27m",
 307         "clk_vga",
 308 };
 309
 310 PNAME(vou_aux_wclk_p) = {
 311         "clk108m",
 312         "clk148m5",
 313         "clk74m25",
 314         "clk54m",
 315         "clk27m",
 316         "clk_vga",
 317         "clk54m_mm0",
 318         "clk"
 319 };
 320
 321 PNAME(vou_ppu_wclk_p) = {
 322         "clk334m",
 323         "clk432m",
 324         "clk396m",
 325         "clk297m",
 326         "clk250m",
 327         "clk125m",
 328         "clk198m",
 329         "clk99m",
 330 };
 331
 332 PNAME(vga_i2c_wclk_p) = {
 333         "osc24m",
 334         "clk99m",
 335 };
 336
 337 PNAME(viu_m0_aclk_p) = {
 338         "clk334m",
 339         "clk432m",
 340         "clk396m",
 341         "clk297m",
 342         "clk250m",
 343         "clk125m",
 344         "clk198m",
 345         "osc24m",
 346 };
 347
 348 PNAME(viu_m1_aclk_p) = {
 349         "clk198m",
 350         "clk250m",
 351         "clk297m",
 352         "clk125m",
 353         "clk396m",
 354         "clk334m",
 355         "clk148m5",
 356         "osc24m",
 357 };
 358
 359 PNAME(viu_clk_p) = {
 360         "clk198m",
 361         "clk334m",
 362         "clk297m",
 363         "clk250m",
 364         "clk396m",
 365         "clk125m",
 366         "clk99m",
 367         "clk148m5",
 368 };
 369
 370 PNAME(viu_jpeg_clk_p) = {
 371         "clk334m",
 372         "clk480m",
 373         "clk432m",
 374         "clk396m",
 375         "clk297m",
 376         "clk250m",
 377         "clk125m",
 378         "clk198m",
 379 };
 380
 381 PNAME(ts_sys_clk_p) = {
 382         "clk192m",
 383         "clk167m",
 384         "clk125m",
 385         "clk99m",
 386 };
 387
 388 PNAME(wdt_ares_p) = {
 389         "osc24m",
 390         "clk32k"
 391 };
 392
 393 static struct clk_zx_pll zx296718_pll_clk[] = {
 394         ZX296718_PLL("pll_cpu", "osc24m",       PLL_CPU_REG,    pll_cpu_table),
 395         ZX296718_PLL("pll_vga", "osc24m",       PLL_VGA_REG,    pll_vga_table),
 396 };
 397
 398 static struct zx_clk_fixed_factor top_ffactor_clk[] = {
 399         FFACTOR(0, "clk4m",             "osc24m", 1, 6,  0),
 400         FFACTOR(0, "clk2m",             "osc24m", 1, 12, 0),
 401         /* pll cpu */
 402         FFACTOR(0, "clk1600m",          "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
 403         FFACTOR(0, "clk800m",           "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
 404         /* pll mac */
 405         FFACTOR(0, "clk25m",            "pll_mac", 1, 40, 0),
 406         FFACTOR(0, "clk125m",           "pll_mac", 1, 8, 0),
 407         FFACTOR(0, "clk250m",           "pll_mac", 1, 4, 0),
 408         FFACTOR(0, "clk50m",            "pll_mac", 1, 20, 0),
 409         FFACTOR(0, "clk500m",           "pll_mac", 1, 2, 0),
 410         FFACTOR(0, "clk1000m",          "pll_mac", 1, 1, 0),
 411         FFACTOR(0, "clk334m",           "pll_mac", 1, 3, 0),
 412         FFACTOR(0, "clk167m",           "pll_mac", 1, 6, 0),
 413         /* pll mm */
 414         FFACTOR(0, "clk54m_mm0",        "pll_mm0", 1, 22, 0),
 415         FFACTOR(0, "clk74m25",          "pll_mm0", 1, 16, 0),
 416         FFACTOR(0, "clk148m5",          "pll_mm0", 1, 8, 0),
 417         FFACTOR(0, "clk297m",           "pll_mm0", 1, 4, 0),
 418         FFACTOR(0, "clk594m",           "pll_mm0", 1, 2, 0),
 419         FFACTOR(0, "pll_mm0_1188m",     "pll_mm0", 1, 1, 0),
 420         FFACTOR(0, "clk396m",           "pll_mm0", 1, 3, 0),
 421         FFACTOR(0, "clk198m",           "pll_mm0", 1, 6, 0),
 422         FFACTOR(0, "clk99m",            "pll_mm0", 1, 12, 0),
 423         FFACTOR(0, "clk49m5",           "pll_mm0", 1, 24, 0),
 424         /* pll mm */
 425         FFACTOR(0, "clk324m",           "pll_mm1", 1, 4, 0),
 426         FFACTOR(0, "clk648m",           "pll_mm1", 1, 2, 0),
 427         FFACTOR(0, "pll_mm1_1296m",     "pll_mm1", 1, 1, 0),
 428         FFACTOR(0, "clk216m",           "pll_mm1", 1, 6, 0),
 429         FFACTOR(0, "clk432m",           "pll_mm1", 1, 3, 0),
 430         FFACTOR(0, "clk108m",           "pll_mm1", 1, 12, 0),
 431         FFACTOR(0, "clk72m",            "pll_mm1", 1, 18, 0),
 432         FFACTOR(0, "clk27m",            "pll_mm1", 1, 48, 0),
 433         FFACTOR(0, "clk54m",            "pll_mm1", 1, 24, 0),
 434         /* vga */
 435         FFACTOR(0, "pll_vga_1800m",     "pll_vga", 1, 1, 0),
 436         FFACTOR(0, "clk_vga",           "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
 437         /* pll ddr */
 438         FFACTOR(0, "clk466m",           "pll_ddr", 1, 2, 0),
 439
 440         /* pll audio */
 441         FFACTOR(0, "pll_audio_1800m",   "pll_audio", 1, 1, 0),
 442         FFACTOR(0, "clk32k768",         "pll_audio", 1, 27000, 0),
 443         FFACTOR(0, "clk16m384",         "pll_audio", 1, 54, 0),
 444         FFACTOR(0, "clk294m",           "pll_audio", 1, 3, 0),
 445
 446         /* pll hsic*/
 447         FFACTOR(0, "clk240m",           "pll_hsic", 1, 4, 0),
 448         FFACTOR(0, "clk480m",           "pll_hsic", 1, 2, 0),
 449         FFACTOR(0, "clk192m",           "pll_hsic", 1, 5, 0),
 450         FFACTOR(0, "clk_pll_24m",       "pll_hsic", 1, 40, 0),
 451         FFACTOR(0, "emmc_mux_div2",     "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
 452 };
 453
 454 static const struct clk_div_table noc_div_table[] = {
 455         { .val = 1, .div = 2, },
 456         { .val = 3, .div = 4, },
 457 };
 458 static struct zx_clk_div top_div_clk[] = {
 459         DIV_T(0, "sys_noc_hclk", "sys_noc_aclk", TOP_CLK_DIV0, 0, 2, 0, noc_div_table),
 460         DIV_T(0, "sys_noc_pclk", "sys_noc_aclk", TOP_CLK_DIV0, 4, 2, 0, noc_div_table),
 461 };
 462
 463 static struct zx_clk_mux top_mux_clk[] = {
 464         MUX(0, "dbg_mux",        dbg_wclk_p,      TOP_CLK_MUX0, 12, 2),
 465         MUX(0, "a72_mux",        a72_coreclk_p,   TOP_CLK_MUX0, 8, 3),
 466         MUX(0, "cpu_peri_mux",   cpu_periclk_p,   TOP_CLK_MUX0, 4, 3),
 467         MUX_F(0, "a53_mux",      a53_coreclk_p,   TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
 468         MUX(0, "sys_noc_aclk",   sys_noc_alck_p,  TOP_CLK_MUX1, 0, 3),
 469         MUX(0, "sec_mux",        sec_wclk_p,      TOP_CLK_MUX2, 16, 3),
 470         MUX(0, "sd1_mux",        sd_nand_wclk_p,  TOP_CLK_MUX2, 12, 3),
 471         MUX(0, "sd0_mux",        sd_nand_wclk_p,  TOP_CLK_MUX2, 8, 3),
 472         MUX(0, "emmc_mux",       emmc_wclk_p,     TOP_CLK_MUX2, 4, 3),
 473         MUX(0, "nand_mux",       sd_nand_wclk_p,  TOP_CLK_MUX2, 0, 3),
 474         MUX(0, "usb_ref24m_mux", usb_ref24m_p,    TOP_CLK_MUX9, 16, 1),
 475         MUX(0, "clk32k",         clk32_p,         TOP_CLK_MUX9, 12, 1),
 476         MUX_F(0, "wdt_mux",      wdt_ares_p,      TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
 477         MUX(0, "timer_mux",      osc,             TOP_CLK_MUX9, 4, 1),
 478         MUX(0, "vde_mux",        vde_aclk_p,      TOP_CLK_MUX4,  0, 3),
 479         MUX(0, "vce_mux",        vce_aclk_p,      TOP_CLK_MUX4,  4, 3),
 480         MUX(0, "hde_mux",        hde_aclk_p,      TOP_CLK_MUX4,  8, 3),
 481         MUX(0, "gpu_mux",        gpu_aclk_p,      TOP_CLK_MUX5,  0, 3),
 482         MUX(0, "sappu_a_mux",    sappu_aclk_p,    TOP_CLK_MUX5,  4, 2),
 483         MUX(0, "sappu_w_mux",    sappu_wclk_p,    TOP_CLK_MUX5,  8, 3),
 484         MUX(0, "vou_a_mux",      vou_aclk_p,      TOP_CLK_MUX7,  0, 3),
 485         MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7,  4, 3, CLK_SET_RATE_PARENT, 0),
 486         MUX_F(0, "vou_aux_w_mux",  vou_aux_wclk_p,  TOP_CLK_MUX7,  8, 3, CLK_SET_RATE_PARENT, 0),
 487         MUX(0, "vou_ppu_w_mux",  vou_ppu_wclk_p,  TOP_CLK_MUX7, 12, 3),
 488         MUX(0, "vga_i2c_mux",    vga_i2c_wclk_p,  TOP_CLK_MUX7, 16, 1),
 489         MUX(0, "viu_m0_a_mux",   viu_m0_aclk_p,   TOP_CLK_MUX6,  0, 3),
 490         MUX(0, "viu_m1_a_mux",   viu_m1_aclk_p,   TOP_CLK_MUX6,  4, 3),
 491         MUX(0, "viu_w_mux",      viu_clk_p,       TOP_CLK_MUX6,  8, 3),
 492         MUX(0, "viu_jpeg_w_mux", viu_jpeg_clk_p,  TOP_CLK_MUX6, 12, 3),
 493         MUX(0, "ts_sys_mux",     ts_sys_clk_p,    TOP_CLK_MUX6, 16, 2),
 494 };
 495
 496 static struct zx_clk_gate top_gate_clk[] = {
 497         GATE(CPU_DBG_GATE,    "dbg_wclk",        "dbg_mux",        TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, 0),
 498         GATE(A72_GATE,        "a72_coreclk",     "a72_mux",        TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, 0),
 499         GATE(CPU_PERI_GATE,   "cpu_peri",        "cpu_peri_mux",   TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
 500         GATE(A53_GATE,        "a53_coreclk",     "a53_mux",        TOP_CLK_GATE0, 0, CLK_SET_RATE_PARENT, 0),
 501         GATE(SD1_WCLK,        "sd1_wclk",        "sd1_mux",        TOP_CLK_GATE1, 13, CLK_SET_RATE_PARENT, 0),
 502         GATE(SD0_WCLK,        "sd0_wclk",        "sd0_mux",        TOP_CLK_GATE1, 9, CLK_SET_RATE_PARENT, 0),
 503         GATE(EMMC_WCLK,       "emmc_wclk",       "emmc_mux_div2",  TOP_CLK_GATE0, 5, CLK_SET_RATE_PARENT, 0),
 504         GATE(EMMC_NAND_AXI,   "emmc_nand_aclk",  "sys_noc_aclk",   TOP_CLK_GATE1, 4, CLK_SET_RATE_PARENT, 0),
 505         GATE(NAND_WCLK,       "nand_wclk",       "nand_mux",       TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
 506         GATE(EMMC_NAND_AHB,   "emmc_nand_hclk",  "sys_noc_hclk",   TOP_CLK_GATE1, 0, CLK_SET_RATE_PARENT, 0),
 507         GATE(0,               "lsp1_pclk",       "sys_noc_pclk",   TOP_CLK_GATE2, 31, 0,                  0),
 508         GATE(LSP1_148M5,      "lsp1_148m5",      "clk148m5",       TOP_CLK_GATE2, 30, 0,                  0),
 509         GATE(LSP1_99M,        "lsp1_99m",        "clk99m",         TOP_CLK_GATE2, 29, 0,                  0),
 510         GATE(LSP1_24M,        "lsp1_24m",        "osc24m",         TOP_CLK_GATE2, 28, 0,                  0),
 511         GATE(LSP0_74M25,      "lsp0_74m25",      "clk74m25",       TOP_CLK_GATE2, 25, 0,                  0),
 512         GATE(0,               "lsp0_pclk",       "sys_noc_pclk",   TOP_CLK_GATE2, 24, 0,                  0),
 513         GATE(LSP0_32K,        "lsp0_32k",        "osc32k",         TOP_CLK_GATE2, 23, 0,                  0),
 514         GATE(LSP0_148M5,      "lsp0_148m5",      "clk148m5",       TOP_CLK_GATE2, 22, 0,                  0),
 515         GATE(LSP0_99M,        "lsp0_99m",        "clk99m",         TOP_CLK_GATE2, 21, 0,                  0),
 516         GATE(LSP0_24M,        "lsp0_24m",        "osc24m",         TOP_CLK_GATE2, 20, 0,                  0),
 517         GATE(AUDIO_99M,       "audio_99m",       "clk99m",         TOP_CLK_GATE5, 27, 0,                  0),
 518         GATE(AUDIO_24M,       "audio_24m",       "osc24m",         TOP_CLK_GATE5, 28, 0,                  0),
 519         GATE(AUDIO_16M384,    "audio_16m384",    "clk16m384",      TOP_CLK_GATE5, 29, 0,                  0),
 520         GATE(AUDIO_32K,       "audio_32k",       "clk32k",         TOP_CLK_GATE5, 30, 0,                  0),
 521         GATE(WDT_WCLK,        "wdt_wclk",        "wdt_mux",        TOP_CLK_GATE6, 9, CLK_SET_RATE_PARENT, 0),
 522         GATE(TIMER_WCLK,      "timer_wclk",      "timer_mux",      TOP_CLK_GATE6, 5, CLK_SET_RATE_PARENT, 0),
 523         GATE(VDE_ACLK,        "vde_aclk",        "vde_mux",        TOP_CLK_GATE3, 0,  CLK_SET_RATE_PARENT, 0),
 524         GATE(VCE_ACLK,        "vce_aclk",        "vce_mux",        TOP_CLK_GATE3, 4,  CLK_SET_RATE_PARENT, 0),
 525         GATE(HDE_ACLK,        "hde_aclk",        "hde_mux",        TOP_CLK_GATE3, 8,  CLK_SET_RATE_PARENT, 0),
 526         GATE(GPU_ACLK,        "gpu_aclk",        "gpu_mux",        TOP_CLK_GATE3, 16, CLK_SET_RATE_PARENT, 0),
 527         GATE(SAPPU_ACLK,      "sappu_aclk",      "sappu_a_mux",    TOP_CLK_GATE3, 20, CLK_SET_RATE_PARENT, 0),
 528         GATE(SAPPU_WCLK,      "sappu_wclk",      "sappu_w_mux",    TOP_CLK_GATE3, 22, CLK_SET_RATE_PARENT, 0),
 529         GATE(VOU_ACLK,        "vou_aclk",        "vou_a_mux",      TOP_CLK_GATE4, 16, CLK_SET_RATE_PARENT, 0),
 530         GATE(VOU_MAIN_WCLK,   "vou_main_wclk",   "vou_main_w_mux", TOP_CLK_GATE4, 18, CLK_SET_RATE_PARENT, 0),
 531         GATE(VOU_AUX_WCLK,    "vou_aux_wclk",    "vou_aux_w_mux",  TOP_CLK_GATE4, 19, CLK_SET_RATE_PARENT, 0),
 532         GATE(VOU_PPU_WCLK,    "vou_ppu_wclk",    "vou_ppu_w_mux",  TOP_CLK_GATE4, 20, CLK_SET_RATE_PARENT, 0),
 533         GATE(MIPI_CFG_CLK,    "mipi_cfg_clk",    "osc24m",         TOP_CLK_GATE4, 21, 0,                   0),
 534         GATE(VGA_I2C_WCLK,    "vga_i2c_wclk",    "vga_i2c_mux",    TOP_CLK_GATE4, 23, CLK_SET_RATE_PARENT, 0),
 535         GATE(MIPI_REF_CLK,    "mipi_ref_clk",    "clk27m",         TOP_CLK_GATE4, 24, 0,                   0),
 536         GATE(HDMI_OSC_CEC,    "hdmi_osc_cec",    "clk2m",          TOP_CLK_GATE4, 22, 0,                   0),
 537         GATE(HDMI_OSC_CLK,    "hdmi_osc_clk",    "clk240m",        TOP_CLK_GATE4, 25, 0,                   0),
 538         GATE(HDMI_XCLK,       "hdmi_xclk",       "osc24m",         TOP_CLK_GATE4, 26, 0,                   0),
 539         GATE(VIU_M0_ACLK,     "viu_m0_aclk",     "viu_m0_a_mux",   TOP_CLK_GATE4, 0,  CLK_SET_RATE_PARENT, 0),
 540         GATE(VIU_M1_ACLK,     "viu_m1_aclk",     "viu_m1_a_mux",   TOP_CLK_GATE4, 1,  CLK_SET_RATE_PARENT, 0),
 541         GATE(VIU_WCLK,        "viu_wclk",        "viu_w_mux",      TOP_CLK_GATE4, 2,  CLK_SET_RATE_PARENT, 0),
 542         GATE(VIU_JPEG_WCLK,   "viu_jpeg_wclk",   "viu_jpeg_w_mux", TOP_CLK_GATE4, 3,  CLK_SET_RATE_PARENT, 0),
 543         GATE(VIU_CFG_CLK,     "viu_cfg_clk",     "osc24m",         TOP_CLK_GATE4, 6,  0,                   0),
 544         GATE(TS_SYS_WCLK,     "ts_sys_wclk",     "ts_sys_mux",     TOP_CLK_GATE5, 2,  CLK_SET_RATE_PARENT, 0),
 545         GATE(TS_SYS_108M,     "ts_sys_108m",     "clk108m",        TOP_CLK_GATE5, 3,  0,                   0),
 546         GATE(USB20_HCLK,      "usb20_hclk",      "sys_noc_hclk",   TOP_CLK_GATE2, 12, 0,                   0),
 547         GATE(USB20_PHY_CLK,   "usb20_phy_clk",   "usb_ref24m_mux", TOP_CLK_GATE2, 13, 0,                   0),
 548         GATE(USB21_HCLK,      "usb21_hclk",      "sys_noc_hclk",   TOP_CLK_GATE2, 14, 0,                   0),
 549         GATE(USB21_PHY_CLK,   "usb21_phy_clk",   "usb_ref24m_mux", TOP_CLK_GATE2, 15, 0,                   0),
 550         GATE(GMAC_RMIICLK,    "gmac_rmii_clk",   "clk50m",         TOP_CLK_GATE2, 3, 0,                    0),
 551         GATE(GMAC_PCLK,       "gmac_pclk",       "clk198m",        TOP_CLK_GATE2, 1, 0,                    0),
 552         GATE(GMAC_ACLK,       "gmac_aclk",       "clk49m5",        TOP_CLK_GATE2, 0, 0,                    0),
 553         GATE(GMAC_RFCLK,      "gmac_refclk",     "clk25m",         TOP_CLK_GATE2, 4, 0,                    0),
 554         GATE(SD1_AHB,         "sd1_hclk",        "sys_noc_hclk",   TOP_CLK_GATE1, 12,  0,                  0),
 555         GATE(SD0_AHB,         "sd0_hclk",        "sys_noc_hclk",   TOP_CLK_GATE1, 8,  0,                   0),
 556         GATE(TEMPSENSOR_GATE, "tempsensor_gate", "clk4m",          TOP_CLK_GATE5, 31,  0,                  0),
 557 };
 558
 559 static struct clk_hw_onecell_data top_hw_onecell_data = {
 560         .num = TOP_NR_CLKS,
 561         .hws = {
 562                 [TOP_NR_CLKS - 1] = NULL,
 563         },
 564 };
 565
 566 static int __init top_clocks_init(struct device_node *np)
 567 {
 568         void __iomem *reg_base;
 569         int i, ret;
 570         const char *name;
 571
 572         reg_base = of_iomap(np, 0);
 573         if (!reg_base) {
 574                 pr_err("%s: Unable to map clk base\n", __func__);
 575                 return -ENXIO;
 576         }
 577
 578         for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) {
 579                 zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base;
 580                 name = zx296718_pll_clk[i].hw.init->name;
 581                 ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw);
 582                 if (ret)
 583                         pr_warn("top clk %s init error!\n", name);
 584         }
 585
 586         for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) {
 587                 if (top_ffactor_clk[i].id)
 588                         top_hw_onecell_data.hws[top_ffactor_clk[i].id] =
 589                                         &top_ffactor_clk[i].factor.hw;
 590
 591                 name = top_ffactor_clk[i].factor.hw.init->name;
 592                 ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw);
 593                 if (ret)
 594                         pr_warn("top clk %s init error!\n", name);
 595         }
 596
 597         for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) {
 598                 if (top_mux_clk[i].id)
 599                         top_hw_onecell_data.hws[top_mux_clk[i].id] =
 600                                         &top_mux_clk[i].mux.hw;
 601
 602                 top_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 603                 name = top_mux_clk[i].mux.hw.init->name;
 604                 ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw);
 605                 if (ret)
 606                         pr_warn("top clk %s init error!\n", name);
 607         }
 608
 609         for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) {
 610                 if (top_gate_clk[i].id)
 611                         top_hw_onecell_data.hws[top_gate_clk[i].id] =
 612                                         &top_gate_clk[i].gate.hw;
 613
 614                 top_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 615                 name = top_gate_clk[i].gate.hw.init->name;
 616                 ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw);
 617                 if (ret)
 618                         pr_warn("top clk %s init error!\n", name);
 619         }
 620
 621         for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) {
 622                 if (top_div_clk[i].id)
 623                         top_hw_onecell_data.hws[top_div_clk[i].id] =
 624                                         &top_div_clk[i].div.hw;
 625
 626                 top_div_clk[i].div.reg += (uintptr_t)reg_base;
 627                 name = top_div_clk[i].div.hw.init->name;
 628                 ret = clk_hw_register(NULL, &top_div_clk[i].div.hw);
 629                 if (ret)
 630                         pr_warn("top clk %s init error!\n", name);
 631         }
 632
 633         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 634                                      &top_hw_onecell_data);
 635         if (ret) {
 636                 pr_err("failed to register top clk provider: %d\n", ret);
 637                 return ret;
 638         }
 639
 640         return 0;
 641 }
 642
 643 static const struct clk_div_table common_even_div_table[] = {
 644         { .val = 0, .div = 1, },
 645         { .val = 1, .div = 2, },
 646         { .val = 3, .div = 4, },
 647         { .val = 5, .div = 6, },
 648         { .val = 7, .div = 8, },
 649         { .val = 9, .div = 10, },
 650         { .val = 11, .div = 12, },
 651         { .val = 13, .div = 14, },
 652         { .val = 15, .div = 16, },
 653 };
 654
 655 static const struct clk_div_table common_div_table[] = {
 656         { .val = 0, .div = 1, },
 657         { .val = 1, .div = 2, },
 658         { .val = 2, .div = 3, },
 659         { .val = 3, .div = 4, },
 660         { .val = 4, .div = 5, },
 661         { .val = 5, .div = 6, },
 662         { .val = 6, .div = 7, },
 663         { .val = 7, .div = 8, },
 664         { .val = 8, .div = 9, },
 665         { .val = 9, .div = 10, },
 666         { .val = 10, .div = 11, },
 667         { .val = 11, .div = 12, },
 668         { .val = 12, .div = 13, },
 669         { .val = 13, .div = 14, },
 670         { .val = 14, .div = 15, },
 671         { .val = 15, .div = 16, },
 672 };
 673
 674 PNAME(lsp0_wclk_common_p) = {
 675         "lsp0_24m",
 676         "lsp0_99m",
 677 };
 678
 679 PNAME(lsp0_wclk_timer3_p) = {
 680         "timer3_div",
 681         "lsp0_32k"
 682 };
 683
 684 PNAME(lsp0_wclk_timer4_p) = {
 685         "timer4_div",
 686         "lsp0_32k"
 687 };
 688
 689 PNAME(lsp0_wclk_timer5_p) = {
 690         "timer5_div",
 691         "lsp0_32k"
 692 };
 693
 694 PNAME(lsp0_wclk_spifc0_p) = {
 695         "lsp0_148m5",
 696         "lsp0_24m",
 697         "lsp0_99m",
 698         "lsp0_74m25"
 699 };
 700
 701 PNAME(lsp0_wclk_ssp_p) = {
 702         "lsp0_148m5",
 703         "lsp0_99m",
 704         "lsp0_24m",
 705 };
 706
 707 static struct zx_clk_mux lsp0_mux_clk[] = {
 708         MUX(0, "timer3_wclk_mux", lsp0_wclk_timer3_p, LSP0_TIMER3_CLK, 4, 1),
 709         MUX(0, "timer4_wclk_mux", lsp0_wclk_timer4_p, LSP0_TIMER4_CLK, 4, 1),
 710         MUX(0, "timer5_wclk_mux", lsp0_wclk_timer5_p, LSP0_TIMER5_CLK, 4, 1),
 711         MUX(0, "uart3_wclk_mux",  lsp0_wclk_common_p, LSP0_UART3_CLK,  4, 1),
 712         MUX(0, "uart1_wclk_mux",  lsp0_wclk_common_p, LSP0_UART1_CLK,  4, 1),
 713         MUX(0, "uart2_wclk_mux",  lsp0_wclk_common_p, LSP0_UART2_CLK,  4, 1),
 714         MUX(0, "spifc0_wclk_mux", lsp0_wclk_spifc0_p, LSP0_SPIFC0_CLK, 4, 2),
 715         MUX(0, "i2c4_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C4_CLK,   4, 1),
 716         MUX(0, "i2c5_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C5_CLK,   4, 1),
 717         MUX(0, "ssp0_wclk_mux",   lsp0_wclk_ssp_p,    LSP0_SSP0_CLK,   4, 1),
 718         MUX(0, "ssp1_wclk_mux",   lsp0_wclk_ssp_p,    LSP0_SSP1_CLK,   4, 1),
 719         MUX(0, "i2c3_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C3_CLK,   4, 1),
 720 };
 721
 722 static struct zx_clk_gate lsp0_gate_clk[] = {
 723         GATE(LSP0_TIMER3_WCLK, "timer3_wclk", "timer3_wclk_mux", LSP0_TIMER3_CLK, 1, CLK_SET_RATE_PARENT, 0),
 724         GATE(LSP0_TIMER4_WCLK, "timer4_wclk", "timer4_wclk_mux", LSP0_TIMER4_CLK, 1, CLK_SET_RATE_PARENT, 0),
 725         GATE(LSP0_TIMER5_WCLK, "timer5_wclk", "timer5_wclk_mux", LSP0_TIMER5_CLK, 1, CLK_SET_RATE_PARENT, 0),
 726         GATE(LSP0_UART3_WCLK,  "uart3_wclk",  "uart3_wclk_mux",  LSP0_UART3_CLK,  1, CLK_SET_RATE_PARENT, 0),
 727         GATE(LSP0_UART1_WCLK,  "uart1_wclk",  "uart1_wclk_mux",  LSP0_UART1_CLK,  1, CLK_SET_RATE_PARENT, 0),
 728         GATE(LSP0_UART2_WCLK,  "uart2_wclk",  "uart2_wclk_mux",  LSP0_UART2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 729         GATE(LSP0_SPIFC0_WCLK, "spifc0_wclk", "spifc0_wclk_mux", LSP0_SPIFC0_CLK, 1, CLK_SET_RATE_PARENT, 0),
 730         GATE(LSP0_I2C4_WCLK,   "i2c4_wclk",   "i2c4_wclk_mux",   LSP0_I2C4_CLK,   1, CLK_SET_RATE_PARENT, 0),
 731         GATE(LSP0_I2C5_WCLK,   "i2c5_wclk",   "i2c5_wclk_mux",   LSP0_I2C5_CLK,   1, CLK_SET_RATE_PARENT, 0),
 732         GATE(LSP0_SSP0_WCLK,   "ssp0_wclk",   "ssp0_div",        LSP0_SSP0_CLK,   1, CLK_SET_RATE_PARENT, 0),
 733         GATE(LSP0_SSP1_WCLK,   "ssp1_wclk",   "ssp1_div",        LSP0_SSP1_CLK,   1, CLK_SET_RATE_PARENT, 0),
 734         GATE(LSP0_I2C3_WCLK,   "i2c3_wclk",   "i2c3_wclk_mux",   LSP0_I2C3_CLK,   1, CLK_SET_RATE_PARENT, 0),
 735 };
 736
 737 static struct zx_clk_div lsp0_div_clk[] = {
 738         DIV_T(0, "timer3_div", "lsp0_24m", LSP0_TIMER3_CLK,  12, 4, 0, common_even_div_table),
 739         DIV_T(0, "timer4_div", "lsp0_24m", LSP0_TIMER4_CLK,  12, 4, 0, common_even_div_table),
 740         DIV_T(0, "timer5_div", "lsp0_24m", LSP0_TIMER5_CLK,  12, 4, 0, common_even_div_table),
 741         DIV_T(0, "ssp0_div", "ssp0_wclk_mux", LSP0_SSP0_CLK, 12, 4, 0, common_even_div_table),
 742         DIV_T(0, "ssp1_div", "ssp1_wclk_mux", LSP0_SSP1_CLK, 12, 4, 0, common_even_div_table),
 743 };
 744
 745 static struct clk_hw_onecell_data lsp0_hw_onecell_data = {
 746         .num = LSP0_NR_CLKS,
 747         .hws = {
 748                 [LSP0_NR_CLKS - 1] = NULL,
 749         },
 750 };
 751
 752 static int __init lsp0_clocks_init(struct device_node *np)
 753 {
 754         void __iomem *reg_base;
 755         int i, ret;
 756         const char *name;
 757
 758         reg_base = of_iomap(np, 0);
 759         if (!reg_base) {
 760                 pr_err("%s: Unable to map clk base\n", __func__);
 761                 return -ENXIO;
 762         }
 763
 764         for (i = 0; i < ARRAY_SIZE(lsp0_mux_clk); i++) {
 765                 if (lsp0_mux_clk[i].id)
 766                         lsp0_hw_onecell_data.hws[lsp0_mux_clk[i].id] =
 767                                         &lsp0_mux_clk[i].mux.hw;
 768
 769                 lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 770                 name = lsp0_mux_clk[i].mux.hw.init->name;
 771                 ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw);
 772                 if (ret)
 773                         pr_warn("lsp0 clk %s init error!\n", name);
 774         }
 775
 776         for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) {
 777                 if (lsp0_gate_clk[i].id)
 778                         lsp0_hw_onecell_data.hws[lsp0_gate_clk[i].id] =
 779                                         &lsp0_gate_clk[i].gate.hw;
 780
 781                 lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 782                 name = lsp0_gate_clk[i].gate.hw.init->name;
 783                 ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw);
 784                 if (ret)
 785                         pr_warn("lsp0 clk %s init error!\n", name);
 786         }
 787
 788         for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) {
 789                 if (lsp0_div_clk[i].id)
 790                         lsp0_hw_onecell_data.hws[lsp0_div_clk[i].id] =
 791                                         &lsp0_div_clk[i].div.hw;
 792
 793                 lsp0_div_clk[i].div.reg += (uintptr_t)reg_base;
 794                 name = lsp0_div_clk[i].div.hw.init->name;
 795                 ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw);
 796                 if (ret)
 797                         pr_warn("lsp0 clk %s init error!\n", name);
 798         }
 799
 800         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 801                                      &lsp0_hw_onecell_data);
 802         if (ret) {
 803                 pr_err("failed to register lsp0 clk provider: %d\n", ret);
 804                 return ret;
 805         }
 806
 807         return 0;
 808 }
 809
 810 PNAME(lsp1_wclk_common_p) = {
 811         "lsp1_24m",
 812         "lsp1_99m",
 813 };
 814
 815 PNAME(lsp1_wclk_ssp_p) = {
 816         "lsp1_148m5",
 817         "lsp1_99m",
 818         "lsp1_24m",
 819 };
 820
 821 static struct zx_clk_mux lsp1_mux_clk[] = {
 822         MUX(0, "uart4_wclk_mux", lsp1_wclk_common_p, LSP1_UART4_CLK, 4, 1),
 823         MUX(0, "uart5_wclk_mux", lsp1_wclk_common_p, LSP1_UART5_CLK, 4, 1),
 824         MUX(0, "pwm_wclk_mux",   lsp1_wclk_common_p, LSP1_PWM_CLK,   4, 1),
 825         MUX(0, "i2c2_wclk_mux",  lsp1_wclk_common_p, LSP1_I2C2_CLK,  4, 1),
 826         MUX(0, "ssp2_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP2_CLK,  4, 2),
 827         MUX(0, "ssp3_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP3_CLK,  4, 2),
 828         MUX(0, "ssp4_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP4_CLK,  4, 2),
 829         MUX(0, "usim1_wclk_mux", lsp1_wclk_common_p, LSP1_USIM1_CLK, 4, 1),
 830 };
 831
 832 static struct zx_clk_div lsp1_div_clk[] = {
 833         DIV_T(0, "pwm_div",  "pwm_wclk_mux",  LSP1_PWM_CLK,  12, 4, CLK_SET_RATE_PARENT, common_div_table),
 834         DIV_T(0, "ssp2_div", "ssp2_wclk_mux", LSP1_SSP2_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 835         DIV_T(0, "ssp3_div", "ssp3_wclk_mux", LSP1_SSP3_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 836         DIV_T(0, "ssp4_div", "ssp4_wclk_mux", LSP1_SSP4_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 837 };
 838
 839 static struct zx_clk_gate lsp1_gate_clk[] = {
 840         GATE(LSP1_UART4_WCLK, "lsp1_uart4_wclk", "uart4_wclk_mux", LSP1_UART4_CLK, 1, CLK_SET_RATE_PARENT, 0),
 841         GATE(LSP1_UART5_WCLK, "lsp1_uart5_wclk", "uart5_wclk_mux", LSP1_UART5_CLK, 1, CLK_SET_RATE_PARENT, 0),
 842         GATE(LSP1_PWM_WCLK,   "lsp1_pwm_wclk",   "pwm_div",        LSP1_PWM_CLK,   1, CLK_SET_RATE_PARENT, 0),
 843         GATE(LSP1_PWM_PCLK,   "lsp1_pwm_pclk",   "lsp1_pclk",      LSP1_PWM_CLK,   0, 0,                   0),
 844         GATE(LSP1_I2C2_WCLK,  "lsp1_i2c2_wclk",  "i2c2_wclk_mux",  LSP1_I2C2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 845         GATE(LSP1_SSP2_WCLK,  "lsp1_ssp2_wclk",  "ssp2_div",       LSP1_SSP2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 846         GATE(LSP1_SSP3_WCLK,  "lsp1_ssp3_wclk",  "ssp3_div",       LSP1_SSP3_CLK,  1, CLK_SET_RATE_PARENT, 0),
 847         GATE(LSP1_SSP4_WCLK,  "lsp1_ssp4_wclk",  "ssp4_div",       LSP1_SSP4_CLK,  1, CLK_SET_RATE_PARENT, 0),
 848         GATE(LSP1_USIM1_WCLK, "lsp1_usim1_wclk", "usim1_wclk_mux", LSP1_USIM1_CLK, 1, CLK_SET_RATE_PARENT, 0),
 849 };
 850
 851 static struct clk_hw_onecell_data lsp1_hw_onecell_data = {
 852         .num = LSP1_NR_CLKS,
 853         .hws = {
 854                 [LSP1_NR_CLKS - 1] = NULL,
 855         },
 856 };
 857
 858 static int __init lsp1_clocks_init(struct device_node *np)
 859 {
 860         void __iomem *reg_base;
 861         int i, ret;
 862         const char *name;
 863
 864         reg_base = of_iomap(np, 0);
 865         if (!reg_base) {
 866                 pr_err("%s: Unable to map clk base\n", __func__);
 867                 return -ENXIO;
 868         }
 869
 870         for (i = 0; i < ARRAY_SIZE(lsp1_mux_clk); i++) {
 871                 if (lsp1_mux_clk[i].id)
 872                         lsp1_hw_onecell_data.hws[lsp1_mux_clk[i].id] =
 873                                         &lsp0_mux_clk[i].mux.hw;
 874
 875                 lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 876                 name = lsp1_mux_clk[i].mux.hw.init->name;
 877                 ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw);
 878                 if (ret)
 879                         pr_warn("lsp1 clk %s init error!\n", name);
 880         }
 881
 882         for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) {
 883                 if (lsp1_gate_clk[i].id)
 884                         lsp1_hw_onecell_data.hws[lsp1_gate_clk[i].id] =
 885                                         &lsp1_gate_clk[i].gate.hw;
 886
 887                 lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 888                 name = lsp1_gate_clk[i].gate.hw.init->name;
 889                 ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw);
 890                 if (ret)
 891                         pr_warn("lsp1 clk %s init error!\n", name);
 892         }
 893
 894         for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) {
 895                 if (lsp1_div_clk[i].id)
 896                         lsp1_hw_onecell_data.hws[lsp1_div_clk[i].id] =
 897                                         &lsp1_div_clk[i].div.hw;
 898
 899                 lsp1_div_clk[i].div.reg += (uintptr_t)reg_base;
 900                 name = lsp1_div_clk[i].div.hw.init->name;
 901                 ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw);
 902                 if (ret)
 903                         pr_warn("lsp1 clk %s init error!\n", name);
 904         }
 905
 906         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 907                                      &lsp1_hw_onecell_data);
 908         if (ret) {
 909                 pr_err("failed to register lsp1 clk provider: %d\n", ret);
 910                 return ret;
 911         }
 912
 913         return 0;
 914 }
 915
 916 PNAME(audio_wclk_common_p) = {
 917         "audio_99m",
 918         "audio_24m",
 919 };
 920
 921 PNAME(audio_timer_p) = {
 922         "audio_24m",
 923         "audio_32k",
 924 };
 925
 926 static struct zx_clk_mux audio_mux_clk[] = {
 927         MUX(I2S0_WCLK_MUX, "i2s0_wclk_mux", audio_wclk_common_p, AUDIO_I2S0_CLK, 0, 1),
 928         MUX(I2S1_WCLK_MUX, "i2s1_wclk_mux", audio_wclk_common_p, AUDIO_I2S1_CLK, 0, 1),
 929         MUX(I2S2_WCLK_MUX, "i2s2_wclk_mux", audio_wclk_common_p, AUDIO_I2S2_CLK, 0, 1),
 930         MUX(I2S3_WCLK_MUX, "i2s3_wclk_mux", audio_wclk_common_p, AUDIO_I2S3_CLK, 0, 1),
 931         MUX(0, "i2c0_wclk_mux", audio_wclk_common_p, AUDIO_I2C0_CLK, 0, 1),
 932         MUX(0, "spdif0_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF0_CLK, 0, 1),
 933         MUX(0, "spdif1_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF1_CLK, 0, 1),
 934         MUX(0, "timer_wclk_mux", audio_timer_p, AUDIO_TIMER_CLK, 0, 1),
 935 };
 936
 937 static struct clk_zx_audio_divider audio_adiv_clk[] = {
 938         AUDIO_DIV(0, "i2s0_wclk_div", "i2s0_wclk_mux", AUDIO_I2S0_DIV_CFG1),
 939         AUDIO_DIV(0, "i2s1_wclk_div", "i2s1_wclk_mux", AUDIO_I2S1_DIV_CFG1),
 940         AUDIO_DIV(0, "i2s2_wclk_div", "i2s2_wclk_mux", AUDIO_I2S2_DIV_CFG1),
 941         AUDIO_DIV(0, "i2s3_wclk_div", "i2s3_wclk_mux", AUDIO_I2S3_DIV_CFG1),
 942         AUDIO_DIV(0, "spdif0_wclk_div", "spdif0_wclk_mux", AUDIO_SPDIF0_DIV_CFG1),
 943         AUDIO_DIV(0, "spdif1_wclk_div", "spdif1_wclk_mux", AUDIO_SPDIF1_DIV_CFG1),
 944 };
 945
 946 static struct zx_clk_div audio_div_clk[] = {
 947         DIV_T(0, "tdm_wclk_div", "audio_16m384", AUDIO_TDM_CLK, 8, 4, 0, common_div_table),
 948 };
 949
 950 static struct zx_clk_gate audio_gate_clk[] = {
 951         GATE(AUDIO_I2S0_WCLK, "i2s0_wclk", "i2s0_wclk_div", AUDIO_I2S0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 952         GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9, CLK_SET_RATE_PARENT, 0),
 953         GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9, CLK_SET_RATE_PARENT, 0),
 954         GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9, CLK_SET_RATE_PARENT, 0),
 955         GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
 956         GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
 957         GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
 958         GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
 959         GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 960         GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div", AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 961         GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div", AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
 962         GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17, CLK_SET_RATE_PARENT, 0),
 963         GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0, 0),
 964 };
 965
 966 static struct clk_hw_onecell_data audio_hw_onecell_data = {
 967         .num = AUDIO_NR_CLKS,
 968         .hws = {
 969                 [AUDIO_NR_CLKS - 1] = NULL,
 970         },
 971 };
 972
 973 static int __init audio_clocks_init(struct device_node *np)
 974 {
 975         void __iomem *reg_base;
 976         int i, ret;
 977         const char *name;
 978
 979         reg_base = of_iomap(np, 0);
 980         if (!reg_base) {
 981                 pr_err("%s: Unable to map audio clk base\n", __func__);
 982                 return -ENXIO;
 983         }
 984
 985         for (i = 0; i < ARRAY_SIZE(audio_mux_clk); i++) {
 986                 if (audio_mux_clk[i].id)
 987                         audio_hw_onecell_data.hws[audio_mux_clk[i].id] =
 988                                         &audio_mux_clk[i].mux.hw;
 989
 990                 audio_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 991                 name = audio_mux_clk[i].mux.hw.init->name;
 992                 ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw);
 993                 if (ret)
 994                         pr_warn("audio clk %s init error!\n", name);
 995         }
 996
 997         for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) {
 998                 if (audio_adiv_clk[i].id)
 999                         audio_hw_onecell_data.hws[audio_adiv_clk[i].id] =
1000                                         &audio_adiv_clk[i].hw;
1001
1002                 audio_adiv_clk[i].reg_base += (uintptr_t)reg_base;
1003                 name = audio_adiv_clk[i].hw.init->name;
1004                 ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw);
1005                 if (ret)
1006                         pr_warn("audio clk %s init error!\n", name);
1007         }
1008
1009         for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) {
1010                 if (audio_div_clk[i].id)
1011                         audio_hw_onecell_data.hws[audio_div_clk[i].id] =
1012                                         &audio_div_clk[i].div.hw;
1013
1014                 audio_div_clk[i].div.reg += (uintptr_t)reg_base;
1015                 name = audio_div_clk[i].div.hw.init->name;
1016                 ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw);
1017                 if (ret)
1018                         pr_warn("audio clk %s init error!\n", name);
1019         }
1020
1021         for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) {
1022                 if (audio_gate_clk[i].id)
1023                         audio_hw_onecell_data.hws[audio_gate_clk[i].id] =
1024                                         &audio_gate_clk[i].gate.hw;
1025
1026                 audio_gate_clk[i].gate.reg += (uintptr_t)reg_base;
1027                 name = audio_gate_clk[i].gate.hw.init->name;
1028                 ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw);
1029                 if (ret)
1030                         pr_warn("audio clk %s init error!\n", name);
1031         }
1032
1033         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
1034                                      &audio_hw_onecell_data);
1035         if (ret) {
1036                 pr_err("failed to register audio clk provider: %d\n", ret);
1037                 return ret;
1038         }
1039
1040         return 0;
1041 }
1042
1043 static const struct of_device_id zx_clkc_match_table[] = {
1044         { .compatible = "zte,zx296718-topcrm", .data = &top_clocks_init },
1045         { .compatible = "zte,zx296718-lsp0crm", .data = &lsp0_clocks_init },
1046         { .compatible = "zte,zx296718-lsp1crm", .data = &lsp1_clocks_init },
1047         { .compatible = "zte,zx296718-audiocrm", .data = &audio_clocks_init },
1048         { }
1049 };
1050
1051 static int zx_clkc_probe(struct platform_device *pdev)
1052 {
1053         int (*init_fn)(struct device_node *np);
1054         struct device_node *np = pdev->dev.of_node;
1055
1056         init_fn = of_device_get_match_data(&pdev->dev);
1057         if (!init_fn) {
1058                 dev_err(&pdev->dev, "Error: No device match found\n");
1059                 return -ENODEV;
1060         }
1061
1062         return init_fn(np);
1063 }
1064
1065 static struct platform_driver zx_clk_driver = {
1066         .probe          = zx_clkc_probe,
1067         .driver         = {
1068                 .name   = "zx296718-clkc",
1069                 .of_match_table = zx_clkc_match_table,
1070         },
1071 };
1072
1073 static int __init zx_clk_init(void)
1074 {
1075         return platform_driver_register(&zx_clk_driver);
1076 }
1077 core_initcall(zx_clk_init);