drivers/clk/zte/clk-zx296702.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2014 Linaro Ltd.
   4  * Copyright (C) 2014 ZTE Corporation.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/of_address.h>
   9 #include <dt-bindings/clock/zx296702-clock.h>
  10 #include "clk.h"
  11
  12 static DEFINE_SPINLOCK(reg_lock);
  13
  14 static void __iomem *topcrm_base;
  15 static void __iomem *lsp0crpm_base;
  16 static void __iomem *lsp1crpm_base;
  17
  18 static struct clk *topclk[ZX296702_TOPCLK_END];
  19 static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
  20 static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
  21
  22 static struct clk_onecell_data topclk_data;
  23 static struct clk_onecell_data lsp0clk_data;
  24 static struct clk_onecell_data lsp1clk_data;
  25
  26 #define CLK_MUX                 (topcrm_base + 0x04)
  27 #define CLK_DIV                 (topcrm_base + 0x08)
  28 #define CLK_EN0                 (topcrm_base + 0x0c)
  29 #define CLK_EN1                 (topcrm_base + 0x10)
  30 #define VOU_LOCAL_CLKEN         (topcrm_base + 0x68)
  31 #define VOU_LOCAL_CLKSEL        (topcrm_base + 0x70)
  32 #define VOU_LOCAL_DIV2_SET      (topcrm_base + 0x74)
  33 #define CLK_MUX1                (topcrm_base + 0x8c)
  34
  35 #define CLK_SDMMC1              (lsp0crpm_base + 0x0c)
  36 #define CLK_GPIO                (lsp0crpm_base + 0x2c)
  37 #define CLK_SPDIF0              (lsp0crpm_base + 0x10)
  38 #define SPDIF0_DIV              (lsp0crpm_base + 0x14)
  39 #define CLK_I2S0                (lsp0crpm_base + 0x18)
  40 #define I2S0_DIV                (lsp0crpm_base + 0x1c)
  41 #define CLK_I2S1                (lsp0crpm_base + 0x20)
  42 #define I2S1_DIV                (lsp0crpm_base + 0x24)
  43 #define CLK_I2S2                (lsp0crpm_base + 0x34)
  44 #define I2S2_DIV                (lsp0crpm_base + 0x38)
  45
  46 #define CLK_UART0               (lsp1crpm_base + 0x20)
  47 #define CLK_UART1               (lsp1crpm_base + 0x24)
  48 #define CLK_SDMMC0              (lsp1crpm_base + 0x2c)
  49 #define CLK_SPDIF1              (lsp1crpm_base + 0x30)
  50 #define SPDIF1_DIV              (lsp1crpm_base + 0x34)
  51
  52 static const struct zx_pll_config pll_a9_config[] = {
  53         { .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
  54         { .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa },
  55         { .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 },
  56         { .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 },
  57         { .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa },
  58         { .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 },
  59 };
  60
  61 static const struct clk_div_table main_hlk_div[] = {
  62         { .val = 1, .div = 2, },
  63         { .val = 3, .div = 4, },
  64         { /* sentinel */ }
  65 };
  66
  67 static const struct clk_div_table a9_as1_aclk_divider[] = {
  68         { .val = 0, .div = 1, },
  69         { .val = 1, .div = 2, },
  70         { .val = 3, .div = 4, },
  71         { /* sentinel */ }
  72 };
  73
  74 static const struct clk_div_table sec_wclk_divider[] = {
  75         { .val = 0, .div = 1, },
  76         { .val = 1, .div = 2, },
  77         { .val = 3, .div = 4, },
  78         { .val = 5, .div = 6, },
  79         { .val = 7, .div = 8, },
  80         { /* sentinel */ }
  81 };
  82
  83 static const char * const matrix_aclk_sel[] = {
  84         "pll_mm0_198M",
  85         "osc",
  86         "clk_148M5",
  87         "pll_lsp_104M",
  88 };
  89
  90 static const char * const a9_wclk_sel[] = {
  91         "pll_a9",
  92         "osc",
  93         "clk_500",
  94         "clk_250",
  95 };
  96
  97 static const char * const a9_as1_aclk_sel[] = {
  98         "clk_250",
  99         "osc",
 100         "pll_mm0_396M",
 101         "pll_mac_333M",
 102 };
 103
 104 static const char * const a9_trace_clkin_sel[] = {
 105         "clk_74M25",
 106         "pll_mm1_108M",
 107         "clk_125",
 108         "clk_148M5",
 109 };
 110
 111 static const char * const decppu_aclk_sel[] = {
 112         "clk_250",
 113         "pll_mm0_198M",
 114         "pll_lsp_104M",
 115         "pll_audio_294M912",
 116 };
 117
 118 static const char * const vou_main_wclk_sel[] = {
 119         "clk_148M5",
 120         "clk_74M25",
 121         "clk_27",
 122         "pll_mm1_54M",
 123 };
 124
 125 static const char * const vou_scaler_wclk_sel[] = {
 126         "clk_250",
 127         "pll_mac_333M",
 128         "pll_audio_294M912",
 129         "pll_mm0_198M",
 130 };
 131
 132 static const char * const r2d_wclk_sel[] = {
 133         "pll_audio_294M912",
 134         "pll_mac_333M",
 135         "pll_a9_350M",
 136         "pll_mm0_396M",
 137 };
 138
 139 static const char * const ddr_wclk_sel[] = {
 140         "pll_mac_333M",
 141         "pll_ddr_266M",
 142         "pll_audio_294M912",
 143         "pll_mm0_198M",
 144 };
 145
 146 static const char * const nand_wclk_sel[] = {
 147         "pll_lsp_104M",
 148         "osc",
 149 };
 150
 151 static const char * const lsp_26_wclk_sel[] = {
 152         "pll_lsp_26M",
 153         "osc",
 154 };
 155
 156 static const char * const vl0_sel[] = {
 157         "vou_main_channel_div",
 158         "vou_aux_channel_div",
 159 };
 160
 161 static const char * const hdmi_sel[] = {
 162         "vou_main_channel_wclk",
 163         "vou_aux_channel_wclk",
 164 };
 165
 166 static const char * const sdmmc0_wclk_sel[] = {
 167         "lsp1_104M_wclk",
 168         "lsp1_26M_wclk",
 169 };
 170
 171 static const char * const sdmmc1_wclk_sel[] = {
 172         "lsp0_104M_wclk",
 173         "lsp0_26M_wclk",
 174 };
 175
 176 static const char * const uart_wclk_sel[] = {
 177         "lsp1_104M_wclk",
 178         "lsp1_26M_wclk",
 179 };
 180
 181 static const char * const spdif0_wclk_sel[] = {
 182         "lsp0_104M_wclk",
 183         "lsp0_26M_wclk",
 184 };
 185
 186 static const char * const spdif1_wclk_sel[] = {
 187         "lsp1_104M_wclk",
 188         "lsp1_26M_wclk",
 189 };
 190
 191 static const char * const i2s_wclk_sel[] = {
 192         "lsp0_104M_wclk",
 193         "lsp0_26M_wclk",
 194 };
 195
 196 static inline struct clk *zx_divtbl(const char *name, const char *parent,
 197                                     void __iomem *reg, u8 shift, u8 width,
 198                                     const struct clk_div_table *table)
 199 {
 200         return clk_register_divider_table(NULL, name, parent, 0, reg, shift,
 201                                           width, 0, table, &reg_lock);
 202 }
 203
 204 static inline struct clk *zx_div(const char *name, const char *parent,
 205                                  void __iomem *reg, u8 shift, u8 width)
 206 {
 207         return clk_register_divider(NULL, name, parent, 0,
 208                                     reg, shift, width, 0, &reg_lock);
 209 }
 210
 211 static inline struct clk *zx_mux(const char *name, const char * const *parents,
 212                 int num_parents, void __iomem *reg, u8 shift, u8 width)
 213 {
 214         return clk_register_mux(NULL, name, parents, num_parents,
 215                                 0, reg, shift, width, 0, &reg_lock);
 216 }
 217
 218 static inline struct clk *zx_gate(const char *name, const char *parent,
 219                                   void __iomem *reg, u8 shift)
 220 {
 221         return clk_register_gate(NULL, name, parent, CLK_IGNORE_UNUSED,
 222                                  reg, shift, CLK_SET_RATE_PARENT, &reg_lock);
 223 }
 224
 225 static void __init zx296702_top_clocks_init(struct device_node *np)
 226 {
 227         struct clk **clk = topclk;
 228         int i;
 229
 230         topcrm_base = of_iomap(np, 0);
 231         WARN_ON(!topcrm_base);
 232
 233         clk[ZX296702_OSC] =
 234                 clk_register_fixed_rate(NULL, "osc", NULL, 0, 30000000);
 235         clk[ZX296702_PLL_A9] =
 236                 clk_register_zx_pll("pll_a9", "osc", 0, topcrm_base
 237                                 + 0x01c, pll_a9_config,
 238                                 ARRAY_SIZE(pll_a9_config), &reg_lock);
 239
 240         /* TODO: pll_a9_350M look like changeble follow a9 pll */
 241         clk[ZX296702_PLL_A9_350M] =
 242                 clk_register_fixed_rate(NULL, "pll_a9_350M", "osc", 0,
 243                                 350000000);
 244         clk[ZX296702_PLL_MAC_1000M] =
 245                 clk_register_fixed_rate(NULL, "pll_mac_1000M", "osc", 0,
 246                                 1000000000);
 247         clk[ZX296702_PLL_MAC_333M] =
 248                 clk_register_fixed_rate(NULL, "pll_mac_333M",    "osc", 0,
 249                                 333000000);
 250         clk[ZX296702_PLL_MM0_1188M] =
 251                 clk_register_fixed_rate(NULL, "pll_mm0_1188M", "osc", 0,
 252                                 1188000000);
 253         clk[ZX296702_PLL_MM0_396M] =
 254                 clk_register_fixed_rate(NULL, "pll_mm0_396M",  "osc", 0,
 255                                 396000000);
 256         clk[ZX296702_PLL_MM0_198M] =
 257                 clk_register_fixed_rate(NULL, "pll_mm0_198M",  "osc", 0,
 258                                 198000000);
 259         clk[ZX296702_PLL_MM1_108M] =
 260                 clk_register_fixed_rate(NULL, "pll_mm1_108M",  "osc", 0,
 261                                 108000000);
 262         clk[ZX296702_PLL_MM1_72M] =
 263                 clk_register_fixed_rate(NULL, "pll_mm1_72M",     "osc", 0,
 264                                 72000000);
 265         clk[ZX296702_PLL_MM1_54M] =
 266                 clk_register_fixed_rate(NULL, "pll_mm1_54M",     "osc", 0,
 267                                 54000000);
 268         clk[ZX296702_PLL_LSP_104M] =
 269                 clk_register_fixed_rate(NULL, "pll_lsp_104M",  "osc", 0,
 270                                 104000000);
 271         clk[ZX296702_PLL_LSP_26M] =
 272                 clk_register_fixed_rate(NULL, "pll_lsp_26M",     "osc", 0,
 273                                 26000000);
 274         clk[ZX296702_PLL_DDR_266M] =
 275                 clk_register_fixed_rate(NULL, "pll_ddr_266M",    "osc", 0,
 276                                 266000000);
 277         clk[ZX296702_PLL_AUDIO_294M912] =
 278                 clk_register_fixed_rate(NULL, "pll_audio_294M912", "osc", 0,
 279                                 294912000);
 280
 281         /* bus clock */
 282         clk[ZX296702_MATRIX_ACLK] =
 283                 zx_mux("matrix_aclk", matrix_aclk_sel,
 284                                 ARRAY_SIZE(matrix_aclk_sel), CLK_MUX, 2, 2);
 285         clk[ZX296702_MAIN_HCLK] =
 286                 zx_divtbl("main_hclk", "matrix_aclk", CLK_DIV, 0, 2,
 287                                 main_hlk_div);
 288         clk[ZX296702_MAIN_PCLK] =
 289                 zx_divtbl("main_pclk", "matrix_aclk", CLK_DIV, 2, 2,
 290                                 main_hlk_div);
 291
 292         /* cpu clock */
 293         clk[ZX296702_CLK_500] =
 294                 clk_register_fixed_factor(NULL, "clk_500", "pll_mac_1000M", 0,
 295                                 1, 2);
 296         clk[ZX296702_CLK_250] =
 297                 clk_register_fixed_factor(NULL, "clk_250", "pll_mac_1000M", 0,
 298                                 1, 4);
 299         clk[ZX296702_CLK_125] =
 300                 clk_register_fixed_factor(NULL, "clk_125", "clk_250", 0, 1, 2);
 301         clk[ZX296702_CLK_148M5] =
 302                 clk_register_fixed_factor(NULL, "clk_148M5", "pll_mm0_1188M", 0,
 303                                 1, 8);
 304         clk[ZX296702_CLK_74M25] =
 305                 clk_register_fixed_factor(NULL, "clk_74M25", "pll_mm0_1188M", 0,
 306                                 1, 16);
 307         clk[ZX296702_A9_WCLK] =
 308                 zx_mux("a9_wclk", a9_wclk_sel, ARRAY_SIZE(a9_wclk_sel), CLK_MUX,
 309                                 0, 2);
 310         clk[ZX296702_A9_AS1_ACLK_MUX] =
 311                 zx_mux("a9_as1_aclk_mux", a9_as1_aclk_sel,
 312                                 ARRAY_SIZE(a9_as1_aclk_sel), CLK_MUX, 4, 2);
 313         clk[ZX296702_A9_TRACE_CLKIN_MUX] =
 314                 zx_mux("a9_trace_clkin_mux", a9_trace_clkin_sel,
 315                                 ARRAY_SIZE(a9_trace_clkin_sel), CLK_MUX1, 0, 2);
 316         clk[ZX296702_A9_AS1_ACLK_DIV] =
 317                 zx_divtbl("a9_as1_aclk_div", "a9_as1_aclk_mux", CLK_DIV, 4, 2,
 318                                 a9_as1_aclk_divider);
 319
 320         /* multi-media clock */
 321         clk[ZX296702_CLK_2] =
 322                 clk_register_fixed_factor(NULL, "clk_2", "pll_mm1_72M", 0,
 323                                 1, 36);
 324         clk[ZX296702_CLK_27] =
 325                 clk_register_fixed_factor(NULL, "clk_27", "pll_mm1_54M", 0,
 326                                 1, 2);
 327         clk[ZX296702_DECPPU_ACLK_MUX] =
 328                 zx_mux("decppu_aclk_mux", decppu_aclk_sel,
 329                                 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 6, 2);
 330         clk[ZX296702_PPU_ACLK_MUX] =
 331                 zx_mux("ppu_aclk_mux", decppu_aclk_sel,
 332                                 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 8, 2);
 333         clk[ZX296702_MALI400_ACLK_MUX] =
 334                 zx_mux("mali400_aclk_mux", decppu_aclk_sel,
 335                                 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 12, 2);
 336         clk[ZX296702_VOU_ACLK_MUX] =
 337                 zx_mux("vou_aclk_mux", decppu_aclk_sel,
 338                                 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 10, 2);
 339         clk[ZX296702_VOU_MAIN_WCLK_MUX] =
 340                 zx_mux("vou_main_wclk_mux", vou_main_wclk_sel,
 341                                 ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 14, 2);
 342         clk[ZX296702_VOU_AUX_WCLK_MUX] =
 343                 zx_mux("vou_aux_wclk_mux", vou_main_wclk_sel,
 344                                 ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 16, 2);
 345         clk[ZX296702_VOU_SCALER_WCLK_MUX] =
 346                 zx_mux("vou_scaler_wclk_mux", vou_scaler_wclk_sel,
 347                                 ARRAY_SIZE(vou_scaler_wclk_sel), CLK_MUX,
 348                                 18, 2);
 349         clk[ZX296702_R2D_ACLK_MUX] =
 350                 zx_mux("r2d_aclk_mux", decppu_aclk_sel,
 351                                 ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 20, 2);
 352         clk[ZX296702_R2D_WCLK_MUX] =
 353                 zx_mux("r2d_wclk_mux", r2d_wclk_sel,
 354                                 ARRAY_SIZE(r2d_wclk_sel), CLK_MUX, 22, 2);
 355
 356         /* other clock */
 357         clk[ZX296702_CLK_50] =
 358                 clk_register_fixed_factor(NULL, "clk_50", "pll_mac_1000M",
 359                                 0, 1, 20);
 360         clk[ZX296702_CLK_25] =
 361                 clk_register_fixed_factor(NULL, "clk_25", "pll_mac_1000M",
 362                                 0, 1, 40);
 363         clk[ZX296702_CLK_12] =
 364                 clk_register_fixed_factor(NULL, "clk_12", "pll_mm1_72M",
 365                                 0, 1, 6);
 366         clk[ZX296702_CLK_16M384] =
 367                 clk_register_fixed_factor(NULL, "clk_16M384",
 368                                 "pll_audio_294M912", 0, 1, 18);
 369         clk[ZX296702_CLK_32K768] =
 370                 clk_register_fixed_factor(NULL, "clk_32K768", "clk_16M384",
 371                                 0, 1, 500);
 372         clk[ZX296702_SEC_WCLK_DIV] =
 373                 zx_divtbl("sec_wclk_div", "pll_lsp_104M", CLK_DIV, 6, 3,
 374                                 sec_wclk_divider);
 375         clk[ZX296702_DDR_WCLK_MUX] =
 376                 zx_mux("ddr_wclk_mux", ddr_wclk_sel,
 377                                 ARRAY_SIZE(ddr_wclk_sel), CLK_MUX, 24, 2);
 378         clk[ZX296702_NAND_WCLK_MUX] =
 379                 zx_mux("nand_wclk_mux", nand_wclk_sel,
 380                                 ARRAY_SIZE(nand_wclk_sel), CLK_MUX, 24, 2);
 381         clk[ZX296702_LSP_26_WCLK_MUX] =
 382                 zx_mux("lsp_26_wclk_mux", lsp_26_wclk_sel,
 383                                 ARRAY_SIZE(lsp_26_wclk_sel), CLK_MUX, 27, 1);
 384
 385         /* gates */
 386         clk[ZX296702_A9_AS0_ACLK] =
 387                 zx_gate("a9_as0_aclk",  "matrix_aclk",          CLK_EN0, 0);
 388         clk[ZX296702_A9_AS1_ACLK] =
 389                 zx_gate("a9_as1_aclk",  "a9_as1_aclk_div",      CLK_EN0, 1);
 390         clk[ZX296702_A9_TRACE_CLKIN] =
 391                 zx_gate("a9_trace_clkin", "a9_trace_clkin_mux", CLK_EN0, 2);
 392         clk[ZX296702_DECPPU_AXI_M_ACLK] =
 393                 zx_gate("decppu_axi_m_aclk", "decppu_aclk_mux", CLK_EN0, 3);
 394         clk[ZX296702_DECPPU_AHB_S_HCLK] =
 395                 zx_gate("decppu_ahb_s_hclk",    "main_hclk",    CLK_EN0, 4);
 396         clk[ZX296702_PPU_AXI_M_ACLK] =
 397                 zx_gate("ppu_axi_m_aclk",       "ppu_aclk_mux", CLK_EN0, 5);
 398         clk[ZX296702_PPU_AHB_S_HCLK] =
 399                 zx_gate("ppu_ahb_s_hclk",       "main_hclk",    CLK_EN0, 6);
 400         clk[ZX296702_VOU_AXI_M_ACLK] =
 401                 zx_gate("vou_axi_m_aclk",       "vou_aclk_mux", CLK_EN0, 7);
 402         clk[ZX296702_VOU_APB_PCLK] =
 403                 zx_gate("vou_apb_pclk", "main_pclk",            CLK_EN0, 8);
 404         clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] =
 405                 zx_gate("vou_main_channel_wclk", "vou_main_wclk_mux",
 406                                 CLK_EN0, 9);
 407         clk[ZX296702_VOU_AUX_CHANNEL_WCLK] =
 408                 zx_gate("vou_aux_channel_wclk", "vou_aux_wclk_mux",
 409                                 CLK_EN0, 10);
 410         clk[ZX296702_VOU_HDMI_OSCLK_CEC] =
 411                 zx_gate("vou_hdmi_osclk_cec", "clk_2",          CLK_EN0, 11);
 412         clk[ZX296702_VOU_SCALER_WCLK] =
 413                 zx_gate("vou_scaler_wclk", "vou_scaler_wclk_mux", CLK_EN0, 12);
 414         clk[ZX296702_MALI400_AXI_M_ACLK] =
 415                 zx_gate("mali400_axi_m_aclk", "mali400_aclk_mux", CLK_EN0, 13);
 416         clk[ZX296702_MALI400_APB_PCLK] =
 417                 zx_gate("mali400_apb_pclk",     "main_pclk",    CLK_EN0, 14);
 418         clk[ZX296702_R2D_WCLK] =
 419                 zx_gate("r2d_wclk",             "r2d_wclk_mux", CLK_EN0, 15);
 420         clk[ZX296702_R2D_AXI_M_ACLK] =
 421                 zx_gate("r2d_axi_m_aclk",       "r2d_aclk_mux", CLK_EN0, 16);
 422         clk[ZX296702_R2D_AHB_HCLK] =
 423                 zx_gate("r2d_ahb_hclk",         "main_hclk",    CLK_EN0, 17);
 424         clk[ZX296702_DDR3_AXI_S0_ACLK] =
 425                 zx_gate("ddr3_axi_s0_aclk",     "matrix_aclk",  CLK_EN0, 18);
 426         clk[ZX296702_DDR3_APB_PCLK] =
 427                 zx_gate("ddr3_apb_pclk",        "main_pclk",    CLK_EN0, 19);
 428         clk[ZX296702_DDR3_WCLK] =
 429                 zx_gate("ddr3_wclk",            "ddr_wclk_mux", CLK_EN0, 20);
 430         clk[ZX296702_USB20_0_AHB_HCLK] =
 431                 zx_gate("usb20_0_ahb_hclk",     "main_hclk",    CLK_EN0, 21);
 432         clk[ZX296702_USB20_0_EXTREFCLK] =
 433                 zx_gate("usb20_0_extrefclk",    "clk_12",       CLK_EN0, 22);
 434         clk[ZX296702_USB20_1_AHB_HCLK] =
 435                 zx_gate("usb20_1_ahb_hclk",     "main_hclk",    CLK_EN0, 23);
 436         clk[ZX296702_USB20_1_EXTREFCLK] =
 437                 zx_gate("usb20_1_extrefclk",    "clk_12",       CLK_EN0, 24);
 438         clk[ZX296702_USB20_2_AHB_HCLK] =
 439                 zx_gate("usb20_2_ahb_hclk",     "main_hclk",    CLK_EN0, 25);
 440         clk[ZX296702_USB20_2_EXTREFCLK] =
 441                 zx_gate("usb20_2_extrefclk",    "clk_12",       CLK_EN0, 26);
 442         clk[ZX296702_GMAC_AXI_M_ACLK] =
 443                 zx_gate("gmac_axi_m_aclk",      "matrix_aclk",  CLK_EN0, 27);
 444         clk[ZX296702_GMAC_APB_PCLK] =
 445                 zx_gate("gmac_apb_pclk",        "main_pclk",    CLK_EN0, 28);
 446         clk[ZX296702_GMAC_125_CLKIN] =
 447                 zx_gate("gmac_125_clkin",       "clk_125",      CLK_EN0, 29);
 448         clk[ZX296702_GMAC_RMII_CLKIN] =
 449                 zx_gate("gmac_rmii_clkin",      "clk_50",       CLK_EN0, 30);
 450         clk[ZX296702_GMAC_25M_CLK] =
 451                 zx_gate("gmac_25M_clk",         "clk_25",       CLK_EN0, 31);
 452         clk[ZX296702_NANDFLASH_AHB_HCLK] =
 453                 zx_gate("nandflash_ahb_hclk", "main_hclk",      CLK_EN1, 0);
 454         clk[ZX296702_NANDFLASH_WCLK] =
 455                 zx_gate("nandflash_wclk",     "nand_wclk_mux",  CLK_EN1, 1);
 456         clk[ZX296702_LSP0_APB_PCLK] =
 457                 zx_gate("lsp0_apb_pclk",        "main_pclk",    CLK_EN1, 2);
 458         clk[ZX296702_LSP0_AHB_HCLK] =
 459                 zx_gate("lsp0_ahb_hclk",        "main_hclk",    CLK_EN1, 3);
 460         clk[ZX296702_LSP0_26M_WCLK] =
 461                 zx_gate("lsp0_26M_wclk",   "lsp_26_wclk_mux",   CLK_EN1, 4);
 462         clk[ZX296702_LSP0_104M_WCLK] =
 463                 zx_gate("lsp0_104M_wclk",       "pll_lsp_104M", CLK_EN1, 5);
 464         clk[ZX296702_LSP0_16M384_WCLK] =
 465                 zx_gate("lsp0_16M384_wclk",     "clk_16M384",   CLK_EN1, 6);
 466         clk[ZX296702_LSP1_APB_PCLK] =
 467                 zx_gate("lsp1_apb_pclk",        "main_pclk",    CLK_EN1, 7);
 468         /* FIXME: wclk enable bit is bit8. We hack it as reserved 31 for
 469          * UART does not work after parent clk is disabled/enabled */
 470         clk[ZX296702_LSP1_26M_WCLK] =
 471                 zx_gate("lsp1_26M_wclk",     "lsp_26_wclk_mux", CLK_EN1, 31);
 472         clk[ZX296702_LSP1_104M_WCLK] =
 473                 zx_gate("lsp1_104M_wclk",    "pll_lsp_104M",    CLK_EN1, 9);
 474         clk[ZX296702_LSP1_32K_CLK] =
 475                 zx_gate("lsp1_32K_clk", "clk_32K768",           CLK_EN1, 10);
 476         clk[ZX296702_AON_HCLK] =
 477                 zx_gate("aon_hclk",             "main_hclk",    CLK_EN1, 11);
 478         clk[ZX296702_SYS_CTRL_PCLK] =
 479                 zx_gate("sys_ctrl_pclk",        "main_pclk",    CLK_EN1, 12);
 480         clk[ZX296702_DMA_PCLK] =
 481                 zx_gate("dma_pclk",             "main_pclk",    CLK_EN1, 13);
 482         clk[ZX296702_DMA_ACLK] =
 483                 zx_gate("dma_aclk",             "matrix_aclk",  CLK_EN1, 14);
 484         clk[ZX296702_SEC_HCLK] =
 485                 zx_gate("sec_hclk",             "main_hclk",    CLK_EN1, 15);
 486         clk[ZX296702_AES_WCLK] =
 487                 zx_gate("aes_wclk",             "sec_wclk_div", CLK_EN1, 16);
 488         clk[ZX296702_DES_WCLK] =
 489                 zx_gate("des_wclk",             "sec_wclk_div", CLK_EN1, 17);
 490         clk[ZX296702_IRAM_ACLK] =
 491                 zx_gate("iram_aclk",            "matrix_aclk",  CLK_EN1, 18);
 492         clk[ZX296702_IROM_ACLK] =
 493                 zx_gate("irom_aclk",            "matrix_aclk",  CLK_EN1, 19);
 494         clk[ZX296702_BOOT_CTRL_HCLK] =
 495                 zx_gate("boot_ctrl_hclk",       "main_hclk",    CLK_EN1, 20);
 496         clk[ZX296702_EFUSE_CLK_30] =
 497                 zx_gate("efuse_clk_30", "osc",                  CLK_EN1, 21);
 498
 499         /* TODO: add VOU Local clocks */
 500         clk[ZX296702_VOU_MAIN_CHANNEL_DIV] =
 501                 zx_div("vou_main_channel_div", "vou_main_channel_wclk",
 502                                 VOU_LOCAL_DIV2_SET, 1, 1);
 503         clk[ZX296702_VOU_AUX_CHANNEL_DIV] =
 504                 zx_div("vou_aux_channel_div", "vou_aux_channel_wclk",
 505                                 VOU_LOCAL_DIV2_SET, 0, 1);
 506         clk[ZX296702_VOU_TV_ENC_HD_DIV] =
 507                 zx_div("vou_tv_enc_hd_div", "vou_tv_enc_hd_mux",
 508                                 VOU_LOCAL_DIV2_SET, 3, 1);
 509         clk[ZX296702_VOU_TV_ENC_SD_DIV] =
 510                 zx_div("vou_tv_enc_sd_div", "vou_tv_enc_sd_mux",
 511                                 VOU_LOCAL_DIV2_SET, 2, 1);
 512         clk[ZX296702_VL0_MUX] =
 513                 zx_mux("vl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
 514                                 VOU_LOCAL_CLKSEL, 8, 1);
 515         clk[ZX296702_VL1_MUX] =
 516                 zx_mux("vl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
 517                                 VOU_LOCAL_CLKSEL, 9, 1);
 518         clk[ZX296702_VL2_MUX] =
 519                 zx_mux("vl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
 520                                 VOU_LOCAL_CLKSEL, 10, 1);
 521         clk[ZX296702_GL0_MUX] =
 522                 zx_mux("gl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
 523                                 VOU_LOCAL_CLKSEL, 5, 1);
 524         clk[ZX296702_GL1_MUX] =
 525                 zx_mux("gl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
 526                                 VOU_LOCAL_CLKSEL, 6, 1);
 527         clk[ZX296702_GL2_MUX] =
 528                 zx_mux("gl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
 529                                 VOU_LOCAL_CLKSEL, 7, 1);
 530         clk[ZX296702_WB_MUX] =
 531                 zx_mux("wb_mux",  vl0_sel, ARRAY_SIZE(vl0_sel),
 532                                 VOU_LOCAL_CLKSEL, 11, 1);
 533         clk[ZX296702_HDMI_MUX] =
 534                 zx_mux("hdmi_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
 535                                 VOU_LOCAL_CLKSEL, 4, 1);
 536         clk[ZX296702_VOU_TV_ENC_HD_MUX] =
 537                 zx_mux("vou_tv_enc_hd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
 538                                 VOU_LOCAL_CLKSEL, 3, 1);
 539         clk[ZX296702_VOU_TV_ENC_SD_MUX] =
 540                 zx_mux("vou_tv_enc_sd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
 541                                 VOU_LOCAL_CLKSEL, 2, 1);
 542         clk[ZX296702_VL0_CLK] =
 543                 zx_gate("vl0_clk", "vl0_mux", VOU_LOCAL_CLKEN, 8);
 544         clk[ZX296702_VL1_CLK] =
 545                 zx_gate("vl1_clk", "vl1_mux", VOU_LOCAL_CLKEN, 9);
 546         clk[ZX296702_VL2_CLK] =
 547                 zx_gate("vl2_clk", "vl2_mux", VOU_LOCAL_CLKEN, 10);
 548         clk[ZX296702_GL0_CLK] =
 549                 zx_gate("gl0_clk", "gl0_mux", VOU_LOCAL_CLKEN, 5);
 550         clk[ZX296702_GL1_CLK] =
 551                 zx_gate("gl1_clk", "gl1_mux", VOU_LOCAL_CLKEN, 6);
 552         clk[ZX296702_GL2_CLK] =
 553                 zx_gate("gl2_clk", "gl2_mux", VOU_LOCAL_CLKEN, 7);
 554         clk[ZX296702_WB_CLK] =
 555                 zx_gate("wb_clk", "wb_mux", VOU_LOCAL_CLKEN, 11);
 556         clk[ZX296702_CL_CLK] =
 557                 zx_gate("cl_clk", "vou_main_channel_div", VOU_LOCAL_CLKEN, 12);
 558         clk[ZX296702_MAIN_MIX_CLK] =
 559                 zx_gate("main_mix_clk", "vou_main_channel_div",
 560                                 VOU_LOCAL_CLKEN, 4);
 561         clk[ZX296702_AUX_MIX_CLK] =
 562                 zx_gate("aux_mix_clk", "vou_aux_channel_div",
 563                                 VOU_LOCAL_CLKEN, 3);
 564         clk[ZX296702_HDMI_CLK] =
 565                 zx_gate("hdmi_clk", "hdmi_mux", VOU_LOCAL_CLKEN, 2);
 566         clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] =
 567                 zx_gate("vou_tv_enc_hd_dac_clk", "vou_tv_enc_hd_div",
 568                                 VOU_LOCAL_CLKEN, 1);
 569         clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] =
 570                 zx_gate("vou_tv_enc_sd_dac_clk", "vou_tv_enc_sd_div",
 571                                 VOU_LOCAL_CLKEN, 0);
 572
 573         /* CA9 PERIPHCLK = a9_wclk / 2 */
 574         clk[ZX296702_A9_PERIPHCLK] =
 575                 clk_register_fixed_factor(NULL, "a9_periphclk", "a9_wclk",
 576                                 0, 1, 2);
 577
 578         for (i = 0; i < ARRAY_SIZE(topclk); i++) {
 579                 if (IS_ERR(clk[i])) {
 580                         pr_err("zx296702 clk %d: register failed with %ld\n",
 581                                 i, PTR_ERR(clk[i]));
 582                         return;
 583                 }
 584         }
 585
 586         topclk_data.clks = topclk;
 587         topclk_data.clk_num = ARRAY_SIZE(topclk);
 588         of_clk_add_provider(np, of_clk_src_onecell_get, &topclk_data);
 589 }
 590 CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk",
 591                 zx296702_top_clocks_init);
 592
 593 static void __init zx296702_lsp0_clocks_init(struct device_node *np)
 594 {
 595         struct clk **clk = lsp0clk;
 596         int i;
 597
 598         lsp0crpm_base = of_iomap(np, 0);
 599         WARN_ON(!lsp0crpm_base);
 600
 601         /* SDMMC1 */
 602         clk[ZX296702_SDMMC1_WCLK_MUX] =
 603                 zx_mux("sdmmc1_wclk_mux", sdmmc1_wclk_sel,
 604                                 ARRAY_SIZE(sdmmc1_wclk_sel), CLK_SDMMC1, 4, 1);
 605         clk[ZX296702_SDMMC1_WCLK_DIV] =
 606                 zx_div("sdmmc1_wclk_div", "sdmmc1_wclk_mux", CLK_SDMMC1, 12, 4);
 607         clk[ZX296702_SDMMC1_WCLK] =
 608                 zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1);
 609         clk[ZX296702_SDMMC1_PCLK] =
 610                 zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0);
 611
 612         clk[ZX296702_GPIO_CLK] =
 613                 zx_gate("gpio_clk", "lsp0_apb_pclk", CLK_GPIO, 0);
 614
 615         /* SPDIF */
 616         clk[ZX296702_SPDIF0_WCLK_MUX] =
 617                 zx_mux("spdif0_wclk_mux", spdif0_wclk_sel,
 618                                 ARRAY_SIZE(spdif0_wclk_sel), CLK_SPDIF0, 4, 1);
 619         clk[ZX296702_SPDIF0_WCLK] =
 620                 zx_gate("spdif0_wclk", "spdif0_wclk_mux", CLK_SPDIF0, 1);
 621         clk[ZX296702_SPDIF0_PCLK] =
 622                 zx_gate("spdif0_pclk", "lsp0_apb_pclk", CLK_SPDIF0, 0);
 623
 624         clk[ZX296702_SPDIF0_DIV] =
 625                 clk_register_zx_audio("spdif0_div", "spdif0_wclk", 0,
 626                                 SPDIF0_DIV);
 627
 628         /* I2S */
 629         clk[ZX296702_I2S0_WCLK_MUX] =
 630                 zx_mux("i2s0_wclk_mux", i2s_wclk_sel,
 631                                 ARRAY_SIZE(i2s_wclk_sel), CLK_I2S0, 4, 1);
 632         clk[ZX296702_I2S0_WCLK] =
 633                 zx_gate("i2s0_wclk", "i2s0_wclk_mux", CLK_I2S0, 1);
 634         clk[ZX296702_I2S0_PCLK] =
 635                 zx_gate("i2s0_pclk", "lsp0_apb_pclk", CLK_I2S0, 0);
 636
 637         clk[ZX296702_I2S0_DIV] =
 638                 clk_register_zx_audio("i2s0_div", "i2s0_wclk", 0, I2S0_DIV);
 639
 640         clk[ZX296702_I2S1_WCLK_MUX] =
 641                 zx_mux("i2s1_wclk_mux", i2s_wclk_sel,
 642                                 ARRAY_SIZE(i2s_wclk_sel), CLK_I2S1, 4, 1);
 643         clk[ZX296702_I2S1_WCLK] =
 644                 zx_gate("i2s1_wclk", "i2s1_wclk_mux", CLK_I2S1, 1);
 645         clk[ZX296702_I2S1_PCLK] =
 646                 zx_gate("i2s1_pclk", "lsp0_apb_pclk", CLK_I2S1, 0);
 647
 648         clk[ZX296702_I2S1_DIV] =
 649                 clk_register_zx_audio("i2s1_div", "i2s1_wclk", 0, I2S1_DIV);
 650
 651         clk[ZX296702_I2S2_WCLK_MUX] =
 652                 zx_mux("i2s2_wclk_mux", i2s_wclk_sel,
 653                                 ARRAY_SIZE(i2s_wclk_sel), CLK_I2S2, 4, 1);
 654         clk[ZX296702_I2S2_WCLK] =
 655                 zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1);
 656         clk[ZX296702_I2S2_PCLK] =
 657                 zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0);
 658
 659         clk[ZX296702_I2S2_DIV] =
 660                 clk_register_zx_audio("i2s2_div", "i2s2_wclk", 0, I2S2_DIV);
 661
 662         for (i = 0; i < ARRAY_SIZE(lsp0clk); i++) {
 663                 if (IS_ERR(clk[i])) {
 664                         pr_err("zx296702 clk %d: register failed with %ld\n",
 665                                 i, PTR_ERR(clk[i]));
 666                         return;
 667                 }
 668         }
 669
 670         lsp0clk_data.clks = lsp0clk;
 671         lsp0clk_data.clk_num = ARRAY_SIZE(lsp0clk);
 672         of_clk_add_provider(np, of_clk_src_onecell_get, &lsp0clk_data);
 673 }
 674 CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk",
 675                 zx296702_lsp0_clocks_init);
 676
 677 static void __init zx296702_lsp1_clocks_init(struct device_node *np)
 678 {
 679         struct clk **clk = lsp1clk;
 680         int i;
 681
 682         lsp1crpm_base = of_iomap(np, 0);
 683         WARN_ON(!lsp1crpm_base);
 684
 685         /* UART0 */
 686         clk[ZX296702_UART0_WCLK_MUX] =
 687                 zx_mux("uart0_wclk_mux", uart_wclk_sel,
 688                                 ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1);
 689         /* FIXME: uart wclk enable bit is bit1 in. We hack it as reserved 31 for
 690          * UART does not work after parent clk is disabled/enabled */
 691         clk[ZX296702_UART0_WCLK] =
 692                 zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31);
 693         clk[ZX296702_UART0_PCLK] =
 694                 zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0);
 695
 696         /* UART1 */
 697         clk[ZX296702_UART1_WCLK_MUX] =
 698                 zx_mux("uart1_wclk_mux", uart_wclk_sel,
 699                                 ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1);
 700         clk[ZX296702_UART1_WCLK] =
 701                 zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1);
 702         clk[ZX296702_UART1_PCLK] =
 703                 zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0);
 704
 705         /* SDMMC0 */
 706         clk[ZX296702_SDMMC0_WCLK_MUX] =
 707                 zx_mux("sdmmc0_wclk_mux", sdmmc0_wclk_sel,
 708                                 ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1);
 709         clk[ZX296702_SDMMC0_WCLK_DIV] =
 710                 zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4);
 711         clk[ZX296702_SDMMC0_WCLK] =
 712                 zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1);
 713         clk[ZX296702_SDMMC0_PCLK] =
 714                 zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0);
 715
 716         clk[ZX296702_SPDIF1_WCLK_MUX] =
 717                 zx_mux("spdif1_wclk_mux", spdif1_wclk_sel,
 718                                 ARRAY_SIZE(spdif1_wclk_sel), CLK_SPDIF1, 4, 1);
 719         clk[ZX296702_SPDIF1_WCLK] =
 720                 zx_gate("spdif1_wclk", "spdif1_wclk_mux", CLK_SPDIF1, 1);
 721         clk[ZX296702_SPDIF1_PCLK] =
 722                 zx_gate("spdif1_pclk", "lsp1_apb_pclk", CLK_SPDIF1, 0);
 723
 724         clk[ZX296702_SPDIF1_DIV] =
 725                 clk_register_zx_audio("spdif1_div", "spdif1_wclk", 0,
 726                                 SPDIF1_DIV);
 727
 728         for (i = 0; i < ARRAY_SIZE(lsp1clk); i++) {
 729                 if (IS_ERR(clk[i])) {
 730                         pr_err("zx296702 clk %d: register failed with %ld\n",
 731                                 i, PTR_ERR(clk[i]));
 732                         return;
 733                 }
 734         }
 735
 736         lsp1clk_data.clks = lsp1clk;
 737         lsp1clk_data.clk_num = ARRAY_SIZE(lsp1clk);
 738         of_clk_add_provider(np, of_clk_src_onecell_get, &lsp1clk_data);
 739 }
 740 CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk",
 741                 zx296702_lsp1_clocks_init);