drivers/clk/tegra/clk-pll.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/slab.h>
   7 #include <linux/io.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12
  13 #include "clk.h"
  14
  15 #define PLL_BASE_BYPASS BIT(31)
  16 #define PLL_BASE_ENABLE BIT(30)
  17 #define PLL_BASE_REF_ENABLE BIT(29)
  18 #define PLL_BASE_OVERRIDE BIT(28)
  19
  20 #define PLL_BASE_DIVP_SHIFT 20
  21 #define PLL_BASE_DIVP_WIDTH 3
  22 #define PLL_BASE_DIVN_SHIFT 8
  23 #define PLL_BASE_DIVN_WIDTH 10
  24 #define PLL_BASE_DIVM_SHIFT 0
  25 #define PLL_BASE_DIVM_WIDTH 5
  26 #define PLLU_POST_DIVP_MASK 0x1
  27
  28 #define PLL_MISC_DCCON_SHIFT 20
  29 #define PLL_MISC_CPCON_SHIFT 8
  30 #define PLL_MISC_CPCON_WIDTH 4
  31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  32 #define PLL_MISC_LFCON_SHIFT 4
  33 #define PLL_MISC_LFCON_WIDTH 4
  34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  35 #define PLL_MISC_VCOCON_SHIFT 0
  36 #define PLL_MISC_VCOCON_WIDTH 4
  37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  38
  39 #define OUT_OF_TABLE_CPCON 8
  40
  41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  42 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  43 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  44
  45 #define PLL_POST_LOCK_DELAY 50
  46
  47 #define PLLDU_LFCON_SET_DIVN 600
  48
  49 #define PLLE_BASE_DIVCML_SHIFT 24
  50 #define PLLE_BASE_DIVCML_MASK 0xf
  51 #define PLLE_BASE_DIVP_SHIFT 16
  52 #define PLLE_BASE_DIVP_WIDTH 6
  53 #define PLLE_BASE_DIVN_SHIFT 8
  54 #define PLLE_BASE_DIVN_WIDTH 8
  55 #define PLLE_BASE_DIVM_SHIFT 0
  56 #define PLLE_BASE_DIVM_WIDTH 8
  57 #define PLLE_BASE_ENABLE BIT(31)
  58
  59 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  60 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  61 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  62 #define PLLE_MISC_READY BIT(15)
  63 #define PLLE_MISC_SETUP_EX_SHIFT 2
  64 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  65 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  66                               PLLE_MISC_SETUP_EX_MASK)
  67 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  68
  69 #define PLLE_SS_CTRL 0x68
  70 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  71 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  72 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  73 #define PLLE_SS_CNTL_CENTER BIT(14)
  74 #define PLLE_SS_CNTL_INVERT BIT(15)
  75 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  76                                 PLLE_SS_CNTL_SSC_BYP)
  77 #define PLLE_SS_MAX_MASK 0x1ff
  78 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
  79 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
  80 #define PLLE_SS_INC_MASK (0xff << 16)
  81 #define PLLE_SS_INC_VAL (0x1 << 16)
  82 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  83 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
  84 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
  85 #define PLLE_SS_COEFFICIENTS_MASK \
  86         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  87 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
  88         (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
  89          PLLE_SS_INCINTRV_VAL_TEGRA114)
  90 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
  91         (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
  92          PLLE_SS_INCINTRV_VAL_TEGRA210)
  93
  94 #define PLLE_AUX_PLLP_SEL       BIT(2)
  95 #define PLLE_AUX_USE_LOCKDET    BIT(3)
  96 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
  97 #define PLLE_AUX_SS_SWCTL       BIT(6)
  98 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
  99 #define PLLE_AUX_SEQ_START_STATE BIT(25)
 100 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 101 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
 102
 103 #define XUSBIO_PLL_CFG0         0x51c
 104 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 105 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 106 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 107 #define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 108 #define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 109
 110 #define SATA_PLL_CFG0           0x490
 111 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 112 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 113 #define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 114 #define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 115
 116 #define PLLE_MISC_PLLE_PTS      BIT(8)
 117 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 118 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 119 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 120 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 121 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 122 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 123
 124 #define PLLCX_MISC_STROBE       BIT(31)
 125 #define PLLCX_MISC_RESET        BIT(30)
 126 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 127 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 128 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 129 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 130 #define PLLCX_MISC_ALPHA_SHIFT 18
 131 #define PLLCX_MISC_DIV_LOW_RANGE \
 132                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 133                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 134 #define PLLCX_MISC_DIV_HIGH_RANGE \
 135                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 136                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 137 #define PLLCX_MISC_COEF_LOW_RANGE \
 138                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 139 #define PLLCX_MISC_KA_SHIFT 2
 140 #define PLLCX_MISC_KB_SHIFT 9
 141 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 142                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 143                             PLLCX_MISC_DIV_LOW_RANGE | \
 144                             PLLCX_MISC_RESET)
 145 #define PLLCX_MISC1_DEFAULT 0x000d2308
 146 #define PLLCX_MISC2_DEFAULT 0x30211200
 147 #define PLLCX_MISC3_DEFAULT 0x200
 148
 149 #define PMC_SATA_PWRGT 0x1ac
 150 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 151 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 152
 153 #define PLLSS_MISC_KCP          0
 154 #define PLLSS_MISC_KVCO         0
 155 #define PLLSS_MISC_SETUP        0
 156 #define PLLSS_EN_SDM            0
 157 #define PLLSS_EN_SSC            0
 158 #define PLLSS_EN_DITHER2        0
 159 #define PLLSS_EN_DITHER         1
 160 #define PLLSS_SDM_RESET         0
 161 #define PLLSS_CLAMP             0
 162 #define PLLSS_SDM_SSC_MAX       0
 163 #define PLLSS_SDM_SSC_MIN       0
 164 #define PLLSS_SDM_SSC_STEP      0
 165 #define PLLSS_SDM_DIN           0
 166 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 167                             (PLLSS_MISC_KVCO << 24) | \
 168                             PLLSS_MISC_SETUP)
 169 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 170                            (PLLSS_EN_SSC << 30) | \
 171                            (PLLSS_EN_DITHER2 << 29) | \
 172                            (PLLSS_EN_DITHER << 28) | \
 173                            (PLLSS_SDM_RESET) << 27 | \
 174                            (PLLSS_CLAMP << 22))
 175 #define PLLSS_CTRL1_DEFAULT \
 176                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 177 #define PLLSS_CTRL2_DEFAULT \
 178                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 179 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 180 #define PLLSS_REF_SRC_SEL_SHIFT 25
 181 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 182
 183 #define UTMIP_PLL_CFG1 0x484
 184 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 185 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
 186 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 187 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 188 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 189 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 190 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 191
 192 #define UTMIP_PLL_CFG2 0x488
 193 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
 194 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 195 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
 197 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 198 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
 199 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 200 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
 201 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
 202 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
 203 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
 204
 205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
 206 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
 207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
 208 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 209 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
 210 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
 211 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 212 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 213 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
 214
 215 #define PLLU_HW_PWRDN_CFG0 0x530
 216 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
 217 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 218 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 219 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
 220 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 221 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
 222
 223 #define XUSB_PLL_CFG0 0x534
 224 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
 225 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
 226
 227 #define PLLU_BASE_CLKENABLE_USB BIT(21)
 228 #define PLLU_BASE_OVERRIDE BIT(24)
 229
 230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
 235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
 236
 237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
 242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
 243
 244 #define mask(w) ((1 << (w)) - 1)
 245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 248                       mask(p->params->div_nmp->divp_width))
 249 #define sdm_din_mask(p) p->params->sdm_din_mask
 250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
 251
 252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 255
 256 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 257 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 258 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 259
 260 #define divm_max(p) (divm_mask(p))
 261 #define divn_max(p) (divn_mask(p))
 262 #define divp_max(p) (1 << (divp_mask(p)))
 263
 264 #define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 265 #define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
 266
 267 static struct div_nmp default_nmp = {
 268         .divn_shift = PLL_BASE_DIVN_SHIFT,
 269         .divn_width = PLL_BASE_DIVN_WIDTH,
 270         .divm_shift = PLL_BASE_DIVM_SHIFT,
 271         .divm_width = PLL_BASE_DIVM_WIDTH,
 272         .divp_shift = PLL_BASE_DIVP_SHIFT,
 273         .divp_width = PLL_BASE_DIVP_WIDTH,
 274 };
 275
 276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 277 {
 278         u32 val;
 279
 280         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 281                 return;
 282
 283         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 284                 return;
 285
 286         val = pll_readl_misc(pll);
 287         val |= BIT(pll->params->lock_enable_bit_idx);
 288         pll_writel_misc(val, pll);
 289 }
 290
 291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 292 {
 293         int i;
 294         u32 val, lock_mask;
 295         void __iomem *lock_addr;
 296
 297         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 298                 udelay(pll->params->lock_delay);
 299                 return 0;
 300         }
 301
 302         lock_addr = pll->clk_base;
 303         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 304                 lock_addr += pll->params->misc_reg;
 305         else
 306                 lock_addr += pll->params->base_reg;
 307
 308         lock_mask = pll->params->lock_mask;
 309
 310         for (i = 0; i < pll->params->lock_delay; i++) {
 311                 val = readl_relaxed(lock_addr);
 312                 if ((val & lock_mask) == lock_mask) {
 313                         udelay(PLL_POST_LOCK_DELAY);
 314                         return 0;
 315                 }
 316                 udelay(2); /* timeout = 2 * lock time */
 317         }
 318
 319         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 320                clk_hw_get_name(&pll->hw));
 321
 322         return -1;
 323 }
 324
 325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
 326 {
 327         return clk_pll_wait_for_lock(pll);
 328 }
 329
 330 static int clk_pll_is_enabled(struct clk_hw *hw)
 331 {
 332         struct tegra_clk_pll *pll = to_clk_pll(hw);
 333         u32 val;
 334
 335         if (pll->params->flags & TEGRA_PLLM) {
 336                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 337                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 338                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 339         }
 340
 341         val = pll_readl_base(pll);
 342
 343         return val & PLL_BASE_ENABLE ? 1 : 0;
 344 }
 345
 346 static void _clk_pll_enable(struct clk_hw *hw)
 347 {
 348         struct tegra_clk_pll *pll = to_clk_pll(hw);
 349         u32 val;
 350
 351         if (pll->params->iddq_reg) {
 352                 val = pll_readl(pll->params->iddq_reg, pll);
 353                 val &= ~BIT(pll->params->iddq_bit_idx);
 354                 pll_writel(val, pll->params->iddq_reg, pll);
 355                 udelay(5);
 356         }
 357
 358         if (pll->params->reset_reg) {
 359                 val = pll_readl(pll->params->reset_reg, pll);
 360                 val &= ~BIT(pll->params->reset_bit_idx);
 361                 pll_writel(val, pll->params->reset_reg, pll);
 362         }
 363
 364         clk_pll_enable_lock(pll);
 365
 366         val = pll_readl_base(pll);
 367         if (pll->params->flags & TEGRA_PLL_BYPASS)
 368                 val &= ~PLL_BASE_BYPASS;
 369         val |= PLL_BASE_ENABLE;
 370         pll_writel_base(val, pll);
 371
 372         if (pll->params->flags & TEGRA_PLLM) {
 373                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 374                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 375                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 376         }
 377 }
 378
 379 static void _clk_pll_disable(struct clk_hw *hw)
 380 {
 381         struct tegra_clk_pll *pll = to_clk_pll(hw);
 382         u32 val;
 383
 384         val = pll_readl_base(pll);
 385         if (pll->params->flags & TEGRA_PLL_BYPASS)
 386                 val &= ~PLL_BASE_BYPASS;
 387         val &= ~PLL_BASE_ENABLE;
 388         pll_writel_base(val, pll);
 389
 390         if (pll->params->flags & TEGRA_PLLM) {
 391                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 392                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 393                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 394         }
 395
 396         if (pll->params->reset_reg) {
 397                 val = pll_readl(pll->params->reset_reg, pll);
 398                 val |= BIT(pll->params->reset_bit_idx);
 399                 pll_writel(val, pll->params->reset_reg, pll);
 400         }
 401
 402         if (pll->params->iddq_reg) {
 403                 val = pll_readl(pll->params->iddq_reg, pll);
 404                 val |= BIT(pll->params->iddq_bit_idx);
 405                 pll_writel(val, pll->params->iddq_reg, pll);
 406                 udelay(2);
 407         }
 408 }
 409
 410 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
 411 {
 412         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 413                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 414
 415                 val |= pll->params->ssc_ctrl_en_mask;
 416                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 417         }
 418 }
 419
 420 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
 421 {
 422         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 423                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 424
 425                 val &= ~pll->params->ssc_ctrl_en_mask;
 426                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 427         }
 428 }
 429
 430 static int clk_pll_enable(struct clk_hw *hw)
 431 {
 432         struct tegra_clk_pll *pll = to_clk_pll(hw);
 433         unsigned long flags = 0;
 434         int ret;
 435
 436         if (clk_pll_is_enabled(hw))
 437                 return 0;
 438
 439         if (pll->lock)
 440                 spin_lock_irqsave(pll->lock, flags);
 441
 442         _clk_pll_enable(hw);
 443
 444         ret = clk_pll_wait_for_lock(pll);
 445
 446         pll_clk_start_ss(pll);
 447
 448         if (pll->lock)
 449                 spin_unlock_irqrestore(pll->lock, flags);
 450
 451         return ret;
 452 }
 453
 454 static void clk_pll_disable(struct clk_hw *hw)
 455 {
 456         struct tegra_clk_pll *pll = to_clk_pll(hw);
 457         unsigned long flags = 0;
 458
 459         if (pll->lock)
 460                 spin_lock_irqsave(pll->lock, flags);
 461
 462         pll_clk_stop_ss(pll);
 463
 464         _clk_pll_disable(hw);
 465
 466         if (pll->lock)
 467                 spin_unlock_irqrestore(pll->lock, flags);
 468 }
 469
 470 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 471 {
 472         struct tegra_clk_pll *pll = to_clk_pll(hw);
 473         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 474
 475         if (p_tohw) {
 476                 while (p_tohw->pdiv) {
 477                         if (p_div <= p_tohw->pdiv)
 478                                 return p_tohw->hw_val;
 479                         p_tohw++;
 480                 }
 481                 return -EINVAL;
 482         }
 483         return -EINVAL;
 484 }
 485
 486 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
 487 {
 488         return _p_div_to_hw(&pll->hw, p_div);
 489 }
 490
 491 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 492 {
 493         struct tegra_clk_pll *pll = to_clk_pll(hw);
 494         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 495
 496         if (p_tohw) {
 497                 while (p_tohw->pdiv) {
 498                         if (p_div_hw == p_tohw->hw_val)
 499                                 return p_tohw->pdiv;
 500                         p_tohw++;
 501                 }
 502                 return -EINVAL;
 503         }
 504
 505         return 1 << p_div_hw;
 506 }
 507
 508 static int _get_table_rate(struct clk_hw *hw,
 509                            struct tegra_clk_pll_freq_table *cfg,
 510                            unsigned long rate, unsigned long parent_rate)
 511 {
 512         struct tegra_clk_pll *pll = to_clk_pll(hw);
 513         struct tegra_clk_pll_freq_table *sel;
 514         int p;
 515
 516         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 517                 if (sel->input_rate == parent_rate &&
 518                     sel->output_rate == rate)
 519                         break;
 520
 521         if (sel->input_rate == 0)
 522                 return -EINVAL;
 523
 524         if (pll->params->pdiv_tohw) {
 525                 p = _p_div_to_hw(hw, sel->p);
 526                 if (p < 0)
 527                         return p;
 528         } else {
 529                 p = ilog2(sel->p);
 530         }
 531
 532         cfg->input_rate = sel->input_rate;
 533         cfg->output_rate = sel->output_rate;
 534         cfg->m = sel->m;
 535         cfg->n = sel->n;
 536         cfg->p = p;
 537         cfg->cpcon = sel->cpcon;
 538         cfg->sdm_data = sel->sdm_data;
 539
 540         return 0;
 541 }
 542
 543 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 544                       unsigned long rate, unsigned long parent_rate)
 545 {
 546         struct tegra_clk_pll *pll = to_clk_pll(hw);
 547         unsigned long cfreq;
 548         u32 p_div = 0;
 549         int ret;
 550
 551         switch (parent_rate) {
 552         case 12000000:
 553         case 26000000:
 554                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 555                 break;
 556         case 13000000:
 557                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 558                 break;
 559         case 16800000:
 560         case 19200000:
 561                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 562                 break;
 563         case 9600000:
 564         case 28800000:
 565                 /*
 566                  * PLL_P_OUT1 rate is not listed in PLLA table
 567                  */
 568                 cfreq = parent_rate / (parent_rate / 1000000);
 569                 break;
 570         default:
 571                 pr_err("%s Unexpected reference rate %lu\n",
 572                        __func__, parent_rate);
 573                 BUG();
 574         }
 575
 576         /* Raise VCO to guarantee 0.5% accuracy */
 577         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 578              cfg->output_rate <<= 1)
 579                 p_div++;
 580
 581         cfg->m = parent_rate / cfreq;
 582         cfg->n = cfg->output_rate / cfreq;
 583         cfg->cpcon = OUT_OF_TABLE_CPCON;
 584
 585         if (cfg->m == 0 || cfg->m > divm_max(pll) ||
 586             cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
 587             cfg->output_rate > pll->params->vco_max) {
 588                 return -EINVAL;
 589         }
 590
 591         cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
 592         cfg->output_rate >>= p_div;
 593
 594         if (pll->params->pdiv_tohw) {
 595                 ret = _p_div_to_hw(hw, 1 << p_div);
 596                 if (ret < 0)
 597                         return ret;
 598                 else
 599                         cfg->p = ret;
 600         } else
 601                 cfg->p = p_div;
 602
 603         return 0;
 604 }
 605
 606 /*
 607  * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
 608  * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
 609  * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
 610  * to indicate that SDM is disabled.
 611  *
 612  * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
 613  */
 614 static void clk_pll_set_sdm_data(struct clk_hw *hw,
 615                                  struct tegra_clk_pll_freq_table *cfg)
 616 {
 617         struct tegra_clk_pll *pll = to_clk_pll(hw);
 618         u32 val;
 619         bool enabled;
 620
 621         if (!pll->params->sdm_din_reg)
 622                 return;
 623
 624         if (cfg->sdm_data) {
 625                 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
 626                 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
 627                 pll_writel_sdm_din(val, pll);
 628         }
 629
 630         val = pll_readl_sdm_ctrl(pll);
 631         enabled = (val & sdm_en_mask(pll));
 632
 633         if (cfg->sdm_data == 0 && enabled)
 634                 val &= ~pll->params->sdm_ctrl_en_mask;
 635
 636         if (cfg->sdm_data != 0 && !enabled)
 637                 val |= pll->params->sdm_ctrl_en_mask;
 638
 639         pll_writel_sdm_ctrl(val, pll);
 640 }
 641
 642 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 643                             struct tegra_clk_pll_freq_table *cfg)
 644 {
 645         u32 val;
 646         struct tegra_clk_pll_params *params = pll->params;
 647         struct div_nmp *div_nmp = params->div_nmp;
 648
 649         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 650                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 651                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 652                 val = pll_override_readl(params->pmc_divp_reg, pll);
 653                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 654                 val |= cfg->p << div_nmp->override_divp_shift;
 655                 pll_override_writel(val, params->pmc_divp_reg, pll);
 656
 657                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 658                 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
 659                         (divn_mask(pll) << div_nmp->override_divn_shift));
 660                 val |= (cfg->m << div_nmp->override_divm_shift) |
 661                         (cfg->n << div_nmp->override_divn_shift);
 662                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 663         } else {
 664                 val = pll_readl_base(pll);
 665
 666                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 667                          divp_mask_shifted(pll));
 668
 669                 val |= (cfg->m << divm_shift(pll)) |
 670                        (cfg->n << divn_shift(pll)) |
 671                        (cfg->p << divp_shift(pll));
 672
 673                 pll_writel_base(val, pll);
 674
 675                 clk_pll_set_sdm_data(&pll->hw, cfg);
 676         }
 677 }
 678
 679 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 680                          struct tegra_clk_pll_freq_table *cfg)
 681 {
 682         u32 val;
 683         struct tegra_clk_pll_params *params = pll->params;
 684         struct div_nmp *div_nmp = params->div_nmp;
 685
 686         *cfg = (struct tegra_clk_pll_freq_table) { };
 687
 688         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 689                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 690                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 691                 val = pll_override_readl(params->pmc_divp_reg, pll);
 692                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 693
 694                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 695                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 696                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 697         }  else {
 698                 val = pll_readl_base(pll);
 699
 700                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 701                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 702                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 703
 704                 if (pll->params->sdm_din_reg) {
 705                         if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
 706                                 val = pll_readl_sdm_din(pll);
 707                                 val &= sdm_din_mask(pll);
 708                                 cfg->sdm_data = sdin_din_to_data(val);
 709                         }
 710                 }
 711         }
 712 }
 713
 714 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 715                               struct tegra_clk_pll_freq_table *cfg,
 716                               unsigned long rate)
 717 {
 718         u32 val;
 719
 720         val = pll_readl_misc(pll);
 721
 722         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 723         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 724
 725         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 726                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 727                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 728                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 729         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 730                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 731                 if (rate >= (pll->params->vco_max >> 1))
 732                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 733         }
 734
 735         pll_writel_misc(val, pll);
 736 }
 737
 738 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 739                         unsigned long rate)
 740 {
 741         struct tegra_clk_pll *pll = to_clk_pll(hw);
 742         struct tegra_clk_pll_freq_table old_cfg;
 743         int state, ret = 0;
 744
 745         state = clk_pll_is_enabled(hw);
 746
 747         _get_pll_mnp(pll, &old_cfg);
 748
 749         if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 750                         (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 751                 ret = pll->params->dyn_ramp(pll, cfg);
 752                 if (!ret)
 753                         return 0;
 754         }
 755
 756         if (state) {
 757                 pll_clk_stop_ss(pll);
 758                 _clk_pll_disable(hw);
 759         }
 760
 761         if (!pll->params->defaults_set && pll->params->set_defaults)
 762                 pll->params->set_defaults(pll);
 763
 764         _update_pll_mnp(pll, cfg);
 765
 766         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 767                 _update_pll_cpcon(pll, cfg, rate);
 768
 769         if (state) {
 770                 _clk_pll_enable(hw);
 771                 ret = clk_pll_wait_for_lock(pll);
 772                 pll_clk_start_ss(pll);
 773         }
 774
 775         return ret;
 776 }
 777
 778 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 779                         unsigned long parent_rate)
 780 {
 781         struct tegra_clk_pll *pll = to_clk_pll(hw);
 782         struct tegra_clk_pll_freq_table cfg, old_cfg;
 783         unsigned long flags = 0;
 784         int ret = 0;
 785
 786         if (pll->params->flags & TEGRA_PLL_FIXED) {
 787                 if (rate != pll->params->fixed_rate) {
 788                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 789                                 __func__, clk_hw_get_name(hw),
 790                                 pll->params->fixed_rate, rate);
 791                         return -EINVAL;
 792                 }
 793                 return 0;
 794         }
 795
 796         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 797             pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
 798                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 799                        clk_hw_get_name(hw), rate);
 800                 WARN_ON(1);
 801                 return -EINVAL;
 802         }
 803         if (pll->lock)
 804                 spin_lock_irqsave(pll->lock, flags);
 805
 806         _get_pll_mnp(pll, &old_cfg);
 807         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
 808                 cfg.p = old_cfg.p;
 809
 810         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
 811                 old_cfg.sdm_data != cfg.sdm_data)
 812                 ret = _program_pll(hw, &cfg, rate);
 813
 814         if (pll->lock)
 815                 spin_unlock_irqrestore(pll->lock, flags);
 816
 817         return ret;
 818 }
 819
 820 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 821                         unsigned long *prate)
 822 {
 823         struct tegra_clk_pll *pll = to_clk_pll(hw);
 824         struct tegra_clk_pll_freq_table cfg;
 825
 826         if (pll->params->flags & TEGRA_PLL_FIXED) {
 827                 /* PLLM/MB are used for memory; we do not change rate */
 828                 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
 829                         return clk_hw_get_rate(hw);
 830                 return pll->params->fixed_rate;
 831         }
 832
 833         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 834             pll->params->calc_rate(hw, &cfg, rate, *prate))
 835                 return -EINVAL;
 836
 837         return cfg.output_rate;
 838 }
 839
 840 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 841                                          unsigned long parent_rate)
 842 {
 843         struct tegra_clk_pll *pll = to_clk_pll(hw);
 844         struct tegra_clk_pll_freq_table cfg;
 845         u32 val;
 846         u64 rate = parent_rate;
 847         int pdiv;
 848
 849         val = pll_readl_base(pll);
 850
 851         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 852                 return parent_rate;
 853
 854         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 855             !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 856                         !(val & PLL_BASE_OVERRIDE)) {
 857                 struct tegra_clk_pll_freq_table sel;
 858                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 859                                         parent_rate)) {
 860                         pr_err("Clock %s has unknown fixed frequency\n",
 861                                clk_hw_get_name(hw));
 862                         BUG();
 863                 }
 864                 return pll->params->fixed_rate;
 865         }
 866
 867         _get_pll_mnp(pll, &cfg);
 868
 869         if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
 870                 pdiv = 1;
 871         } else {
 872                 pdiv = _hw_to_p_div(hw, cfg.p);
 873                 if (pdiv < 0) {
 874                         WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
 875                              clk_hw_get_name(hw), cfg.p);
 876                         pdiv = 1;
 877                 }
 878         }
 879
 880         if (pll->params->set_gain)
 881                 pll->params->set_gain(&cfg);
 882
 883         cfg.m *= pdiv;
 884
 885         rate *= cfg.n;
 886         do_div(rate, cfg.m);
 887
 888         return rate;
 889 }
 890
 891 static int clk_plle_training(struct tegra_clk_pll *pll)
 892 {
 893         u32 val;
 894         unsigned long timeout;
 895
 896         if (!pll->pmc)
 897                 return -ENOSYS;
 898
 899         /*
 900          * PLLE is already disabled, and setup cleared;
 901          * create falling edge on PLLE IDDQ input.
 902          */
 903         val = readl(pll->pmc + PMC_SATA_PWRGT);
 904         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 905         writel(val, pll->pmc + PMC_SATA_PWRGT);
 906
 907         val = readl(pll->pmc + PMC_SATA_PWRGT);
 908         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 909         writel(val, pll->pmc + PMC_SATA_PWRGT);
 910
 911         val = readl(pll->pmc + PMC_SATA_PWRGT);
 912         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 913         writel(val, pll->pmc + PMC_SATA_PWRGT);
 914
 915         val = pll_readl_misc(pll);
 916
 917         timeout = jiffies + msecs_to_jiffies(100);
 918         while (1) {
 919                 val = pll_readl_misc(pll);
 920                 if (val & PLLE_MISC_READY)
 921                         break;
 922                 if (time_after(jiffies, timeout)) {
 923                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 924                         return -EBUSY;
 925                 }
 926                 udelay(300);
 927         }
 928
 929         return 0;
 930 }
 931
 932 static int clk_plle_enable(struct clk_hw *hw)
 933 {
 934         struct tegra_clk_pll *pll = to_clk_pll(hw);
 935         struct tegra_clk_pll_freq_table sel;
 936         unsigned long input_rate;
 937         u32 val;
 938         int err;
 939
 940         if (clk_pll_is_enabled(hw))
 941                 return 0;
 942
 943         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 944
 945         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 946                 return -EINVAL;
 947
 948         clk_pll_disable(hw);
 949
 950         val = pll_readl_misc(pll);
 951         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 952         pll_writel_misc(val, pll);
 953
 954         val = pll_readl_misc(pll);
 955         if (!(val & PLLE_MISC_READY)) {
 956                 err = clk_plle_training(pll);
 957                 if (err)
 958                         return err;
 959         }
 960
 961         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 962                 /* configure dividers */
 963                 val = pll_readl_base(pll);
 964                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 965                          divm_mask_shifted(pll));
 966                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 967                 val |= sel.m << divm_shift(pll);
 968                 val |= sel.n << divn_shift(pll);
 969                 val |= sel.p << divp_shift(pll);
 970                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 971                 pll_writel_base(val, pll);
 972         }
 973
 974         val = pll_readl_misc(pll);
 975         val |= PLLE_MISC_SETUP_VALUE;
 976         val |= PLLE_MISC_LOCK_ENABLE;
 977         pll_writel_misc(val, pll);
 978
 979         val = readl(pll->clk_base + PLLE_SS_CTRL);
 980         val &= ~PLLE_SS_COEFFICIENTS_MASK;
 981         val |= PLLE_SS_DISABLE;
 982         writel(val, pll->clk_base + PLLE_SS_CTRL);
 983
 984         val = pll_readl_base(pll);
 985         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 986         pll_writel_base(val, pll);
 987
 988         clk_pll_wait_for_lock(pll);
 989
 990         return 0;
 991 }
 992
 993 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 994                                          unsigned long parent_rate)
 995 {
 996         struct tegra_clk_pll *pll = to_clk_pll(hw);
 997         u32 val = pll_readl_base(pll);
 998         u32 divn = 0, divm = 0, divp = 0;
 999         u64 rate = parent_rate;
1000
1001         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1002         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1003         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1004         divm *= divp;
1005
1006         rate *= divn;
1007         do_div(rate, divm);
1008         return rate;
1009 }
1010
1011 const struct clk_ops tegra_clk_pll_ops = {
1012         .is_enabled = clk_pll_is_enabled,
1013         .enable = clk_pll_enable,
1014         .disable = clk_pll_disable,
1015         .recalc_rate = clk_pll_recalc_rate,
1016         .round_rate = clk_pll_round_rate,
1017         .set_rate = clk_pll_set_rate,
1018 };
1019
1020 const struct clk_ops tegra_clk_plle_ops = {
1021         .recalc_rate = clk_plle_recalc_rate,
1022         .is_enabled = clk_pll_is_enabled,
1023         .disable = clk_pll_disable,
1024         .enable = clk_plle_enable,
1025 };
1026
1027 /*
1028  * Structure defining the fields for USB UTMI clocks Parameters.
1029  */
1030 struct utmi_clk_param {
1031         /* Oscillator Frequency in Hz */
1032         u32 osc_frequency;
1033         /* UTMIP PLL Enable Delay Count  */
1034         u8 enable_delay_count;
1035         /* UTMIP PLL Stable count */
1036         u8 stable_count;
1037         /*  UTMIP PLL Active delay count */
1038         u8 active_delay_count;
1039         /* UTMIP PLL Xtal frequency count */
1040         u8 xtal_freq_count;
1041 };
1042
1043 static const struct utmi_clk_param utmi_parameters[] = {
1044         {
1045                 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1046                 .stable_count = 0x33, .active_delay_count = 0x05,
1047                 .xtal_freq_count = 0x7f
1048         }, {
1049                 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1050                 .stable_count = 0x4b, .active_delay_count = 0x06,
1051                 .xtal_freq_count = 0xbb
1052         }, {
1053                 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1054                 .stable_count = 0x2f, .active_delay_count = 0x04,
1055                 .xtal_freq_count = 0x76
1056         }, {
1057                 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1058                 .stable_count = 0x66, .active_delay_count = 0x09,
1059                 .xtal_freq_count = 0xfe
1060         }, {
1061                 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1062                 .stable_count = 0x41, .active_delay_count = 0x0a,
1063                 .xtal_freq_count = 0xa4
1064         }, {
1065                 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1066                 .stable_count = 0x0, .active_delay_count = 0x6,
1067                 .xtal_freq_count = 0x80
1068         },
1069 };
1070
1071 static int clk_pllu_enable(struct clk_hw *hw)
1072 {
1073         struct tegra_clk_pll *pll = to_clk_pll(hw);
1074         struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1075         struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1076         const struct utmi_clk_param *params = NULL;
1077         unsigned long flags = 0, input_rate;
1078         unsigned int i;
1079         int ret = 0;
1080         u32 value;
1081
1082         if (!osc) {
1083                 pr_err("%s: failed to get OSC clock\n", __func__);
1084                 return -EINVAL;
1085         }
1086
1087         input_rate = clk_hw_get_rate(osc);
1088
1089         if (pll->lock)
1090                 spin_lock_irqsave(pll->lock, flags);
1091
1092         _clk_pll_enable(hw);
1093
1094         ret = clk_pll_wait_for_lock(pll);
1095         if (ret < 0)
1096                 goto out;
1097
1098         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1099                 if (input_rate == utmi_parameters[i].osc_frequency) {
1100                         params = &utmi_parameters[i];
1101                         break;
1102                 }
1103         }
1104
1105         if (!params) {
1106                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1107                        input_rate);
1108                 ret = -EINVAL;
1109                 goto out;
1110         }
1111
1112         value = pll_readl_base(pll);
1113         value &= ~PLLU_BASE_OVERRIDE;
1114         pll_writel_base(value, pll);
1115
1116         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1117         /* Program UTMIP PLL stable and active counts */
1118         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1119         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1120         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1121         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1122         /* Remove power downs from UTMIP PLL control bits */
1123         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1124         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1125         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1126         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1127
1128         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1129         /* Program UTMIP PLL delay and oscillator frequency counts */
1130         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1131         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1132         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1133         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1134         /* Remove power downs from UTMIP PLL control bits */
1135         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1136         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1137         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1138         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1139
1140 out:
1141         if (pll->lock)
1142                 spin_unlock_irqrestore(pll->lock, flags);
1143
1144         return ret;
1145 }
1146
1147 static const struct clk_ops tegra_clk_pllu_ops = {
1148         .is_enabled = clk_pll_is_enabled,
1149         .enable = clk_pllu_enable,
1150         .disable = clk_pll_disable,
1151         .recalc_rate = clk_pll_recalc_rate,
1152         .round_rate = clk_pll_round_rate,
1153         .set_rate = clk_pll_set_rate,
1154 };
1155
1156 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1157                            unsigned long parent_rate)
1158 {
1159         u16 mdiv = parent_rate / pll_params->cf_min;
1160
1161         if (pll_params->flags & TEGRA_MDIV_NEW)
1162                 return (!pll_params->mdiv_default ? mdiv :
1163                         min(mdiv, pll_params->mdiv_default));
1164
1165         if (pll_params->mdiv_default)
1166                 return pll_params->mdiv_default;
1167
1168         if (parent_rate > pll_params->cf_max)
1169                 return 2;
1170         else
1171                 return 1;
1172 }
1173
1174 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1175                                 struct tegra_clk_pll_freq_table *cfg,
1176                                 unsigned long rate, unsigned long parent_rate)
1177 {
1178         struct tegra_clk_pll *pll = to_clk_pll(hw);
1179         unsigned int p;
1180         int p_div;
1181
1182         if (!rate)
1183                 return -EINVAL;
1184
1185         p = DIV_ROUND_UP(pll->params->vco_min, rate);
1186         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1187         cfg->output_rate = rate * p;
1188         cfg->n = cfg->output_rate * cfg->m / parent_rate;
1189         cfg->input_rate = parent_rate;
1190
1191         p_div = _p_div_to_hw(hw, p);
1192         if (p_div < 0)
1193                 return p_div;
1194
1195         cfg->p = p_div;
1196
1197         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1198                 return -EINVAL;
1199
1200         return 0;
1201 }
1202
1203 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1204         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1205         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1206         defined(CONFIG_ARCH_TEGRA_210_SOC)
1207
1208 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1209 {
1210         struct tegra_clk_pll *pll = to_clk_pll(hw);
1211
1212         return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1213 }
1214
1215 static unsigned long _clip_vco_min(unsigned long vco_min,
1216                                    unsigned long parent_rate)
1217 {
1218         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1219 }
1220
1221 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1222                                void __iomem *clk_base,
1223                                unsigned long parent_rate)
1224 {
1225         u32 val;
1226         u32 step_a, step_b;
1227
1228         switch (parent_rate) {
1229         case 12000000:
1230         case 13000000:
1231         case 26000000:
1232                 step_a = 0x2B;
1233                 step_b = 0x0B;
1234                 break;
1235         case 16800000:
1236                 step_a = 0x1A;
1237                 step_b = 0x09;
1238                 break;
1239         case 19200000:
1240                 step_a = 0x12;
1241                 step_b = 0x08;
1242                 break;
1243         default:
1244                 pr_err("%s: Unexpected reference rate %lu\n",
1245                         __func__, parent_rate);
1246                 WARN_ON(1);
1247                 return -EINVAL;
1248         }
1249
1250         val = step_a << pll_params->stepa_shift;
1251         val |= step_b << pll_params->stepb_shift;
1252         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1253
1254         return 0;
1255 }
1256
1257 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1258                               struct tegra_clk_pll_freq_table *cfg,
1259                               unsigned long rate, unsigned long parent_rate)
1260 {
1261         struct tegra_clk_pll *pll = to_clk_pll(hw);
1262         int err = 0;
1263
1264         err = _get_table_rate(hw, cfg, rate, parent_rate);
1265         if (err < 0)
1266                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1267         else {
1268                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1269                         WARN_ON(1);
1270                         err = -EINVAL;
1271                         goto out;
1272                 }
1273         }
1274
1275         if (cfg->p >  pll->params->max_p)
1276                 err = -EINVAL;
1277
1278 out:
1279         return err;
1280 }
1281
1282 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1283                                 unsigned long parent_rate)
1284 {
1285         struct tegra_clk_pll *pll = to_clk_pll(hw);
1286         struct tegra_clk_pll_freq_table cfg, old_cfg;
1287         unsigned long flags = 0;
1288         int ret;
1289
1290         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1291         if (ret < 0)
1292                 return ret;
1293
1294         if (pll->lock)
1295                 spin_lock_irqsave(pll->lock, flags);
1296
1297         _get_pll_mnp(pll, &old_cfg);
1298         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1299                 cfg.p = old_cfg.p;
1300
1301         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1302                 ret = _program_pll(hw, &cfg, rate);
1303
1304         if (pll->lock)
1305                 spin_unlock_irqrestore(pll->lock, flags);
1306
1307         return ret;
1308 }
1309
1310 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1311                                 unsigned long *prate)
1312 {
1313         struct tegra_clk_pll *pll = to_clk_pll(hw);
1314         struct tegra_clk_pll_freq_table cfg;
1315         int ret, p_div;
1316         u64 output_rate = *prate;
1317
1318         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1319         if (ret < 0)
1320                 return ret;
1321
1322         p_div = _hw_to_p_div(hw, cfg.p);
1323         if (p_div < 0)
1324                 return p_div;
1325
1326         if (pll->params->set_gain)
1327                 pll->params->set_gain(&cfg);
1328
1329         output_rate *= cfg.n;
1330         do_div(output_rate, cfg.m * p_div);
1331
1332         return output_rate;
1333 }
1334
1335 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1336 {
1337         u32 val;
1338
1339         val = pll_readl_misc(pll);
1340         val |= PLLCX_MISC_STROBE;
1341         pll_writel_misc(val, pll);
1342         udelay(2);
1343
1344         val &= ~PLLCX_MISC_STROBE;
1345         pll_writel_misc(val, pll);
1346 }
1347
1348 static int clk_pllc_enable(struct clk_hw *hw)
1349 {
1350         struct tegra_clk_pll *pll = to_clk_pll(hw);
1351         u32 val;
1352         int ret;
1353         unsigned long flags = 0;
1354
1355         if (clk_pll_is_enabled(hw))
1356                 return 0;
1357
1358         if (pll->lock)
1359                 spin_lock_irqsave(pll->lock, flags);
1360
1361         _clk_pll_enable(hw);
1362         udelay(2);
1363
1364         val = pll_readl_misc(pll);
1365         val &= ~PLLCX_MISC_RESET;
1366         pll_writel_misc(val, pll);
1367         udelay(2);
1368
1369         _pllcx_strobe(pll);
1370
1371         ret = clk_pll_wait_for_lock(pll);
1372
1373         if (pll->lock)
1374                 spin_unlock_irqrestore(pll->lock, flags);
1375
1376         return ret;
1377 }
1378
1379 static void _clk_pllc_disable(struct clk_hw *hw)
1380 {
1381         struct tegra_clk_pll *pll = to_clk_pll(hw);
1382         u32 val;
1383
1384         _clk_pll_disable(hw);
1385
1386         val = pll_readl_misc(pll);
1387         val |= PLLCX_MISC_RESET;
1388         pll_writel_misc(val, pll);
1389         udelay(2);
1390 }
1391
1392 static void clk_pllc_disable(struct clk_hw *hw)
1393 {
1394         struct tegra_clk_pll *pll = to_clk_pll(hw);
1395         unsigned long flags = 0;
1396
1397         if (pll->lock)
1398                 spin_lock_irqsave(pll->lock, flags);
1399
1400         _clk_pllc_disable(hw);
1401
1402         if (pll->lock)
1403                 spin_unlock_irqrestore(pll->lock, flags);
1404 }
1405
1406 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1407                                         unsigned long input_rate, u32 n)
1408 {
1409         u32 val, n_threshold;
1410
1411         switch (input_rate) {
1412         case 12000000:
1413                 n_threshold = 70;
1414                 break;
1415         case 13000000:
1416         case 26000000:
1417                 n_threshold = 71;
1418                 break;
1419         case 16800000:
1420                 n_threshold = 55;
1421                 break;
1422         case 19200000:
1423                 n_threshold = 48;
1424                 break;
1425         default:
1426                 pr_err("%s: Unexpected reference rate %lu\n",
1427                         __func__, input_rate);
1428                 return -EINVAL;
1429         }
1430
1431         val = pll_readl_misc(pll);
1432         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1433         val |= n <= n_threshold ?
1434                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1435         pll_writel_misc(val, pll);
1436
1437         return 0;
1438 }
1439
1440 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1441                                 unsigned long parent_rate)
1442 {
1443         struct tegra_clk_pll_freq_table cfg, old_cfg;
1444         struct tegra_clk_pll *pll = to_clk_pll(hw);
1445         unsigned long flags = 0;
1446         int state, ret = 0;
1447
1448         if (pll->lock)
1449                 spin_lock_irqsave(pll->lock, flags);
1450
1451         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1452         if (ret < 0)
1453                 goto out;
1454
1455         _get_pll_mnp(pll, &old_cfg);
1456
1457         if (cfg.m != old_cfg.m) {
1458                 WARN_ON(1);
1459                 goto out;
1460         }
1461
1462         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1463                 goto out;
1464
1465         state = clk_pll_is_enabled(hw);
1466         if (state)
1467                 _clk_pllc_disable(hw);
1468
1469         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1470         if (ret < 0)
1471                 goto out;
1472
1473         _update_pll_mnp(pll, &cfg);
1474
1475         if (state)
1476                 ret = clk_pllc_enable(hw);
1477
1478 out:
1479         if (pll->lock)
1480                 spin_unlock_irqrestore(pll->lock, flags);
1481
1482         return ret;
1483 }
1484
1485 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1486                              struct tegra_clk_pll_freq_table *cfg,
1487                              unsigned long rate, unsigned long parent_rate)
1488 {
1489         u16 m, n;
1490         u64 output_rate = parent_rate;
1491
1492         m = _pll_fixed_mdiv(pll->params, parent_rate);
1493         n = rate * m / parent_rate;
1494
1495         output_rate *= n;
1496         do_div(output_rate, m);
1497
1498         if (cfg) {
1499                 cfg->m = m;
1500                 cfg->n = n;
1501         }
1502
1503         return output_rate;
1504 }
1505
1506 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1507                                 unsigned long parent_rate)
1508 {
1509         struct tegra_clk_pll_freq_table cfg, old_cfg;
1510         struct tegra_clk_pll *pll = to_clk_pll(hw);
1511         unsigned long flags = 0;
1512         int state, ret = 0;
1513
1514         if (pll->lock)
1515                 spin_lock_irqsave(pll->lock, flags);
1516
1517         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1518         _get_pll_mnp(pll, &old_cfg);
1519         cfg.p = old_cfg.p;
1520
1521         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1522                 state = clk_pll_is_enabled(hw);
1523                 if (state)
1524                         _clk_pll_disable(hw);
1525
1526                 _update_pll_mnp(pll, &cfg);
1527
1528                 if (state) {
1529                         _clk_pll_enable(hw);
1530                         ret = clk_pll_wait_for_lock(pll);
1531                 }
1532         }
1533
1534         if (pll->lock)
1535                 spin_unlock_irqrestore(pll->lock, flags);
1536
1537         return ret;
1538 }
1539
1540 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1541                                          unsigned long parent_rate)
1542 {
1543         struct tegra_clk_pll_freq_table cfg;
1544         struct tegra_clk_pll *pll = to_clk_pll(hw);
1545         u64 rate = parent_rate;
1546
1547         _get_pll_mnp(pll, &cfg);
1548
1549         rate *= cfg.n;
1550         do_div(rate, cfg.m);
1551
1552         return rate;
1553 }
1554
1555 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1556                                  unsigned long *prate)
1557 {
1558         struct tegra_clk_pll *pll = to_clk_pll(hw);
1559
1560         return _pllre_calc_rate(pll, NULL, rate, *prate);
1561 }
1562
1563 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1564 {
1565         struct tegra_clk_pll *pll = to_clk_pll(hw);
1566         struct tegra_clk_pll_freq_table sel;
1567         u32 val;
1568         int ret;
1569         unsigned long flags = 0;
1570         unsigned long input_rate;
1571
1572         if (clk_pll_is_enabled(hw))
1573                 return 0;
1574
1575         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1576
1577         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1578                 return -EINVAL;
1579
1580         if (pll->lock)
1581                 spin_lock_irqsave(pll->lock, flags);
1582
1583         val = pll_readl_base(pll);
1584         val &= ~BIT(29); /* Disable lock override */
1585         pll_writel_base(val, pll);
1586
1587         val = pll_readl(pll->params->aux_reg, pll);
1588         val |= PLLE_AUX_ENABLE_SWCTL;
1589         val &= ~PLLE_AUX_SEQ_ENABLE;
1590         pll_writel(val, pll->params->aux_reg, pll);
1591         udelay(1);
1592
1593         val = pll_readl_misc(pll);
1594         val |= PLLE_MISC_LOCK_ENABLE;
1595         val |= PLLE_MISC_IDDQ_SW_CTRL;
1596         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1597         val |= PLLE_MISC_PLLE_PTS;
1598         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1599         pll_writel_misc(val, pll);
1600         udelay(5);
1601
1602         val = pll_readl(PLLE_SS_CTRL, pll);
1603         val |= PLLE_SS_DISABLE;
1604         pll_writel(val, PLLE_SS_CTRL, pll);
1605
1606         val = pll_readl_base(pll);
1607         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1608                  divm_mask_shifted(pll));
1609         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1610         val |= sel.m << divm_shift(pll);
1611         val |= sel.n << divn_shift(pll);
1612         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1613         pll_writel_base(val, pll);
1614         udelay(1);
1615
1616         _clk_pll_enable(hw);
1617         ret = clk_pll_wait_for_lock(pll);
1618
1619         if (ret < 0)
1620                 goto out;
1621
1622         val = pll_readl(PLLE_SS_CTRL, pll);
1623         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1624         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1625         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1626         pll_writel(val, PLLE_SS_CTRL, pll);
1627         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1628         pll_writel(val, PLLE_SS_CTRL, pll);
1629         udelay(1);
1630         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1631         pll_writel(val, PLLE_SS_CTRL, pll);
1632         udelay(1);
1633
1634         /* Enable hw control of xusb brick pll */
1635         val = pll_readl_misc(pll);
1636         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1637         pll_writel_misc(val, pll);
1638
1639         val = pll_readl(pll->params->aux_reg, pll);
1640         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1641         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1642         pll_writel(val, pll->params->aux_reg, pll);
1643         udelay(1);
1644         val |= PLLE_AUX_SEQ_ENABLE;
1645         pll_writel(val, pll->params->aux_reg, pll);
1646
1647         val = pll_readl(XUSBIO_PLL_CFG0, pll);
1648         val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1649                 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1650         val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1651                  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1652         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1653         udelay(1);
1654         val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1655         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1656
1657         /* Enable hw control of SATA pll */
1658         val = pll_readl(SATA_PLL_CFG0, pll);
1659         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1660         val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1661         val |= SATA_PLL_CFG0_SEQ_START_STATE;
1662         pll_writel(val, SATA_PLL_CFG0, pll);
1663
1664         udelay(1);
1665
1666         val = pll_readl(SATA_PLL_CFG0, pll);
1667         val |= SATA_PLL_CFG0_SEQ_ENABLE;
1668         pll_writel(val, SATA_PLL_CFG0, pll);
1669
1670 out:
1671         if (pll->lock)
1672                 spin_unlock_irqrestore(pll->lock, flags);
1673
1674         return ret;
1675 }
1676
1677 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1678 {
1679         struct tegra_clk_pll *pll = to_clk_pll(hw);
1680         unsigned long flags = 0;
1681         u32 val;
1682
1683         if (pll->lock)
1684                 spin_lock_irqsave(pll->lock, flags);
1685
1686         _clk_pll_disable(hw);
1687
1688         val = pll_readl_misc(pll);
1689         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1690         pll_writel_misc(val, pll);
1691         udelay(1);
1692
1693         if (pll->lock)
1694                 spin_unlock_irqrestore(pll->lock, flags);
1695 }
1696
1697 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1698 {
1699         struct tegra_clk_pll *pll = to_clk_pll(hw);
1700         const struct utmi_clk_param *params = NULL;
1701         struct clk *osc = __clk_lookup("osc");
1702         unsigned long flags = 0, input_rate;
1703         unsigned int i;
1704         int ret = 0;
1705         u32 value;
1706
1707         if (!osc) {
1708                 pr_err("%s: failed to get OSC clock\n", __func__);
1709                 return -EINVAL;
1710         }
1711
1712         if (clk_pll_is_enabled(hw))
1713                 return 0;
1714
1715         input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1716
1717         if (pll->lock)
1718                 spin_lock_irqsave(pll->lock, flags);
1719
1720         _clk_pll_enable(hw);
1721
1722         ret = clk_pll_wait_for_lock(pll);
1723         if (ret < 0)
1724                 goto out;
1725
1726         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1727                 if (input_rate == utmi_parameters[i].osc_frequency) {
1728                         params = &utmi_parameters[i];
1729                         break;
1730                 }
1731         }
1732
1733         if (!params) {
1734                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1735                        input_rate);
1736                 ret = -EINVAL;
1737                 goto out;
1738         }
1739
1740         value = pll_readl_base(pll);
1741         value &= ~PLLU_BASE_OVERRIDE;
1742         pll_writel_base(value, pll);
1743
1744         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1745         /* Program UTMIP PLL stable and active counts */
1746         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1747         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1748         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1749         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1750         /* Remove power downs from UTMIP PLL control bits */
1751         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1752         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1753         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1754         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1755
1756         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1757         /* Program UTMIP PLL delay and oscillator frequency counts */
1758         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1759         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1760         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1761         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1762         /* Remove power downs from UTMIP PLL control bits */
1763         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1764         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1765         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1766         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1767         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1768
1769         /* Setup HW control of UTMIPLL */
1770         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1771         value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1772         value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1773         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1774         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1775
1776         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1777         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1778         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1779         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1780
1781         udelay(1);
1782
1783         /*
1784          * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1785          * to USB2
1786          */
1787         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1788         value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1789         value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1790         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1791
1792         udelay(1);
1793
1794         /* Enable HW control of UTMIPLL */
1795         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1796         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1797         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1798
1799 out:
1800         if (pll->lock)
1801                 spin_unlock_irqrestore(pll->lock, flags);
1802
1803         return ret;
1804 }
1805 #endif
1806
1807 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1808                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1809                 spinlock_t *lock)
1810 {
1811         struct tegra_clk_pll *pll;
1812
1813         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1814         if (!pll)
1815                 return ERR_PTR(-ENOMEM);
1816
1817         pll->clk_base = clk_base;
1818         pll->pmc = pmc;
1819
1820         pll->params = pll_params;
1821         pll->lock = lock;
1822
1823         if (!pll_params->div_nmp)
1824                 pll_params->div_nmp = &default_nmp;
1825
1826         return pll;
1827 }
1828
1829 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1830                 const char *name, const char *parent_name, unsigned long flags,
1831                 const struct clk_ops *ops)
1832 {
1833         struct clk_init_data init;
1834
1835         init.name = name;
1836         init.ops = ops;
1837         init.flags = flags;
1838         init.parent_names = (parent_name ? &parent_name : NULL);
1839         init.num_parents = (parent_name ? 1 : 0);
1840
1841         /* Default to _calc_rate if unspecified */
1842         if (!pll->params->calc_rate) {
1843                 if (pll->params->flags & TEGRA_PLLM)
1844                         pll->params->calc_rate = _calc_dynamic_ramp_rate;
1845                 else
1846                         pll->params->calc_rate = _calc_rate;
1847         }
1848
1849         if (pll->params->set_defaults)
1850                 pll->params->set_defaults(pll);
1851
1852         /* Data in .init is copied by clk_register(), so stack variable OK */
1853         pll->hw.init = &init;
1854
1855         return clk_register(NULL, &pll->hw);
1856 }
1857
1858 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1859                 void __iomem *clk_base, void __iomem *pmc,
1860                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1861                 spinlock_t *lock)
1862 {
1863         struct tegra_clk_pll *pll;
1864         struct clk *clk;
1865
1866         pll_params->flags |= TEGRA_PLL_BYPASS;
1867
1868         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1869         if (IS_ERR(pll))
1870                 return ERR_CAST(pll);
1871
1872         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1873                                       &tegra_clk_pll_ops);
1874         if (IS_ERR(clk))
1875                 kfree(pll);
1876
1877         return clk;
1878 }
1879
1880 static struct div_nmp pll_e_nmp = {
1881         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1882         .divn_width = PLLE_BASE_DIVN_WIDTH,
1883         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1884         .divm_width = PLLE_BASE_DIVM_WIDTH,
1885         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1886         .divp_width = PLLE_BASE_DIVP_WIDTH,
1887 };
1888
1889 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1890                 void __iomem *clk_base, void __iomem *pmc,
1891                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1892                 spinlock_t *lock)
1893 {
1894         struct tegra_clk_pll *pll;
1895         struct clk *clk;
1896
1897         pll_params->flags |= TEGRA_PLL_BYPASS;
1898
1899         if (!pll_params->div_nmp)
1900                 pll_params->div_nmp = &pll_e_nmp;
1901
1902         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1903         if (IS_ERR(pll))
1904                 return ERR_CAST(pll);
1905
1906         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1907                                       &tegra_clk_plle_ops);
1908         if (IS_ERR(clk))
1909                 kfree(pll);
1910
1911         return clk;
1912 }
1913
1914 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1915                 void __iomem *clk_base, unsigned long flags,
1916                 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1917 {
1918         struct tegra_clk_pll *pll;
1919         struct clk *clk;
1920
1921         pll_params->flags |= TEGRA_PLLU;
1922
1923         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1924         if (IS_ERR(pll))
1925                 return ERR_CAST(pll);
1926
1927         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1928                                       &tegra_clk_pllu_ops);
1929         if (IS_ERR(clk))
1930                 kfree(pll);
1931
1932         return clk;
1933 }
1934
1935 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1936         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1937         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1938         defined(CONFIG_ARCH_TEGRA_210_SOC)
1939 static const struct clk_ops tegra_clk_pllxc_ops = {
1940         .is_enabled = clk_pll_is_enabled,
1941         .enable = clk_pll_enable,
1942         .disable = clk_pll_disable,
1943         .recalc_rate = clk_pll_recalc_rate,
1944         .round_rate = clk_pll_ramp_round_rate,
1945         .set_rate = clk_pllxc_set_rate,
1946 };
1947
1948 static const struct clk_ops tegra_clk_pllc_ops = {
1949         .is_enabled = clk_pll_is_enabled,
1950         .enable = clk_pllc_enable,
1951         .disable = clk_pllc_disable,
1952         .recalc_rate = clk_pll_recalc_rate,
1953         .round_rate = clk_pll_ramp_round_rate,
1954         .set_rate = clk_pllc_set_rate,
1955 };
1956
1957 static const struct clk_ops tegra_clk_pllre_ops = {
1958         .is_enabled = clk_pll_is_enabled,
1959         .enable = clk_pll_enable,
1960         .disable = clk_pll_disable,
1961         .recalc_rate = clk_pllre_recalc_rate,
1962         .round_rate = clk_pllre_round_rate,
1963         .set_rate = clk_pllre_set_rate,
1964 };
1965
1966 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1967         .is_enabled =  clk_pll_is_enabled,
1968         .enable = clk_plle_tegra114_enable,
1969         .disable = clk_plle_tegra114_disable,
1970         .recalc_rate = clk_pll_recalc_rate,
1971 };
1972
1973 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1974         .is_enabled =  clk_pll_is_enabled,
1975         .enable = clk_pllu_tegra114_enable,
1976         .disable = clk_pll_disable,
1977         .recalc_rate = clk_pll_recalc_rate,
1978 };
1979
1980 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1981                           void __iomem *clk_base, void __iomem *pmc,
1982                           unsigned long flags,
1983                           struct tegra_clk_pll_params *pll_params,
1984                           spinlock_t *lock)
1985 {
1986         struct tegra_clk_pll *pll;
1987         struct clk *clk, *parent;
1988         unsigned long parent_rate;
1989         u32 val, val_iddq;
1990
1991         parent = __clk_lookup(parent_name);
1992         if (!parent) {
1993                 WARN(1, "parent clk %s of %s must be registered first\n",
1994                         parent_name, name);
1995                 return ERR_PTR(-EINVAL);
1996         }
1997
1998         if (!pll_params->pdiv_tohw)
1999                 return ERR_PTR(-EINVAL);
2000
2001         parent_rate = clk_get_rate(parent);
2002
2003         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2004
2005         if (pll_params->adjust_vco)
2006                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2007                                                              parent_rate);
2008
2009         /*
2010          * If the pll has a set_defaults callback, it will take care of
2011          * configuring dynamic ramping and setting IDDQ in that path.
2012          */
2013         if (!pll_params->set_defaults) {
2014                 int err;
2015
2016                 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2017                 if (err)
2018                         return ERR_PTR(err);
2019
2020                 val = readl_relaxed(clk_base + pll_params->base_reg);
2021                 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2022
2023                 if (val & PLL_BASE_ENABLE)
2024                         WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2025                 else {
2026                         val_iddq |= BIT(pll_params->iddq_bit_idx);
2027                         writel_relaxed(val_iddq,
2028                                        clk_base + pll_params->iddq_reg);
2029                 }
2030         }
2031
2032         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2033         if (IS_ERR(pll))
2034                 return ERR_CAST(pll);
2035
2036         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2037                                       &tegra_clk_pllxc_ops);
2038         if (IS_ERR(clk))
2039                 kfree(pll);
2040
2041         return clk;
2042 }
2043
2044 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2045                           void __iomem *clk_base, void __iomem *pmc,
2046                           unsigned long flags,
2047                           struct tegra_clk_pll_params *pll_params,
2048                           spinlock_t *lock, unsigned long parent_rate)
2049 {
2050         u32 val;
2051         struct tegra_clk_pll *pll;
2052         struct clk *clk;
2053
2054         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2055
2056         if (pll_params->adjust_vco)
2057                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2058                                                              parent_rate);
2059
2060         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2061         if (IS_ERR(pll))
2062                 return ERR_CAST(pll);
2063
2064         /* program minimum rate by default */
2065
2066         val = pll_readl_base(pll);
2067         if (val & PLL_BASE_ENABLE)
2068                 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2069                                 BIT(pll_params->iddq_bit_idx));
2070         else {
2071                 int m;
2072
2073                 m = _pll_fixed_mdiv(pll_params, parent_rate);
2074                 val = m << divm_shift(pll);
2075                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2076                 pll_writel_base(val, pll);
2077         }
2078
2079         /* disable lock override */
2080
2081         val = pll_readl_misc(pll);
2082         val &= ~BIT(29);
2083         pll_writel_misc(val, pll);
2084
2085         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2086                                       &tegra_clk_pllre_ops);
2087         if (IS_ERR(clk))
2088                 kfree(pll);
2089
2090         return clk;
2091 }
2092
2093 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2094                           void __iomem *clk_base, void __iomem *pmc,
2095                           unsigned long flags,
2096                           struct tegra_clk_pll_params *pll_params,
2097                           spinlock_t *lock)
2098 {
2099         struct tegra_clk_pll *pll;
2100         struct clk *clk, *parent;
2101         unsigned long parent_rate;
2102
2103         if (!pll_params->pdiv_tohw)
2104                 return ERR_PTR(-EINVAL);
2105
2106         parent = __clk_lookup(parent_name);
2107         if (!parent) {
2108                 WARN(1, "parent clk %s of %s must be registered first\n",
2109                         parent_name, name);
2110                 return ERR_PTR(-EINVAL);
2111         }
2112
2113         parent_rate = clk_get_rate(parent);
2114
2115         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2116
2117         if (pll_params->adjust_vco)
2118                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2119                                                              parent_rate);
2120
2121         pll_params->flags |= TEGRA_PLL_BYPASS;
2122         pll_params->flags |= TEGRA_PLLM;
2123         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2124         if (IS_ERR(pll))
2125                 return ERR_CAST(pll);
2126
2127         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2128                                       &tegra_clk_pll_ops);
2129         if (IS_ERR(clk))
2130                 kfree(pll);
2131
2132         return clk;
2133 }
2134
2135 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2136                           void __iomem *clk_base, void __iomem *pmc,
2137                           unsigned long flags,
2138                           struct tegra_clk_pll_params *pll_params,
2139                           spinlock_t *lock)
2140 {
2141         struct clk *parent, *clk;
2142         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2143         struct tegra_clk_pll *pll;
2144         struct tegra_clk_pll_freq_table cfg;
2145         unsigned long parent_rate;
2146
2147         if (!p_tohw)
2148                 return ERR_PTR(-EINVAL);
2149
2150         parent = __clk_lookup(parent_name);
2151         if (!parent) {
2152                 WARN(1, "parent clk %s of %s must be registered first\n",
2153                         parent_name, name);
2154                 return ERR_PTR(-EINVAL);
2155         }
2156
2157         parent_rate = clk_get_rate(parent);
2158
2159         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2160
2161         pll_params->flags |= TEGRA_PLL_BYPASS;
2162         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2163         if (IS_ERR(pll))
2164                 return ERR_CAST(pll);
2165
2166         /*
2167          * Most of PLLC register fields are shadowed, and can not be read
2168          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2169          * Initialize PLL to default state: disabled, reset; shadow registers
2170          * loaded with default parameters; dividers are preset for half of
2171          * minimum VCO rate (the latter assured that shadowed divider settings
2172          * are within supported range).
2173          */
2174
2175         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2176         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2177
2178         while (p_tohw->pdiv) {
2179                 if (p_tohw->pdiv == 2) {
2180                         cfg.p = p_tohw->hw_val;
2181                         break;
2182                 }
2183                 p_tohw++;
2184         }
2185
2186         if (!p_tohw->pdiv) {
2187                 WARN_ON(1);
2188                 return ERR_PTR(-EINVAL);
2189         }
2190
2191         pll_writel_base(0, pll);
2192         _update_pll_mnp(pll, &cfg);
2193
2194         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2195         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2196         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2197         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2198
2199         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2200
2201         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2202                                       &tegra_clk_pllc_ops);
2203         if (IS_ERR(clk))
2204                 kfree(pll);
2205
2206         return clk;
2207 }
2208
2209 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2210                                 const char *parent_name,
2211                                 void __iomem *clk_base, unsigned long flags,
2212                                 struct tegra_clk_pll_params *pll_params,
2213                                 spinlock_t *lock)
2214 {
2215         struct tegra_clk_pll *pll;
2216         struct clk *clk;
2217         u32 val, val_aux;
2218
2219         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2220         if (IS_ERR(pll))
2221                 return ERR_CAST(pll);
2222
2223         /* ensure parent is set to pll_re_vco */
2224
2225         val = pll_readl_base(pll);
2226         val_aux = pll_readl(pll_params->aux_reg, pll);
2227
2228         if (val & PLL_BASE_ENABLE) {
2229                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2230                         (val_aux & PLLE_AUX_PLLP_SEL))
2231                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2232                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2233                                         "pll_re_vco");
2234         } else {
2235                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2236                 pll_writel(val_aux, pll_params->aux_reg, pll);
2237         }
2238
2239         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2240                                       &tegra_clk_plle_tegra114_ops);
2241         if (IS_ERR(clk))
2242                 kfree(pll);
2243
2244         return clk;
2245 }
2246
2247 struct clk *
2248 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2249                                  void __iomem *clk_base, unsigned long flags,
2250                                  struct tegra_clk_pll_params *pll_params,
2251                                  spinlock_t *lock)
2252 {
2253         struct tegra_clk_pll *pll;
2254         struct clk *clk;
2255
2256         pll_params->flags |= TEGRA_PLLU;
2257
2258         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2259         if (IS_ERR(pll))
2260                 return ERR_CAST(pll);
2261
2262         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2263                                       &tegra_clk_pllu_tegra114_ops);
2264         if (IS_ERR(clk))
2265                 kfree(pll);
2266
2267         return clk;
2268 }
2269 #endif
2270
2271 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2272 static const struct clk_ops tegra_clk_pllss_ops = {
2273         .is_enabled = clk_pll_is_enabled,
2274         .enable = clk_pll_enable,
2275         .disable = clk_pll_disable,
2276         .recalc_rate = clk_pll_recalc_rate,
2277         .round_rate = clk_pll_ramp_round_rate,
2278         .set_rate = clk_pllxc_set_rate,
2279 };
2280
2281 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2282                                 void __iomem *clk_base, unsigned long flags,
2283                                 struct tegra_clk_pll_params *pll_params,
2284                                 spinlock_t *lock)
2285 {
2286         struct tegra_clk_pll *pll;
2287         struct clk *clk, *parent;
2288         struct tegra_clk_pll_freq_table cfg;
2289         unsigned long parent_rate;
2290         u32 val, val_iddq;
2291         int i;
2292
2293         if (!pll_params->div_nmp)
2294                 return ERR_PTR(-EINVAL);
2295
2296         parent = __clk_lookup(parent_name);
2297         if (!parent) {
2298                 WARN(1, "parent clk %s of %s must be registered first\n",
2299                         parent_name, name);
2300                 return ERR_PTR(-EINVAL);
2301         }
2302
2303         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2304         if (IS_ERR(pll))
2305                 return ERR_CAST(pll);
2306
2307         val = pll_readl_base(pll);
2308         val &= ~PLLSS_REF_SRC_SEL_MASK;
2309         pll_writel_base(val, pll);
2310
2311         parent_rate = clk_get_rate(parent);
2312
2313         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2314
2315         /* initialize PLL to minimum rate */
2316
2317         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2318         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2319
2320         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2321                 ;
2322         if (!i) {
2323                 kfree(pll);
2324                 return ERR_PTR(-EINVAL);
2325         }
2326
2327         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2328
2329         _update_pll_mnp(pll, &cfg);
2330
2331         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2332         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2333         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2334         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2335
2336         val = pll_readl_base(pll);
2337         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2338         if (val & PLL_BASE_ENABLE) {
2339                 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2340                         WARN(1, "%s is on but IDDQ set\n", name);
2341                         kfree(pll);
2342                         return ERR_PTR(-EINVAL);
2343                 }
2344         } else {
2345                 val_iddq |= BIT(pll_params->iddq_bit_idx);
2346                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2347         }
2348
2349         val &= ~PLLSS_LOCK_OVERRIDE;
2350         pll_writel_base(val, pll);
2351
2352         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2353                                         &tegra_clk_pllss_ops);
2354
2355         if (IS_ERR(clk))
2356                 kfree(pll);
2357
2358         return clk;
2359 }
2360 #endif
2361
2362 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2363 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2364                           const char *parent_name, void __iomem *clk_base,
2365                           void __iomem *pmc, unsigned long flags,
2366                           struct tegra_clk_pll_params *pll_params,
2367                           spinlock_t *lock, unsigned long parent_rate)
2368 {
2369         struct tegra_clk_pll *pll;
2370         struct clk *clk;
2371
2372         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2373
2374         if (pll_params->adjust_vco)
2375                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2376                                                              parent_rate);
2377
2378         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2379         if (IS_ERR(pll))
2380                 return ERR_CAST(pll);
2381
2382         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2383                                       &tegra_clk_pll_ops);
2384         if (IS_ERR(clk))
2385                 kfree(pll);
2386
2387         return clk;
2388 }
2389
2390 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2391 {
2392         struct tegra_clk_pll *pll = to_clk_pll(hw);
2393         u32 val;
2394
2395         val = pll_readl_base(pll);
2396
2397         return val & PLLE_BASE_ENABLE ? 1 : 0;
2398 }
2399
2400 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2401 {
2402         struct tegra_clk_pll *pll = to_clk_pll(hw);
2403         struct tegra_clk_pll_freq_table sel;
2404         u32 val;
2405         int ret = 0;
2406         unsigned long flags = 0;
2407         unsigned long input_rate;
2408
2409         if (clk_plle_tegra210_is_enabled(hw))
2410                 return 0;
2411
2412         input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2413
2414         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2415                 return -EINVAL;
2416
2417         if (pll->lock)
2418                 spin_lock_irqsave(pll->lock, flags);
2419
2420         val = pll_readl(pll->params->aux_reg, pll);
2421         if (val & PLLE_AUX_SEQ_ENABLE)
2422                 goto out;
2423
2424         val = pll_readl_base(pll);
2425         val &= ~BIT(30); /* Disable lock override */
2426         pll_writel_base(val, pll);
2427
2428         val = pll_readl_misc(pll);
2429         val |= PLLE_MISC_LOCK_ENABLE;
2430         val |= PLLE_MISC_IDDQ_SW_CTRL;
2431         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2432         val |= PLLE_MISC_PLLE_PTS;
2433         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2434         pll_writel_misc(val, pll);
2435         udelay(5);
2436
2437         val = pll_readl(PLLE_SS_CTRL, pll);
2438         val |= PLLE_SS_DISABLE;
2439         pll_writel(val, PLLE_SS_CTRL, pll);
2440
2441         val = pll_readl_base(pll);
2442         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2443                  divm_mask_shifted(pll));
2444         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2445         val |= sel.m << divm_shift(pll);
2446         val |= sel.n << divn_shift(pll);
2447         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2448         pll_writel_base(val, pll);
2449         udelay(1);
2450
2451         val = pll_readl_base(pll);
2452         val |= PLLE_BASE_ENABLE;
2453         pll_writel_base(val, pll);
2454
2455         ret = clk_pll_wait_for_lock(pll);
2456
2457         if (ret < 0)
2458                 goto out;
2459
2460         val = pll_readl(PLLE_SS_CTRL, pll);
2461         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2462         val &= ~PLLE_SS_COEFFICIENTS_MASK;
2463         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2464         pll_writel(val, PLLE_SS_CTRL, pll);
2465         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2466         pll_writel(val, PLLE_SS_CTRL, pll);
2467         udelay(1);
2468         val &= ~PLLE_SS_CNTL_INTERP_RESET;
2469         pll_writel(val, PLLE_SS_CTRL, pll);
2470         udelay(1);
2471
2472         val = pll_readl_misc(pll);
2473         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2474         pll_writel_misc(val, pll);
2475
2476         val = pll_readl(pll->params->aux_reg, pll);
2477         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2478         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2479         pll_writel(val, pll->params->aux_reg, pll);
2480         udelay(1);
2481         val |= PLLE_AUX_SEQ_ENABLE;
2482         pll_writel(val, pll->params->aux_reg, pll);
2483
2484 out:
2485         if (pll->lock)
2486                 spin_unlock_irqrestore(pll->lock, flags);
2487
2488         return ret;
2489 }
2490
2491 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2492 {
2493         struct tegra_clk_pll *pll = to_clk_pll(hw);
2494         unsigned long flags = 0;
2495         u32 val;
2496
2497         if (pll->lock)
2498                 spin_lock_irqsave(pll->lock, flags);
2499
2500         /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2501         val = pll_readl(pll->params->aux_reg, pll);
2502         if (val & PLLE_AUX_SEQ_ENABLE)
2503                 goto out;
2504
2505         val = pll_readl_base(pll);
2506         val &= ~PLLE_BASE_ENABLE;
2507         pll_writel_base(val, pll);
2508
2509         val = pll_readl(pll->params->aux_reg, pll);
2510         val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2511         pll_writel(val, pll->params->aux_reg, pll);
2512
2513         val = pll_readl_misc(pll);
2514         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2515         pll_writel_misc(val, pll);
2516         udelay(1);
2517
2518 out:
2519         if (pll->lock)
2520                 spin_unlock_irqrestore(pll->lock, flags);
2521 }
2522
2523 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2524         .is_enabled =  clk_plle_tegra210_is_enabled,
2525         .enable = clk_plle_tegra210_enable,
2526         .disable = clk_plle_tegra210_disable,
2527         .recalc_rate = clk_pll_recalc_rate,
2528 };
2529
2530 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2531                                 const char *parent_name,
2532                                 void __iomem *clk_base, unsigned long flags,
2533                                 struct tegra_clk_pll_params *pll_params,
2534                                 spinlock_t *lock)
2535 {
2536         struct tegra_clk_pll *pll;
2537         struct clk *clk;
2538         u32 val, val_aux;
2539
2540         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2541         if (IS_ERR(pll))
2542                 return ERR_CAST(pll);
2543
2544         /* ensure parent is set to pll_re_vco */
2545
2546         val = pll_readl_base(pll);
2547         val_aux = pll_readl(pll_params->aux_reg, pll);
2548
2549         if (val & PLLE_BASE_ENABLE) {
2550                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2551                         (val_aux & PLLE_AUX_PLLP_SEL))
2552                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2553                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2554                                         "pll_re_vco");
2555         } else {
2556                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2557                 pll_writel(val_aux, pll_params->aux_reg, pll);
2558         }
2559
2560         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2561                                       &tegra_clk_plle_tegra210_ops);
2562         if (IS_ERR(clk))
2563                 kfree(pll);
2564
2565         return clk;
2566 }
2567
2568 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2569                         const char *parent_name, void __iomem *clk_base,
2570                         void __iomem *pmc, unsigned long flags,
2571                         struct tegra_clk_pll_params *pll_params,
2572                         spinlock_t *lock)
2573 {
2574         struct clk *parent, *clk;
2575         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2576         struct tegra_clk_pll *pll;
2577         unsigned long parent_rate;
2578
2579         if (!p_tohw)
2580                 return ERR_PTR(-EINVAL);
2581
2582         parent = __clk_lookup(parent_name);
2583         if (!parent) {
2584                 WARN(1, "parent clk %s of %s must be registered first\n",
2585                         name, parent_name);
2586                 return ERR_PTR(-EINVAL);
2587         }
2588
2589         parent_rate = clk_get_rate(parent);
2590
2591         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2592
2593         if (pll_params->adjust_vco)
2594                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2595                                                              parent_rate);
2596
2597         pll_params->flags |= TEGRA_PLL_BYPASS;
2598         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2599         if (IS_ERR(pll))
2600                 return ERR_CAST(pll);
2601
2602         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2603                                       &tegra_clk_pll_ops);
2604         if (IS_ERR(clk))
2605                 kfree(pll);
2606
2607         return clk;
2608 }
2609
2610 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2611                                 const char *parent_name, void __iomem *clk_base,
2612                                 unsigned long flags,
2613                                 struct tegra_clk_pll_params *pll_params,
2614                                 spinlock_t *lock)
2615 {
2616         struct tegra_clk_pll *pll;
2617         struct clk *clk, *parent;
2618         unsigned long parent_rate;
2619         u32 val;
2620
2621         if (!pll_params->div_nmp)
2622                 return ERR_PTR(-EINVAL);
2623
2624         parent = __clk_lookup(parent_name);
2625         if (!parent) {
2626                 WARN(1, "parent clk %s of %s must be registered first\n",
2627                         name, parent_name);
2628                 return ERR_PTR(-EINVAL);
2629         }
2630
2631         val = readl_relaxed(clk_base + pll_params->base_reg);
2632         if (val & PLLSS_REF_SRC_SEL_MASK) {
2633                 WARN(1, "not supported reference clock for %s\n", name);
2634                 return ERR_PTR(-EINVAL);
2635         }
2636
2637         parent_rate = clk_get_rate(parent);
2638
2639         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2640
2641         if (pll_params->adjust_vco)
2642                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2643                                                              parent_rate);
2644
2645         pll_params->flags |= TEGRA_PLL_BYPASS;
2646         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2647         if (IS_ERR(pll))
2648                 return ERR_CAST(pll);
2649
2650         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2651                                         &tegra_clk_pll_ops);
2652
2653         if (IS_ERR(clk))
2654                 kfree(pll);
2655
2656         return clk;
2657 }
2658
2659 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2660                           void __iomem *clk_base, void __iomem *pmc,
2661                           unsigned long flags,
2662                           struct tegra_clk_pll_params *pll_params,
2663                           spinlock_t *lock)
2664 {
2665         struct tegra_clk_pll *pll;
2666         struct clk *clk, *parent;
2667         unsigned long parent_rate;
2668
2669         if (!pll_params->pdiv_tohw)
2670                 return ERR_PTR(-EINVAL);
2671
2672         parent = __clk_lookup(parent_name);
2673         if (!parent) {
2674                 WARN(1, "parent clk %s of %s must be registered first\n",
2675                         parent_name, name);
2676                 return ERR_PTR(-EINVAL);
2677         }
2678
2679         parent_rate = clk_get_rate(parent);
2680
2681         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2682
2683         if (pll_params->adjust_vco)
2684                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2685                                                              parent_rate);
2686
2687         pll_params->flags |= TEGRA_PLL_BYPASS;
2688         pll_params->flags |= TEGRA_PLLMB;
2689         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2690         if (IS_ERR(pll))
2691                 return ERR_CAST(pll);
2692
2693         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2694                                       &tegra_clk_pll_ops);
2695         if (IS_ERR(clk))
2696                 kfree(pll);
2697
2698         return clk;
2699 }
2700
2701 #endif