drivers/clk/sunxi-ng/ccu-sun8i-a33.c

   1 /*
   2  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk-provider.h>
  15 #include <linux/of_address.h>
  16
  17 #include "ccu_common.h"
  18 #include "ccu_reset.h"
  19
  20 #include "ccu_div.h"
  21 #include "ccu_gate.h"
  22 #include "ccu_mp.h"
  23 #include "ccu_mult.h"
  24 #include "ccu_nk.h"
  25 #include "ccu_nkm.h"
  26 #include "ccu_nkmp.h"
  27 #include "ccu_nm.h"
  28 #include "ccu_phase.h"
  29
  30 #include "ccu-sun8i-a23-a33.h"
  31
  32 static struct ccu_nkmp pll_cpux_clk = {
  33         .enable = BIT(31),
  34         .lock   = BIT(28),
  35
  36         .n      = _SUNXI_CCU_MULT(8, 5),
  37         .k      = _SUNXI_CCU_MULT(4, 2),
  38         .m      = _SUNXI_CCU_DIV(0, 2),
  39         .p      = _SUNXI_CCU_DIV_MAX(16, 2, 4),
  40
  41         .common = {
  42                 .reg            = 0x000,
  43                 .hw.init        = CLK_HW_INIT("pll-cpux", "osc24M",
  44                                               &ccu_nkmp_ops,
  45                                               0),
  46         },
  47 };
  48
  49 /*
  50  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  51  * the base (2x, 4x and 8x), and one variable divider (the one true
  52  * pll audio).
  53  *
  54  * With sigma-delta modulation for fractional-N on the audio PLL,
  55  * we have to use specific dividers. This means the variable divider
  56  * can no longer be used, as the audio codec requests the exact clock
  57  * rates we support through this mechanism. So we now hard code the
  58  * variable divider to 1. This means the clock rates will no longer
  59  * match the clock names.
  60  */
  61 #define SUN8I_A33_PLL_AUDIO_REG 0x008
  62
  63 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
  64         { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
  65         { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
  66 };
  67
  68 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
  69                                        "osc24M", 0x008,
  70                                        8, 7,    /* N */
  71                                        0, 5,    /* M */
  72                                        pll_audio_sdm_table, BIT(24),
  73                                        0x284, BIT(31),
  74                                        BIT(31), /* gate */
  75                                        BIT(28), /* lock */
  76                                        CLK_SET_RATE_UNGATE);
  77
  78 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
  79                                         "osc24M", 0x010,
  80                                         8, 7,           /* N */
  81                                         0, 4,           /* M */
  82                                         BIT(24),        /* frac enable */
  83                                         BIT(25),        /* frac select */
  84                                         270000000,      /* frac rate 0 */
  85                                         297000000,      /* frac rate 1 */
  86                                         BIT(31),        /* gate */
  87                                         BIT(28),        /* lock */
  88                                         CLK_SET_RATE_UNGATE);
  89
  90 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
  91                                         "osc24M", 0x018,
  92                                         8, 7,           /* N */
  93                                         0, 4,           /* M */
  94                                         BIT(24),        /* frac enable */
  95                                         BIT(25),        /* frac select */
  96                                         270000000,      /* frac rate 0 */
  97                                         297000000,      /* frac rate 1 */
  98                                         BIT(31),        /* gate */
  99                                         BIT(28),        /* lock */
 100                                         CLK_SET_RATE_UNGATE);
 101
 102 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
 103                                     "osc24M", 0x020,
 104                                     8, 5,               /* N */
 105                                     4, 2,               /* K */
 106                                     0, 2,               /* M */
 107                                     BIT(31),            /* gate */
 108                                     BIT(28),            /* lock */
 109                                     0);
 110
 111 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
 112                                            "osc24M", 0x028,
 113                                            8, 5,        /* N */
 114                                            4, 2,        /* K */
 115                                            BIT(31),     /* gate */
 116                                            BIT(28),     /* lock */
 117                                            2,           /* post-div */
 118                                            CLK_SET_RATE_UNGATE);
 119
 120 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
 121                                         "osc24M", 0x038,
 122                                         8, 7,           /* N */
 123                                         0, 4,           /* M */
 124                                         BIT(24),        /* frac enable */
 125                                         BIT(25),        /* frac select */
 126                                         270000000,      /* frac rate 0 */
 127                                         297000000,      /* frac rate 1 */
 128                                         BIT(31),        /* gate */
 129                                         BIT(28),        /* lock */
 130                                         CLK_SET_RATE_UNGATE);
 131
 132 /*
 133  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
 134  *
 135  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
 136  * integer / fractional clock with switchable multipliers and dividers.
 137  * This is not supported here. We hardcode the PLL to MIPI mode.
 138  */
 139 #define SUN8I_A33_PLL_MIPI_REG  0x040
 140 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
 141                                     "pll-video", 0x040,
 142                                     8, 4,               /* N */
 143                                     4, 2,               /* K */
 144                                     0, 4,               /* M */
 145                                     BIT(31) | BIT(23) | BIT(22), /* gate */
 146                                     BIT(28),            /* lock */
 147                                     CLK_SET_RATE_UNGATE);
 148
 149 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
 150                                         "osc24M", 0x044,
 151                                         8, 7,           /* N */
 152                                         0, 4,           /* M */
 153                                         BIT(24),        /* frac enable */
 154                                         BIT(25),        /* frac select */
 155                                         270000000,      /* frac rate 0 */
 156                                         297000000,      /* frac rate 1 */
 157                                         BIT(31),        /* gate */
 158                                         BIT(28),        /* lock */
 159                                         CLK_SET_RATE_UNGATE);
 160
 161 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
 162                                         "osc24M", 0x048,
 163                                         8, 7,           /* N */
 164                                         0, 4,           /* M */
 165                                         BIT(24),        /* frac enable */
 166                                         BIT(25),        /* frac select */
 167                                         270000000,      /* frac rate 0 */
 168                                         297000000,      /* frac rate 1 */
 169                                         BIT(31),        /* gate */
 170                                         BIT(28),        /* lock */
 171                                         CLK_SET_RATE_UNGATE);
 172
 173 static struct ccu_mult pll_ddr1_clk = {
 174         .enable = BIT(31),
 175         .lock   = BIT(28),
 176         .mult   = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
 177         .common = {
 178                 .reg            = 0x04c,
 179                 .hw.init        = CLK_HW_INIT("pll-ddr1", "osc24M",
 180                                               &ccu_mult_ops,
 181                                               CLK_SET_RATE_UNGATE),
 182         },
 183 };
 184
 185 static const char * const cpux_parents[] = { "osc32k", "osc24M",
 186                                              "pll-cpux" , "pll-cpux" };
 187 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
 188                      0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 189
 190 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 191
 192 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 193                                              "axi" , "pll-periph" };
 194 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
 195         { .index = 3, .shift = 6, .width = 2 },
 196 };
 197 static struct ccu_div ahb1_clk = {
 198         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 199
 200         .mux            = {
 201                 .shift  = 12,
 202                 .width  = 2,
 203
 204                 .var_predivs    = ahb1_predivs,
 205                 .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
 206         },
 207
 208         .common         = {
 209                 .reg            = 0x054,
 210                 .features       = CCU_FEATURE_VARIABLE_PREDIV,
 211                 .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
 212                                                       ahb1_parents,
 213                                                       &ccu_div_ops,
 214                                                       0),
 215         },
 216 };
 217
 218 static struct clk_div_table apb1_div_table[] = {
 219         { .val = 0, .div = 2 },
 220         { .val = 1, .div = 2 },
 221         { .val = 2, .div = 4 },
 222         { .val = 3, .div = 8 },
 223         { /* Sentinel */ },
 224 };
 225 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
 226                            0x054, 8, 2, apb1_div_table, 0);
 227
 228 static const char * const apb2_parents[] = { "osc32k", "osc24M",
 229                                              "pll-periph" , "pll-periph" };
 230 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
 231                              0, 5,      /* M */
 232                              16, 2,     /* P */
 233                              24, 2,     /* mux */
 234                              0);
 235
 236 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
 237                       0x060, BIT(1), 0);
 238 static SUNXI_CCU_GATE(bus_ss_clk,       "bus-ss",       "ahb1",
 239                       0x060, BIT(5), 0);
 240 static SUNXI_CCU_GATE(bus_dma_clk,      "bus-dma",      "ahb1",
 241                       0x060, BIT(6), 0);
 242 static SUNXI_CCU_GATE(bus_mmc0_clk,     "bus-mmc0",     "ahb1",
 243                       0x060, BIT(8), 0);
 244 static SUNXI_CCU_GATE(bus_mmc1_clk,     "bus-mmc1",     "ahb1",
 245                       0x060, BIT(9), 0);
 246 static SUNXI_CCU_GATE(bus_mmc2_clk,     "bus-mmc2",     "ahb1",
 247                       0x060, BIT(10), 0);
 248 static SUNXI_CCU_GATE(bus_nand_clk,     "bus-nand",     "ahb1",
 249                       0x060, BIT(13), 0);
 250 static SUNXI_CCU_GATE(bus_dram_clk,     "bus-dram",     "ahb1",
 251                       0x060, BIT(14), 0);
 252 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
 253                       0x060, BIT(19), 0);
 254 static SUNXI_CCU_GATE(bus_spi0_clk,     "bus-spi0",     "ahb1",
 255                       0x060, BIT(20), 0);
 256 static SUNXI_CCU_GATE(bus_spi1_clk,     "bus-spi1",     "ahb1",
 257                       0x060, BIT(21), 0);
 258 static SUNXI_CCU_GATE(bus_otg_clk,      "bus-otg",      "ahb1",
 259                       0x060, BIT(24), 0);
 260 static SUNXI_CCU_GATE(bus_ehci_clk,     "bus-ehci",     "ahb1",
 261                       0x060, BIT(26), 0);
 262 static SUNXI_CCU_GATE(bus_ohci_clk,     "bus-ohci",     "ahb1",
 263                       0x060, BIT(29), 0);
 264
 265 static SUNXI_CCU_GATE(bus_ve_clk,       "bus-ve",       "ahb1",
 266                       0x064, BIT(0), 0);
 267 static SUNXI_CCU_GATE(bus_lcd_clk,      "bus-lcd",      "ahb1",
 268                       0x064, BIT(4), 0);
 269 static SUNXI_CCU_GATE(bus_csi_clk,      "bus-csi",      "ahb1",
 270                       0x064, BIT(8), 0);
 271 static SUNXI_CCU_GATE(bus_de_be_clk,    "bus-de-be",    "ahb1",
 272                       0x064, BIT(12), 0);
 273 static SUNXI_CCU_GATE(bus_de_fe_clk,    "bus-de-fe",    "ahb1",
 274                       0x064, BIT(14), 0);
 275 static SUNXI_CCU_GATE(bus_gpu_clk,      "bus-gpu",      "ahb1",
 276                       0x064, BIT(20), 0);
 277 static SUNXI_CCU_GATE(bus_msgbox_clk,   "bus-msgbox",   "ahb1",
 278                       0x064, BIT(21), 0);
 279 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
 280                       0x064, BIT(22), 0);
 281 static SUNXI_CCU_GATE(bus_drc_clk,      "bus-drc",      "ahb1",
 282                       0x064, BIT(25), 0);
 283 static SUNXI_CCU_GATE(bus_sat_clk,      "bus-sat",      "ahb1",
 284                       0x064, BIT(26), 0);
 285
 286 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
 287                       0x068, BIT(0), 0);
 288 static SUNXI_CCU_GATE(bus_pio_clk,      "bus-pio",      "apb1",
 289                       0x068, BIT(5), 0);
 290 static SUNXI_CCU_GATE(bus_i2s0_clk,     "bus-i2s0",     "apb1",
 291                       0x068, BIT(12), 0);
 292 static SUNXI_CCU_GATE(bus_i2s1_clk,     "bus-i2s1",     "apb1",
 293                       0x068, BIT(13), 0);
 294
 295 static SUNXI_CCU_GATE(bus_i2c0_clk,     "bus-i2c0",     "apb2",
 296                       0x06c, BIT(0), 0);
 297 static SUNXI_CCU_GATE(bus_i2c1_clk,     "bus-i2c1",     "apb2",
 298                       0x06c, BIT(1), 0);
 299 static SUNXI_CCU_GATE(bus_i2c2_clk,     "bus-i2c2",     "apb2",
 300                       0x06c, BIT(2), 0);
 301 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
 302                       0x06c, BIT(16), 0);
 303 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
 304                       0x06c, BIT(17), 0);
 305 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
 306                       0x06c, BIT(18), 0);
 307 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
 308                       0x06c, BIT(19), 0);
 309 static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
 310                       0x06c, BIT(20), 0);
 311
 312 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
 313 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
 314                                   0, 4,         /* M */
 315                                   16, 2,        /* P */
 316                                   24, 2,        /* mux */
 317                                   BIT(31),      /* gate */
 318                                   0);
 319
 320 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
 321                                   0, 4,         /* M */
 322                                   16, 2,        /* P */
 323                                   24, 2,        /* mux */
 324                                   BIT(31),      /* gate */
 325                                   0);
 326
 327 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
 328                        0x088, 20, 3, 0);
 329 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
 330                        0x088, 8, 3, 0);
 331
 332 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
 333                                   0, 4,         /* M */
 334                                   16, 2,        /* P */
 335                                   24, 2,        /* mux */
 336                                   BIT(31),      /* gate */
 337                                   0);
 338
 339 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
 340                        0x08c, 20, 3, 0);
 341 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
 342                        0x08c, 8, 3, 0);
 343
 344 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
 345                                   0, 4,         /* M */
 346                                   16, 2,        /* P */
 347                                   24, 2,        /* mux */
 348                                   BIT(31),      /* gate */
 349                                   0);
 350
 351 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
 352                        0x090, 20, 3, 0);
 353 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
 354                        0x090, 8, 3, 0);
 355
 356 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
 357                                   0, 4,         /* M */
 358                                   16, 2,        /* P */
 359                                   24, 2,        /* mux */
 360                                   BIT(31),      /* gate */
 361                                   0);
 362
 363 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 364                                   0, 4,         /* M */
 365                                   16, 2,        /* P */
 366                                   24, 2,        /* mux */
 367                                   BIT(31),      /* gate */
 368                                   0);
 369
 370 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 371                                   0, 4,         /* M */
 372                                   16, 2,        /* P */
 373                                   24, 2,        /* mux */
 374                                   BIT(31),      /* gate */
 375                                   0);
 376
 377 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
 378                                             "pll-audio-2x", "pll-audio" };
 379 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
 380                                0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 381
 382 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
 383                                0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 384
 385 /* TODO: the parent for most of the USB clocks is not known */
 386 static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "osc24M",
 387                       0x0cc, BIT(8), 0);
 388 static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "osc24M",
 389                       0x0cc, BIT(9), 0);
 390 static SUNXI_CCU_GATE(usb_hsic_clk,     "usb-hsic",     "pll-hsic",
 391                       0x0cc, BIT(10), 0);
 392 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
 393                       0x0cc, BIT(11), 0);
 394 static SUNXI_CCU_GATE(usb_ohci_clk,     "usb-ohci",     "osc24M",
 395                       0x0cc, BIT(16), 0);
 396
 397 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
 398                    0x0f4, 0, 4, CLK_IS_CRITICAL);
 399
 400 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
 401 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
 402                      0x0f8, 16, 1, 0);
 403
 404 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "dram",
 405                       0x100, BIT(0), 0);
 406 static SUNXI_CCU_GATE(dram_csi_clk,     "dram-csi",     "dram",
 407                       0x100, BIT(1), 0);
 408 static SUNXI_CCU_GATE(dram_drc_clk,     "dram-drc",     "dram",
 409                       0x100, BIT(16), 0);
 410 static SUNXI_CCU_GATE(dram_de_fe_clk,   "dram-de-fe",   "dram",
 411                       0x100, BIT(24), 0);
 412 static SUNXI_CCU_GATE(dram_de_be_clk,   "dram-de-be",   "dram",
 413                       0x100, BIT(26), 0);
 414
 415 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
 416                                            "pll-gpu", "pll-de" };
 417 static const u8 de_table[] = { 0, 2, 3, 5 };
 418 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
 419                                        de_parents, de_table,
 420                                        0x104, 0, 4, 24, 3, BIT(31), 0);
 421
 422 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
 423                                        de_parents, de_table,
 424                                        0x10c, 0, 4, 24, 3, BIT(31), 0);
 425
 426 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
 427                                                 "pll-mipi" };
 428 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
 429 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
 430                                      lcd_ch0_parents, lcd_ch0_table,
 431                                      0x118, 24, 3, BIT(31),
 432                                      CLK_SET_RATE_PARENT);
 433
 434 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
 435 static const u8 lcd_ch1_table[] = { 0, 2 };
 436 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
 437                                        lcd_ch1_parents, lcd_ch1_table,
 438                                        0x12c, 0, 4, 24, 2, BIT(31), 0);
 439
 440 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
 441                                                  "pll-mipi", "pll-ve" };
 442 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
 443 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
 444                                        csi_sclk_parents, csi_sclk_table,
 445                                        0x134, 16, 4, 24, 3, BIT(31), 0);
 446
 447 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
 448                                                  "osc24M" };
 449 static const u8 csi_mclk_table[] = { 0, 3, 5 };
 450 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
 451                                        csi_mclk_parents, csi_mclk_table,
 452                                        0x134, 0, 5, 8, 3, BIT(15), 0);
 453
 454 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
 455                              0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
 456
 457 static SUNXI_CCU_GATE(ac_dig_clk,       "ac-dig",       "pll-audio",
 458                       0x140, BIT(31), CLK_SET_RATE_PARENT);
 459 static SUNXI_CCU_GATE(ac_dig_4x_clk,    "ac-dig-4x",    "pll-audio-4x",
 460                       0x140, BIT(30), CLK_SET_RATE_PARENT);
 461 static SUNXI_CCU_GATE(avs_clk,          "avs",          "osc24M",
 462                       0x144, BIT(31), 0);
 463
 464 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
 465                                              "pll-ddr0", "pll-ddr1" };
 466 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
 467                                  0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
 468
 469 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
 470 static const u8 dsi_sclk_table[] = { 0, 2 };
 471 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
 472                                        dsi_sclk_parents, dsi_sclk_table,
 473                                        0x168, 16, 4, 24, 2, BIT(31), 0);
 474
 475 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
 476 static const u8 dsi_dphy_table[] = { 0, 2 };
 477 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
 478                                        dsi_dphy_parents, dsi_dphy_table,
 479                                        0x168, 0, 4, 8, 2, BIT(15), 0);
 480
 481 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
 482                                        de_parents, de_table,
 483                                        0x180, 0, 4, 24, 3, BIT(31), 0);
 484
 485 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
 486                              0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 487
 488 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
 489 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
 490                                  0x1b0, 0, 3, 24, 2, BIT(31), 0);
 491
 492 static struct ccu_common *sun8i_a33_ccu_clks[] = {
 493         &pll_cpux_clk.common,
 494         &pll_audio_base_clk.common,
 495         &pll_video_clk.common,
 496         &pll_ve_clk.common,
 497         &pll_ddr0_clk.common,
 498         &pll_periph_clk.common,
 499         &pll_gpu_clk.common,
 500         &pll_mipi_clk.common,
 501         &pll_hsic_clk.common,
 502         &pll_de_clk.common,
 503         &pll_ddr1_clk.common,
 504         &pll_ddr_clk.common,
 505         &cpux_clk.common,
 506         &axi_clk.common,
 507         &ahb1_clk.common,
 508         &apb1_clk.common,
 509         &apb2_clk.common,
 510         &bus_mipi_dsi_clk.common,
 511         &bus_ss_clk.common,
 512         &bus_dma_clk.common,
 513         &bus_mmc0_clk.common,
 514         &bus_mmc1_clk.common,
 515         &bus_mmc2_clk.common,
 516         &bus_nand_clk.common,
 517         &bus_dram_clk.common,
 518         &bus_hstimer_clk.common,
 519         &bus_spi0_clk.common,
 520         &bus_spi1_clk.common,
 521         &bus_otg_clk.common,
 522         &bus_ehci_clk.common,
 523         &bus_ohci_clk.common,
 524         &bus_ve_clk.common,
 525         &bus_lcd_clk.common,
 526         &bus_csi_clk.common,
 527         &bus_de_fe_clk.common,
 528         &bus_de_be_clk.common,
 529         &bus_gpu_clk.common,
 530         &bus_msgbox_clk.common,
 531         &bus_spinlock_clk.common,
 532         &bus_drc_clk.common,
 533         &bus_sat_clk.common,
 534         &bus_codec_clk.common,
 535         &bus_pio_clk.common,
 536         &bus_i2s0_clk.common,
 537         &bus_i2s1_clk.common,
 538         &bus_i2c0_clk.common,
 539         &bus_i2c1_clk.common,
 540         &bus_i2c2_clk.common,
 541         &bus_uart0_clk.common,
 542         &bus_uart1_clk.common,
 543         &bus_uart2_clk.common,
 544         &bus_uart3_clk.common,
 545         &bus_uart4_clk.common,
 546         &nand_clk.common,
 547         &mmc0_clk.common,
 548         &mmc0_sample_clk.common,
 549         &mmc0_output_clk.common,
 550         &mmc1_clk.common,
 551         &mmc1_sample_clk.common,
 552         &mmc1_output_clk.common,
 553         &mmc2_clk.common,
 554         &mmc2_sample_clk.common,
 555         &mmc2_output_clk.common,
 556         &ss_clk.common,
 557         &spi0_clk.common,
 558         &spi1_clk.common,
 559         &i2s0_clk.common,
 560         &i2s1_clk.common,
 561         &usb_phy0_clk.common,
 562         &usb_phy1_clk.common,
 563         &usb_hsic_clk.common,
 564         &usb_hsic_12M_clk.common,
 565         &usb_ohci_clk.common,
 566         &dram_clk.common,
 567         &dram_ve_clk.common,
 568         &dram_csi_clk.common,
 569         &dram_drc_clk.common,
 570         &dram_de_fe_clk.common,
 571         &dram_de_be_clk.common,
 572         &de_be_clk.common,
 573         &de_fe_clk.common,
 574         &lcd_ch0_clk.common,
 575         &lcd_ch1_clk.common,
 576         &csi_sclk_clk.common,
 577         &csi_mclk_clk.common,
 578         &ve_clk.common,
 579         &ac_dig_clk.common,
 580         &ac_dig_4x_clk.common,
 581         &avs_clk.common,
 582         &mbus_clk.common,
 583         &dsi_sclk_clk.common,
 584         &dsi_dphy_clk.common,
 585         &drc_clk.common,
 586         &gpu_clk.common,
 587         &ats_clk.common,
 588 };
 589
 590 /* We hardcode the divider to 1 for now */
 591 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
 592                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 593 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
 594                         "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
 595 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
 596                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 597 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
 598                         "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
 599 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
 600                         "pll-periph", 1, 2, 0);
 601 static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
 602                         "pll-video", 1, 2, 0);
 603
 604 static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
 605         .hws    = {
 606                 [CLK_PLL_CPUX]          = &pll_cpux_clk.common.hw,
 607                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 608                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 609                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 610                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 611                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 612                 [CLK_PLL_VIDEO]         = &pll_video_clk.common.hw,
 613                 [CLK_PLL_VIDEO_2X]      = &pll_video_2x_clk.hw,
 614                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 615                 [CLK_PLL_DDR0]          = &pll_ddr0_clk.common.hw,
 616                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 617                 [CLK_PLL_PERIPH_2X]     = &pll_periph_2x_clk.hw,
 618                 [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
 619                 [CLK_PLL_MIPI]          = &pll_mipi_clk.common.hw,
 620                 [CLK_PLL_HSIC]          = &pll_hsic_clk.common.hw,
 621                 [CLK_PLL_DE]            = &pll_de_clk.common.hw,
 622                 [CLK_PLL_DDR1]          = &pll_ddr1_clk.common.hw,
 623                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 624                 [CLK_CPUX]              = &cpux_clk.common.hw,
 625                 [CLK_AXI]               = &axi_clk.common.hw,
 626                 [CLK_AHB1]              = &ahb1_clk.common.hw,
 627                 [CLK_APB1]              = &apb1_clk.common.hw,
 628                 [CLK_APB2]              = &apb2_clk.common.hw,
 629                 [CLK_BUS_MIPI_DSI]      = &bus_mipi_dsi_clk.common.hw,
 630                 [CLK_BUS_SS]            = &bus_ss_clk.common.hw,
 631                 [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
 632                 [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
 633                 [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
 634                 [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
 635                 [CLK_BUS_NAND]          = &bus_nand_clk.common.hw,
 636                 [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
 637                 [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
 638                 [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
 639                 [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
 640                 [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
 641                 [CLK_BUS_EHCI]          = &bus_ehci_clk.common.hw,
 642                 [CLK_BUS_OHCI]          = &bus_ohci_clk.common.hw,
 643                 [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
 644                 [CLK_BUS_LCD]           = &bus_lcd_clk.common.hw,
 645                 [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
 646                 [CLK_BUS_DE_BE]         = &bus_de_be_clk.common.hw,
 647                 [CLK_BUS_DE_FE]         = &bus_de_fe_clk.common.hw,
 648                 [CLK_BUS_GPU]           = &bus_gpu_clk.common.hw,
 649                 [CLK_BUS_MSGBOX]        = &bus_msgbox_clk.common.hw,
 650                 [CLK_BUS_SPINLOCK]      = &bus_spinlock_clk.common.hw,
 651                 [CLK_BUS_DRC]           = &bus_drc_clk.common.hw,
 652                 [CLK_BUS_SAT]           = &bus_sat_clk.common.hw,
 653                 [CLK_BUS_CODEC]         = &bus_codec_clk.common.hw,
 654                 [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
 655                 [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
 656                 [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
 657                 [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
 658                 [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
 659                 [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
 660                 [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
 661                 [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
 662                 [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
 663                 [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
 664                 [CLK_BUS_UART4]         = &bus_uart4_clk.common.hw,
 665                 [CLK_NAND]              = &nand_clk.common.hw,
 666                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 667                 [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
 668                 [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
 669                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 670                 [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
 671                 [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
 672                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 673                 [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
 674                 [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
 675                 [CLK_SS]                = &ss_clk.common.hw,
 676                 [CLK_SPI0]              = &spi0_clk.common.hw,
 677                 [CLK_SPI1]              = &spi1_clk.common.hw,
 678                 [CLK_I2S0]              = &i2s0_clk.common.hw,
 679                 [CLK_I2S1]              = &i2s1_clk.common.hw,
 680                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 681                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 682                 [CLK_USB_HSIC]          = &usb_hsic_clk.common.hw,
 683                 [CLK_USB_HSIC_12M]      = &usb_hsic_12M_clk.common.hw,
 684                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 685                 [CLK_DRAM]              = &dram_clk.common.hw,
 686                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 687                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 688                 [CLK_DRAM_DRC]          = &dram_drc_clk.common.hw,
 689                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 690                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 691                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 692                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 693                 [CLK_LCD_CH0]           = &lcd_ch0_clk.common.hw,
 694                 [CLK_LCD_CH1]           = &lcd_ch1_clk.common.hw,
 695                 [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
 696                 [CLK_CSI_MCLK]          = &csi_mclk_clk.common.hw,
 697                 [CLK_VE]                = &ve_clk.common.hw,
 698                 [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
 699                 [CLK_AC_DIG_4X]         = &ac_dig_4x_clk.common.hw,
 700                 [CLK_AVS]               = &avs_clk.common.hw,
 701                 [CLK_MBUS]              = &mbus_clk.common.hw,
 702                 [CLK_DSI_SCLK]          = &dsi_sclk_clk.common.hw,
 703                 [CLK_DSI_DPHY]          = &dsi_dphy_clk.common.hw,
 704                 [CLK_DRC]               = &drc_clk.common.hw,
 705                 [CLK_GPU]               = &gpu_clk.common.hw,
 706                 [CLK_ATS]               = &ats_clk.common.hw,
 707         },
 708         .num    = CLK_NUMBER,
 709 };
 710
 711 static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
 712         [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
 713         [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
 714         [RST_USB_HSIC]          =  { 0x0cc, BIT(2) },
 715
 716         [RST_MBUS]              =  { 0x0fc, BIT(31) },
 717
 718         [RST_BUS_MIPI_DSI]      =  { 0x2c0, BIT(1) },
 719         [RST_BUS_SS]            =  { 0x2c0, BIT(5) },
 720         [RST_BUS_DMA]           =  { 0x2c0, BIT(6) },
 721         [RST_BUS_MMC0]          =  { 0x2c0, BIT(8) },
 722         [RST_BUS_MMC1]          =  { 0x2c0, BIT(9) },
 723         [RST_BUS_MMC2]          =  { 0x2c0, BIT(10) },
 724         [RST_BUS_NAND]          =  { 0x2c0, BIT(13) },
 725         [RST_BUS_DRAM]          =  { 0x2c0, BIT(14) },
 726         [RST_BUS_HSTIMER]       =  { 0x2c0, BIT(19) },
 727         [RST_BUS_SPI0]          =  { 0x2c0, BIT(20) },
 728         [RST_BUS_SPI1]          =  { 0x2c0, BIT(21) },
 729         [RST_BUS_OTG]           =  { 0x2c0, BIT(24) },
 730         [RST_BUS_EHCI]          =  { 0x2c0, BIT(26) },
 731         [RST_BUS_OHCI]          =  { 0x2c0, BIT(29) },
 732
 733         [RST_BUS_VE]            =  { 0x2c4, BIT(0) },
 734         [RST_BUS_LCD]           =  { 0x2c4, BIT(4) },
 735         [RST_BUS_CSI]           =  { 0x2c4, BIT(8) },
 736         [RST_BUS_DE_BE]         =  { 0x2c4, BIT(12) },
 737         [RST_BUS_DE_FE]         =  { 0x2c4, BIT(14) },
 738         [RST_BUS_GPU]           =  { 0x2c4, BIT(20) },
 739         [RST_BUS_MSGBOX]        =  { 0x2c4, BIT(21) },
 740         [RST_BUS_SPINLOCK]      =  { 0x2c4, BIT(22) },
 741         [RST_BUS_DRC]           =  { 0x2c4, BIT(25) },
 742         [RST_BUS_SAT]           =  { 0x2c4, BIT(26) },
 743
 744         [RST_BUS_LVDS]          =  { 0x2c8, BIT(0) },
 745
 746         [RST_BUS_CODEC]         =  { 0x2d0, BIT(0) },
 747         [RST_BUS_I2S0]          =  { 0x2d0, BIT(12) },
 748         [RST_BUS_I2S1]          =  { 0x2d0, BIT(13) },
 749
 750         [RST_BUS_I2C0]          =  { 0x2d8, BIT(0) },
 751         [RST_BUS_I2C1]          =  { 0x2d8, BIT(1) },
 752         [RST_BUS_I2C2]          =  { 0x2d8, BIT(2) },
 753         [RST_BUS_UART0]         =  { 0x2d8, BIT(16) },
 754         [RST_BUS_UART1]         =  { 0x2d8, BIT(17) },
 755         [RST_BUS_UART2]         =  { 0x2d8, BIT(18) },
 756         [RST_BUS_UART3]         =  { 0x2d8, BIT(19) },
 757         [RST_BUS_UART4]         =  { 0x2d8, BIT(20) },
 758 };
 759
 760 static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
 761         .ccu_clks       = sun8i_a33_ccu_clks,
 762         .num_ccu_clks   = ARRAY_SIZE(sun8i_a33_ccu_clks),
 763
 764         .hw_clks        = &sun8i_a33_hw_clks,
 765
 766         .resets         = sun8i_a33_ccu_resets,
 767         .num_resets     = ARRAY_SIZE(sun8i_a33_ccu_resets),
 768 };
 769
 770 static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
 771         .common = &pll_cpux_clk.common,
 772         /* copy from pll_cpux_clk */
 773         .enable = BIT(31),
 774         .lock   = BIT(28),
 775 };
 776
 777 static struct ccu_mux_nb sun8i_a33_cpu_nb = {
 778         .common         = &cpux_clk.common,
 779         .cm             = &cpux_clk.mux,
 780         .delay_us       = 1, /* > 8 clock cycles at 24 MHz */
 781         .bypass_index   = 1, /* index of 24 MHz oscillator */
 782 };
 783
 784 static void __init sun8i_a33_ccu_setup(struct device_node *node)
 785 {
 786         void __iomem *reg;
 787         u32 val;
 788
 789         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 790         if (IS_ERR(reg)) {
 791                 pr_err("%pOF: Could not map the clock registers\n", node);
 792                 return;
 793         }
 794
 795         /* Force the PLL-Audio-1x divider to 1 */
 796         val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
 797         val &= ~GENMASK(19, 16);
 798         writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
 799
 800         /* Force PLL-MIPI to MIPI mode */
 801         val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
 802         val &= ~BIT(16);
 803         writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
 804
 805         sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
 806
 807         /* Gate then ungate PLL CPU after any rate changes */
 808         ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
 809
 810         /* Reparent CPU during PLL CPU rate changes */
 811         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
 812                                   &sun8i_a33_cpu_nb);
 813 }
 814 CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
 815                sun8i_a33_ccu_setup);